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spi: correct spi mode selection logic#79

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kwd-doodling merged 1 commit intointel:mainfrom
xiaolusu:spi_cpol_cpha
Apr 30, 2026
Merged

spi: correct spi mode selection logic#79
kwd-doodling merged 1 commit intointel:mainfrom
xiaolusu:spi_cpol_cpha

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Fix by writing each value to its correct register field: cpha -> SCPH (Serial Clock Phase)
cpol -> SCPOL (Serial Clock Polarity)

This bug only affected SPI Mode 1 (CPOL=0, CPHA=1) and Mode 2 (CPOL=1, CPHA=0), which got silently swapped.
Mode 0 and Mode 3 were unaffected as both fields had the same value.

Fix by writing each value to its correct register field:
cpha -> SCPH (Serial Clock Phase)
cpol -> SCPOL (Serial Clock Polarity)

This bug only affected SPI Mode 1 (CPOL=0, CPHA=1) and Mode 2 (CPOL=1,
CPHA=0), which got silently swapped.
Mode 0 and Mode 3 were unaffected as both fields had the same value.

Signed-off-by: Xiaolu Sun <xiaolu.sun@intel.com>
@kwd-doodling kwd-doodling merged commit 7c8942c into intel:main Apr 30, 2026
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3 participants