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spi: correct spi mode selection logic CodeQL Advanced #121: Commit 7c8942c pushed by kwd-doodling
8m 55s main
main
8m 55s
spi: correct spi mode selection logic SEDI Doxygen Document Update #66: Commit 7c8942c pushed by kwd-doodling
6m 56s main
main
6m 56s
spi: correct spi mode selection logic checkpatch #150: Pull request #79 synchronize by kwd-doodling
8m 45s xiaolusu:spi_cpol_cpha
xiaolusu:spi_cpol_cpha
8m 45s
spi: correct spi mode selection logic iut_zephyr_build #305: Pull request #79 synchronize by kwd-doodling
9m 57s xiaolusu:spi_cpol_cpha
xiaolusu:spi_cpol_cpha
9m 57s
spi: correct spi mode selection logic CodeQL Advanced #120: Pull request #79 synchronize by kwd-doodling
3m 41s xiaolusu:spi_cpol_cpha
xiaolusu:spi_cpol_cpha
3m 41s
i2c: Add SET_BUS_DATA control commands to update default bus timings CodeQL Advanced #119: Commit c5359ed pushed by kwd-doodling
13m 4s main
main
13m 4s
i2c: Add SET_BUS_DATA control commands to update default bus timings SEDI Doxygen Document Update #65: Commit c5359ed pushed by kwd-doodling
5m 25s main
main
5m 25s
i2c: Add SET_BUS_DATA control commands to update default bus timings iut_zephyr_build #304: Pull request #80 opened by kwd-doodling
21m 31s dwang4_i2c_set_bus_timings
dwang4_i2c_set_bus_timings
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i2c: Add SET_BUS_DATA control commands to update default bus timings checkpatch #149: Pull request #80 opened by kwd-doodling
19m 9s dwang4_i2c_set_bus_timings
dwang4_i2c_set_bus_timings
19m 9s
i2c: Add SET_BUS_DATA control commands to update default bus timings CodeQL Advanced #118: Pull request #80 opened by kwd-doodling
20m 39s dwang4_i2c_set_bus_timings
dwang4_i2c_set_bus_timings
20m 39s
iut_zephyr_build iut_zephyr_build #303: Scheduled
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CodeQL Advanced CodeQL Advanced #117: Scheduled
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main
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iut_zephyr_build iut_zephyr_build #302: Scheduled
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main
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iut_zephyr_build iut_zephyr_build #301: Scheduled
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main
5m 51s
spi: correct spi mode selection logic checkpatch #148: Pull request #79 opened by xiaolusu
17m 25s xiaolusu:spi_cpol_cpha
xiaolusu:spi_cpol_cpha
17m 25s
spi: correct spi mode selection logic iut_zephyr_build #300: Pull request #79 opened by xiaolusu
25m 7s xiaolusu:spi_cpol_cpha
xiaolusu:spi_cpol_cpha
25m 7s
spi: correct spi mode selection logic CodeQL Advanced #116: Pull request #79 opened by xiaolusu
18m 31s xiaolusu:spi_cpol_cpha
xiaolusu:spi_cpol_cpha
18m 31s
CodeQL Advanced CodeQL Advanced #115: Scheduled
1m 5s main
main
1m 5s
iut_zephyr_build iut_zephyr_build #299: Scheduled
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main
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i2c: fine tune register values to meet frequency requirement SEDI Doxygen Document Update #64: Commit a985186 pushed by ddeshat
1m 2s main
main
1m 2s
i2c: fine tune register values to meet frequency requirement CodeQL Advanced #114: Commit a985186 pushed by ddeshat
1m 1s main
main
1m 1s
i2c: fine tune register values to meet the 100 kHz frequency requirement iut_zephyr_build #298: Pull request #78 synchronize by ddeshat
7m 18s ddeshat:ish_i2c
ddeshat:ish_i2c
7m 18s
i2c: fine tune register values to meet the 100 kHz frequency requirement checkpatch #147: Pull request #78 synchronize by ddeshat
9s ddeshat:ish_i2c
ddeshat:ish_i2c
9s
i2c: fine tune register values to meet the 100 kHz frequency requirement CodeQL Advanced #113: Pull request #78 synchronize by ddeshat
1m 7s ddeshat:ish_i2c
ddeshat:ish_i2c
1m 7s
i2c: fine tune register values to meet the 100 kHz frequency requirement CodeQL Advanced #112: Pull request #78 synchronize by ddeshat
59s ddeshat:ish_i2c
ddeshat:ish_i2c
59s