Comment cleanup (includes #131)

.github/workflows/build.yml

@@ -63,9 +63,9 @@ jobs:
         uses: taiki-e/install-action@just
       - name: Install Rust
         run: |
-          rustup install nightly-2026-02-26
-          rustup component add rust-src --toolchain nightly-2026-02-26
-          rustup default nightly-2026-02-26
+          rustup install stable
+          rustup default stable
+          rustup component add rust-src
       - name: Build
         run: |
           just build-tier3 ${{ matrix.target }}
@@ -89,9 +89,9 @@ jobs:
         uses: taiki-e/install-action@just
       - name: Install Rust
         run: |
-          rustup install nightly-2026-02-26
-          rustup component add rust-src --toolchain nightly-2026-02-26
-          rustup default nightly-2026-02-26
+          rustup install stable
+          rustup default stable
+          rustup component add rust-src
       - name: Build
         run: |
           just build-tier3-no-atomics ${{ matrix.target }}

aarch32-cpu/Cargo.toml

@@ -51,11 +51,25 @@ serde = ["dep:serde", "arbitrary-int/serde"]
 check-asm = []
 
 [package.metadata.docs.rs]
-# This is a list of supported Tier 2 targets, as of latest stable
 targets = [
-    "armv7r-none-eabihf",
-    "armv7r-none-eabi",
-    "armv7a-none-eabihf",
+    "armebv7r-none-eabi",
+    "armebv7r-none-eabihf",
+    "armv4t-none-eabi",
+    "armv5te-none-eabi",
+    "armv6-none-eabi",
+    "armv6-none-eabihf",
     "armv7a-none-eabi",
-    "armv8r-none-eabihf"
+    "armv7a-none-eabihf",
+    "armv7r-none-eabi",
+    "armv7r-none-eabihf",
+    "armv8r-none-eabihf",
+    "thumbv4t-none-eabi",
+    "thumbv5te-none-eabi",
+    "thumbv6-none-eabi",
+    "thumbv7a-none-eabi",
+    "thumbv7a-none-eabihf",
+    "thumbv7r-none-eabi",
+    "thumbv7r-none-eabihf",
+    "thumbv8r-none-eabihf",
 ]
+cargo-args = ["-Z", "build-std"]

aarch32-cpu/src/asmv4.rs

@@ -66,6 +66,7 @@ pub fn core_id() -> u32 {
     r & 0x00FF_FFFF
 }
 
+/// LLVM intrinsic for memory barriers
 #[no_mangle]
 pub extern "C" fn __sync_synchronize() {
     // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block

aarch32-cpu/src/generic_timer/el0.rs

@@ -2,7 +2,7 @@
 
 use crate::register;
 
-/// Represents our Physical Timer when we are running at EL0.
+/// Represents our Generic Physical Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
@@ -75,11 +75,11 @@ impl super::GenericTimer for El0PhysicalTimer {
     }
 }
 
-/// Represents our Virtual Timer when we are running at EL0.
+/// Represents our Generic Virtual Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
-/// [El1PhysicalTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
+/// [El1VirtualTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
 pub struct El0VirtualTimer();
 
 impl El0VirtualTimer {

aarch32-cpu/src/lib.rs

@@ -1,7 +1,14 @@
 //! CPU/peripheral support for Arm AArch32
 #![no_std]
+#![deny(missing_docs)]
+#![deny(unsafe_op_in_unsafe_fn)]
+#![deny(clippy::missing_safety_doc)]
+#![deny(clippy::unnecessary_safety_comment)]
+#![deny(clippy::unnecessary_safety_doc)]
 
-mod critical_section;
+pub mod cache;
+pub mod interrupt;
+pub mod register;
 
 #[cfg(any(
     doc,
@@ -21,26 +28,22 @@ pub mod asm;
 #[path = "asmv4.rs"]
 pub mod asm;
 
-pub mod cache;
-
 #[cfg(any(test, doc, arm_architecture = "v7-a", arm_architecture = "v8-r"))]
 pub mod generic_timer;
 
-pub mod interrupt;
-
-#[cfg(any(test, doc, arm_architecture = "v7-a"))]
+#[cfg(any(test, arm_profile = "a", arm_profile = "legacy"))]
 pub mod mmu;
 
-pub mod register;
+#[cfg(any(test, arm_architecture = "v7-r"))]
+pub mod pmsav7;
+
+#[cfg(any(test, arm_architecture = "v8-r"))]
+pub mod pmsav8;
 
 #[cfg(target_arch = "arm")]
 pub mod stacks;
 
-#[cfg(any(test, doc, arm_architecture = "v7-r"))]
-pub mod pmsav7;
-
-#[cfg(any(test, doc, arm_architecture = "v8-r"))]
-pub mod pmsav8;
+mod critical_section;
 
 /// Generate an SVC call with no parameters.
 ///