Chisel is an experimental Rowhammer fuzzer focused on exploring how access patterns, interleaving, and timing affect disturbance errors in DRAM. It is a lightweight framework intended for research and experimentation rather than production use.
- Multi-bank-aware access and pattern generation
- Configurable hammering strategies and sequencing
- Control over timing and ordering of memory accesses
- Multithreaded execution to simulate concurrent access patterns
- Flexible output/logging to assist analysis
Chisel is intended to be configurable so researchers can experiment with:
- Access/pattern generators
- Interleaving strategies across banks and threads
- Timing controls (delays, pacing)
Chisel was developed as an experimental tool to support investigations into Rowhammer effects and related memory disturbance phenomena. If you use Chisel in published work, please cite or acknowledge this repository appropriately.
Contributions, bug reports, and improvements are welcome. Typical ways to contribute:
- Open issues to report bugs or request features
- Submit pull requests with clear descriptions and tests where appropriate
- Suggest or provide example experiments and datasets