Created a 4-bit arithmetic-logic unit using various digital design techniques and hierarchical modeling in VHDL.
Consists of an arithmetic unit and a logical unit to handle both functions based on the user-input select lines. The functionality was demonstrated on a Xilinx Spartan-6 FPGA and the output was displayed on a seven-segment display with an LED to indicate overflow.
| Four-Bit Architecture: The ALU operates on four-bit binary inputs, allowing for processing a wide range of data. |
| Arithmetic Operations: Supports fundamental arithmetic operations, including addition, subtraction, and more, on four-bit numbers. |
| Logical Operations: Performs logical operations such as AND, OR, XOR, and NOT, enabling manipulation of binary data. |
| Single-Stage Design: The ALU is designed with a single-stage architecture for simplicity and efficiency. |
| Block Diagram: Refer to the block diagram (block-diagram-onestage-alu.png) for a visual representation of the ALU's components and their connections. |
