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RISC-V: Add INSN_DREF to memory read/write instructions#90

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RISC-V: Add INSN_DREF to memory read/write instructions#90
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riscv-opcode-dref

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@a4lg a4lg commented Nov 18, 2022

@a4lg a4lg force-pushed the riscv-opcode-dref branch 4 times, most recently from a852c00 to 9404ae4 Compare November 19, 2022 11:57
@a4lg a4lg added the bug Something isn't working label Nov 19, 2022
@a4lg a4lg force-pushed the riscv-opcode-dref branch 13 times, most recently from 89d5460 to b9a94e8 Compare November 26, 2022 00:28
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RISC-V: Add INSN_DREF to memory read/write instructions
a2ca1a3 
This commit adds INSN_DREF flag (and optional size-related flag) to the
instructions that read/write the memory directly.  It however excludes
cache-related instructions that do synchronization of some sort but
otherwise don't touch the contents of the memory.

INSN_DREF and optional size flag are added to following instructions:

-   "cbo.zero" (from the 'Zicboz' extension)
-   All instructions from following custom extensions:
    -   'XTheadFMemIdx'
    -   'XTheadInt'
    -   'XTheadMemIdx'
    -   'XTheadMemPair'

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Add INSN_DREF and optional size
	flag on the instructions directly read/write memory.
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