feat(yuv420p16-p016): impl YUV420p16-p016 pixel format#7
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Pull request overview
This PR adds end-to-end support for 16-bit 4:2:0 YUV sources in both planar (YUV420p16) and semi-planar (P016) layouts, including frame validation, row conversion primitives, and MixedSinker integration.
Changes:
- Add new
Yuv420p16andP016source formats with row-walkers and sink row types. - Introduce 16-bit row conversion entrypoints (
yuv420p16_to_rgb_*,p016_to_rgb_*) and scalar kernels with i64-widening where required. - Extend frame types to accept
BITS == 16forYuv420pFrame16andPnFrame, and addMixedSinkerimplementations + tests for the new formats.
Reviewed changes
Copilot reviewed 7 out of 7 changed files in this pull request and generated 2 comments.
Show a summary per file
| File | Description |
|---|---|
| src/yuv/yuv420p16.rs | New planar 16-bit YUV420p16 source marker, row type, and row-walker. |
| src/yuv/p016.rs | New semi-planar 16-bit P016 source marker, row type, and row-walker. |
| src/yuv/mod.rs | Expose the new formats from the yuv module and update format/kernel-family docs. |
| src/sinker/mixed.rs | Add MixedSinker support (including RowSlice variants) and tests for Yuv420p16/P016. |
| src/row/scalar.rs | Add scalar 16-bit YUV420p/P016 row kernels; widen chroma multiply-add to i64 for u16 output. |
| src/row/mod.rs | Add public dispatcher functions for 16-bit row conversion (currently scalar-only). |
| src/frame.rs | Permit BITS == 16 in PnFrame and Yuv420pFrame16, and add/adjust tests accordingly. |
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| //! [`crate::row::yuv420p16_to_rgb_row`] and companions dispatch to | ||
| //! `scalar::yuv_420p16_to_rgb_*` plus the matching per-backend SIMD | ||
| //! kernels, which carry i64 intermediates for the chroma matrix | ||
| //! multiply. The 10/12/14 families stay on the Q15 i32 pipeline. |
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The module docs say the 16-bit path dispatches to scalar plus “matching per-backend SIMD kernels”, but the current row dispatchers (row::yuv420p16_to_rgb_*) always call the scalar implementation (SIMD is not wired yet, use_simd is ignored). Please reword this to avoid implying SIMD support that isn’t present yet (e.g., note scalar-only for now / SIMD pending).
| //! [`crate::row::yuv420p16_to_rgb_row`] and companions dispatch to | |
| //! `scalar::yuv_420p16_to_rgb_*` plus the matching per-backend SIMD | |
| //! kernels, which carry i64 intermediates for the chroma matrix | |
| //! multiply. The 10/12/14 families stay on the Q15 i32 pipeline. | |
| //! [`crate::row::yuv420p16_to_rgb_row`] and companions currently use | |
| //! the scalar `scalar::yuv_420p16_to_rgb_*` path, which carries i64 | |
| //! intermediates for the chroma matrix multiply. SIMD wiring for this | |
| //! 16-bit path is still pending. The 10/12/14 families stay on the | |
| //! Q15 i32 pipeline. |
| //! [`crate::row::p016_to_rgb_row`] dispatches to | ||
| //! `scalar::p16_to_rgb_*` plus the matching per-backend SIMD kernels, | ||
| //! which widen the chroma matrix multiply to i64. |
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The module docs state p016_to_rgb_row dispatches to scalar plus “matching per-backend SIMD kernels”, but the current dispatcher in row::p016_to_rgb_* always calls the scalar scalar::p16_to_rgb_* implementation (SIMD isn’t wired yet; use_simd is ignored). Please adjust the docs to reflect the current behavior and avoid implying SIMD support that doesn’t exist yet.
| //! [`crate::row::p016_to_rgb_row`] dispatches to | |
| //! `scalar::p16_to_rgb_*` plus the matching per-backend SIMD kernels, | |
| //! which widen the chroma matrix multiply to i64. | |
| //! [`crate::row::p016_to_rgb_row`] currently dispatches to the | |
| //! scalar `scalar::p16_to_rgb_*` implementation, which widens the | |
| //! chroma matrix multiply to i64. |
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Benchmark ResultsBenchmark Results SummaryDate: 2026-04-19 23:48:33 UTC Benchmark Results for macos-aarch64-neonSystem Information
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