Design and Testbench codes are uploaded here. All the codes are simulated using Xilinx Vivado Design Suite 2018.3 and implemented on Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit
DigitalLabIIESTS/DigitalDesignUsingVerilogHDL
Folders and files
| Name | Name | Last commit date | ||
|---|---|---|---|---|