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This commit introduces the CPU verification mechanism to validate Triton kernels without NPU hardware. Key changes include: - Add cpu_backend.py: CPU-based execution backend using LLVM/MLIR infrastructure - Add DebugCPUVerifyPass: Validates that external dialect ops are lowered before CPU execution - Add test/ascend/cpu_verify/: Minimal test cases for vec_add, matmul, and flash attention Usage: export DLC_CPU_VERIFY=1 export LLVM_BINARY_DIR=/path/to/llvm/bin python test/ascend/cpu_verify/test_vec_add.py The CPU backend converts Triton IR to LLVM IR via MLIR passes and executes natively on CPU for rapid iteration and debugging.
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This commit introduces a robust framework for software pipelining on NPU targets by implementing stage-based loop partitioning and unrolling.
StageDependencyAnalyzer:
DimAnalyzer & DimensionDisjointSet:
NPUUnrollPipeline: