diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index a9c16ac089d..4ee379d9c69 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -220,8 +220,8 @@ jobs: config_file: ${{ env.verible_config }} extra_args: "--waiver_files=verible_waiver" - otbn_standalone_tests: - name: Run OTBN smoke Test + acc_standalone_tests: + name: Run ACC smoke Test needs: quick_lint runs-on: group: zerorisc-none @@ -246,15 +246,15 @@ jobs: python3 --version fusesoc --version verilator --version - - name: OTBN ISS test - run: make -C hw/ip/otbn/dv/otbnsim test + - name: ACC ISS test + run: make -C hw/ip/acc/dv/accsim test - name: OBTN smoke test - run: ./hw/ip/otbn/dv/smoke/run_smoke.sh + run: ./hw/ip/acc/dv/smoke/run_smoke.sh - name: Assemble & link code snippets - run: make -C hw/ip/otbn/util asm-check + run: make -C hw/ip/acc/util asm-check - otbn_crypto_tests: - name: Run OTBN crypto tests + acc_crypto_tests: + name: Run ACC crypto tests needs: quick_lint runs-on: group: zerorisc-none @@ -267,7 +267,7 @@ jobs: - name: Prepare environment uses: ./.github/actions/prepare-env - name: Execute tests - run: ./bazelisk.sh test --test_tag_filters=-nightly //sw/otbn/crypto/... + run: ./bazelisk.sh test --test_tag_filters=-nightly //sw/acc/crypto/... verilator_earlgrey: name: Verilated Earl Grey @@ -358,12 +358,12 @@ jobs: # # 1. `//hw/...` is out of scope. # 2. `//quality/...` is tested by the lint jobs. - # 3. `//sw/otbn/crypto/...` is tested by the OTBN job. + # 3. `//sw/acc/crypto/...` is tested by the ACC job. # 4. `//third_party/...` which is not our code. printf "%s\n" \ "-//hw/..." \ "-//quality/..." \ - "-//sw/otbn/crypto/..." \ + "-//sw/acc/crypto/..." \ "-//third_party/..." \ >> "$target_pattern_file" # Exclude anything that requires a bitstream splice. diff --git a/.github/workflows/zr-ci.yml b/.github/workflows/zr-ci.yml new file mode 100644 index 00000000000..a1e620bd628 --- /dev/null +++ b/.github/workflows/zr-ci.yml @@ -0,0 +1,589 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright zeroRISC Inc. +# Confidential information of zeroRISC Inc. All rights reserved. + +name: zeroRISC CI +on: + pull_request: + branches-ignore: + - "backport-*" + - "gh-readonly-queue/**" + tags: + - "*" + merge_group: + types: + - checks_requested + workflow_call: + +permissions: + contents: read + # Needed for workload identity federation + id-token: write + # Needed for reviewdog (verible linter) + pull-requests: write + +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +env: + VIVADO_VERSION: "2024.1" + # Release tag from https://github.com/lowRISC/lowrisc-toolchains/releases + TOOLCHAIN_VERSION: 20220210-1 + +jobs: + quick_lint: + name: Lint (quick) + runs-on: + group: zerorisc-none + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # Required so we can lint commit messages. + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Show environment + run: ./ci/scripts/show-env.sh + - name: License headers + run: ./ci/scripts/check-licence-headers.sh "$GITHUB_BASE_REF" + if: ${{ github.event_name == 'pull_request' }} + - name: Executable bits + run: ./ci/scripts/exec-check.sh + - name: Non-ASCII characters + run: ./ci/scripts/check-ascii.sh + - name: Check Bazel build graph + run: ./bazelisk.sh build --nobuild //... + - name: Python (flake8) + run: ./ci/scripts/python-lint.sh "$GITHUB_BASE_REF" + if: ${{ github.event_name == 'pull_request' }} + - name: Python (mypy) + run: ./ci/scripts/mypy.sh + - name: Python (ruff) + run: ruff check + - name: Validate testplans with schema + run: ./ci/scripts/validate_testplans.sh + - name: C/C++ formatting + run: ./bazelisk.sh test //quality:clang_format_check + - name: Rust formatting + run: ./bazelisk.sh test //quality:rustfmt_check + - name: Shellcheck + run: ./bazelisk.sh test //quality:shellcheck_check + - name: Header guards + run: ./ci/scripts/include-guard.sh "$GITHUB_BASE_REF" + if: ${{ github.event_name == 'pull_request' }} + - name: Trailing whitespace + run: ./ci/scripts/whitespace.sh "$GITHUB_BASE_REF" + if: ${{ github.event_name == 'pull_request' }} + - name: Broken links + run: ./ci/scripts/check-links.sh + - name: Generated documentation + run: ./ci/scripts/check-cmdgen.sh + - name: Lock files + run: ./ci/scripts/check-lock-files.sh + + slow_lint: + name: Lint (slow) + runs-on: + group: zerorisc-none + needs: quick_lint + if: ${{ github.event_name != 'merge_group' }} + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # Bitstream cache requires all commits. + - name: Prepare environment + uses: ./.github/actions/prepare-env + with: + install-verible: true + - name: Countermeasures implemented (earlgrey) + run: ./ci/scripts/check-countermeasures.sh earlgrey + - name: Countermeasures implemented (englishbreakfast) + run: ./ci/scripts/check-countermeasures.sh englishbreakfast + - name: Bazel test suite tags + run: ./ci/scripts/check_bazel_test_suites.py + continue-on-error: true + # See #21973: disabled until Verilator tags are fixed. + # - name: Check Bazel tags + # run: ./ci/scripts/check-bazel-tags.sh + # continue-on-error: true + - name: Banned Bazel rules + run: ./ci/scripts/check-bazel-banned-rules.sh + - name: Bazel target names + run: ./ci/scripts/check_bazel_target_names.py + - name: DV software images + run: ./ci/scripts/check_dv_sw_images.sh + continue-on-error: true + # zR: Currently commented out because it expects an upstream status report + # to exist for the current (internal) commit. + #- name: Build documentation + # run: ./ci/scripts/build-docs.sh + - name: Generated files + run: ./ci/scripts/check-generated.sh + env: + OT_DESTRUCTIVE: 1 # Required by the script to clean up. + - name: Buildifier + run: ./bazelisk.sh test //quality:buildifier_check + - name: Vendored files + run: ./ci/scripts/check-vendoring.sh + - name: Verible RTL + run: ./ci/scripts/verible-lint.sh rtl earlgrey + - name: Verible DV + run: ./ci/scripts/verible-lint.sh dv earlgrey + - name: Verible FPV + run: ./ci/scripts/verible-lint.sh fpv earlgrey + - name: Validate alert classification for Earl Grey + run: ./ci/scripts/validate_alert_classification.py hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson "$(realpath hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson)" + - name: Validate alert classification for Darjeeling + run: ./ci/scripts/validate_alert_classification.py hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson "$(realpath hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson)" + + dependency-licenses: + name: Check software dependency licenses + runs-on: + group: zerorisc-none + needs: quick_lint + steps: + - uses: actions/checkout@v4 + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Check Python licenses + run: | + ALLOWED=( + 'apache' + 'Apache 2.0' + 'Apache-2.0' + 'Apache Software License' + 'BSD' + 'BSD-3-Clause' + 'BSD License' + '3-Clause BSD License' + 'Freeware' + 'GNU Lesser General Public License v2 or later (LGPLv2+)' + 'GNU Lesser General Public License v3 (LGPLv3)' + 'GNU Library or Lesser General Public License (LGPL)' + 'MIT' + 'MIT License' + 'Mozilla Public License 2.0 (MPL 2.0)' + 'Public Domain' + 'Python Software Foundation License' + 'UNKNOWN' + '3-Clause BSD License' + ) + ALLOWED_SEMI=${ALLOWED[0]} + for lic in "${ALLOWED[@]}"; do + ALLOWED_SEMI="$ALLOWED_SEMI;$lic" + done; + pip-licenses --allow-only "$ALLOWED_SEMI" + - name: Install cargo + run: | + curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y + echo "~/.cargo/bin" >> "$GITHUB_PATH" + - name: Check Rust licenses + run: | + cargo install cargo-deny --version 0.18.4 + cargo deny --all-features --manifest-path third_party/rust/Cargo.toml check licenses + cargo deny --all-features --manifest-path third_party/tock/Cargo.toml check licenses + + build_docs: + name: Build documentation + runs-on: + group: zerorisc-none + needs: quick_lint + if: ${{ github.event_name != 'merge_group' }} + env: + BUCKET: gold-hybrid-255313-prod + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # Bitstream cache requires all commits. + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Build documentation + run: util/site/build-docs.sh build + - name: Upload files as artifact + uses: actions/upload-artifact@v4 + with: + name: docs + path: build-site/ + overwrite: true + + verible_lint: + name: Verible lint + runs-on: + group: zerorisc-none + needs: quick_lint + if: ${{ github.event_name == 'pull_request' }} + env: + verible_config: hw/lint/tools/veriblelint/lowrisc-styleguide.rules.verible_lint + verible_version: v0.0-3430-g060bde0f + steps: + - uses: actions/checkout@v4 + - name: Prepare Verible config + run: | + echo "Concatenating Verible waivers" + find . -type f -name '*.vbl' -exec cat {} \; >> verible_waiver + + echo "::group::Verible config" + cat "$verible_config" + echo "::endgroup::" + + echo "::group::Verible waiver" + cat "verible_waiver" + echo "::endgroup::" + - name: Install Verible + uses: ./.github/actions/third_party/verible + with: + verible_version: ${{ env.verible_version }} + - name: Run Verible linter with reviewdog + shell: bash + env: + INPUT_CONFIG_FILE: ${{ env.verible_config }} + INPUT_EXTRA_ARGS: '--waiver_files=verible_waiver' + INPUT_EXTENSIONS: '' + INPUT_FAIL_ON_ERROR: 'false' + INPUT_GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + INPUT_LOG_FILE: 'verible-verilog-lint.log' + INPUT_PATHS: '.' + INPUT_REVIEWDOG_REPORTER: 'github-pr-check' + INPUT_SUGGEST_FIXES: 'false' + run: ./.github/actions/third_party/verible/entrypoint.sh + - name: Upload Verible linter log + uses: actions/upload-artifact@v4 + with: + name: verible-linter + path: 'verible-verilog-lint.log' + + acc_standalone_tests: + name: Run ACC smoke Test + needs: quick_lint + runs-on: + group: zerorisc-none + if: ${{ github.event_name != 'merge_group' }} + timeout-minutes: 10 + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # Bitstream cache requires all commits. + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Install toolchain + run: | + TOOLCHAIN_PATH=/tools/riscv + sudo util/get-toolchain.py \ + --install-dir="$TOOLCHAIN_PATH" \ + --release-version="$TOOLCHAIN_VERSION" \ + --update + echo "$TOOLCHAIN_PATH/bin" >> $GITHUB_PATH + - name: Display environment + run: | + python3 --version + fusesoc --version + verilator --version + - name: ACC ISS test + run: make -C hw/ip/acc/dv/accsim test + - name: OBTN smoke test + run: ./hw/ip/acc/dv/smoke/run_smoke.sh + - name: Assemble & link code snippets + run: make -C hw/ip/acc/util asm-check + + acc_crypto_tests: + name: Run ACC crypto tests + needs: quick_lint + runs-on: + group: zerorisc-none + if: ${{ github.event_name != 'merge_group' }} + timeout-minutes: 60 + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # Bitstream cache requires all commits. + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Execute tests + run: ./bazelisk.sh test --test_tag_filters=-nightly //sw/acc/crypto/... + + verilator_earlgrey: + name: Verilated Earl Grey + runs-on: + group: zerorisc-large + needs: quick_lint + if: ${{ github.event_name != 'merge_group' }} + timeout-minutes: 240 + steps: + - uses: actions/checkout@v4 + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Run fast Verilator tests + run: ./ci/scripts/run-verilator-tests.sh + - name: Publish Bazel test results + uses: ./.github/actions/publish-bazel-test-results + if: ${{ !cancelled() }} + with: + artifact-name: verilator_earlgrey-test-results + + chip_earlgrey_cw310_hyperdebug: + name: Earl Grey for CW310 Hyperdebug + needs: quick_lint + if: github.event_name == 'pull_request' + uses: ./.github/workflows/bitstream.yml + secrets: inherit + with: + top_name: earlgrey + design_suffix: cw310_hyperdebug + vivado_version: '2024.1' + + chip_earlgrey_cw340: + name: Earl Grey for CW340 + needs: quick_lint + if: github.event_name == 'pull_request' + uses: ./.github/workflows/bitstream.yml + secrets: inherit + with: + top_name: earlgrey + design_suffix: cw340 + + # Hyper310 FPGA jobs + execute_tests_hyper310: + name: Hyper310 Tests + needs: chip_earlgrey_cw310_hyperdebug + uses: ./.github/workflows/hyper310-pr.yml + if: ${{ github.event_name != 'merge_group' }} + secrets: inherit + with: + bitstream: chip_earlgrey_cw310_hyperdebug + + # CW340 FPGA jobs + execute_tests_cw340: + name: CW340 Tests + needs: chip_earlgrey_cw340 + uses: ./.github/workflows/cw340-pr.yml + if: ${{ github.event_name != 'merge_group' }} + secrets: inherit + with: + bitstream: chip_earlgrey_cw340 + + sw_build_test: + name: Build and test software + runs-on: + group: zerorisc-large + timeout-minutes: 120 + needs: quick_lint + if: ${{ github.event_name != 'merge_group' }} + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # Required for bitstream cache to work. + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Check Bazel build graph + run: | + # Test the graph with both an empty and filled bitstream cache. + ./ci/scripts/test-empty-bitstream-cache.sh + ./bazelisk.sh build --nobuild //... + - name: Select software targets + run: | + target_pattern_file="$(mktemp)" + echo "target_pattern_file=${target_pattern_file}" >> "$GITHUB_ENV" + + # Start with building the whole graph. + echo '//...' > "$target_pattern_file" + # Exclude some targets: + # + # 1. `//hw/...` is out of scope. + # 2. `//quality/...` is tested by the lint jobs. + # 3. `//sw/acc/crypto/...` is tested by the ACC job. + # 4. `//third_party/...` which is not our code. + printf "%s\n" \ + "-//hw/..." \ + "-//quality/..." \ + "-//sw/acc/crypto/..." \ + "-//third_party/..." \ + >> "$target_pattern_file" + # Exclude anything that requires a bitstream splice. + ./bazelisk.sh cquery \ + --noinclude_aspects \ + --output=starlark \ + --starlark:expr='"-{}".format(target.label)' \ + --define DISABLE_VERILATOR_BUILD=true \ + -- "rdeps(//..., kind(bitstream_splice, //...))" \ + >> "$target_pattern_file" + - name: Build software targets + run: | + # Build everything we selected, excluding some tags. + ./bazelisk.sh build \ + --build_tests_only=false \ + --define DISABLE_VERILATOR_BUILD=true \ + --test_tag_filters=-broken,-cw310,-verilator,-dv \ + --target_pattern_file="$target_pattern_file" + - name: Run software unit tests + run: | + ./bazelisk.sh test \ + --build_tests_only=false \ + --test_output=errors \ + --define DISABLE_VERILATOR_BUILD=true \ + --test_tag_filters=-broken,-cw310,-verilator,-dv,-silicon \ + --target_pattern_file="$target_pattern_file" + - name: Publish Bazel test results + uses: ./.github/actions/publish-bazel-test-results + if: ${{ !cancelled() }} + with: + artifact-name: sw_build_test-test-results + - name: Check for unrunnable tests + run: ./ci/scripts/check-unrunnable-tests.sh + continue-on-error: true + + dj_sw_build_test: + name: Build and test Darjeeling software + runs-on: + group: zerorisc-large + timeout-minutes: 120 + needs: quick_lint + if: ${{ github.event_name != 'merge_group' }} + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 # Required for bitstream cache to work. + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Check Bazel build graph + run: | + # Test the graph with both an empty and filled bitstream cache. + ./ci/scripts/test-empty-bitstream-cache.sh + ./bazelisk.sh build --nobuild --//hw/top=darjeeling //... + - name: Build software targets + run: | + # Compile some selected targets + ./bazelisk.sh build \ + --build_tests_only=false \ + --//hw/top=darjeeling \ + //sw/device/tests/... + + qemu_smoketest: + name: QEMU smoketest + runs-on: + group: zerorisc-none + needs: quick_lint + if: ${{ github.event_name != 'merge_group' }} + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 + - name: Prepare environment + uses: ./.github/actions/prepare-env + - name: Execute QEMU smoketest + run: | + ./bazelisk.sh test //sw/device/tests:rom_exit_immediately_sim_qemu_base + + qemu_local_dev_test: + name: Test QEMU local development override + runs-on: ubuntu-22.04 + needs: quick_lint + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 + path: opentitan + - name: Prepare environment + uses: ./opentitan/.github/actions/prepare-env + with: + working-directory: opentitan + - uses: actions/checkout@v4 + with: + repository: lowRISC/qemu + ref: v9.2.0-2025-02-11 + fetch-depth: 0 + path: qemu + - name: Check that overrides works + run: | + # The following packages are required to build QEMU. + sudo apt-get install -y ninja-build libpixman-1-dev libglib2.0-dev + # We need to symlink the BUILD file and create an empty REPO file. + ln -s $PWD/opentitan/third_party/qemu/BUILD.qemu_opentitan.bazel qemu/BUILD.bazel + touch qemu/REPO.bazel + # Just make sure all expected targets are there after building. + opentitan/bazelisk.sh build --override_repository="+qemu+qemu_opentitan_src=$PWD/qemu/" //third_party/qemu/... + - name: Upload error logs + if: failure() + uses: actions/upload-artifact@v4 + with: + name: qemu-override-build-logs + path: qemu/build/*.log + + # We would like to gate PR on quick lint and merge queue on bitstream caching. + # GitHub requires a single job name to be used for branch protection rule, so we use 2 jobs with + # conditional names so the non-skipped ones woud be called "Merge blocker". + # + # TODO: Enable these once `cache_bitstreams` is re-enabled. + # + # merge_blocker_pr: + # name: Merge blocker${{ github.event_name != 'pull_request' && ' (skipped)' || '' }} + # runs-on: ubuntu-latest + # needs: quick_lint + # if: ${{ !cancelled() && github.event_name == 'pull_request' }} + # steps: + # - name: Complete + # run: ${{ needs.quick_lint.result == 'success' }} + # + # merge_blocker_merge: + # name: Merge blocker${{ github.event_name != 'merge_group' && ' (skipped)' || '' }} + # runs-on: ubuntu-latest + # needs: cache_bitstreams + # if: ${{ !cancelled() && github.event_name == 'merge_group' }} + # steps: + # - name: Complete + # run: ${{ needs.cache_bitstreams.result == 'success' }} + +# Hardware DV tests + dvsim-multitop: + name: Multitop quick DVSim tests + needs: quick_lint + uses: ./.github/workflows/dv-multitop.yml + secrets: inherit + with: + run-type: "quick" + item: "smoke" + priority: 10 + + dvsim-earlgrey: + name: Earlgrey quick DVSim tests + needs: quick_lint + uses: ./.github/workflows/dv-earlgrey.yml + secrets: inherit + with: + run-type: "quick" + item: "smoke" + priority: 10 + + dvsim-earlgrey-report: + name: Earlgrey quick DVSim report + needs: [dvsim-multitop, dvsim-earlgrey] + uses: ./.github/workflows/dv-report.yml + secrets: inherit + with: + run-type: "quick" + top-name: "earlgrey" + hjson: hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson + item: "smoke" + + dvsim-darjeeling: + name: Darjeeling quick DVSim tests + needs: quick_lint + uses: ./.github/workflows/dv-darjeeling.yml + secrets: inherit + with: + run-type: "quick" + item: "smoke" + priority: 10 + + dvsim-darjeeling-report: + name: Darjeeling quick DVSim report + needs: [dvsim-multitop, dvsim-darjeeling] + uses: ./.github/workflows/dv-report.yml + secrets: inherit + with: + run-type: "quick" + top-name: "darjeeling" + hjson: hw/top_darjeeling/dv/top_darjeeling_sim_cfgs.hjson + item: "smoke" diff --git a/BLOCKFILE b/BLOCKFILE index ba11f0f5059..9d5044a070d 100644 --- a/BLOCKFILE +++ b/BLOCKFILE @@ -46,7 +46,7 @@ hw/ip/i2c/rtl/* hw/ip/keymgr/rtl/* hw/ip/kmac/rtl/* hw/ip/lc_ctrl/rtl/* -hw/ip/otbn/rtl/* +hw/ip/acc/rtl/* hw/ip/otp_ctrl/rtl/* hw/ip/otp_macro/rtl/* hw/ip/pattgen/rtl/* @@ -86,7 +86,7 @@ hw/ip/hmac/data/hmac.hjson hw/ip/rv_dm/data/rv_dm.hjson hw/ip/kmac/data/kmac.hjson hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson -hw/ip/otbn/data/otbn.hjson +hw/ip/acc/data/acc.hjson hw/ip/otp_macro/data/otp_macro.hjson hw/ip/entropy_src/data/entropy_src.hjson hw/ip/aes/data/aes.hjson diff --git a/bench/collect_stats.sh b/bench/collect_stats.sh index f70d4f96bde..6af3319edcc 100755 --- a/bench/collect_stats.sh +++ b/bench/collect_stats.sh @@ -18,8 +18,8 @@ echo "./bazelisk.sh test $bzlpath" ./bazelisk.sh test $bzlpath # Collect the test logs for each target. -echo "Collecting logs for all otbn_autogen_sim_test targets..." -targets=$(./bazelisk.sh query "kind(otbn_autogen_sim_test, $bzlpath)") +echo "Collecting logs for all acc_autogen_sim_test targets..." +targets=$(./bazelisk.sh query "kind(acc_autogen_sim_test, $bzlpath)") for target in $targets do shortname=$(echo $target | cut -d ":" -f 2) @@ -29,7 +29,7 @@ do if grep -q "cycles" $logfile; then cp -f $logfile $statsfile else - echo "Target $shortname does not appear to include execution statistics. Is the 'stats' parameter set in the otbn_autogen_sim_test rule?" + echo "Target $shortname does not appear to include execution statistics. Is the 'stats' parameter set in the acc_autogen_sim_test rule?" exit 1 fi done diff --git a/ci/scripts/check_dv_sw_images.py b/ci/scripts/check_dv_sw_images.py index aa289a977ec..60d6cf2f017 100755 --- a/ci/scripts/check_dv_sw_images.py +++ b/ci/scripts/check_dv_sw_images.py @@ -26,7 +26,7 @@ class SwType(Enum): ROM = 0 # Ibex SW - first stage boot ROM. TEST_SLOT_A = 1 # Ibex SW - test SW in (flash) slot A. TEST_SLOT_B = 2 # Ibex SW - test SW in (flash) slot B. - OTBN = 3 # Otbn SW + ACC = 3 # Acc SW OTP = 4 # Customized OTP image DEBUG = 5 # Debug SW - injected into SRAM. diff --git a/ci/scripts/mypy.sh b/ci/scripts/mypy.sh index 50bf9c305b4..950970220fd 100755 --- a/ci/scripts/mypy.sh +++ b/ci/scripts/mypy.sh @@ -8,9 +8,9 @@ set -e dirs_with_lint_makefile=( - hw/ip/otbn/dv/rig - hw/ip/otbn/dv/otbnsim - hw/ip/otbn/util + hw/ip/acc/dv/rig + hw/ip/acc/dv/accsim + hw/ip/acc/util hw/ip/rom_ctrl/util util/reggen ) diff --git a/ci/scripts/run-verilator-tests.sh b/ci/scripts/run-verilator-tests.sh index ebefcdd6d0f..eac0b3b88b7 100755 --- a/ci/scripts/run-verilator-tests.sh +++ b/ci/scripts/run-verilator-tests.sh @@ -19,8 +19,8 @@ set -e //sw/device/tests:aes_smoketest_sim_verilator \ //sw/device/tests:uart_smoketest_sim_verilator \ //sw/device/tests:crt_test_sim_verilator \ - //sw/device/tests:otbn_randomness_test_sim_verilator \ - //sw/device/tests:otbn_irq_test_sim_verilator \ + //sw/device/tests:acc_randomness_test_sim_verilator \ + //sw/device/tests:acc_irq_test_sim_verilator \ //sw/device/tests:kmac_mode_cshake_test_sim_verilator \ //sw/device/tests:kmac_mode_kmac_test_sim_verilator \ //sw/device/tests:flash_ctrl_test_sim_verilator \ diff --git a/hw/BUILD b/hw/BUILD index 600fa80dac0..a1119f29fe2 100644 --- a/hw/BUILD +++ b/hw/BUILD @@ -99,7 +99,7 @@ fusesoc_build( cores = [ ":cores", ], - data = ["//hw/ip/otbn:rtl_files"], + data = ["//hw/ip/acc:rtl_files"], make_options = ":make_options", output_groups = opentitan_select_top_attr("top_verilator_binary"), systems = opentitan_select_top_attr("top_verilator_core"), diff --git a/hw/Makefile b/hw/Makefile index 34dc545fc5f..7fc6d3a498b 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -33,7 +33,7 @@ IPS ?= aes \ kmac \ lc_ctrl \ mbx \ - otbn \ + acc \ otp_macro \ pattgen \ pwm \ diff --git a/hw/bitstream/vivado/BUILD b/hw/bitstream/vivado/BUILD index f8a7c9c66ef..4cb00c1ea17 100644 --- a/hw/bitstream/vivado/BUILD +++ b/hw/bitstream/vivado/BUILD @@ -46,7 +46,7 @@ fusesoc_build( _OTP_RMA, ], cores = ["//hw:cores"], - data = ["//hw/ip/otbn:rtl_files"], + data = ["//hw/ip/acc:rtl_files"], flags = [ "--BootRomInitFile=" + _CW310_TESTROM_PATH, "--OtpMacroMemInitFile=" + _OTP_RMA_PATH, @@ -87,7 +87,7 @@ fusesoc_build( _OTP_RMA, ], cores = ["//hw:cores"], - data = ["//hw/ip/otbn:rtl_files"], + data = ["//hw/ip/acc:rtl_files"], flags = [ "--BootRomInitFile=" + _CW310_TESTROM_PATH, "--OtpMacroMemInitFile=" + _OTP_RMA_PATH, @@ -128,7 +128,7 @@ fusesoc_build( _OTP_RMA, ], cores = ["//hw:cores"], - data = ["//hw/ip/otbn:rtl_files"], + data = ["//hw/ip/acc:rtl_files"], flags = [ "--BootRomInitFile=" + _CW340_TESTROM_PATH, "--OtpMacroMemInitFile=" + _OTP_RMA_PATH, diff --git a/hw/doc/cores.md b/hw/doc/cores.md index 68b5a62e9fd..dcbe1368d5c 100644 --- a/hw/doc/cores.md +++ b/hw/doc/cores.md @@ -4,6 +4,6 @@ Cores in OpenTitan are processing units that can run programs. Currently, there are two cores in OpenTitan: * [Ibex](../top_earlgrey/ip_autogen/rv_core_ibex/README.md) (RV32IMCB) -* [OTBN](../ip/otbn/README.md) (programmable coprocessor for asymmetric cryptographic algorithms, 256-bit datapath) +* [ACC](../ip/acc/README.md) (programmable coprocessor for asymmetric cryptographic algorithms, 256-bit datapath) Since cores are the interface between hardware and software, please also consult the [software resources](../../sw/README.md). diff --git a/hw/dv/sv/kmac_app_agent/kmac_app_agent_pkg.sv b/hw/dv/sv/kmac_app_agent/kmac_app_agent_pkg.sv index 9e763b6ddc8..a83e36e7ca7 100644 --- a/hw/dv/sv/kmac_app_agent/kmac_app_agent_pkg.sv +++ b/hw/dv/sv/kmac_app_agent/kmac_app_agent_pkg.sv @@ -24,7 +24,7 @@ package kmac_app_agent_pkg; AppKeymgr, AppLc, AppRom, - AppOtbn + AppAcc } kmac_app_e; // Create enum to determine size for NUM_APP_INTF diff --git a/hw/dv/sv/kmac_app_agent/kmac_app_intf.sv b/hw/dv/sv/kmac_app_agent/kmac_app_intf.sv index ec23c17093b..35ba003de59 100644 --- a/hw/dv/sv/kmac_app_agent/kmac_app_intf.sv +++ b/hw/dv/sv/kmac_app_agent/kmac_app_intf.sv @@ -29,7 +29,7 @@ interface kmac_app_intf (input clk, input rst_n); wire hold_tmp; logic next_d; logic hold_d; - logic otbn_start_d, otbn_start; + logic acc_start_d, acc_start; logic [3:0] per_ctr_d, per_ctr; logic [3:0] max_per; @@ -42,9 +42,9 @@ interface kmac_app_intf (input clk, input rst_n); StStart, StWait, StNext - } otbn_state_e; + } acc_state_e; - otbn_state_e otbn_state_d, otbn_state; + acc_state_e acc_state_d, acc_state; // all the host pins are handled by push_pull driver, only include clk and rst here clocking host_cb @(posedge clk); @@ -85,12 +85,12 @@ interface kmac_app_intf (input clk, input rst_n); // The following fsm is temporary for driving next/hold in the interface // It should be removed once the restructuring of the sequencer/driver is complete - // Hold is asserted 1'b1 at the start of the OTBN app req and returns to 1'b0 after last rsp + // Hold is asserted 1'b1 at the start of the ACC app req and returns to 1'b0 after last rsp // Hold is asserted 1'b0 on the cycle immediately following last rsp_done // Combinational decode of the state always_comb begin - otbn_state_d = otbn_state; - otbn_start_d = otbn_start; + acc_state_d = acc_state; + acc_start_d = acc_start; // Set next/hold default hold_d = 1'b0; @@ -99,12 +99,12 @@ interface kmac_app_intf (input clk, input rst_n); // Default the counters per_ctr_d = '0; - unique case (otbn_state) + unique case (acc_state) // Set hold at start of req StIdle: begin - if (otbn_start) begin - otbn_state_d = StWait; + if (acc_start) begin + acc_state_d = StWait; hold_d = 1'b1; end end @@ -112,11 +112,11 @@ interface kmac_app_intf (input clk, input rst_n); // Wait until first rsp to determine if more are needed // Counters are constrained in kmac_app_host_seq StWait: begin - if (otbn_start) begin + if (acc_start) begin hold_d = 1'b1; per_ctr_d = per_ctr; if (rsp_done == 1'b1) begin - otbn_state_d = StNext; + acc_state_d = StNext; per_ctr_d = per_ctr + 1'b1; if ((per_ctr + 1) < max_per) begin next_d = 1'b1; @@ -130,18 +130,18 @@ interface kmac_app_intf (input clk, input rst_n); // Next should only be high for a single clock cycle // If response has reached total word len end FSM cycle StNext: begin - if (otbn_start) begin + if (acc_start) begin hold_d = 1'b1; next_d = 1'b0; per_ctr_d = per_ctr; if (per_ctr == max_per) begin - otbn_state_d = StIdle; - otbn_start_d = 1'b0; + acc_state_d = StIdle; + acc_start_d = 1'b0; per_ctr_d = '0; hold_d = 1'b0; end else begin if (rsp_done == 1'b0) begin - otbn_state_d = StWait; + acc_state_d = StWait; end end end @@ -155,17 +155,17 @@ interface kmac_app_intf (input clk, input rst_n); // Register the state always_ff @(posedge clk) begin if (!rst_n) begin - otbn_state <= StIdle; + acc_state <= StIdle; hold <= 1'b0; next <= 1'b0; per_ctr <= 1'b0; - otbn_start <= 1'b0; + acc_start <= 1'b0; end else begin - otbn_state <= otbn_state_d; + acc_state <= acc_state_d; hold <= hold_d; next <= next_d; per_ctr <= per_ctr_d; - otbn_start <= otbn_start_d; + acc_start <= acc_start_d; end end diff --git a/hw/dv/sv/kmac_app_agent/seq_lib/kmac_app_host_seq.sv b/hw/dv/sv/kmac_app_agent/seq_lib/kmac_app_host_seq.sv index 0aecdc719df..b88bb38b5a5 100644 --- a/hw/dv/sv/kmac_app_agent/seq_lib/kmac_app_host_seq.sv +++ b/hw/dv/sv/kmac_app_agent/seq_lib/kmac_app_host_seq.sv @@ -50,7 +50,7 @@ class kmac_app_host_seq extends kmac_app_base_seq; endfunction - // Send the OTBN-specific header word + // Send the ACC-specific header word virtual task send_header(); // Create the CFG msg req with only first byte valid @@ -82,9 +82,9 @@ class kmac_app_host_seq extends kmac_app_base_seq; init_msg_size_bytes = msg_size_bytes; - // If mode is OTBN send CFG - if (mode == AppOtbn) begin - cfg.vif.otbn_start = 1'b1; + // If mode is ACC send CFG + if (mode == AppAcc) begin + cfg.vif.acc_start = 1'b1; cfg.vif.max_per = max_digest_word; send_header(); end diff --git a/hw/formal/tools/vcformal/fpv.tcl b/hw/formal/tools/vcformal/fpv.tcl index 145cb1e8ee4..e449a7931e2 100644 --- a/hw/formal/tools/vcformal/fpv.tcl +++ b/hw/formal/tools/vcformal/fpv.tcl @@ -135,7 +135,7 @@ if {$env(DUT_TOP) == "aes"} { create_reset rst_ni -sense low create_clock clk_edn_i -period 100 create_reset rst_edn_ni -sense low -} elseif {$env(DUT_TOP) == "otbn"} { +} elseif {$env(DUT_TOP) == "acc"} { create_clock clk_i -period 100 create_reset rst_ni -sense low create_clock clk_edn_i -period 100 diff --git a/hw/ip/BUILD b/hw/ip/BUILD index b527f0870b1..547f6f74a18 100644 --- a/hw/ip/BUILD +++ b/hw/ip/BUILD @@ -14,6 +14,7 @@ filegroup( "*/README.md", ], ) + [ + "//hw/ip/acc:rtl_files", "//hw/ip/adc_ctrl:rtl_files", "//hw/ip/aes:rtl_files", "//hw/ip/aon_timer:rtl_files", @@ -28,7 +29,6 @@ filegroup( "//hw/ip/kmac:rtl_files", "//hw/ip/lc_ctrl:rtl_files", "//hw/ip/mbx:rtl_files", - "//hw/ip/otbn:rtl_files", "//hw/ip/otp_ctrl:rtl_files", "//hw/ip/otp_macro:rtl_files", "//hw/ip/pattgen:rtl_files", @@ -61,6 +61,7 @@ filegroup( filegroup( name = "doc_files", srcs = glob(["**/*.md"]) + [ + "//hw/ip/acc:doc_files", "//hw/ip/adc_ctrl:doc_files", "//hw/ip/aes:doc_files", "//hw/ip/aon_timer:doc_files", @@ -76,7 +77,6 @@ filegroup( "//hw/ip/kmac:doc_files", "//hw/ip/lc_ctrl:doc_files", "//hw/ip/mbx:doc_files", - "//hw/ip/otbn:doc_files", "//hw/ip/pattgen:doc_files", "//hw/ip/prim:doc_files", "//hw/ip/rom_ctrl:doc_files", diff --git a/hw/ip/README.md b/hw/ip/README.md index 9b5acdaa23d..78a9f231015 100644 --- a/hw/ip/README.md +++ b/hw/ip/README.md @@ -4,6 +4,7 @@ | HW Block | Brief Summary | |------------------|-----------------------------------------------------------------------------------------------------------------------------------| +| [`acc`] | Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures | | [`adc_ctrl`] | Low-power controller for a dual-channel ADC with filtering and debouncing capability | | [`aes`] | AES encryption and decryption engine with SCA and FI countermeasures | | [`aon_timer`] | Wakeup and watchdog timers running on a low-power, always-on clock | @@ -19,7 +20,6 @@ | [`kmac`] | Accelerator for Keccak-based keyed hash message authentication code and SHA-3 hash functions; with SCA and FI countermeasures | | [`lc_ctrl`] | Manages device life cycle states and transitions, and controls key manager, flash, OTP, and debug access | | [`mbx`] | DOE mailbox for use as an integrated OpenTitan communication channel. | -| [`otbn`] | Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures | | [`otp_macro`] | OTP macro simulation model and CSR block | | [`pattgen`] | Transmission of short time-dependent data patterns on two clock-parallel output channels | | [`rom_ctrl`] | Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset | @@ -36,6 +36,7 @@ +[`acc`]: ./acc/README.md [`adc_ctrl`]: ./adc_ctrl/README.md [`aes`]: ./aes/README.md [`aon_timer`]: ./aon_timer/README.md @@ -51,7 +52,6 @@ [`kmac`]: ./kmac/README.md [`lc_ctrl`]: ./lc_ctrl/README.md [`mbx`]: ./mbx/README.md -[`otbn`]: ./otbn/README.md [`otp_macro`]: ./otp_macro/README.md [`pattgen`]: ./pattgen/README.md [`rom_ctrl`]: ./rom_ctrl/README.md diff --git a/hw/ip/otbn/.flake8 b/hw/ip/acc/.flake8 similarity index 100% rename from hw/ip/otbn/.flake8 rename to hw/ip/acc/.flake8 diff --git a/hw/ip/otbn/BUILD b/hw/ip/acc/BUILD similarity index 86% rename from hw/ip/otbn/BUILD rename to hw/ip/acc/BUILD index 196399fb04b..f84a16a2e44 100644 --- a/hw/ip/otbn/BUILD +++ b/hw/ip/acc/BUILD @@ -14,7 +14,7 @@ filegroup( "README.md", ], ) + [ - "//hw/ip/otbn/data:all_files", + "//hw/ip/acc/data:all_files", ], ) @@ -24,6 +24,6 @@ filegroup( "**/*.md", "**/*.svg", ]) + [ - "//hw/ip/otbn/dv/otbnsim:doc_files", + "//hw/ip/acc/dv/accsim:doc_files", ], ) diff --git a/hw/ip/otbn/README.md b/hw/ip/acc/README.md similarity index 72% rename from hw/ip/otbn/README.md rename to hw/ip/acc/README.md index 94506869248..bfd297cd481 100644 --- a/hw/ip/otbn/README.md +++ b/hw/ip/acc/README.md @@ -1,22 +1,17 @@ -# OpenTitan Big Number Accelerator (OTBN) Technical Specification +# Asymmetric Cryptographic Coprocessor (ACC) Technical Specification -[`otbn`](https://reports.opentitan.org/hw/ip/otbn/dv/uvm/latest/report.html): -![](https://dashboards.lowrisc.org/badges/dv/otbn/test.svg) -![](https://dashboards.lowrisc.org/badges/dv/otbn/passing.svg) -![](https://dashboards.lowrisc.org/badges/dv/otbn/functional.svg) -![](https://dashboards.lowrisc.org/badges/dv/otbn/code.svg) # Overview -This document specifies functionality of the OpenTitan Big Number Accelerator, or OTBN. -OTBN is a coprocessor for asymmetric cryptographic operations like RSA or Elliptic Curve Cryptography (ECC). +This document specifies functionality of the Asymmetric Cryptographic Coprocessor, or ACC. +ACC is a fork from the OpenTitan Bignum Accelerator (OTBN). -This module conforms to the [Comportable guideline for peripheral functionality](../../../doc/contributing/hw/comportability/README.md). -See that document for integration overview within the broader top level system. +ACC follows the [comportability guidelines for peripheral functionality](../../../doc/contributing/hw/comportability/README.md). +Refer to the guidelines for an integration overview within a broader top level system. ## Features -* Processor optimized for wide integer arithmetic +* Processor optimized for wide integer and vector arithmetic * 32b wide control path with 32 32b wide registers * 256b wide data path with 32 256b wide registers * Full control-flow support with conditional branch and unconditional jump instructions, hardware loops, and hardware-managed call/return stacks. @@ -25,30 +20,31 @@ See that document for integration overview within the broader top level system. ## Description -OTBN is a processor, specialized for the execution of security-sensitive asymmetric (public-key) cryptography code, such as RSA or ECC. -Such algorithms are dominated by wide integer arithmetic, which are supported by OTBN's 256b wide data path, registers, and instructions which operate these wide data words. +ACC is a processor, specialized for the execution of security-sensitive asymmetric (public-key) cryptography code, such as RSA or ECC. +Such algorithms are dominated by wide integer arithmetic, which are supported by ACC's 256b wide data path, registers, and instructions which operate these wide data words. On the other hand, the control flow is clearly separated from the data, and reduced to a minimum to avoid data leakage. -The data OTBN processes is security-sensitive, and the processor design centers around that. +The data ACC processes is security-sensitive, and the processor design centers around that. The design is kept as simple as possible to reduce the attack surface and aid verification and testing. For example, no interrupts or exceptions are included in the design, and all instructions are designed to be executable within a single cycle. -OTBN is designed as a self-contained co-processor with its own instruction and data memory, which is accessible as a bus device. +ACC is designed as a self-contained co-processor with its own instruction and data memory, which is accessible as a bus device. ## Compatibility -OTBN is not designed to be compatible with other cryptographic accelerators. -It received some inspiration from assembly code available from the [Chromium EC project](https://chromium.googlesource.com/chromiumos/platform/ec/), +ACC is not designed to be compatible with other cryptographic accelerators, with the only exception being [KMAC](../kmac/README.md). +There is a custom interface connection between KMAC and ACC for accelerating hash based post quantum cryptographic algorithms. +ACC received some inspiration from assembly code available from the [Chromium EC project](https://chromium.googlesource.com/chromiumos/platform/ec/), which has been formally verified within the [Fiat Crypto project](http://adam.chlipala.net/papers/FiatCryptoSP19/FiatCryptoSP19.pdf). # Instruction Set -OTBN is a processor with a custom instruction set. +ACC is a processor with a custom instruction set. The full ISA description can be found in our [ISA manual](./doc/isa.md). The instruction set is split into two groups: * The **base instruction subset** operates on the 32b General Purpose Registers (GPRs). - Its instructions are used for the control flow of a OTBN application. + Its instructions are used for the control flow of an ACC application. The base instructions are inspired by RISC-V's RV32I instruction set, but not compatible with it. * The **big number instruction subset** operates on 256b Wide Data Registers (WDRs). Its instructions are used for data processing. @@ -57,7 +53,7 @@ The instruction set is split into two groups: ### General Purpose Registers (GPRs) -OTBN has 32 General Purpose Registers (GPRs), each of which is 32b wide. +ACC has 32 General Purpose Registers (GPRs), each of which is 32b wide. The GPRs are defined in line with RV32I and are mainly used for control flow. They are accessed through the base instruction subset. GPRs aren't used by the main data path; this operates on the [Wide Data Registers](#wide-data-registers-wdrs), a separate register file, controlled by the big number instructions. @@ -81,16 +77,16 @@ Access to the [call stack](#call-stack) -Note: Currently, OTBN has no "standard calling convention," and GPRs other than `x0` and `x1` can be used for any purpose. +Note: Currently, ACC has no "standard calling convention," and GPRs other than `x0` and `x1` can be used for any purpose. If a calling convention is needed at some point, it is expected to be aligned with the RISC-V standard calling conventions, and the roles assigned to registers in that convention. Even without a agreed-on calling convention, software authors are encouraged to follow the RISC-V calling convention where it makes sense. For example, good choices for temporary registers are `x6`, `x7`, `x28`, `x29`, `x30`, and `x31`. ### Call Stack -OTBN has an in-built call stack which is accessed through the `x1` GPR. +ACC has a built-in call stack which is accessed through the `x1` GPR. This is intended to be used as a return address stack, containing return addresses for the current stack of function calls. -See the documentation for {{#otbn-insn-ref JAL}} and {{#otbn-insn-ref JALR}} for a description of how to use it for this purpose. +See the documentation for {{#acc-insn-ref JAL}} and {{#acc-insn-ref JALR}} for a description of how to use it for this purpose. The call stack has a maximum depth of 8 elements. Each instruction that reads from `x1` pops a single element from the stack. @@ -105,13 +101,13 @@ Providing the stack has at least one element, this is allowed, even if the stack Control and Status Registers (CSRs) are 32b wide registers used for "special" purposes, as detailed in their description; they are not related to the GPRs. -CSRs can be accessed through dedicated instructions, {{#otbn-insn-ref CSRRS}} and {{#otbn-insn-ref CSRRW}}. +CSRs can be accessed through dedicated instructions, {{#acc-insn-ref CSRRS}} and {{#acc-insn-ref CSRRW}}. Writes to read-only (RO) registers are ignored; they do not signal an error. -All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is written to [`CMD.start`](doc/registers.md#cmd)). +All read-write (RW) CSRs are set to 0 when ACC starts an operation (when 1 is written to [`CMD.start`](doc/registers.md#cmd)). - - + @@ -194,7 +190,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -203,7 +199,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -212,7 +208,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -221,7 +217,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -230,7 +226,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -239,7 +235,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -248,7 +244,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -257,7 +253,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -317,7 +313,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w Primarily intended to be used for key generation.
The number is sourced from the EDN via a single-entry cache. - Reads when the cache is empty will cause OTBN to be stalled until a new random number is fetched from the EDN. + Reads when the cache is empty will cause ACC to be stalled until a new random number is fetched from the EDN. @@ -340,7 +336,7 @@ All read-write (RW) CSRs are set to 0 when OTBN starts an operation (when 1 is w ### Wide Data Registers (WDRs) -In addition to the 32b wide GPRs, OTBN has a second "wide" register file, which is used by the big number instruction subset. +In addition to the 32b wide GPRs, ACC has a second "wide" register file, which is used by the big number instruction subset. This register file consists of NWDR = 32 Wide Data Registers (WDRs). Each WDR is WLEN = 256b wide. @@ -357,15 +353,15 @@ GPRs are accessible from the base instruction subset, and WDRs are accessible fr ### Wide Special Purpose Registers (WSRs) -OTBN has 256b Wide Special purpose Registers (WSRs). +ACC has 256b Wide Special purpose Registers (WSRs). These are analogous to the 32b CSRs, but are used by big number instructions. -They can be accessed with the {{#otbn-insn-ref BN.WSRR}} and {{#otbn-insn-ref BN.WSRW}} instructions. +They can be accessed with the {{#acc-insn-ref BN.WSRR}} and {{#acc-insn-ref BN.WSRW}} instructions. Writes to read-only (RO) registers are ignored; they do not signal an error. -All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is written to [`CMD.start`](doc/registers.md#cmd)). +All read-write (RW) WSRs are set to 0 when ACC starts an operation (when 1 is written to [`CMD.start`](doc/registers.md#cmd)). - - +
RW MOD0 - Bits [31:0] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [31:0] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
RW MOD1 - Bits [63:32] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [63:32] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
RW MOD2 - Bits [95:64] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [95:64] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
RW MOD3 - Bits [127:96] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [127:96] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
RW MOD4 - Bits [159:128] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [159:128] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
RW MOD5 - Bits [191:160] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [191:160] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
RW MOD6 - Bits [223:192] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [223:192] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
RW MOD7 - Bits [255:224] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [255:224] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR.
@@ -381,7 +377,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -394,7 +390,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w Primarily intended to be used for key generation.
The number is sourced from the EDN via a single-entry cache. - Reads when the cache is empty will cause OTBN to be stalled until a new random number is fetched from the EDN. + Reads when the cache is empty will cause ACC to be stalled until a new random number is fetched from the EDN. @@ -415,7 +411,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -423,7 +419,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -431,7 +427,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -442,7 +438,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -452,7 +448,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -463,7 +459,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w @@ -501,7 +497,7 @@ All read-write (RW) WSRs are set to 0 when OTBN starts an operation (when 1 is w ### Flags -In addition to the wide register file, OTBN maintains global state in two groups of flags for the use by wide integer operations. +In addition to the wide register file, ACC maintains global state in two groups of flags for the use by wide integer operations. Flag groups are named Flag Group 0 (`FG0`), and Flag Group 1 (`FG1`). Each group consists of four flags. Each flag is a single bit. @@ -522,31 +518,31 @@ The `M`, `L`, and `Z` flags are determined based on the result of the operation ### Loop Stack -OTBN has two instructions for hardware-assisted loops: {{#otbn-insn-ref LOOP}} and {{#otbn-insn-ref LOOPI}}. +ACC has two instructions for hardware-assisted loops: {{#acc-insn-ref LOOP}} and {{#acc-insn-ref LOOPI}}. Both use the same state for tracking control flow. This is a stack of tuples containing a loop count, start address and end address. The stack has a maximum depth of eight and the top of the stack is the current loop. # Security Features -OTBN is a security co-processor. +ACC is a security co-processor. It contains various security features and is hardened against side-channel analysis and fault injection attacks. -The following sections describe the high-level security features of OTBN. +The following sections describe the high-level security features of ACC. Refer to the [Design Details](#design-details) section for a more in-depth description. ## Data Integrity Protection -OTBN's data integrity protection is designed to protect the data stored and processed within OTBN from modifications through physical attacks. +ACC's data integrity protection is designed to protect the data stored and processed within ACC from modifications through physical attacks. -Data in OTBN travels along a data path which includes the data memory (DMEM), the load-store-unit (LSU), the register files (GPR and WDR), and the execution units. -Whenever possible, data transmitted or stored within OTBN is protected with an integrity protection code which guarantees the detection of at least three modified bits per 32 bit word. +Data in ACC travels along a data path which includes the data memory (DMEM), the load-store-unit (LSU), the register files (GPR and WDR), and the execution units. +Whenever possible, data transmitted or stored within ACC is protected with an integrity protection code which guarantees the detection of at least three modified bits per 32 bit word. Additionally, instructions and data stored in the instruction and data memory, respectively, are scrambled with a lightweight, non-cryptographically-secure cipher. Refer to the [Data Integrity Protection](./doc/theory_of_operation.md#data-integrity-protection) section for details of how the data integrity protections are implemented. ## Secure Wipe -OTBN provides a mechanism to securely wipe all state it stores, including the instruction memory. +ACC provides a mechanism to securely wipe all state it stores, including the instruction memory. The full secure wipe mechanism is split into three parts: - [Data memory secure wipe](./doc/theory_of_operation.md#data-memory-dmem-secure-wipe) @@ -556,8 +552,8 @@ The full secure wipe mechanism is split into three parts: A secure wipe is performed automatically in certain situations, or can be requested manually by the host software. The full secure wipe is automatically initiated as a local reaction to a fatal error. In addition, it can be triggered by the [Life Cycle Controller](../lc_ctrl/README.md) before RMA entry using the `lc_rma_req/ack` interface. -In both cases OTBN enters the locked state afterwards and needs to be reset. -A secure wipe of only the internal state is performed after reset, whenever an OTBN operation is complete, and after a recoverable error. +In both cases ACC enters the locked state afterwards and needs to be reset. +A secure wipe of only the internal state is performed after reset, whenever an ACC operation is complete, and after a recoverable error. Finally, host software can manually trigger the data memory and instruction memory secure wipe operations by issuing an appropriate [command](./doc/theory_of_operation.md#operations-and-commands). @@ -565,29 +561,29 @@ Refer to the [Secure Wipe](./doc/theory_of_operation.md#secure-wipe) section for ## Instruction Counter -In order to detect and mitigate fault injection attacks on the OTBN, the host CPU can read the number of executed instructions from [`INSN_CNT`](doc/registers.md#insn_cnt) and verify whether it matches the expectation. -The host CPU can clear the instruction counter when OTBN is not running. +In order to detect and mitigate fault injection attacks on the ACC, the host CPU can read the number of executed instructions from [`INSN_CNT`](doc/registers.md#insn_cnt) and verify whether it matches the expectation. +The host CPU can clear the instruction counter when ACC is not running. Writing any value to [`INSN_CNT`](doc/registers.md#insn_cnt) clears this register to zero. -Write attempts while OTBN is running are ignored. +Write attempts while ACC is running are ignored. ## Key Sideloading -OTBN software can make use of a single 384b wide key provided by the [Key Manager](../keymgr/README.md), which is made available in two shares. -The key is passed through a dedicated connection between the Key Manager and OTBN to avoid exposing it to other components. +ACC software can make use of a single 384b wide key provided by the [Key Manager](../keymgr/README.md), which is made available in two shares. +The key is passed through a dedicated connection between the Key Manager and ACC to avoid exposing it to other components. Software can access the first share of the key through the [`KEY_S0_L`](#key-s0-l) and [`KEY_S0_H`](#key-s0-h) WSRs, and the second share of the key through the [`KEY_S1_L`](#key-s1-l) and [`KEY_S1_H`](#key-s1-h) WSRs. -It is up to host software to configure the Key Manager so that it provides the right key to OTBN at the start of the operation, and to remove the key again once the operation on OTBN has completed. -A `KEY_INVALID` software error is raised if OTBN software accesses any of the `KEY_*` WSRs when the Key Manager has not presented a key. +It is up to host software to configure the Key Manager so that it provides the right key to ACC at the start of the operation, and to remove the key again once the operation on ACC has completed. +A `KEY_INVALID` software error is raised if ACC software accesses any of the `KEY_*` WSRs when the Key Manager has not presented a key. ## Blanking -To reduce side channel leakage OTBN employs a blanking technique on certain control and data paths. +To reduce side channel leakage ACC employs a blanking technique on certain control and data paths. When a path is blanked it is forced to 0 (by ANDing the path with a blanking signal) preventing sensitive data bits producing a power signature via that path where that path isn't needed for the current instruction. Blanking controls all come directly from flops to prevent glitches in decode logic reducing the effectiveness of the blanking. These control signals are determined in the [prefetch stage](#instruction-prefetch) via pre-decode logic. Full decoding is still performed in the execution stage with the full decode results checked against the pre-decode blanking control. -If the full decode disagrees with the pre-decode OTBN raises a `BAD_INTERNAL_STATE` fatal error. +If the full decode disagrees with the pre-decode ACC raises a `BAD_INTERNAL_STATE` fatal error. Blanking is applied in the following locations: diff --git a/hw/ip/otbn/otbn.core b/hw/ip/acc/acc.core similarity index 70% rename from hw/ip/otbn/otbn.core rename to hw/ip/acc/acc.core index 5929892d76d..924cc06b36a 100644 --- a/hw/ip/otbn/otbn.core +++ b/hw/ip/acc/acc.core @@ -3,8 +3,8 @@ CAPI=2: # Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:otbn:0.1" -description: "OpenTitan Big Number Accelerator (OTBN)" +name: "lowrisc:ip:acc:0.1" +description: "OpenTitan Big Number Accelerator (ACC)" filesets: files_rtl_core: @@ -22,31 +22,31 @@ filesets: - lowrisc:ip:keymgr_pkg - lowrisc:ip:edn_pkg - lowrisc:ip:kmac_pkg - - lowrisc:ip:otbn_pkg + - lowrisc:ip:acc_pkg - lowrisc:prim:onehot_check files: - - rtl/otbn_controller.sv - - rtl/otbn_decoder.sv - - rtl/otbn_predecode.sv - - rtl/otbn_instruction_fetch.sv - - rtl/otbn_rf_base.sv - - rtl/otbn_rf_bignum.sv - - rtl/otbn_rf_base_ff.sv - - rtl/otbn_rf_bignum_ff.sv - - rtl/otbn_rf_base_fpga.sv - - rtl/otbn_rf_bignum_fpga.sv - - rtl/otbn_lsu.sv - - rtl/otbn_alu_base.sv - - rtl/otbn_alu_bignum.sv - - rtl/otbn_mac_bignum.sv + - rtl/acc_controller.sv + - rtl/acc_decoder.sv + - rtl/acc_predecode.sv + - rtl/acc_instruction_fetch.sv + - rtl/acc_rf_base.sv + - rtl/acc_rf_bignum.sv + - rtl/acc_rf_base_ff.sv + - rtl/acc_rf_bignum_ff.sv + - rtl/acc_rf_base_fpga.sv + - rtl/acc_rf_bignum_fpga.sv + - rtl/acc_lsu.sv + - rtl/acc_alu_base.sv + - rtl/acc_alu_bignum.sv + - rtl/acc_mac_bignum.sv - rtl/bn_vec_core/unified_mul.sv - - rtl/bn_vec_core/otbn_bignum_mul.sv + - rtl/bn_vec_core/acc_bignum_mul.sv - rtl/bn_vec_core/buffer_bit.sv - - rtl/otbn_loop_controller.sv - - rtl/otbn_stack.sv - - rtl/otbn_rnd.sv - - rtl/otbn_start_stop_control.sv - - rtl/otbn_core.sv + - rtl/acc_loop_controller.sv + - rtl/acc_stack.sv + - rtl/acc_rnd.sv + - rtl/acc_start_stop_control.sv + - rtl/acc_core.sv file_type: systemVerilogSource files_rtl_top: @@ -59,12 +59,12 @@ filesets: - lowrisc:prim:lc_sync - lowrisc:ip:edn_pkg - lowrisc:prim:edn_req - - lowrisc:ip:otbn_pkg + - lowrisc:ip:acc_pkg - lowrisc:ip:otp_ctrl_pkg files: - - rtl/otbn_reg_top.sv - - rtl/otbn_scramble_ctrl.sv - - rtl/otbn.sv + - rtl/acc_reg_top.sv + - rtl/acc_scramble_ctrl.sv + - rtl/acc.sv file_type: systemVerilogSource files_verilator_waiver: @@ -73,7 +73,7 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable files: - - lint/otbn.vlt + - lint/acc.vlt file_type: vlt files_ascentlint_waiver: @@ -82,7 +82,7 @@ filesets: - lowrisc:lint:common - lowrisc:lint:comportable files: - - lint/otbn.waiver + - lint/acc.waiver file_type: waiver parameters: @@ -97,7 +97,7 @@ targets: - tool_ascentlint ? (files_ascentlint_waiver) - files_rtl_core - files_rtl_top - toplevel: otbn + toplevel: acc lint: <<: *default_target @@ -113,7 +113,7 @@ targets: lint-core: filesets: - files_rtl_core - toplevel: otbn_core + toplevel: acc_core default_tool: verilator parameters: - SYNTHESIS=true diff --git a/hw/ip/otbn/otbn_pkg.core b/hw/ip/acc/acc_pkg.core similarity index 75% rename from hw/ip/otbn/otbn_pkg.core rename to hw/ip/acc/acc_pkg.core index 5fe055107af..3dcdf755192 100644 --- a/hw/ip/otbn/otbn_pkg.core +++ b/hw/ip/acc/acc_pkg.core @@ -2,8 +2,8 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:otbn_pkg:0.1" -description: "Constants used by OTBN" +name: "lowrisc:ip:acc_pkg:0.1" +description: "Constants used by ACC" filesets: files_pkg: @@ -11,8 +11,8 @@ filesets: - lowrisc:prim:assert - lowrisc:ip:otp_ctrl_pkg files: - - rtl/otbn_reg_pkg.sv - - rtl/otbn_pkg.sv + - rtl/acc_reg_pkg.sv + - rtl/acc_pkg.sv file_type: systemVerilogSource targets: diff --git a/hw/ip/otbn/data/BUILD b/hw/ip/acc/data/BUILD similarity index 100% rename from hw/ip/otbn/data/BUILD rename to hw/ip/acc/data/BUILD diff --git a/hw/ip/otbn/data/otbn.hjson b/hw/ip/acc/data/acc.hjson similarity index 83% rename from hw/ip/otbn/data/otbn.hjson rename to hw/ip/acc/data/acc.hjson index 47adee42c14..dd8fcb3349f 100644 --- a/hw/ip/otbn/data/otbn.hjson +++ b/hw/ip/acc/data/acc.hjson @@ -4,17 +4,17 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192) // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors { - name: "otbn", + name: "acc", human_name: "OpenTitan Big Number Accelerator", one_line_desc: "Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures", one_paragraph_desc: ''' - OpenTitan Big Number Accelerator (OTBN) is a programmable coprocessor for asymmetric cryptographic algorithms such as RSA or elliptic curve cryptography (ECC). - Such algorithms are dominated by wide integer arithmetic, which are executed on OTBN's 256-bit-wide data path. - The data OTBN processes is often security sensitive, and OTBN is designed to reduce the attack surface by + OpenTitan Big Number Accelerator (ACC) is a programmable coprocessor for asymmetric cryptographic algorithms such as RSA or elliptic curve cryptography (ECC). + Such algorithms are dominated by wide integer arithmetic, which are executed on ACC's 256-bit-wide data path. + The data ACC processes is often security sensitive, and ACC is designed to reduce the attack surface by (1) keeping the instruction set and the processor design as simple as possible to aid verification, (2) minimizing control flow and clearly separating it from data flow, - (3) limiting OTBN's instruction fetch and data memory accesses to separate, dedicated on-chip memories, - (4) giving OTBN software direct access to cryptographically secure random numbers, + (3) limiting ACC's instruction fetch and data memory accesses to separate, dedicated on-chip memories, + (4) giving ACC software direct access to cryptographically secure random numbers, and (5) implementing various hardware countermeasures to deter side-channel analysis (SCA) and fault injection (FI) attacks. ''' // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. @@ -22,7 +22,7 @@ design_spec: "../doc", dv_doc: "../doc/dv", hw_checklist: "../doc/checklist", - sw_checklist: "/sw/device/lib/dif/dif_otbn" + sw_checklist: "/sw/device/lib/dif/dif_acc" revisions: [ { version: "0.1.0", @@ -55,19 +55,19 @@ { name: "Stub", type: "bit", default: "0", - desc: "Stub out the core of Otbn logic" + desc: "Stub out the core of Acc logic" local: "false", expose: "true" }, { name: "RegFile", - type: "otbn_pkg::regfile_e", - default: "otbn_pkg::RegFileFF", - desc: "Selection of the register file implementation. See otbn_pkg.sv." + type: "acc_pkg::regfile_e", + default: "acc_pkg::RegFileFF", + desc: "Selection of the register file implementation. See acc_pkg.sv." local: "false", expose: "true" }, { name: "RndCnstUrndPrngSeed", - type: "otbn_pkg::urnd_prng_seed_t", + type: "acc_pkg::urnd_prng_seed_t", desc: ''' Default seed of the PRNG used for URND. ''' @@ -96,23 +96,23 @@ local: "false" expose: "true" } - { name: "RndCnstOtbnKey", - type: "otp_ctrl_pkg::otbn_key_t", + { name: "RndCnstAccKey", + type: "otp_ctrl_pkg::acc_key_t", desc: ''' Compile-time random reset value for IMem/DMem scrambling key. ''' randcount: "128", randtype: "data" }, - { name: "RndCnstOtbnNonce", - type: "otp_ctrl_pkg::otbn_nonce_t", + { name: "RndCnstAccNonce", + type: "otp_ctrl_pkg::acc_nonce_t", desc: ''' Compile-time random reset value for IMem/DMem scrambling nonce. ''' randcount: "64", randtype: "data" }, - { name: "OtbnPQCEn", + { name: "AccPQCEn", type: "bit", default: "0", desc: ''' @@ -124,7 +124,7 @@ ] interrupt_list: [ { name: "done" - desc: "OTBN has completed the operation." + desc: "ACC has completed the operation." } ] alert_list: [ @@ -138,9 +138,9 @@ inter_signal_list: [ // Key request to OTP - { struct: "otbn_otp_key" + { struct: "acc_otp_key" type: "req_rsp" - name: "otbn_otp_key" + name: "acc_otp_key" act: "req" default: "'0" package: "otp_ctrl_pkg" @@ -169,7 +169,7 @@ package: "kmac_pkg" }, - // OTBN is not performing any operation and can be clock/power-gated. + // ACC is not performing any operation and can be clock/power-gated. { name: "idle", type: "uni", struct: "mubi4", @@ -231,7 +231,7 @@ }, // Key sideload - { struct: "otbn_key_req" + { struct: "acc_key_req" type: "uni" name: "keymgr_key" act: "rcv" @@ -240,27 +240,27 @@ ], features: [ { - name: "OTBN.ISA" + name: "ACC.ISA" desc: ''' - OTBN implements a custom ISA based on RV32I. It is split into base (32-bit) and bignum + ACC implements a custom ISA based on RV32I. It is split into base (32-bit) and bignum (256-bit) parts. There is a separate register file for each. ''', - name: "OTBN.RANDOM" + name: "ACC.RANDOM" desc: ''' - OTBN has a connection to the EDN allowing it to receive 256-bits of entropy. + ACC has a connection to the EDN allowing it to receive 256-bits of entropy. ''' - name: "OTBN.KEYMGR" + name: "ACC.KEYMGR" desc: ''' - OTBN has a connection to the keymgr and it can receive key material from it. + ACC has a connection to the keymgr and it can receive key material from it. ''' - name: "OTBN.SECUREWIPE" + name: "ACC.SECUREWIPE" desc: ''' - OTBN has a secure wipe facility that can target the internal state as well as the + ACC has a secure wipe facility that can target the internal state as well as the instruction and data memories. ''' - name: "OTBN.MEM_SCRAMBLE" + name: "ACC.MEM_SCRAMBLE" desc: ''' - OTBN scrambles its instruction and data memories using keys received from OTP. + ACC scrambles its instruction and data memories using keys received from OTP. ''' } ] @@ -271,13 +271,13 @@ { name: "DATA.MEM.INTEGRITY", desc: ''' Dmem is protected with ECC integrity. - This is carried through to OTBN's register file. + This is carried through to ACC's register file. ''' } { name: "INSTRUCTION.MEM.INTEGRITY", desc: ''' Imem is protected with ECC integrity. - This is carried through into OTBN's execute stage. + This is carried through into ACC's execute stage. ''' } { name: "BUS.INTEGRITY", @@ -371,10 +371,10 @@ } { name: "START_STOP_CTRL.STATE.CONSISTENCY" desc: ''' - The secure wipe handshake between otbn_controller and - otbn_start_stop_control uses a level-based req/ack interface. At the - otbn_controller end, there is a check for unexpected acks. In - otbn_start_stop_control, there is a check for secure wipe requests when + The secure wipe handshake between acc_controller and + acc_start_stop_control uses a level-based req/ack interface. At the + acc_controller end, there is a check for unexpected acks. In + acc_start_stop_control, there is a check for secure wipe requests when we aren't in a state that allows it, and also a check for if the request drops at an unexpected time. ''' @@ -393,8 +393,8 @@ } { name: "DATA_REG_SW.SEC_WIPE" desc: ''' - Securely wipe programmer visible OTBN register (GPRs, WDRs, CSRs, WSRs) state with random data. - Initiated after reset, at the end of any OTBN operation, upon recoverable and fatal errors, and before RMA entry. + Securely wipe programmer visible ACC register (GPRs, WDRs, CSRs, WSRs) state with random data. + Initiated after reset, at the end of any ACC operation, upon recoverable and fatal errors, and before RMA entry. ''' } { name: "WRITE.MEM.INTEGRITY" @@ -407,7 +407,7 @@ } { name: "CTRL_FLOW.SCA" desc: ''' - OTBN architecture does not have any data dependent timing behaviour + ACC architecture does not have any data dependent timing behaviour ''' } { name: "DATA.MEM.SW_NOACCESS" @@ -434,13 +434,13 @@ desc: ''' Command Register - A command initiates an OTBN operation. While performing the operation, - OTBN is busy; the !!STATUS register reflects that. + A command initiates an ACC operation. While performing the operation, + ACC is busy; the !!STATUS register reflects that. All operations signal their completion by raising the done interrupt; alternatively, software may poll the !!STATUS register. - Writes are ignored if OTBN is not idle. + Writes are ignored if ACC is not idle. Unrecognized commands are ignored. ''', swaccess: "wo", @@ -484,13 +484,13 @@ When set software errors produce fatal errors, rather than recoverable errors. - Writes are ignored if OTBN is not idle. + Writes are ignored if ACC is not idle. ''' } ], tags: [ // Don't write this register in the automated CSR tests, because those - // tests are not aware whether OTBN is idle or not. If OTBN is not idle, + // tests are not aware whether ACC is idle or not. If ACC is not idle, // it ignores the write and the test would fail. "excl:CsrAllTests:CsrExclWrite" ] @@ -504,26 +504,26 @@ name: "status", resval: "0x04", // Note: Keep the list of status codes in sync with status_e in - // otbn_pkg.sv. + // acc_pkg.sv. desc: ''' - Indicates the current operational state OTBN is in. + Indicates the current operational state ACC is in. All BUSY values represent an operation started by a write to the !!CMD register. | Value | Name | Description | |:------|:-------------------|:------------------------------------------------------| - | 0x00 | IDLE | OTBN is idle: it is not performing any action. | - | 0x01 | BUSY_EXECUTE | OTBN is busy executing software. | - | 0x02 | BUSY_SEC_WIPE_DMEM | OTBN is busy securely wiping the data memory. | - | 0x03 | BUSY_SEC_WIPE_IMEM | OTBN is busy securely wiping the instruction memory. | - | 0x04 | BUSY_SEC_WIPE_INT | OTBN is busy securely wiping the internal state. | - | 0xFF | LOCKED | OTBN is locked as reaction to a fatal error, and must be reset to unlock it again. See also the section "Reaction to Fatal Errors". | + | 0x00 | IDLE | ACC is idle: it is not performing any action. | + | 0x01 | BUSY_EXECUTE | ACC is busy executing software. | + | 0x02 | BUSY_SEC_WIPE_DMEM | ACC is busy securely wiping the data memory. | + | 0x03 | BUSY_SEC_WIPE_IMEM | ACC is busy securely wiping the instruction memory. | + | 0x04 | BUSY_SEC_WIPE_INT | ACC is busy securely wiping the internal state. | + | 0xFF | LOCKED | ACC is locked as reaction to a fatal error, and must be reset to unlock it again. See also the section "Reaction to Fatal Errors". | ''' tags: [ // Exclude this field from the automated CSR tests. The register model does not know - // OTBN automatically transitions from the reset state to `IDLE` as it completes the + // ACC automatically transitions from the reset state to `IDLE` as it completes the // initial secure wipe of the internal state. "excl:CsrAllTests:CsrExclAll" ] @@ -539,8 +539,8 @@ Refer to the "List of Errors" section for a detailed description of the errors. - The host CPU can clear this register when OTBN is not running, - by writing any value. Write attempts while OTBN is running are ignored. + The host CPU can clear this register when ACC is not running, + by writing any value. Write attempts while ACC is running are ignored. ''', swaccess: "rw", hwaccess: "hrw", @@ -644,8 +644,8 @@ Fatal Alert Cause Register Describes any errors that led to a fatal alert. - A fatal error puts OTBN in locked state; the value of this register - does not change until OTBN is reset. + A fatal error puts ACC in locked state; the value of this register + does not change until ACC is reset. Refer to the "List of Errors" section for a detailed description of the errors. @@ -708,10 +708,10 @@ this register remains at 0. Instructions triggering an error do not count towards the total. - Always reads as 0 if OTBN is locked. + Always reads as 0 if ACC is locked. - The host CPU can clear this register when OTBN is not running, - by writing any value. Write attempts while OTBN is running are ignored. + The host CPU can clear this register when ACC is not running, + by writing any value. Write attempts while ACC is running are ignored. ''', swaccess: "rw", hwaccess: "hrw", @@ -773,11 +773,11 @@ Instruction Memory Access The instruction memory may only be accessed through this window - while OTBN is idle. + while ACC is idle. - If OTBN is busy or locked, read accesses return 0 and write accesses + If ACC is busy or locked, read accesses return 0 and write accesses are ignored. - If OTBN is busy, any access additionally triggers an + If ACC is busy, any access additionally triggers an ILLEGAL_BUS_ACCESS fatal error. ''' } @@ -796,12 +796,12 @@ desc: ''' Data Memory Access - The data memory may only be accessed through this window while OTBN + The data memory may only be accessed through this window while ACC is idle. - If OTBN is busy or locked, read accesses return 0 and write accesses + If ACC is busy or locked, read accesses return 0 and write accesses are ignored. - If OTBN is busy, any access additionally triggers an + If ACC is busy, any access additionally triggers an ILLEGAL_BUS_ACCESS fatal error. Note that DMEM is actually 4kiB in size, but only the first 3kiB of diff --git a/hw/ip/otbn/data/otbn.ld.tpl b/hw/ip/acc/data/acc.ld.tpl similarity index 87% rename from hw/ip/otbn/data/otbn.ld.tpl rename to hw/ip/acc/data/acc.ld.tpl index b4d0cd308f7..3f3e2a2a292 100644 --- a/hw/ip/otbn/data/otbn.ld.tpl +++ b/hw/ip/acc/data/acc.ld.tpl @@ -3,11 +3,11 @@ /* SPDX-License-Identifier: Apache-2.0 */ /* - OTBN has a pure Harvard architecture, with instruction and data + ACC has a pure Harvard architecture, with instruction and data memory both starting at address 0. - This linker script template is interpolated by otbn_ld.py after it gets - the LMAs and memory sizes from otbn.hjson. + This linker script template is interpolated by acc_ld.py after it gets + the LMAs and memory sizes from acc.hjson. */ MEMORY @@ -20,7 +20,7 @@ MEMORY LMA addresses (for VMAs in imem/dmem, respectively) Note that the DMEM load region is the first 3kiB of DMEM itself, - to model the fact that OTBN can write to the whole region but + to model the fact that ACC can write to the whole region but only the first 3kiB are bus-accessible. */ imem_load (rw) : ORIGIN = ${imem_lma}, LENGTH = ${imem_length} diff --git a/hw/ip/otbn/data/otbn_sec_cm_testplan.hjson b/hw/ip/acc/data/acc_sec_cm_testplan.hjson similarity index 80% rename from hw/ip/otbn/data/otbn_sec_cm_testplan.hjson rename to hw/ip/acc/data/acc_sec_cm_testplan.hjson index 534c7e7b2f2..6ca6bfdced8 100644 --- a/hw/ip/otbn/data/otbn_sec_cm_testplan.hjson +++ b/hw/ip/acc/data/acc_sec_cm_testplan.hjson @@ -12,7 +12,7 @@ // make further manual updates. // // These countermeasures and their descriptions can be found here: -// .../otbn/data/otbn.hjson +// .../acc/data/acc.hjson // // It is possible that the testing of some of these countermeasures may already // be covered as a testpoint in a different testplan. This duplication is ok - @@ -20,7 +20,7 @@ // to the testpoints below using the `tests` key. // // Please ensure that this testplan is imported in: -// .../otbn/data/otbn_testplan.hjson +// .../acc/data/acc_testplan.hjson { testpoints: [ { @@ -31,25 +31,25 @@ Hence there is no need to have a directed test for this countermeasure. ''' stage: V2S - tests: ["otbn_smoke"] + tests: ["acc_smoke"] } { name: sec_cm_data_mem_integrity desc: '''Verify the countermeasure(s) DATA.MEM.INTEGRITY. - Run an OTBN program multiple times and corrupt the DMEM while the OTBN + Run an ACC program multiple times and corrupt the DMEM while the ACC is still running. ''' stage: V2S - tests: ["otbn_dmem_err"] + tests: ["acc_dmem_err"] } { name: sec_cm_instruction_mem_integrity desc: '''Verify the countermeasure(s) INSTRUCTION.MEM.INTEGRITY. - Run an OTBN program multiple times and corrupt the IMEM while the OTBN + Run an ACC program multiple times and corrupt the IMEM while the ACC is still running. ''' stage: V2S - tests: ["otbn_imem_err"] + tests: ["acc_imem_err"] } { name: sec_cm_bus_integrity @@ -57,16 +57,16 @@ This entry is covered by tl_access_test. ''' stage: V2S - tests: ["otbn_tl_intg_err"] + tests: ["acc_tl_intg_err"] } { name: sec_cm_controller_fsm_global_esc desc: '''Verify the countermeasure(s) CONTROLLER.FSM.GLOBAL_ESC. - Run an OTBN program, drive lc_escalate_en_i port randomly to - see global escalation locking up OTBN. + Run an ACC program, drive lc_escalate_en_i port randomly to + see global escalation locking up ACC. ''' stage: V2S - tests: ["otbn_escalate"] + tests: ["acc_escalate"] } { name: sec_cm_controller_fsm_local_esc @@ -75,13 +75,13 @@ 1. IMEM/DMEM error tests to see local escalation related with integrity Checking 2. Zero state URND test to see local escalation regarding a URND value of all zeros 3. Illegal memory access test to see local escalation while having illegal read and - write accesses to the IMEM when the OTBN is busy. - 4. Bad internal state errors that are triggered by otbn_sec_cm test will also cause + write accesses to the IMEM when the ACC is busy. + 4. Bad internal state errors that are triggered by acc_sec_cm test will also cause local escalation to the locked state. ''' stage: V2S - tests: ["otbn_imem_err", "otbn_dmem_err", "otbn_zero_state_err_urnd", "otbn_illegal_mem_acc", - "otbn_sec_cm"] + tests: ["acc_imem_err", "acc_dmem_err", "acc_zero_state_err_urnd", "acc_illegal_mem_acc", + "acc_sec_cm"] } { name: sec_cm_controller_fsm_sparse @@ -89,7 +89,7 @@ This countermeasure is verified with a standardized test. ''' stage: V2S - tests: ["otbn_sec_cm"] + tests: ["acc_sec_cm"] } { name: sec_cm_scramble_key_sideload @@ -100,7 +100,7 @@ scramble key by SW. ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_scramble_ctrl_fsm_local_esc @@ -109,13 +109,13 @@ 1. IMEM/DMEM error tests to see local escalation related with integrity Checking 2. Zero state URND test to see local escalation regarding a URND value of all zeros 3. Illegal memory access test to see local escalation while having illegal read and - write accesses to the IMEM when the OTBN is busy. - 4. Bad internal state errors that are triggered by otbn_sec_cm test will also cause + write accesses to the IMEM when the ACC is busy. + 4. Bad internal state errors that are triggered by acc_sec_cm test will also cause local escalation to the locked state. ''' stage: V2S - tests: ["otbn_imem_err", "otbn_dmem_err", "otbn_zero_state_err_urnd", "otbn_illegal_mem_acc", - "otbn_sec_cm"] + tests: ["acc_imem_err", "acc_dmem_err", "acc_zero_state_err_urnd", "acc_illegal_mem_acc", + "acc_sec_cm"] } { name: sec_cm_scramble_ctrl_fsm_sparse @@ -123,16 +123,16 @@ This countermeasure is verified with a standardized test. ''' stage: V2S - tests: ["otbn_sec_cm"] + tests: ["acc_sec_cm"] } { name: sec_cm_start_stop_ctrl_fsm_global_esc desc: '''Verify the countermeasure(s) START_STOP_CTRL.FSM.GLOBAL_ESC. - Run an OTBN program, drive lc_escalate_en_i port randomly to - see global escalation locking up the start-stop control FSM in OTBN. + Run an ACC program, drive lc_escalate_en_i port randomly to + see global escalation locking up the start-stop control FSM in ACC. ''' stage: V2S - tests: ["otbn_escalate"] + tests: ["acc_escalate"] } { name: sec_cm_start_stop_ctrl_fsm_local_esc @@ -141,12 +141,12 @@ 1. IMEM/DMEM error tests to see local escalation related with integrity Checking 2. Zero state URND test to see local escalation regarding a URND value of all zeros 3. Illegal memory access test to see local escalation while having illegal read and - write accesses to the IMEM when the OTBN is busy. - 4. Bad internal state errors that are triggered by otbn_sec_cm test will also cause + write accesses to the IMEM when the ACC is busy. + 4. Bad internal state errors that are triggered by acc_sec_cm test will also cause local escalation to the locked state. ''' stage: V2S - tests: ["otbn_imem_err", "otbn_dmem_err", "otbn_zero_state_err_urnd", "otbn_illegal_mem_acc", "otbn_sec_cm"] + tests: ["acc_imem_err", "acc_dmem_err", "acc_zero_state_err_urnd", "acc_illegal_mem_acc", "acc_sec_cm"] } { name: sec_cm_start_stop_ctrl_fsm_sparse @@ -154,16 +154,16 @@ This countermeasure is verified with a standardized test. ''' stage: V2S - tests: ["otbn_sec_cm"] + tests: ["acc_sec_cm"] } { name: sec_cm_data_reg_sw_sca desc: '''Verify the countermeasure(s) DATA_REG_SW.SCA. Since this is related with unused parts of the datapath not changing throughout - an OTBN run this security countermeasure is verified with assertions. + an ACC run this security countermeasure is verified with assertions. ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_ctrl_redun @@ -173,7 +173,7 @@ Possible control flow paths are listed in the countermeasure description. ''' stage: V2S - tests: ["otbn_ctrl_redun"] + tests: ["acc_ctrl_redun"] } { name: sec_cm_pc_ctrl_flow_redun @@ -183,7 +183,7 @@ predecoder and decoder that results with a fatal error. ''' stage: V2S - tests: ["otbn_pc_ctrl_flow_redun"] + tests: ["acc_pc_ctrl_flow_redun"] } { name: sec_cm_rnd_bus_consistency @@ -192,7 +192,7 @@ word of the received RND data. ''' stage: V2S - tests: ["otbn_rnd_sec_cm"] + tests: ["acc_rnd_sec_cm"] } { name: sec_cm_rnd_rng_digest @@ -201,13 +201,13 @@ Expect to trigger RND_REP_CHK_FAIL recoverable error for repeated EDN words. ''' stage: V2S - tests: ["otbn_rnd_sec_cm"] + tests: ["acc_rnd_sec_cm"] } { name: sec_cm_rf_base_data_reg_sw_integrity desc: "Verify the countermeasure(s) RF_BASE.DATA_REG_SW.INTEGRITY." stage: V2S - tests: ["otbn_rf_base_intg_err"] + tests: ["acc_rf_base_intg_err"] } { name: sec_cm_rf_base_data_reg_sw_glitch_detect @@ -215,7 +215,7 @@ This countermeasure is verified with a standardized test. ''' stage: V2S - tests: ["otbn_sec_cm"] + tests: ["acc_sec_cm"] } { name: sec_cm_stack_wr_ptr_ctr_redun @@ -223,13 +223,13 @@ This countermeasure is verified with a standardized test. ''' stage: V2S - tests: ["otbn_sec_cm"] + tests: ["acc_sec_cm"] } { name: sec_cm_rf_bignum_data_reg_sw_integrity desc: "Verify the countermeasure(s) RF_BIGNUM.DATA_REG_SW.INTEGRITY." stage: V2S - tests: ["otbn_rf_bignum_intg_err"] + tests: ["acc_rf_bignum_intg_err"] } { name: sec_cm_rf_bignum_data_reg_sw_glitch_detect @@ -237,7 +237,7 @@ This countermeasure is verified with a standardized test. ''' stage: V2S - tests: ["otbn_sec_cm"] + tests: ["acc_sec_cm"] } { name: sec_cm_loop_stack_ctr_redun @@ -245,7 +245,7 @@ This countermeasure is verified with a standardized test. ''' stage: V2S - tests: ["otbn_sec_cm"] + tests: ["acc_sec_cm"] } { name: sec_cm_loop_stack_addr_integrity @@ -254,7 +254,7 @@ related with integrity failure. ''' stage: V2S - tests: ["otbn_stack_addr_integ_chk"] + tests: ["acc_stack_addr_integ_chk"] } { name: sec_cm_call_stack_addr_integrity @@ -263,7 +263,7 @@ related with integrity failure. ''' stage: V2S - tests: ["otbn_stack_addr_integ_chk"] + tests: ["acc_stack_addr_integ_chk"] } { name: sec_cm_start_stop_ctrl_state_consistency @@ -273,7 +273,7 @@ status. ''' stage: V2S - tests: ["otbn_sec_wipe_err"] + tests: ["acc_sec_wipe_err"] } { name: sec_cm_data_mem_sec_wipe @@ -283,7 +283,7 @@ Related assertions: DmemSecWipeRequiresUrndKey_A and DmemSecWipeRequiresOtpKey_A ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_instruction_mem_sec_wipe @@ -293,46 +293,46 @@ Related assertions: ImemSecWipeRequiresUrndKey_A and ImemSecWipeRequiresOtpKey_A ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_data_reg_sw_sec_wipe desc: '''Verify the countermeasure(s) DATA_REG_SW.SEC_WIPE. - Golden model of OTBN in Python models secure wiping cycle accurately. So in every + Golden model of ACC in Python models secure wiping cycle accurately. So in every test at least one internal secure wipe because of exiting a reset. Hence there is no need for a specific test. ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_write_mem_integrity desc: '''Verify the countermeasure(s) WRITE.MEM.INTEGRITY. DV environment calculates CRC values independently from RTL with every memory write - over the bus and than calculates it with the design. otbn_multi does not use backdoor + over the bus and than calculates it with the design. acc_multi does not use backdoor writes to memory so it's guaranteed to see CRC checking for IMEM and DMEM there. ''' stage: V2S - tests: ["otbn_multi"] + tests: ["acc_multi"] } { name: sec_cm_ctrl_flow_count desc: '''Verify the countermeasure(s) CTRL_FLOW.COUNT. - Golden model of OTBN in Python models instruction counter register cycle accurately. + Golden model of ACC in Python models instruction counter register cycle accurately. So in every test there is a comparison between model instruction counter value and design instruction counter value. Hence there is no need for a specific test. ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_ctrl_flow_sca desc: '''Verify the countermeasure(s) CTRL_FLOW.SCA. Since this is related with unused parts of the control path not changing - throughout an OTBN run this security countermeasure is verified with assertions. + throughout an ACC run this security countermeasure is verified with assertions. ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_data_mem_sw_noaccess @@ -341,20 +341,20 @@ DMEM. Expected result is a error response from the TLUL bus. ''' stage: V2S - tests: ["otbn_sw_no_acc"] + tests: ["acc_sw_no_acc"] } { name: sec_cm_key_sideload desc: '''Verify the countermeasure(s) KEY.SIDELOAD. - DV environment cannot verify the architectural choice of having sideloaded keys. OTBN + DV environment cannot verify the architectural choice of having sideloaded keys. ACC on top using this architecture, also raises an error in the case of invalid sideload keys. Invalid sideload keys are allowed in the sideload key sequence fifty percent of the - time by default. In that scenario OTBN would generate a KEY_INVALID recoverable software error. - This happens test agnostic so otbn_single is mapped to represent an OTBN run in general. + time by default. In that scenario ACC would generate a KEY_INVALID recoverable software error. + This happens test agnostic so acc_single is mapped to represent an ACC run in general. ''' stage: V2S - tests: ["otbn_single"] + tests: ["acc_single"] } { name: sec_cm_tlul_fifo_ctr_redun diff --git a/hw/ip/otbn/data/otbn_testplan.hjson b/hw/ip/acc/data/acc_testplan.hjson similarity index 80% rename from hw/ip/otbn/data/otbn_testplan.hjson rename to hw/ip/acc/data/acc_testplan.hjson index 95dad5cb0db..d75ff6d0b3b 100644 --- a/hw/ip/otbn/data/otbn_testplan.hjson +++ b/hw/ip/acc/data/acc_testplan.hjson @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 { - name: "otbn" + name: "acc" import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", "hw/dv/tools/dvsim/testplans/mem_testplan.hjson", "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", @@ -12,28 +12,28 @@ "hw/dv/tools/dvsim/testplans/passthru_mem_intg_testplan.hjson", "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", - "otbn_sec_cm_testplan.hjson"] + "acc_sec_cm_testplan.hjson"] testpoints: [ { name: smoke desc: ''' Smoke test, running a single fixed binary - This runs the binary from otbn/dv/smoke/smoke_test.s, which is + This runs the binary from acc/dv/smoke/smoke_test.s, which is designed to check most of the implemented instructions. The unchanging binary should mean this basic test is particularly appropriate for CI. ''' stage: V1 - tests: ["otbn_smoke"] + tests: ["acc_smoke"] } { name: single_binary desc: ''' Run a single randomly-chosen binary - This test drives the main bulk of OTBN testing. It picks a random + This test drives the main bulk of ACC testing. It picks a random binary from a pre-generated set and runs it, comparing against the model. We'll run this with a large number of seeds and use functional coverage to track when verification of the internals of @@ -44,7 +44,7 @@ ''' stage: V1 - tests: ["otbn_single"] + tests: ["acc_single"] } { @@ -60,7 +60,7 @@ ''' stage: V2 - tests: ["otbn_reset"] + tests: ["acc_reset"] } { @@ -71,12 +71,12 @@ These are directed tests, designed to exhaustively trigger all the cases where a single instruction execution can fail for more than one reason. Since each of these instructions causes the operation - to fail, we have to run an OTBN operation for each. To do this, we + to fail, we have to run an ACC operation for each. To do this, we compile and run all the binaries in a collection of ISS unit tests. We have coverage points to ensure we see every event we expect. ''' stage: V2 - tests: ["otbn_multi_err"] + tests: ["acc_multi_err"] } { @@ -85,7 +85,7 @@ Inject ECC errors into DMEM and IMEM and expect an alert ''' stage: V2S - tests: ["otbn_imem_err", "otbn_dmem_err"] + tests: ["acc_imem_err", "acc_dmem_err"] } { name: internal_integrity @@ -93,10 +93,10 @@ Corrupt internal state and expect an alert ''' stage: V2S - tests: ["otbn_alu_bignum_mod_err", - "otbn_controller_ispr_rdata_err", - "otbn_mac_bignum_acc_err", - "otbn_urnd_err"] + tests: ["acc_alu_bignum_mod_err", + "acc_controller_ispr_rdata_err", + "acc_mac_bignum_acc_err", + "acc_urnd_err"] } { name: back_to_back @@ -109,7 +109,7 @@ ''' stage: V2 - tests: ["otbn_multi"] + tests: ["acc_multi"] } { name: stress_all @@ -117,7 +117,7 @@ Run assorted sequences back-to-back. ''' stage: V2 - tests: ["otbn_stress_all"] + tests: ["acc_stress_all"] } { name: lc_escalation @@ -125,7 +125,7 @@ Trigger the life cycle escalation input. ''' stage: V2 - tests: ["otbn_escalate"] + tests: ["acc_escalate"] } { name: zero_state_err_urnd @@ -134,7 +134,7 @@ Check that fatal error is asserted. ''' stage: V2 - tests: ["otbn_zero_state_err_urnd"] + tests: ["acc_zero_state_err_urnd"] } { name: illegal_bus_access @@ -143,7 +143,7 @@ ILLEGAL_BUS_ACCESS. Check that *mem_rdata_bus pins are at 0 when reads are done ''' stage: V2S - tests: ["otbn_illegal_mem_acc"] + tests: ["acc_illegal_mem_acc"] } { name: sw_errs_fatal_chk @@ -152,33 +152,33 @@ When set software errors produce fatal errors, rather than recoverable errors. ''' stage: V2 - tests: ["otbn_sw_errs_fatal_chk"] + tests: ["acc_sw_errs_fatal_chk"] } { - name: otbn_mem_gnt_acc_err + name: acc_mem_gnt_acc_err desc: ''' Trigger a fault to cause the IMEM/DMEM grant signal to be false when req is asserted. This in turn should cause dmem_missed_gnt/imem_missed_gnt to get asserted resulting in a fatal alert (a bad_internal_state fatal error). ''' stage: V2S - tests: ["otbn_mem_gnt_acc_err"] + tests: ["acc_mem_gnt_acc_err"] } { - name: otbn_non_sec_partial_wipe + name: acc_non_sec_partial_wipe desc: ''' See a local wipe signal be raised when a secure wipe is not running. When this happens, we expect the RTL to stop with a fatal alert. The signals tracked are: - - sec_wipe_mod_urnd_i in otbn_alu_bignum - - sec_wipe_zero_i in otbn_controller - - sec_wipe_base in otbn_core - - sec_wipe_wdr_q in otbn_core - - sec_wipe_stack_reset_i in otbn_rf_base + - sec_wipe_mod_urnd_i in acc_alu_bignum + - sec_wipe_zero_i in acc_controller + - sec_wipe_base in acc_core + - sec_wipe_wdr_q in acc_core + - sec_wipe_stack_reset_i in acc_rf_base ''' stage: V2S - tests: ["otbn_partial_wipe"] + tests: ["acc_partial_wipe"] } ] } diff --git a/hw/ip/otbn/data/base-insns.yml b/hw/ip/acc/data/base-insns.yml similarity index 95% rename from hw/ip/otbn/data/base-insns.yml rename to hw/ip/acc/data/base-insns.yml index f661946fa90..eb66d05b11b 100644 --- a/hw/ip/otbn/data/base-insns.yml +++ b/hw/ip/acc/data/base-insns.yml @@ -373,7 +373,7 @@ doc: | The JAL instruction has the same behavior as in RV32I, jumping by the given offset and writing `PC+4` as a link address to the destination register. - OTBN has a hardware managed call stack, accessed through `x1`, which should be used when calling subroutines. + ACC has a hardware managed call stack, accessed through `x1`, which should be used when calling subroutines. Do so by using `x1` as the link register: `jal x1, `. errs: - *grd-call-stack @@ -394,7 +394,7 @@ doc: | The JALR instruction has the same behavior as in RV32I, jumping by ` + ` and writing `PC+4` as a link address to the destination register. - OTBN has a hardware managed call stack, accessed through `x1`, which should be used when calling and returning from subroutines. + ACC has a hardware managed call stack, accessed through `x1`, which should be used when calling and returning from subroutines. To return from a subroutine, use `jalr x0, x1, 0`. This pops a link address from the call stack and branches to it. To call a subroutine through a function pointer, use `jalr x1, , 0`. @@ -587,12 +587,12 @@ The number of instructions in the loop is given in the `bodysize` immediate. The `LOOP` instruction doesn't support a zero iteration count. - If the value in `grs` is zero, OTBN stops, setting bit `loop` in `ERR_BITS`. + If the value in `grs` is zero, ACC stops, setting bit `loop` in `ERR_BITS`. Starting a loop pushes an entry on to the [loop stack](../#loop-stack). - If the stack is already full, OTBN stops, setting bit `loop` in `ERR_BITS`. + If the stack is already full, ACC stops, setting bit `loop` in `ERR_BITS`. `LOOP`, `LOOPI`, jump and branch instructions are all permitted inside a loop but may not appear as the last instruction in a loop. - OTBN will stop on that instruction, setting bit `loop` in `ERR_BITS`. + ACC will stop on that instruction, setting bit `loop` in `ERR_BITS`. For more information on how to correctly use `LOOP` see [loop nesting](programmers_guide.md#loop-nesting). errs: @@ -619,12 +619,12 @@ The number of instructions in the loop is given in the `bodysize` immediate. The `LOOPI` instruction doesn't support a zero iteration count. - If the value of `iterations` is zero, OTBN stops with the `ErrCodeLoop` error. + If the value of `iterations` is zero, ACC stops with the `ErrCodeLoop` error. Starting a loop pushes an entry on to the [loop stack](../#loop-stack). - If the stack is already full, OTBN stops, setting bit `loop` in `ERR_BITS`. + If the stack is already full, ACC stops, setting bit `loop` in `ERR_BITS`. `LOOP`, `LOOPI`, jump and branch instructions are all permitted inside a loop but may not appear as the last instruction in a loop. - OTBN will stop on that instruction, setting bit `loop` in `ERR_BITS`. + ACC will stop on that instruction, setting bit `loop` in `ERR_BITS`. For more information on how to correctly use `LOOPI` see [loop nesting](programmers_guide.md#loop-nesting). encoding: @@ -675,7 +675,7 @@ # Implement the de-facto UNIMP RISC-V instruction alias according to # https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md -# OTBN does not support the cycle CSR (0xC00), hence the illegal instruction +# ACC does not support the cycle CSR (0xC00), hence the illegal instruction # exception stems from the missing CSR instead of writing to a read-only, but # the end result is the same. - mnemonic: unimp diff --git a/hw/ip/otbn/data/bignum-insns.yml b/hw/ip/acc/data/bignum-insns.yml similarity index 99% rename from hw/ip/otbn/data/bignum-insns.yml rename to hw/ip/acc/data/bignum-insns.yml index 1c4ecb9f10c..f6abc22fe43 100644 --- a/hw/ip/otbn/data/bignum-insns.yml +++ b/hw/ip/acc/data/bignum-insns.yml @@ -3,7 +3,7 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028). # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. # Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/hw/ip/otbn/data/csr.yml b/hw/ip/acc/data/csr.yml similarity index 77% rename from hw/ip/otbn/data/csr.yml rename to hw/ip/acc/data/csr.yml index 20f0d5c128f..4a38369ac4d 100644 --- a/hw/ip/otbn/data/csr.yml +++ b/hw/ip/acc/data/csr.yml @@ -46,49 +46,49 @@ - name: mod0 address: 0x7d0 doc: | - Bits [31:0] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [31:0] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: mod1 address: 0x7d1 doc: | - Bits [63:32] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [63:32] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: mod2 address: 0x7d2 doc: | - Bits [95:64] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [95:64] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: mod3 address: 0x7d3 doc: | - Bits [127:96] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [127:96] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: mod4 address: 0x7d4 doc: | - Bits [159:128] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [159:128] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: mod5 address: 0x7d5 doc: | - Bits [191:160] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [191:160] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: mod6 address: 0x7d6 doc: | - Bits [223:192] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [223:192] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: mod7 address: 0x7d7 doc: | - Bits [255:224] of the modulus operand, used in the {{#otbn-insn-ref BN.ADDM}}/{{#otbn-insn-ref BN.SUBM}} instructions. + Bits [255:224] of the modulus operand, used in the {{#acc-insn-ref BN.ADDM}}/{{#acc-insn-ref BN.SUBM}} instructions. This CSR is mapped to the MOD WSR. - name: rnd_prefetch @@ -135,7 +135,7 @@ Primarily intended to be used for key generation. The number is sourced from the EDN via a single-entry cache. - Reads when the cache is empty will cause OTBN to be stalled until a new random number is fetched from the EDN. + Reads when the cache is empty will cause ACC to be stalled until a new random number is fetched from the EDN. - name: urnd address: 0xfc1 diff --git a/hw/ip/otbn/data/enc-schemes.yml b/hw/ip/acc/data/enc-schemes.yml similarity index 97% rename from hw/ip/otbn/data/enc-schemes.yml rename to hw/ip/acc/data/enc-schemes.yml index b7ab10490dd..d0c6087bc57 100644 --- a/hw/ip/otbn/data/enc-schemes.yml +++ b/hw/ip/acc/data/enc-schemes.yml @@ -4,12 +4,12 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028) # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. -# Instruction encoding schemes for OTBN +# Instruction encoding schemes for ACC # # These are used by the instructions in insns.yml. A scheme defines the mapping # between instruction operands and bits in the encoding. A scheme names zero or @@ -163,7 +163,7 @@ custom4: parents: - rv(opcode=b11111) -# A partial scheme for custom instructions with opcode b11111 +# A partial scheme for custom instructions with opcode b10010 custom5: parents: - rv(opcode=b10010) @@ -187,7 +187,7 @@ wdr3: wrs2: 24-20 wrs1: 19-15 -# A partial scheme for instructions that take two source WDRs and produce a +# A partial scheme for instructions that take one source WDR and produce a # dest WDR. wdr2: parents: diff --git a/hw/ip/otbn/data/insns.yml b/hw/ip/acc/data/insns.yml similarity index 99% rename from hw/ip/otbn/data/insns.yml rename to hw/ip/acc/data/insns.yml index 4a0152450df..14b3354b521 100644 --- a/hw/ip/otbn/data/insns.yml +++ b/hw/ip/acc/data/insns.yml @@ -223,7 +223,7 @@ insn-groups: - key: base title: Base Instruction Subset doc: | - The base instruction set of OTBN is a limited 32b instruction set. + The base instruction set of ACC is a limited 32b instruction set. It is used together with the 32b wide General Purpose Register file. The primary use of the base instruction set is the control flow in applications. diff --git a/hw/ip/otbn/data/wsr.yml b/hw/ip/acc/data/wsr.yml similarity index 72% rename from hw/ip/otbn/data/wsr.yml rename to hw/ip/acc/data/wsr.yml index 89874c76e4e..c96db43481e 100644 --- a/hw/ip/otbn/data/wsr.yml +++ b/hw/ip/acc/data/wsr.yml @@ -1,7 +1,7 @@ # Copyright lowRISC contributors (OpenTitan project). # Copyright zeroRISC Inc. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028). # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. # Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -10,7 +10,7 @@ - name: mod address: 0 doc: | - The modulus used by the {{#otbn-insn-ref BN.ADDM}} and {{#otbn-insn-ref BN.SUBM}} instructions. + The modulus used by the {{#acc-insn-ref BN.ADDM}} and {{#acc-insn-ref BN.SUBM}} instructions. This WSR is also visible as CSRs `MOD0` through to `MOD7`. - name: rnd @@ -21,7 +21,7 @@ Primarily intended to be used for key generation. The number is sourced from the EDN via a single-entry cache. - Reads when the cache is empty will cause OTBN to be stalled until a new random number is fetched from the EDN. + Reads when the cache is empty will cause ACC to be stalled until a new random number is fetched from the EDN. - name: urnd address: 2 @@ -37,18 +37,18 @@ - name: acc address: 3 doc: | - The accumulator register used by the {{#otbn-insn-ref BN.MULQACC}} instruction. + The accumulator register used by the {{#acc-insn-ref BN.MULQACC}} instruction. - name: acch address: 11 doc: | - The high bits of the accumulator register used by the {{#otbn-insn-ref BN.MULV}} instruction. + The high bits of the accumulator register used by the {{#acc-insn-ref BN.MULV}} instruction. - name: key_s0_l address: 4 read-only: true doc: | - Bits [255:0] of share 0 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [255:0] of share 0 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md). A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key. @@ -57,7 +57,7 @@ read-only: true doc: | Bits [255:128] of this register are always zero. - Bits [127:0] contain bits [383:256] of share 0 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [127:0] contain bits [383:256] of share 0 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md). A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key. @@ -65,7 +65,7 @@ address: 6 read-only: true doc: | - Bits [255:0] of share 1 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [255:0] of share 1 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md). A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key. @@ -74,7 +74,7 @@ read-only: true doc: | Bits [255:128] of this register are always zero. - Bits [127:0] contain bits [383:256] of share 1 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [127:0] contain bits [383:256] of share 1 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md). A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key. diff --git a/hw/ip/otbn/defs.bzl b/hw/ip/acc/defs.bzl similarity index 72% rename from hw/ip/otbn/defs.bzl rename to hw/ip/acc/defs.bzl index 0b78d924d4d..0faf5a1aa07 100644 --- a/hw/ip/otbn/defs.bzl +++ b/hw/ip/acc/defs.bzl @@ -3,7 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 load("//rules/opentitan:hw.bzl", "opentitan_ip") -OTBN = opentitan_ip( - name = "otbn", - hjson = "//hw/ip/otbn/data:otbn.hjson", +ACC = opentitan_ip( + name = "acc", + hjson = "//hw/ip/acc/data:acc.hjson", ) diff --git a/hw/ip/otbn/doc/otbn_blockarch.svg b/hw/ip/acc/doc/acc_blockarch.svg similarity index 99% rename from hw/ip/otbn/doc/otbn_blockarch.svg rename to hw/ip/acc/doc/acc_blockarch.svg index db1f970bfbd..0f2b2d9e86e 100644 --- a/hw/ip/otbn/doc/otbn_blockarch.svg +++ b/hw/ip/acc/doc/acc_blockarch.svg @@ -4,7 +4,7 @@ viewBox="0 0 1076.6736 886.2356" stroke-miterlimit="10" id="svg2383" - sodipodi:docname="otbn_blockarch.svg" + sodipodi:docname="acc_blockarch.svg" inkscape:version="1.4.2 (ebf0e940d0, 2025-05-08)" width="1076.6736" height="886.2356" @@ -769,7 +769,7 @@ sodipodi:role="line" id="tspan25041" x="21.057205" - y="72.174202">otbn_otp_key_o + y="72.174202">acc_otp_key_o otbn_otp_key_i + y="34.174198">acc_otp_key_i OTBN Core + style="stroke-width:1.92105">ACC Core OTBN Sideload Key Interface + style="font-size:8px">ACC Sideload Key Interface Big Number Accelerator - OTBN + id="tspan3807">Number Accelerator - ACC > 63` would do something like the below diagram: ![Diagram showing registers being concatenated](rshi.svg) @@ -128,7 +128,7 @@ Note that `bn.rshi` can work as a more typical right-shift by setting the high r ### Shifted operands -Many bignum instructions on OTBN include a shift argument. +Many bignum instructions on ACC include a shift argument. For example, to compute `w1 + (w2 << 32)`, you can simply write: ```armasm bn.add w3, w1, w2 << 32 @@ -150,8 +150,8 @@ Specifically, that means the following instructions: - `bn.or` : bitwise or - `bn.xor` : bitwise xor -This shift argument makes manipulating sub-parts of words on OTBN concise and ergonomic. -For example, here is how you can flip the endianness of each 32-bit word in a 256-bit word in 7 instructions (taken directly from our OTBN SHA-256 implementation): +This shift argument makes manipulating sub-parts of words on ACC concise and ergonomic. +For example, here is how you can flip the endianness of each 32-bit word in a 256-bit word in 7 instructions (taken directly from our ACC SHA-256 implementation): ```armasm /** * Flip the bytes in each 32-bit word of a 256-bit value. @@ -185,19 +185,32 @@ bswap32_w23: ret ``` +### Vector operations + +To accelerate the lattice-based cryptography ML-KEM and ML-DSA algorithms, ACC has vectorized variants of several bignum instructions. +Specifically, the following instructions operate on vectors: +- `bn.addv` : vector add +- `bn.subv` : vector subtract +- `bn.shv` : vector shift +- `bn.trn` : vector transpose +- `bn.mulv` : vector multiply and accumulate +- `bn.mulv.l` : vector multiply and accumulate with lane index + +For a more detailed overview of the instruction encodings, see the [ISA guide](isa.md). + ## Implementation process -At a high level, the process for developing code on OTBN looks something like this: +At a high level, the process for developing code on ACC looks something like this: -![OTBN development process diagram](otbn_development_process.svg) +![ACC development process diagram](acc_development_process.svg) -OTBN-simulator tests usually function as a quick check or as unit tests for internal routines, so they are most useful for quick feedback on changes. +ACC-simulator tests usually function as a quick check or as unit tests for internal routines, so they are most useful for quick feedback on changes. Ibex-side tests are more useful for running large or randomized test suites on completed programs, which helps to find bugs in corner cases. Finally, [SCA analysis](#sca-methodology) can run on either whole programs or small, sensitive subroutines, and helps to determine whether defenses against power and EM side-channels are working. ## An example program -This is an entire, standalone OTBN program that computes `(a + b << 16) mod m`, where `a`, `b` and `m` are all up to 256 bits (and `a, b < m`): +This is an entire, standalone ACC program that computes `(a + b << 16) mod m`, where `a`, `b` and `m` are all up to 256 bits (and `a, b < m`): ```armasm .section .text.start main: @@ -266,12 +279,12 @@ Some notes to help explain the code above: - The first argument to `loopi` is the number of iterations, and the second is the number of instructions in the loop body - `.bss` marks data memory that is not initialized; the program would still work if we used `.data`, but the binary would be bigger because Ibex would store a bunch of placeholder zeroes -To see all current OTBN programs from the OpenTitan codebase, see the [sw/otbn](https://github.com/lowRISC/opentitan/tree/master/sw/otbn) directory. +To see all current ACC programs from the codebase, see the `sw/acc/` directory. The `crypto/` subdirectory contains code we use in production, while the `code-snippets` subdirectory contains small example programs. ## Performance -Here are some cycle counts from OTBN programs! +Here are some cycle counts from ACC programs! Look below for instructions on how to reproduce these benchmarks. | Operation | Cycles | Commit | Target | Constant time | @@ -293,106 +306,104 @@ Look below for instructions on how to reproduce these benchmarks. A few notes: -- Because some OTBN code is still under development, these cycle counts are expected to change a bit as we optimize the code and add hardening countermeasures against fault injection and power/EM side-channel attacks. -- Some of these benchmarks include significant overhead from these countermeasures (for example, we run the inner loop of P-256 scalar multiplication 320 times instead of 256), but in OpenTitan's threat model the price is worthwhile. -- For non-constant-time code, due to the nature of the OTBN benchmarks, it is currently difficult to run multiple tests, so the numbers above reflect only one test each and should be treated as a rough estimate. +- Because some ACC code is still under development, these cycle counts are expected to change a bit as we optimize the code and add hardening countermeasures against fault injection and power/EM side-channel attacks. +- Some of these benchmarks include significant overhead from these countermeasures (for example, we run the inner loop of P-256 scalar multiplication 320 times instead of 256), but in the current threat model the price is worthwhile. +- For non-constant-time code, due to the nature of the ACC benchmarks, it is currently difficult to run multiple tests, so the numbers above reflect only one test each and should be treated as a rough estimate. ### Benchmark reproduction -To reproduce these benchmarks yourself, checkout the specified commit from OpenTitan, then run the OTBN simulator directly on the specified programs. +To reproduce these benchmarks yourself, checkout the specified commit, then run the ACC simulator directly on the specified programs. #### Step 1: Build the tests. -To build the tests with Bazel, run `bazel build //sw/otbn/crypto/tests:`, e.g. `bazel build //sw/otbn/crypto/tests:p256_ecdsa_verify_test`. -Then you'll need to find the `.elf` file that Bazel generates; for me this is e.g. `bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/otbn/crypto/tests/p256_ecdsa_verify_test.elf`. +To build the tests with Bazel, run `bazel build //sw/acc/crypto/tests:`, e.g. `bazel build //sw/acc/crypto/tests:p256_ecdsa_verify_test`. +Then you'll need to find the `.elf` file that Bazel generates; for me this is e.g. `bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/acc/crypto/tests/p256_ecdsa_verify_test.elf`. You can find the path for yours by running: ``` -bazel aquery 'outputs(".*.elf", //sw/otbn/crypto/tests:p256_ecdsa_verify_test)' | grep 'Outputs' +bazel aquery 'outputs(".*.elf", //sw/acc/crypto/tests:p256_ecdsa_verify_test)' | grep 'Outputs' ``` -Alternatively, you can build the tests manually with `otbn_as.py` and `otbn_ld.py`, as described in the [OTBN development guide](developing_otbn.md#build-otbn-software). -In this case you won't need to dig around for the `.elf` file, but you will need to look at `sw/otbn/crypto/tests/BUILD` to see which assembly files need to be included in each target. +Alternatively, you can build the tests manually with `acc_as.py` and `acc_ld.py`, as described in the [ACC development guide](developing_acc.md#build-acc-software). +In this case you won't need to dig around for the `.elf` file, but you will need to look at `sw/acc/crypto/tests/BUILD` to see which assembly files need to be included in each target. #### Step 2: Run the simulator. -Once you have the `.elf` file, either from Bazel or from the manual build process, run `hw/ip/dv/otbnsim/standalone.py --dump-stats - path/to/test.elf` to get a nice printout with the cycle counts plus other statistics. -See the [OTBN development guide](developing_otbn.md#run-the-python-simulator) for more information about using the OTBN simulator. +Once you have the `.elf` file, either from Bazel or from the manual build process, run `hw/ip/dv/accsim/standalone.py --dump-stats - path/to/test.elf` to get a nice printout with the cycle counts plus other statistics. +See the [ACC development guide](developing_acc.md#run-the-python-simulator) for more information about using the ACC simulator. ## SCA methodology -Current code for side channel analysis (SCA) on OTBN is in the [sw/device/sca](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/sw/device/sca) directory. +Current code for side channel analysis (SCA) on ACC is in the [sw/device/sca](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/sw/device/sca) directory. The main focus of this code is analysis of power/EM side channels. For timing side channels, we use [static analysis scripts](#static-checks) instead. This code runs on Ibex and communicates with scripts from the [ot-sca](https://github.com/lowRISC/ot-sca) repository. -Typically, the SCA code uses a binary entrypoint to the OTBN program that has more degrees of freedom than the one intended for production code. -For example, ECDSA-P256 has the entrypoint [p256_ecdsa](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/sw/otbn/crypto/p256_ecdsa.s) for production code, and [p256_ecdsa_sca](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/sw/otbn/crypto/p256_ecdsa_sca.s) for side channel analysis. +Typically, the SCA code uses a binary entrypoint to the ACC program that has more degrees of freedom than the one intended for production code. +For example, ECDSA-P256 has the entrypoint [p256_ecdsa](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/sw/acc/crypto/p256_ecdsa.s) for production code, and [p256_ecdsa_sca](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/sw/acc/crypto/p256_ecdsa_sca.s) for side channel analysis. They call the same underlying library, but the SCA-specific entrypoint allows the caller to select the per-signature secret value `k`, which is always randomly generated in the production-code version. We can then determine if information about `k` is leaking by trying different known values and seeing if values of `k` that are similar in a certain way have similarities in their traces. For example, during development we were able to fix a bug in our original implementation that leaked information about the number of leading zeroes in `k`. ## Modeling and formal methods -OTBN is well-suited to modeling because of its relatively simple ISA (52 instructions) and predictable timing behavior. -This means we can easily simulate OTBN's behavior in software and in formal methods tools. +ACC is well-suited to modeling because of its relatively simple ISA and predictable timing behavior. +This means we can easily simulate ACC's behavior in software and in formal methods tools. ### Machine-readable instruction specifications -OTBN instructions are recorded in [YAML files](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/otbn/data/bignum-insns.yml) that include syntax, encoding, and information-flow data. -The OTBN [ISA documentation](isa.md), assembler, simulation tools, and static checkers all read these files. +ACC instructions are recorded in [YAML files](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/acc/data/bignum-insns.yml) that include syntax, encoding, and information-flow data. +The ACC [ISA documentation](isa.md), assembler, simulation tools, and static checkers all read these files. -### OTBN simulator +### ACC simulator -The OTBN simulator is a Python model of OTBN that is regularly tested against the exact behavior of the SystemVerilog implementation. -Both software and hardware engineers on OpenTitan use it for debugging. -Detailed information on the OTBN simulator can be found [here](developing_otbn.md#run-the-python-simulator), but the highlights are: +The ACC simulator is a Python model of ACC that is regularly tested against the exact behavior of the SystemVerilog implementation. +Both software and hardware engineers use it for debugging. +Detailed information on the ACC simulator can be found [here](developing_acc.md#run-the-python-simulator), but the highlights are: - cycle-by-cycle printouts for instructions and updates to registers/flags/memory -- much faster than simulating OTBN in Verilator +- much faster than simulating ACC in Verilator -A typical workflow when developing for OTBN is to write both the program itself and a few self-contained tests that can run on the simulator. +A typical workflow when developing for ACC is to write both the program itself and a few self-contained tests that can run on the simulator. If the tests fail, then the cycle-by-cycle printouts help to determine what went wrong. -The simulator is also a good way to get accurate OTBN cycle counts. +The simulator is also a good way to get accurate ACC cycle counts. -You can see the current OTBN simulator tests under [sw/otbn/crypto/tests](https://github.com/lowRISC/opentitan/tree/master/sw/otbn/crypto/tests). +You can see the current ACC simulator tests under [sw/acc/crypto/tests](https://github.com/lowRISC/opentitan/tree/master/sw/acc/crypto/tests). ### Formal methods -OTBN is a large part of the reason OpenTitan has a long history of successful formal-methods collaborations. +ACC is a large part of the reason for a long history of successful formal-methods collaborations. -For example, the OTBN program we use for RSA signature verification in secure boot is [formally verified](https://www.andrew.cmu.edu/user/bparno/papers/galapagos.pdf) in Dafny/Vale. -The authors of the paper created a system called Galápagos, in which a proven-correct low-level implementation can be instantiated for different architectures, including OTBN. +For example, the ACC program we use for RSA signature verification in secure boot is [formally verified](https://www.andrew.cmu.edu/user/bparno/papers/galapagos.pdf) in Dafny/Vale. +The authors of the paper created a system called Galápagos, in which a proven-correct low-level implementation can be instantiated for different architectures, including ACC. For RSA, they proved that the low-level implementation was equivalent to modular exponentiation, i.e. that it indeed computed `(sig ^ e) mod n`, where `sig` is the signature and `(n, e)` is the RSA public key. -We use their OTBN code in production silicon. +Their ACC code is used in production silicon. There is no performance hit from the verified code, and since it is burned into hardware ROM it is essential that this code is correct. -We are also pursuing other ongoing collaborations in formal methods, including adding OTBN to the Jasmin compiler. -In the meantime, we occasionally prove small and particularly tricky parts of programs against simplified OTBN models in Coq, such as [here](https://github.com/lowRISC/opentitan/pull/19768). +We are also pursuing other ongoing collaborations in formal methods, including adding ACC to the Jasmin compiler. +In the meantime, we occasionally prove small and particularly tricky parts of programs against simplified ACC models in Coq, such as [here](https://github.com/lowRISC/opentitan/pull/19768). ### Static checks -Building on top of the OTBN simulator, we also have Python tools that model OTBN's control flow and statically: -- [check](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/otbn/util/check_const_time.py) if an OTBN program or function is constant-time relative to secrets -- [print](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/otbn/util/analyze_information_flow.py) out the information-flow graph for OTBN functions -- [determine](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/otbn/util/get_instruction_count_range.py) the minimum and maximum possible instruction count for a program +Building on top of the ACC simulator, we also have Python tools that model ACC's control flow and statically: +- [check](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/acc/util/check_const_time.py) if an ACC program or function is constant-time relative to secrets +- [print](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/acc/util/analyze_information_flow.py) out the information-flow graph for ACC functions +- [determine](https://github.com/lowRISC/opentitan/blob/7528f848214589e837ce3b0dacac8385c458b772/hw/ip/acc/util/get_instruction_count_range.py) the minimum and maximum possible instruction count for a program Some of these have Bazel build integration. -For example, many OTBN functions have a Bazel build target like this that runs the constant-time checker in CI: +For example, many ACC functions have a Bazel build target like this that runs the constant-time checker in CI: ``` -otbn_consttime_test( +acc_consttime_test( name = "p256_base_mult_consttime", subroutine = "p256_base_mult", deps = [ - "//sw/otbn/crypto:p256_ecdsa", + "//sw/acc/crypto:p256_ecdsa", ], ) ``` ## Future Ideas -For future versions of OTBN, we are considering: -- ISA extensions and more memory to support lattice-based cryptography -- A direct interface from OTBN to the [KMAC][kmac] hardware block, which would allow OTBN to directly run SHA-3 and SHAKE functions -- More isolation from Ibex, including potentially giving OTBN its own ROM so that Ibex doesn't need to load secrets into it +For future versions of ACC, we are considering: +- More isolation from Ibex, including potentially giving ACC its own ROM so that Ibex doesn't need to load secrets into it [kmac]: ../../../../hw/ip/kmac/README.md [keymgr]: ../../../../hw/ip/keymgr/README.md diff --git a/hw/ip/otbn/doc/otbn_operation.svg b/hw/ip/acc/doc/acc_operation.svg similarity index 100% rename from hw/ip/otbn/doc/otbn_operation.svg rename to hw/ip/acc/doc/acc_operation.svg diff --git a/hw/ip/otbn/doc/otbn_operational_states.svg b/hw/ip/acc/doc/acc_operational_states.svg similarity index 99% rename from hw/ip/otbn/doc/otbn_operational_states.svg rename to hw/ip/acc/doc/acc_operational_states.svg index d5890af9c1f..9f54901ee8e 100644 --- a/hw/ip/otbn/doc/otbn_operational_states.svg +++ b/hw/ip/acc/doc/acc_operational_states.svg @@ -7,7 +7,7 @@ stroke-linecap="square" stroke-miterlimit="10" id="svg119" - sodipodi:docname="otbn_operational_states.svg" + sodipodi:docname="acc_operational_states.svg" inkscape:version="1.2.1 (9c6d41e410, 2022-07-14)" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" diff --git a/hw/ip/otbn/doc/checklist.md b/hw/ip/acc/doc/checklist.md similarity index 96% rename from hw/ip/otbn/doc/checklist.md rename to hw/ip/acc/doc/checklist.md index e1581849c80..a2e443dedde 100644 --- a/hw/ip/otbn/doc/checklist.md +++ b/hw/ip/acc/doc/checklist.md @@ -1,6 +1,6 @@ -# OTBN Checklist +# ACC Checklist -This checklist is for [Hardware Stage](../../../../doc/project_governance/development_stages.md) transitions for the [OTBN peripheral.](../README.md) +This checklist is for [Hardware Stage](../../../../doc/project_governance/development_stages.md) transitions for the [ACC peripheral.](../README.md) All checklist items refer to the content in the [Checklist.](../../../../doc/project_governance/checklist/README.md) ## Design Checklist @@ -9,7 +9,7 @@ All checklist items refer to the content in the [Checklist.](../../../../doc/pro Type | Item | Resolution | Note/Collaterals --------------|--------------------------------|-------------|------------------ -Documentation | [SPEC_COMPLETE][] | Done | [OTBN Design Spec](../README.md). The specification is feature-complete, we were able to successfully run larger chunks of crypto code with the described feature set. At the same time, the specification has (known and unknown) issues, such as incomplete or buggy descriptions of individual instructions. These issues are being worked on as they are discovered while the design is in the D1 stage. +Documentation | [SPEC_COMPLETE][] | Done | [ACC Design Spec](../README.md). The specification is feature-complete, we were able to successfully run larger chunks of crypto code with the described feature set. At the same time, the specification has (known and unknown) issues, such as incomplete or buggy descriptions of individual instructions. These issues are being worked on as they are discovered while the design is in the D1 stage. Documentation | [CSR_DEFINED][] | Done | RTL | [CLKRST_CONNECTED][] | Done | RTL | [IP_TOP][] | Done | @@ -33,7 +33,7 @@ Code Quality | [LINT_SETUP][] | Done | Type | Item | Resolution | Note/Collaterals --------------|---------------------------|-------------|------------------ -Documentation | [NEW_FEATURES][] | Done | New features are [Key Sideload](https://www.github.com/lowrisc/opentitan/pull/8650), [Private OTBN DMem](https://www.github.com/lowrisc/opentitan/pull/8890), [XoShiRo PRNG](https://www.github.com/lowrisc/opentitan/pull/7944) and [Prefetch Stage](https://www.github.com/lowrisc/opentitan/issues/8898) +Documentation | [NEW_FEATURES][] | Done | New features are [Key Sideload](https://www.github.com/lowrisc/opentitan/pull/8650), [Private ACC DMem](https://www.github.com/lowrisc/opentitan/pull/8890), [XoShiRo PRNG](https://www.github.com/lowrisc/opentitan/pull/7944) and [Prefetch Stage](https://www.github.com/lowrisc/opentitan/issues/8898) Documentation | [BLOCK_DIAGRAM][] | Done | Documentation | [DOC_INTERFACE][] | Done | Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. @@ -123,8 +123,8 @@ Review | Signoff date | Not Started | Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ -Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTBN DV document](../dv/README.md) -Documentation | [TESTPLAN_COMPLETED][] | Done | [OTBN Testplan](../dv/README.md#testplan) +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [ACC DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [ACC Testplan](../dv/README.md#testplan) Testbench | [TB_TOP_CREATED][] | Done | Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | Testbench | [SIM_TB_ENV_CREATED][] | Done | diff --git a/hw/ip/acc/doc/developing_acc.md b/hw/ip/acc/doc/developing_acc.md new file mode 100644 index 00000000000..c39162da819 --- /dev/null +++ b/hw/ip/acc/doc/developing_acc.md @@ -0,0 +1,111 @@ +# Asymmetric Cryptographic Coprocessor (ACC) + +This directory contains the implementation of the Asymmetric Cryptographic Coprocessor (ACC). +ACC is a coprocessor for asymmetric cryptographic operations like RSA or Elliptic Curve Cryptography (ECC). + +See [here](../README.md) for documentation on the current version of ACC; documentation matching the code in this directory can be found in the `doc` directory. + +ACC is under active development. +Please ask questions and report issues through the [GitHub issue tracker](https://github.com/lowRISC/opentitan/issues). + +## Develop ACC + +### Build ACC software + +An assembler, linker and disassembler for ACC can be found in `hw/ip/acc/util` (For more details about these tools see the [user guide](../../../../doc/contributing/sw/acc_sw.md)). + +These tools are wrappers around a RISC-V and binutils toolchain so one must be available. +The toolchain can be installed with the [`util/get-toolchain.py`](../../../../util/get-toolchain.py) script. +Simply call the script from `$REPO_TOP` and make sure to select the correct architecture. + +When the toolchain is installed, the `acc_as.py` and `acc_ld.py` can be used to build .elf files for use with simulations. +They work similarly to binutils programs they wrap. + +``` +hw/ip/acc/util/acc_as.py -o prog_bin/prog.o prog.s +hw/ip/acc/util/acc_ld.py -o prog_bin/prog.elf prog_bin/prog.o +``` + +Will assemble and link `prog.s` resulting in `prog_bin/prog.elf` that can be run directly on the ISS or the standalone RTL simulation. + +### Work with the ISA + +The instruction set is described in machine readable form in `data/insns.yml`. +This is parsed by Python code in `util/insn_yaml.py`, which runs various basic checks on the data. +The binutils-based toolchain described above uses this information. +Other users include: + + - `util/yaml_to_doc.py`: Generates a Markdown snippet which is included in the ACC specification. + + - `dv/rig/acc-rig`: A random instruction generator for ACC. See dv/rig/README.md for further information. + +### Run the Python simulator +The quickest way to run an ACC-only program is to use the Python simulator. +First, generate a `.elf.` file either using the usual build process or by manually running `acc_as.py` and `acc_ld.py` as shown above. +Then, from `$REPO_TOP`: +```console +$ hw/ip/acc/dv/accsim/standalone.py -t path/to/prog.elf +``` + +### Run the standalone RTL simulation +A standalone environment to run ACC alone in Verilator is included. +Build it with `fusesoc` as follows: + +```sh +fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ip:acc_top_sim +``` + +It includes functionality to set the initial Dmem and Imem contents from a .elf file. +The start address is hard coded to 0. +Modify the `ImemStartAddr` parameter in `./dv/verilator/acc_top_sim.sv` to change this. +A .elf (see above for build instructions) can be loaded and run as follows: + +```sh +./build/lowrisc_ip_acc_top_sim_0.1/sim-verilator/Vacc_top_sim \ + --load-elf=prog_bin/prog.elf +``` + +The simulation automatically halts on an `ecall` instruction and prints the final register values. +The ISS is run in parallel and final register and memory state will be cross-checked. + +Tracing functionality is available in the `Vacc_top_sim` binary. +To obtain a full .fst wave trace pass the `-t` flag. +To get an instruction level trace pass the `--acc-trace-file=trace.log` argument. +The instruction trace format is documented in `hw/ip/acc/dv/tracer`. + +To run several auto-generated binaries against the Verilated RTL, use the script at `dv/verilator/run-some.py`. +For example, + +```sh +hw/ip/acc/dv/verilator/run-some.py --size=1500 --count=50 X +``` + +will generate and run 50 binaries, each of which will execute up to 1500 instructions when run. +The generated binaries, a Verilated model and the output from running them can all be found in the directory called `X`. + +### Run the smoke test + +A smoke test which exercises some functionality of ACC can be found, together with its expected outputs (in the form of final register values), in `./hw/ip/acc/dv/smoke`. +The test can be run using a script. + +```sh +hw/ip/acc/dv/smoke/run_smoke.sh +``` + +This will build the standalone simulation, build the smoke test binary, run it and check the results are as expected. + +### Run the ISS on its own + +There are currently two versions of the ISS and they can be found in `dv/accsim`. +The easiest to use is `dv/accsim/standalone.py`. +This takes an ACC binary as an ELF file (as produced by the standard linker script for `acc_ld.py`) and can dump the resulting DMEM if given the `--dmem-dump` argument. +To see an instruction trace, pass the `--verbose` flag. + +There is also `dv/accsim/accsim.py`. +This takes flat binary files with the contents of IMEM and DMEM and, when finished, generates a cycle count and dumps DMEM contents. +This is used to implement the model inside of simulation, but is probably not very convenient for command-line use otherwise. + +## Test the ISS + +The ISS has a simple test suite, which runs various instructions and makes sure they behave as expected. +You can find the tests in `dv/accsim/test` and can run them with `make -C dv/accsim test`. diff --git a/hw/ip/otbn/doc/interfaces.md b/hw/ip/acc/doc/interfaces.md similarity index 57% rename from hw/ip/otbn/doc/interfaces.md rename to hw/ip/acc/doc/interfaces.md index 12ff597b8b1..73b8d6964ae 100644 --- a/hw/ip/otbn/doc/interfaces.md +++ b/hw/ip/acc/doc/interfaces.md @@ -1,7 +1,7 @@ # Hardware Interfaces - -Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`otbn`** has the following hardware interfaces defined + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`acc`** has the following hardware interfaces defined - Primary Clock: **`clk_i`** - Other Clocks: **`clk_edn_i`**, **`clk_otp_i`** - Bus Device Interfaces (TL-UL): **`tl`** @@ -12,7 +12,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | Port Name | Package::Struct | Type | Act | Width | Description | |:-----------------|:--------------------------------|:--------|:------|--------:|:--------------| -| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | req | 1 | | +| acc_otp_key | otp_ctrl_pkg::acc_otp_key | req_rsp | req | 1 | | | edn_rnd | edn_pkg::edn | req_rsp | req | 1 | | | edn_urnd | edn_pkg::edn | req_rsp | req | 1 | | | kmac_data | kmac_pkg::app | req_rsp | req | 1 | | @@ -24,14 +24,14 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | | lc_rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | | lc_rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| keymgr_key | keymgr_pkg::otbn_key_req | uni | rcv | 1 | | +| keymgr_key | keymgr_pkg::acc_key_req | uni | rcv | 1 | | | tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Interrupts -| Interrupt Name | Type | Description | -|:-----------------|:-------|:----------------------------------| -| done | Event | OTBN has completed the operation. | +| Interrupt Name | Type | Description | +|:-----------------|:-------|:---------------------------------| +| done | Event | ACC has completed the operation. | ## Security Alerts @@ -42,70 +42,70 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## Security Countermeasures -| Countermeasure ID | Description | -|:-----------------------------------------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| OTBN.MEM.SCRAMBLE | Both the imem and dmem are scrambled by using prim_ram_1p_scr. | -| OTBN.DATA.MEM.INTEGRITY | Dmem is protected with ECC integrity. This is carried through to OTBN's register file. | -| OTBN.INSTRUCTION.MEM.INTEGRITY | Imem is protected with ECC integrity. This is carried through into OTBN's execute stage. | -| OTBN.BUS.INTEGRITY | End-to-end bus integrity scheme. | -| OTBN.CONTROLLER.FSM.GLOBAL_ESC | The controller FSM moves to a terminal error state upon global escalation. | -| OTBN.CONTROLLER.FSM.LOCAL_ESC | The controller FSM moves to a terminal error state upon local escalation. Can be triggered by CONTROLLER.FSM.SPARSE, SCRAMBLE_CTRL.FSM.SPARSE, and START_STOP_CTRL.FSM.SPARSE. | -| OTBN.CONTROLLER.FSM.SPARSE | The controller FSM uses a sparse state encoding. | -| OTBN.SCRAMBLE.KEY.SIDELOAD | The scrambling key is sideloaded from OTP and thus unreadable by SW. | -| OTBN.SCRAMBLE_CTRL.FSM.LOCAL_ESC | The scramble control FSM moves to a terminal error state upon local escalation. Can be triggered by SCRAMBLE_CTRL.FSM.SPARSE. | -| OTBN.SCRAMBLE_CTRL.FSM.SPARSE | The scramble control FSM uses a sparse state encoding. | -| OTBN.START_STOP_CTRL.FSM.GLOBAL_ESC | The start-stop control FSM moves to a terminal error state upon global escalation. | -| OTBN.START_STOP_CTRL.FSM.LOCAL_ESC | The start-stop control FSM moves to a terminal error state upon local escalation. Can be triggered by START_STOP_CTRL.FSM.SPARSE. | -| OTBN.START_STOP_CTRL.FSM.SPARSE | The start-stop control FSM uses a sparse state encoding. | -| OTBN.DATA_REG_SW.SCA | Blanking of bignum data paths when unused by the executing instruction. | -| OTBN.CTRL.REDUN | Check pre-decoded control matches separately decoded control from main decoder. This includes control signals used for blanking, pushing/popping the call stack, controlling loop and branch/jump instructions, as well as the actual branch target. | -| OTBN.PC.CTRL_FLOW.REDUN | Check prefetch stage PC and execute stage PC match. The prefetch stage and execute stage store their PC's separately and have separate increment calculations. | -| OTBN.RND.BUS.CONSISTENCY | Comparison on successive bus values received over the EDN RND interface. | -| OTBN.RND.RNG.DIGEST | Checking that the random numbers received over the EDN RND interface have not been generated from entropy that failed the FIPS health checks in the entropy source. | -| OTBN.RF_BASE.DATA_REG_SW.INTEGRITY | Register file is protected with ECC integrity. | -| OTBN.RF_BASE.DATA_REG_SW.GLITCH_DETECT | This countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes. | -| OTBN.STACK_WR_PTR.CTR.REDUN | The write pointer of the stack (used for calls and loops) is redundant. If the two instances of the counter mismatch, an error is emitted. | -| OTBN.RF_BIGNUM.DATA_REG_SW.INTEGRITY | Register file is protected with ECC integrity. | -| OTBN.RF_BIGNUM.DATA_REG_SW.GLITCH_DETECT | This countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes. | -| OTBN.LOOP_STACK.CTR.REDUN | The iteration counter of each entry in the loop step uses cross counts via prim_count. | -| OTBN.LOOP_STACK.ADDR.INTEGRITY | Loop start and end address on the loop stack are protected with ECC integrity. | -| OTBN.CALL_STACK.ADDR.INTEGRITY | Call stack entries are protected with ECC integrity. | -| OTBN.START_STOP_CTRL.STATE.CONSISTENCY | The secure wipe handshake between otbn_controller and otbn_start_stop_control uses a level-based req/ack interface. At the otbn_controller end, there is a check for unexpected acks. In otbn_start_stop_control, there is a check for secure wipe requests when we aren't in a state that allows it, and also a check for if the request drops at an unexpected time. | -| OTBN.DATA.MEM.SEC_WIPE | Rotate the scrambling key, effectively wiping the dmem. Initiated on command, upon fatal errors and before RMA entry. | -| OTBN.INSTRUCTION.MEM.SEC_WIPE | Rotate the scrambling key, effectively wiping the imem. Initiated on command, upon fatal errors and before RMA entry. | -| OTBN.DATA_REG_SW.SEC_WIPE | Securely wipe programmer visible OTBN register (GPRs, WDRs, CSRs, WSRs) state with random data. Initiated after reset, at the end of any OTBN operation, upon recoverable and fatal errors, and before RMA entry. | -| OTBN.WRITE.MEM.INTEGRITY | A software visible checksum is calculated for all dmem and imem writes | -| OTBN.CTRL_FLOW.COUNT | A software visible count of instructions executed | -| OTBN.CTRL_FLOW.SCA | OTBN architecture does not have any data dependent timing behaviour | -| OTBN.DATA.MEM.SW_NOACCESS | A portion of DMEM is invisible to CPU software | -| OTBN.KEY.SIDELOAD | Keys can be sideloaded without exposing them to the CPU | -| OTBN.TLUL_FIFO.CTR.REDUN | The TL-UL response FIFO pointers are implemented with duplicate counters. | +| Countermeasure ID | Description | +|:----------------------------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| ACC.MEM.SCRAMBLE | Both the imem and dmem are scrambled by using prim_ram_1p_scr. | +| ACC.DATA.MEM.INTEGRITY | Dmem is protected with ECC integrity. This is carried through to ACC's register file. | +| ACC.INSTRUCTION.MEM.INTEGRITY | Imem is protected with ECC integrity. This is carried through into ACC's execute stage. | +| ACC.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| ACC.CONTROLLER.FSM.GLOBAL_ESC | The controller FSM moves to a terminal error state upon global escalation. | +| ACC.CONTROLLER.FSM.LOCAL_ESC | The controller FSM moves to a terminal error state upon local escalation. Can be triggered by CONTROLLER.FSM.SPARSE, SCRAMBLE_CTRL.FSM.SPARSE, and START_STOP_CTRL.FSM.SPARSE. | +| ACC.CONTROLLER.FSM.SPARSE | The controller FSM uses a sparse state encoding. | +| ACC.SCRAMBLE.KEY.SIDELOAD | The scrambling key is sideloaded from OTP and thus unreadable by SW. | +| ACC.SCRAMBLE_CTRL.FSM.LOCAL_ESC | The scramble control FSM moves to a terminal error state upon local escalation. Can be triggered by SCRAMBLE_CTRL.FSM.SPARSE. | +| ACC.SCRAMBLE_CTRL.FSM.SPARSE | The scramble control FSM uses a sparse state encoding. | +| ACC.START_STOP_CTRL.FSM.GLOBAL_ESC | The start-stop control FSM moves to a terminal error state upon global escalation. | +| ACC.START_STOP_CTRL.FSM.LOCAL_ESC | The start-stop control FSM moves to a terminal error state upon local escalation. Can be triggered by START_STOP_CTRL.FSM.SPARSE. | +| ACC.START_STOP_CTRL.FSM.SPARSE | The start-stop control FSM uses a sparse state encoding. | +| ACC.DATA_REG_SW.SCA | Blanking of bignum data paths when unused by the executing instruction. | +| ACC.CTRL.REDUN | Check pre-decoded control matches separately decoded control from main decoder. This includes control signals used for blanking, pushing/popping the call stack, controlling loop and branch/jump instructions, as well as the actual branch target. | +| ACC.PC.CTRL_FLOW.REDUN | Check prefetch stage PC and execute stage PC match. The prefetch stage and execute stage store their PC's separately and have separate increment calculations. | +| ACC.RND.BUS.CONSISTENCY | Comparison on successive bus values received over the EDN RND interface. | +| ACC.RND.RNG.DIGEST | Checking that the random numbers received over the EDN RND interface have not been generated from entropy that failed the FIPS health checks in the entropy source. | +| ACC.RF_BASE.DATA_REG_SW.INTEGRITY | Register file is protected with ECC integrity. | +| ACC.RF_BASE.DATA_REG_SW.GLITCH_DETECT | This countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes. | +| ACC.STACK_WR_PTR.CTR.REDUN | The write pointer of the stack (used for calls and loops) is redundant. If the two instances of the counter mismatch, an error is emitted. | +| ACC.RF_BIGNUM.DATA_REG_SW.INTEGRITY | Register file is protected with ECC integrity. | +| ACC.RF_BIGNUM.DATA_REG_SW.GLITCH_DETECT | This countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes. | +| ACC.LOOP_STACK.CTR.REDUN | The iteration counter of each entry in the loop step uses cross counts via prim_count. | +| ACC.LOOP_STACK.ADDR.INTEGRITY | Loop start and end address on the loop stack are protected with ECC integrity. | +| ACC.CALL_STACK.ADDR.INTEGRITY | Call stack entries are protected with ECC integrity. | +| ACC.START_STOP_CTRL.STATE.CONSISTENCY | The secure wipe handshake between acc_controller and acc_start_stop_control uses a level-based req/ack interface. At the acc_controller end, there is a check for unexpected acks. In acc_start_stop_control, there is a check for secure wipe requests when we aren't in a state that allows it, and also a check for if the request drops at an unexpected time. | +| ACC.DATA.MEM.SEC_WIPE | Rotate the scrambling key, effectively wiping the dmem. Initiated on command, upon fatal errors and before RMA entry. | +| ACC.INSTRUCTION.MEM.SEC_WIPE | Rotate the scrambling key, effectively wiping the imem. Initiated on command, upon fatal errors and before RMA entry. | +| ACC.DATA_REG_SW.SEC_WIPE | Securely wipe programmer visible ACC register (GPRs, WDRs, CSRs, WSRs) state with random data. Initiated after reset, at the end of any ACC operation, upon recoverable and fatal errors, and before RMA entry. | +| ACC.WRITE.MEM.INTEGRITY | A software visible checksum is calculated for all dmem and imem writes | +| ACC.CTRL_FLOW.COUNT | A software visible count of instructions executed | +| ACC.CTRL_FLOW.SCA | ACC architecture does not have any data dependent timing behaviour | +| ACC.DATA.MEM.SW_NOACCESS | A portion of DMEM is invisible to CPU software | +| ACC.KEY.SIDELOAD | Keys can be sideloaded without exposing them to the CPU | +| ACC.TLUL_FIFO.CTR.REDUN | The TL-UL response FIFO pointers are implemented with duplicate counters. | ## Hardware Interface Requirements -OTBN connects to other components in an OpenTitan system. +ACC connects to other components in a top-level system. This section lists requirements on those interfaces that go beyond the physical connectivity. ### Entropy Distribution Network (EDN) -OTBN has two EDN connections: `edn_urnd` and `edn_rnd`. -What kind of randomness is provided on the EDN connections is configurable at runtime, but unknown to OTBN. -To maintain its security properties, OTBN requires the following configuration for the two EDN connections: +ACC has two EDN connections: `edn_urnd` and `edn_rnd`. +What kind of randomness is provided on the EDN connections is configurable at runtime, but unknown to ACC. +To maintain its security properties, ACC requires the following configuration for the two EDN connections: -* OTBN has no specific requirements on the randomness drawn from `edn_urnd`. +* ACC has no specific requirements on the randomness drawn from `edn_urnd`. For performance reasons, requests on this EDN connection should be answered quickly. * `edn_rnd` must provide AIS31-compliant class PTG.3 random numbers. The randomness from this interface is made available through the `RND` WSR and intended to be used for key generation. ### Life Cycle Controller (LC_CTRL) -OTBN has three LC_CTRL connections: one for triggering life cycle escalation requests (`lc_escalate_en`) and two for handling RMA entry (`lc_rma_req/ack`). +ACC has three LC_CTRL connections: one for triggering life cycle escalation requests (`lc_escalate_en`) and two for handling RMA entry (`lc_rma_req/ack`). -As LC_CTRL might sit in a different clock domain and since all these connections are using multi-bit signals, OTBN might observe staggered signal transitions due to the clock domain crossings. +As LC_CTRL might sit in a different clock domain and since all these connections are using multi-bit signals, ACC might observe staggered signal transitions due to the clock domain crossings. To avoid spurious life cycle escalations and to enable reliable RMA entry, it should be ensured that: -* The `lc_escalate_en` and `lc_rma_req` inputs are stably driven to `lc_ctrl_pkg::Off` before releasing the reset of OTBN. -* When triggering RMA entry, the `lc_rma_req` input switches from `lc_ctrl_pkg::Off` to `lc_ctrl_pkg::On` exactly once, and then remains `On` until OTBN signals completion of the secure wipe operation with the `lc_rma_ack` output switching to `lc_ctrl_pkg::On`. +* The `lc_escalate_en` and `lc_rma_req` inputs are stably driven to `lc_ctrl_pkg::Off` before releasing the reset of ACC. +* When triggering RMA entry, the `lc_rma_req` input switches from `lc_ctrl_pkg::Off` to `lc_ctrl_pkg::On` exactly once, and then remains `On` until ACC signals completion of the secure wipe operation with the `lc_rma_ack` output switching to `lc_ctrl_pkg::On`. diff --git a/hw/ip/otbn/doc/isa.md b/hw/ip/acc/doc/isa.md similarity index 89% rename from hw/ip/otbn/doc/isa.md rename to hw/ip/acc/doc/isa.md index 440497e8c55..72c7060e017 100644 --- a/hw/ip/otbn/doc/isa.md +++ b/hw/ip/acc/doc/isa.md @@ -1,7 +1,7 @@ -# OpenTitan Big Number Accelerator (OTBN) Instruction Set Architecture +# Asymmetric Cryptographic Coprocessor (ACC) Instruction Set Architecture -This document describes the instruction set for OTBN. -For more details about the processor itself, see the [OTBN Technical Specification](../README.md). +This document describes the instruction set for ACC. +For more details about the processor itself, see the [ACC Technical Specification](../README.md). In particular, this document assumes knowledge of the *Processor State* section from that guide. The instruction set is split into *base* and *big number* subsets. @@ -27,7 +27,7 @@ For example, the `SW` instruction's `offset` operand is split across two ranges # Pseudo-code for operation descriptions Each instruction has an Operation section. -This is written in a Python-like pseudo-code, generated from the instruction set simulator (which can be found at `hw/ip/otbn/dv/otbnsim`). +This is written in a Python-like pseudo-code, generated from the instruction set simulator (which can be found at `hw/ip/acc/dv/accsim`). The code is generated from Python, but there are some extra changes made to aid readability. All instruction operands are considered to be in scope and have integer values. @@ -104,16 +104,16 @@ def extract_quarter_word(value: int, qwsel: int) -> int: # Errors -OTBN can detect various errors when it is operating. -For details about OTBN's approach to error handling, see the [Errors section](../README.md#design-details-errors) of the Technical Specification. +ACC can detect various errors when it is operating. +For details about ACC's approach to error handling, see the [Errors section](../README.md#design-details-errors) of the Technical Specification. The instruction descriptions below describe any software errors that executing the instruction can cause. These errors are listed explicitly and also appear in the pseudo-code description, where the code sets a bit in the `ERR_BITS` register with a call to `state.stop_at_end_of_cycle()`. Other errors are possible at runtime. Specifically, any instruction that reads from a GPR or WDR might detect a register integrity error. -In this case, OTBN will set the `REG_INTG_VIOLATION` bit. +In this case, ACC will set the `REG_INTG_VIOLATION` bit. Similarly, an instruction that loads from memory might detect a DMEM integrity error. -In this case, OTBN will set the `DMEM_INTG_VIOLATION` bit. +In this case, ACC will set the `DMEM_INTG_VIOLATION` bit. TODO: Specify interactions between these fatal errors and any other errors. @@ -122,8 +122,8 @@ In particular, how do they interact with instructions that could cause other err # Base Instruction Subset -{{#otbn-isa base }} +{{#acc-isa base }} # Big Number Instruction Subset -{{#otbn-isa bignum }} +{{#acc-isa bignum }} diff --git a/hw/ip/otbn/doc/programmers_guide.md b/hw/ip/acc/doc/programmers_guide.md similarity index 79% rename from hw/ip/otbn/doc/programmers_guide.md rename to hw/ip/acc/doc/programmers_guide.md index e195a0ed780..386de315839 100644 --- a/hw/ip/otbn/doc/programmers_guide.md +++ b/hw/ip/acc/doc/programmers_guide.md @@ -1,33 +1,33 @@ # Programmer's Guide -## Running applications on OTBN +## Running applications on ACC -OTBN is a specialized coprocessor which is used from the host CPU. -This section describes how to interact with OTBN from the host CPU to execute an existing OTBN application. -The section [Writing OTBN applications](#writing-otbn-applications) describes how to write such applications. +ACC is a specialized coprocessor which is used from the host CPU. +This section describes how to interact with ACC from the host CPU to execute an existing ACC application. +The section [Writing ACC applications](#writing-acc-applications) describes how to write such applications. ### High-level operation sequence -The high-level sequence by which the host processor should use OTBN is as follows. +The high-level sequence by which the host processor should use ACC is as follows. 1. Optional: Initialise [`LOAD_CHECKSUM`](registers.md#load_checksum). -1. Write the OTBN application binary to [`IMEM`](registers.md#imem), starting at address 0. +1. Write the ACC application binary to [`IMEM`](registers.md#imem), starting at address 0. 1. Optional: Write constants and input arguments, as mandated by the calling convention of the loaded application, to the half of DMEM accessible through the [`DMEM`](registers.md#dmem) window. 1. Optional: Read back [`LOAD_CHECKSUM`](registers.md#load_checksum) and perform an integrity check. -1. Start the operation on OTBN by [issuing the `EXECUTE` command](./theory_of_operation.md#operations-and-commands). +1. Start the operation on ACC by [issuing the `EXECUTE` command](./theory_of_operation.md#operations-and-commands). Now neither data nor instruction memory may be accessed from the host CPU. - After it has been started the OTBN application runs to completion without further interaction with the host. + After it has been started the ACC application runs to completion without further interaction with the host. 1. Wait for the operation to complete (see below). - As soon as the OTBN operation has completed the data and instruction memories can be accessed again from the host CPU. + As soon as the ACC operation has completed the data and instruction memories can be accessed again from the host CPU. 1. Check if the operation was successful by reading the [`ERR_BITS`](registers.md#err_bits) register. 1. Optional: Retrieve results by reading [`DMEM`](registers.md#dmem), as mandated by the calling convention of the loaded application. -OTBN applications are run to completion. +ACC applications are run to completion. The host CPU can determine if an application has completed by either polling [`STATUS`](registers.md#status) or listening for an interrupt. * To poll for a completed operation, software should repeatedly read the [`STATUS`](registers.md#status) register. The operation is complete if [`STATUS`](registers.md#status) is `IDLE` or `LOCKED`, otherwise the operation is in progress. - When [`STATUS`](registers.md#status) has become `LOCKED` a fatal error has occurred and OTBN must be reset to perform further operations. + When [`STATUS`](registers.md#status) has become `LOCKED` a fatal error has occurred and ACC must be reset to perform further operations. * Alternatively, software can listen for the `done` interrupt to determine if the operation has completed. The standard sequence of working with interrupts has to be followed, i.e. the interrupt has to be enabled, an interrupt service routine has to be registered, etc. The [DIF](#device-interface-functions-difs) contains helpers to do so conveniently. @@ -35,36 +35,36 @@ The host CPU can determine if an application has completed by either polling [`S Note: This operation sequence only covers functional aspects. Depending on the application additional steps might be necessary, such as deleting secrets from the memories. -## Writing OTBN applications +## Writing ACC applications -OTBN applications are (small) pieces of software written in OTBN assembly. -The full instruction set is described in the [ISA manual](./isa.md), and example software is available in the `sw/otbn` directory of the OpenTitan source tree. +ACC applications are (small) pieces of software written in ACC assembly. +The full instruction set is described in the [ISA manual](./isa.md), and example software is available in the `sw/acc` directory of the source tree. -A hands-on user guide to develop OTBN software can be found in the section [Writing and building software for OTBN](../../../../doc/contributing/sw/otbn_sw.md). +A hands-on user guide to develop ACC software can be found in the section [Writing and building software for ACC](../../../../doc/contributing/sw/acc_sw.md). ### Toolchain support -OTBN comes with a toolchain consisting of an assembler, a linker, and helper tools such as objdump. +ACC comes with a toolchain consisting of an assembler, a linker, and helper tools such as objdump. The toolchain wraps a RV32 GCC toolchain and supports many of its features. The following tools are available: -* `otbn_as.py`: The OTBN assembler. -* `otbn_ld.py`: The OTBN linker. -* `otbn_objdump.py`: objdump for OTBN. +* `acc_as.py`: The ACC assembler. +* `acc_ld.py`: The ACC linker. +* `acc_objdump.py`: objdump for ACC. Other tools from the RV32 toolchain can be used directly, such as objcopy. -### Passing of data between the host CPU and OTBN +### Passing of data between the host CPU and ACC -Passing data between the host CPU and OTBN is done through the first 2kiB of data memory (DMEM). -No standard or required calling convention exists, every application is free to pass data in and out of OTBN in whatever format it finds convenient. -All data passing must be done when OTBN [is idle](./theory_of_operation.md#operational-states); otherwise both the instruction and the data memory are inaccessible from the host CPU. +Passing data between the host CPU and ACC is done through the first 2kiB of data memory (DMEM). +No standard or required calling convention exists, every application is free to pass data in and out of ACC in whatever format it finds convenient. +All data passing must be done when ACC [is idle](./theory_of_operation.md#operational-states); otherwise both the instruction and the data memory are inaccessible from the host CPU. ### Returning from an application -The software running on OTBN signals completion by executing the [`ECALL`](isa.md#ecall) instruction. +The software running on ACC signals completion by executing the [`ECALL`](isa.md#ecall) instruction. -Once OTBN has executed the [`ECALL`](isa.md#ecall) instruction, the following things happen: +Once ACC has executed the [`ECALL`](isa.md#ecall) instruction, the following things happen: - No more instructions are fetched or executed. - A [secure wipe of internal state](./theory_of_operation.md#internal-state-secure-wipe) is performed. @@ -72,15 +72,15 @@ Once OTBN has executed the [`ECALL`](isa.md#ecall) instruction, the following th - The current operation is marked as complete by setting [`INTR_STATE.done`](registers.md#intr_state) and clearing [`STATUS`](registers.md#status). The first 2kiB of DMEM can be used to pass data back to the host processor, e.g. a "return value" or an "exit code". -Refer to the section [Passing of data between the host CPU and OTBN](#passing-of-data-between-the-host-cpu-and-otbn) for more information. +Refer to the section [Passing of data between the host CPU and ACC](#passing-of-data-between-the-host-cpu-and-acc) for more information. ### Using hardware loops -OTBN provides two hardware loop instructions: [`LOOP`](isa.md#loop) and [`LOOPI`](isa.md#loopi) . +ACC provides two hardware loop instructions: [`LOOP`](isa.md#loop) and [`LOOPI`](isa.md#loopi) . #### Loop nesting -OTBN permits loop nesting and branches and jumps inside loops. +ACC permits loop nesting and branches and jumps inside loops. However, it doesn't have support for early termination of loops: there's no way to pop an entry from the loop stack without executing the last instruction of the loop the correct number of times. It can also only pop one level of the loop stack per instruction. @@ -89,7 +89,7 @@ To avoid polluting the loop stack and avoid surprising behaviour, the programmer * Nested loops have distinct end addresses. * The end instruction of an outer loop is not executed before an inner loop finishes. -OTBN does not detect these conditions being violated, so no error will be signaled should they occur. +ACC does not detect these conditions being violated, so no error will be signaled should they occur. (Note indentation in the code examples is for clarity and has no functional impact.) @@ -146,7 +146,7 @@ outer_body: ### Algorithic Examples: Multiplication with BN.MULQACC -The big number instruction subset of OTBN generally operates on WLEN bit numbers. +The big number instruction subset of ACC generally operates on WLEN bit numbers. [`BN.MULQACC`](isa.md#bnmulqacc) operates with WLEN/4 bit operands (with a full WLEN accumulator). This section outlines two techniques to perform larger multiplies by composing multiple [`BN.MULQACC`](isa.md#bnmulqacc) instructions. @@ -351,14 +351,14 @@ The outlined technique can be extended to arbitrary bit widths but requires unro
RW MOD - The modulus used by the {{#otbn-insn-ref BN.ADDM}} and {{#otbn-insn-ref BN.SUBM}} instructions. + The modulus used by the {{#acc-insn-ref BN.ADDM}} and {{#acc-insn-ref BN.SUBM}} instructions. This WSR is also visible as CSRs `MOD0` through to `MOD7`.
RW ACC - The accumulator register used by the {{#otbn-insn-ref BN.MULQACC}} instruction. + The accumulator register used by the {{#acc-insn-ref BN.MULQACC}} instruction.
RW ACCH - The high bits of the accumulator register used by the {{#otbn-insn-ref BN.MULV}} instruction. + The high bits of the accumulator register used by the {{#acc-insn-ref BN.MULV}} instruction.
RO KEY_S0_L - Bits [255:0] of share 0 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [255:0] of share 0 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md).
A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key. 		KEY_S0_H Bits [255:128] of this register are always zero. - Bits [127:0] contain bits [383:256] of share 0 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [127:0] contain bits [383:256] of share 0 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md).
A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key. 		RO KEY_S1_L - Bits [255:0] of share 1 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [255:0] of share 1 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md).
A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key. 		KEY_S1_H Bits [255:128] of this register are always zero. - Bits [127:0] contain bits [383:256] of share 1 of the 384b OTBN sideload key provided by the [Key Manager](../keymgr/README.md). + Bits [127:0] contain bits [383:256] of share 1 of the 384b ACC sideload key provided by the [Key Manager](../keymgr/README.md).
A `KEY_INVALID` software error is raised on read if the Key Manager has not provided a valid key.
-Code snippets giving examples of 256x256 and 384x384 multiplies can be found in `sw/otbn/code-snippets/mul256.s` and `sw/otbn/code-snippets/mul384.s`. +Code snippets giving examples of 256x256 and 384x384 multiplies can be found in `sw/acc/code-snippets/mul256.s` and `sw/acc/code-snippets/mul384.s`. ## Device Interface Functions (DIFs) -- [Device Interface Functions](../../../../sw/device/lib/dif/dif_otbn.h) +- [Device Interface Functions](../../../../sw/device/lib/dif/dif_acc.h) ## Driver -A higher-level driver for the OTBN block is available at `sw/device/lib/runtime/otbn.h`. +A higher-level driver for the ACC block is available at `sw/device/lib/runtime/acc.h`. -Another driver for OTBN is part of the silicon creator code at `sw/device/silicon_creator/lib/drivers/otbn.h`. +Another driver for ACC is part of the silicon creator code at `sw/device/silicon_creator/lib/drivers/acc.h`. diff --git a/hw/ip/otbn/doc/registers.md b/hw/ip/acc/doc/registers.md similarity index 77% rename from hw/ip/otbn/doc/registers.md rename to hw/ip/acc/doc/registers.md index cfe8fa70842..429e0d7896d 100644 --- a/hw/ip/otbn/doc/registers.md +++ b/hw/ip/acc/doc/registers.md @@ -1,23 +1,23 @@ # Registers - + ## Summary -| Name | Offset | Length | Description | -|:-----------------------------------------------|:---------|---------:|:------------------------------------------------| -| otbn.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | -| otbn.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | -| otbn.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | -| otbn.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | -| otbn.[`CMD`](#cmd) | 0x10 | 4 | Command Register | -| otbn.[`CTRL`](#ctrl) | 0x14 | 4 | Control Register | -| otbn.[`STATUS`](#status) | 0x18 | 4 | Status Register | -| otbn.[`ERR_BITS`](#err_bits) | 0x1c | 4 | Operation Result Register | -| otbn.[`FATAL_ALERT_CAUSE`](#fatal_alert_cause) | 0x20 | 4 | Fatal Alert Cause Register | -| otbn.[`INSN_CNT`](#insn_cnt) | 0x24 | 4 | Instruction Count Register | -| otbn.[`LOAD_CHECKSUM`](#load_checksum) | 0x28 | 4 | A 32-bit CRC checksum of data written to memory | -| otbn.[`IMEM`](#imem) | 0x8000 | 32768 | Instruction Memory Access | -| otbn.[`DMEM`](#dmem) | 0x18000 | 31744 | Data Memory Access | +| Name | Offset | Length | Description | +|:----------------------------------------------|:---------|---------:|:------------------------------------------------| +| acc.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | +| acc.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | +| acc.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | +| acc.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | +| acc.[`CMD`](#cmd) | 0x10 | 4 | Command Register | +| acc.[`CTRL`](#ctrl) | 0x14 | 4 | Control Register | +| acc.[`STATUS`](#status) | 0x18 | 4 | Status Register | +| acc.[`ERR_BITS`](#err_bits) | 0x1c | 4 | Operation Result Register | +| acc.[`FATAL_ALERT_CAUSE`](#fatal_alert_cause) | 0x20 | 4 | Fatal Alert Cause Register | +| acc.[`INSN_CNT`](#insn_cnt) | 0x24 | 4 | Instruction Count Register | +| acc.[`LOAD_CHECKSUM`](#load_checksum) | 0x28 | 4 | A 32-bit CRC checksum of data written to memory | +| acc.[`IMEM`](#imem) | 0x8000 | 32768 | Instruction Memory Access | +| acc.[`DMEM`](#dmem) | 0x18000 | 31744 | Data Memory Access | ## INTR_STATE Interrupt State Register @@ -31,10 +31,10 @@ Interrupt State Register {"reg": [{"name": "done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} ``` -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw1c | 0x0 | done | OTBN has completed the operation. | +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw1c | 0x0 | done | ACC has completed the operation. | ## INTR_ENABLE Interrupt Enable Register @@ -91,13 +91,13 @@ Alert Test Register ## CMD Command Register -A command initiates an OTBN operation. While performing the operation, -OTBN is busy; the [`STATUS`](#status) register reflects that. +A command initiates an ACC operation. While performing the operation, +ACC is busy; the [`STATUS`](#status) register reflects that. All operations signal their completion by raising the done interrupt; alternatively, software may poll the [`STATUS`](#status) register. -Writes are ignored if OTBN is not idle. +Writes are ignored if ACC is not idle. Unrecognized commands are ignored. - Offset: `0x10` - Reset default: `0x0` @@ -135,10 +135,10 @@ Control Register {"reg": [{"name": "software_errs_fatal", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} ``` -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:--------------------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw | 0x0 | software_errs_fatal | Controls the reaction to software errors. When set software errors produce fatal errors, rather than recoverable errors. Writes are ignored if OTBN is not idle. | +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | software_errs_fatal | Controls the reaction to software errors. When set software errors produce fatal errors, rather than recoverable errors. Writes are ignored if ACC is not idle. | ## STATUS Status Register @@ -158,19 +158,19 @@ Status Register | 7:0 | ro | 0x4 | [status](#status--status) | ### STATUS . status -Indicates the current operational state OTBN is in. +Indicates the current operational state ACC is in. All BUSY values represent an operation started by a write to the [`CMD`](#cmd) register. | Value | Name | Description | |:------|:-------------------|:------------------------------------------------------| -| 0x00 | IDLE | OTBN is idle: it is not performing any action. | -| 0x01 | BUSY_EXECUTE | OTBN is busy executing software. | -| 0x02 | BUSY_SEC_WIPE_DMEM | OTBN is busy securely wiping the data memory. | -| 0x03 | BUSY_SEC_WIPE_IMEM | OTBN is busy securely wiping the instruction memory. | -| 0x04 | BUSY_SEC_WIPE_INT | OTBN is busy securely wiping the internal state. | -| 0xFF | LOCKED | OTBN is locked as reaction to a fatal error, and must be reset to unlock it again. See also the section "Reaction to Fatal Errors". | +| 0x00 | IDLE | ACC is idle: it is not performing any action. | +| 0x01 | BUSY_EXECUTE | ACC is busy executing software. | +| 0x02 | BUSY_SEC_WIPE_DMEM | ACC is busy securely wiping the data memory. | +| 0x03 | BUSY_SEC_WIPE_IMEM | ACC is busy securely wiping the instruction memory. | +| 0x04 | BUSY_SEC_WIPE_INT | ACC is busy securely wiping the internal state. | +| 0xFF | LOCKED | ACC is locked as reaction to a fatal error, and must be reset to unlock it again. See also the section "Reaction to Fatal Errors". | ## ERR_BITS @@ -181,8 +181,8 @@ Describes the errors detected during an operation. Refer to the "List of Errors" section for a detailed description of the errors. -The host CPU can clear this register when OTBN is not running, -by writing any value. Write attempts while OTBN is running are ignored. +The host CPU can clear this register when ACC is not running, +by writing any value. Write attempts while ACC is running are ignored. - Offset: `0x1c` - Reset default: `0x0` - Reset mask: `0xff00ff` @@ -218,8 +218,8 @@ by writing any value. Write attempts while OTBN is running are ignored. Fatal Alert Cause Register Describes any errors that led to a fatal alert. -A fatal error puts OTBN in locked state; the value of this register -does not change until OTBN is reset. +A fatal error puts ACC in locked state; the value of this register +does not change until ACC is reset. Refer to the "List of Errors" section for a detailed description of the errors. @@ -256,10 +256,10 @@ Only the EXECUTE operation counts instructions; for all other operations this register remains at 0. Instructions triggering an error do not count towards the total. -Always reads as 0 if OTBN is locked. +Always reads as 0 if ACC is locked. -The host CPU can clear this register when OTBN is not running, -by writing any value. Write attempts while OTBN is running are ignored. +The host CPU can clear this register when ACC is not running, +by writing any value. Write attempts while ACC is running are ignored. - Offset: `0x24` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -296,11 +296,11 @@ See the "Memory Load Integrity" section of the manual for full details. Instruction Memory Access The instruction memory may only be accessed through this window -while OTBN is idle. +while ACC is idle. -If OTBN is busy or locked, read accesses return 0 and write accesses +If ACC is busy or locked, read accesses return 0 and write accesses are ignored. -If OTBN is busy, any access additionally triggers an +If ACC is busy, any access additionally triggers an ILLEGAL_BUS_ACCESS fatal error. - Word Aligned Offset Range: `0x8000`to`0xfffc` @@ -311,12 +311,12 @@ ILLEGAL_BUS_ACCESS fatal error. ## DMEM Data Memory Access -The data memory may only be accessed through this window while OTBN +The data memory may only be accessed through this window while ACC is idle. -If OTBN is busy or locked, read accesses return 0 and write accesses +If ACC is busy or locked, read accesses return 0 and write accesses are ignored. -If OTBN is busy, any access additionally triggers an +If ACC is busy, any access additionally triggers an ILLEGAL_BUS_ACCESS fatal error. Note that DMEM is actually 4kiB in size, but only the first 3kiB of diff --git a/hw/ip/otbn/doc/rshi.svg b/hw/ip/acc/doc/rshi.svg similarity index 100% rename from hw/ip/otbn/doc/rshi.svg rename to hw/ip/acc/doc/rshi.svg diff --git a/hw/ip/otbn/doc/theory_of_operation.md b/hw/ip/acc/doc/theory_of_operation.md similarity index 68% rename from hw/ip/otbn/doc/theory_of_operation.md rename to hw/ip/acc/doc/theory_of_operation.md index 91beb0acdaf..c201385091b 100644 --- a/hw/ip/otbn/doc/theory_of_operation.md +++ b/hw/ip/acc/doc/theory_of_operation.md @@ -2,50 +2,52 @@ ## Block Diagram -![OTBN architecture block diagram](./otbn_blockarch.svg) +![ACC architecture block diagram](./acc_blockarch.svg) ## Design Details ### Memories -The OTBN processor core has access to two dedicated memories: an instruction memory (IMEM), and a data memory (DMEM). -The IMEM is 8 KiB, the DMEM is 4 KiB. +The ACC processor core has access to two dedicated memories: an instruction memory (IMEM), and a data memory (DMEM). +In the classical instantiation mode the IMEM is 8 KiB and the DMEM is 4 KiB. +If ACC is instantiated with `AccPQCEn` to enable PQC, IMEM and DMEM should be 32 KiB each to support first-order-masking of ML-DSA-87. The memory layout follows the Harvard architecture. Both memories are byte-addressed, with addresses starting at 0. -The instruction memory (IMEM) is 32b wide and provides the instruction stream to the OTBN processor. +The instruction memory (IMEM) is 32b wide and provides the instruction stream to the ACC processor. It cannot be read from or written to by user code through load or store instructions. -The data memory (DMEM) is 256b wide and read-write accessible from the base and big number instruction subsets of the OTBN processor core. +The data memory (DMEM) is 256b wide and read-write accessible from the base and big number instruction subsets of the ACC processor core. There are four instructions that can access data memory. -In the base instruction subset, there are {{#otbn-insn-ref LW}} (load word) and {{#otbn-insn-ref SW}} (store word). +In the base instruction subset, there are {{#acc-insn-ref LW}} (load word) and {{#acc-insn-ref SW}} (store word). These access 32b-aligned 32b words. -In the big number instruction subset, there are {{#otbn-insn-ref BN.LID}} (load indirect) and {{#otbn-insn-ref BN.SID}} (store indirect). +In the big number instruction subset, there are {{#acc-insn-ref BN.LID}} (load indirect) and {{#acc-insn-ref BN.SID}} (store indirect). These access 256b-aligned 256b words. -Both memories can be accessed through OTBN's register interface ([`DMEM`](registers.md#dmem) and [`IMEM`](registers.md#imem)). +Both memories can be accessed through ACC's register interface ([`DMEM`](registers.md#dmem) and [`IMEM`](registers.md#imem)). All memory accesses through the register interface must be word-aligned 32b word accesses. -When OTBN is in any state other than [idle](#operational-states), reads return zero and writes have no effect. -Furthermore, a memory access when OTBN is neither idle nor locked will cause OTBN to generate a fatal error with code `ILLEGAL_BUS_ACCESS`. -A host processor can check whether OTBN is busy by reading the [`STATUS`](registers.md#status) register. +When ACC is in any state other than [idle](#operational-states), reads return zero and writes have no effect. +Furthermore, a memory access when ACC is neither idle nor locked will cause ACC to generate a fatal error with code `ILLEGAL_BUS_ACCESS`. +A host processor can check whether ACC is busy by reading the [`STATUS`](registers.md#status) register. The underlying memories used to implement the IMEM and DMEM may not grant all access requests (see [Memory Scrambling](#memory-scrambling) for details). A request won't be granted if new scrambling keys have been requested for the memory that aren't yet available. -Functionally it should be impossible for either OTBN or a host processor to make a memory request whilst new scrambling keys are unavailable. -OTBN is in the busy state whilst keys are requested so OTBN will not execute any programs and a host processor access will generated an `ILLEGAL_BUS_ACCESS` fatal error. +Functionally it should be impossible for either ACC or a host processor to make a memory request whilst new scrambling keys are unavailable. +ACC is in the busy state whilst keys are requested so ACC will not execute any programs and a host processor access will generated an `ILLEGAL_BUS_ACCESS` fatal error. Should a request not be granted due to a fault, a `BAD_INTERNAL_STATE` fatal error will be raised. -While DMEM is 4kiB, only the first 3kiB (at addresses `0x0` to `0xbff`) is visible through the register interface. -This is to allow OTBN applications to store sensitive information in the other 1kiB, making it harder for that information to leak back to Ibex. +While DMEM is 4 KiB, only the first 3 KiB (at addresses `0x0` to `0xbff`) is visible through the register interface. +When ACC is operating in its PQC mode the first 31 KiB are visible through the register interface. +This is to allow ACC applications to store sensitive information in the other 1 KiB, making it harder for that information to leak back to Ibex. Each memory write through the register interface updates a checksum. See the [Memory Load Integrity](#memory-load-integrity) section for more details. ### Instruction Prefetch -OTBN employs an instruction prefetch stage to enable pre-decoding of instructions to enable the [blanking SCA hardening measure](#blanking). +ACC employs an instruction prefetch stage to enable pre-decoding of instructions to enable the [blanking SCA hardening measure](#blanking). Its operation is entirely transparent to software. It does not speculate and will only prefetch where the next instruction address can be known. This results in a stall cycle for all conditional branches and jumps as the result is neither predicted nor known ahead of time. @@ -53,37 +55,37 @@ Instruction bits held in the prefetch buffer are unscrambled but use the integri ### Random Numbers -OTBN is connected to the [Entropy Distribution Network (EDN)](../../edn/README.md) which can provide random numbers via the `RND` and `URND` CSRs and WSRs. +ACC is connected to the [Entropy Distribution Network (EDN)](../../edn/README.md) which can provide random numbers via the `RND` and `URND` CSRs and WSRs. `RND` provides bits taken directly from the EDN connected via `edn_rnd`. -The EDN interface provides 32b of entropy per transaction and comes from a different clock domain to the OTBN core. -A FIFO is used to synchronize the incoming package to the OTBN clock domain. +The EDN interface provides 32b of entropy per transaction and comes from a different clock domain to the ACC core. +A FIFO is used to synchronize the incoming package to the ACC clock domain. Synchronized packages are then set starting from bottom up to a single `WLEN` value of 256b. In order to service a single EDN request, a total of 8 transactions are required from EDN interface. The `RND` CSR and WSR take their bits from the same source. A read from the `RND` CSR returns the bottom 32b; the other 192b are discarded. -On a read from the `RND` CSR or WSR, OTBN will stall while it waits for data. +On a read from the `RND` CSR or WSR, ACC will stall while it waits for data. It will resume execution on the cycle after it receives the final word of data from the EDN. -As an EDN request can take time, `RND` is backed by a single-entry cache containing the result of the most recent EDN request in OTBN core level. +As an EDN request can take time, `RND` is backed by a single-entry cache containing the result of the most recent EDN request in ACC core level. Writing any value to the `RND_PREFETCH` CSR initiates a prefetch. This requests data from the EDN, storing it in the cache, and can hide the EDN latency. Writes to `RND_PREFETCH` will be ignored whilst a prefetch is in progress or when the cache is already full. If the cache is full, a read from `RND` returns immediately with the contents of the cache, which is then emptied. -If the cache is not full, a read from `RND` will block as described above until OTBN receives the final word of data from the EDN. +If the cache is not full, a read from `RND` will block as described above until ACC receives the final word of data from the EDN. -OTBN discards any data that is in the cache at the start of an operation. -If there is still a pending prefetch when an OTBN operation starts, the results of the prefetch will also discarded. +ACC discards any data that is in the cache at the start of an operation. +If there is still a pending prefetch when an ACC operation starts, the results of the prefetch will also discarded. -`URND` provides bits from a local XoShiRo256++ PRNG within OTBN; reads from it never stall. -This PRNG is seeded once from the EDN connected via `edn_urnd` when OTBN starts execution. -Each new execution of OTBN will reseed the `URND` PRNG. -The PRNG state is advanced every cycle when OTBN is running. +`URND` provides bits from a local XoShiRo256++ PRNG within ACC; reads from it never stall. +This PRNG is seeded once from the EDN connected via `edn_urnd` when ACC starts execution. +Each new execution of ACC will reseed the `URND` PRNG. +The PRNG state is advanced every cycle when ACC is running. The PRNG has a long cycle length but has a fixed point: the sequence of numbers will get stuck if the state ever happens to become zero. This will never happen in normal operation. -If a fault causes the state to become zero, OTBN raises a `BAD_INTERNAL_STATE` fatal error. +If a fault causes the state to become zero, ACC raises a `BAD_INTERNAL_STATE` fatal error. ### Operational States @@ -92,33 +94,33 @@ Source: https://docs.google.com/drawings/d/1C0D4UriRk5pKGFoFtAXYLcJ1oBG1BCDd2omC Download the SVG from Google Draw, open it in Inkscape once and save it without changes to add width/height information to the image. --> -![OTBN operational states](./otbn_operational_states.svg) +![ACC operational states](./acc_operational_states.svg) -OTBN can be in different operational states. -After reset (*init*), OTBN performs a secure wipe of the internal state and then becomes *idle*. -OTBN is *busy* for as long it is performing an operation. -OTBN is *locked* if a fatal error was observed or after handling an RMA request. +ACC can be in different operational states. +After reset (*init*), ACC performs a secure wipe of the internal state and then becomes *idle*. +ACC is *busy* for as long it is performing an operation. +ACC is *locked* if a fatal error was observed or after handling an RMA request. The current operational state is reflected in the [`STATUS`](registers.md#status) register. -- After reset, OTBN is busy with the internal secure wipe and the [`STATUS`](registers.md#status) register is set to `BUSY_SEC_WIPE_INT`. -- If OTBN is idle, the [`STATUS`](registers.md#status) register is set to `IDLE`. -- If OTBN is busy, the [`STATUS`](registers.md#status) register is set to one of the values starting with `BUSY_`. -- If OTBN is locked, the [`STATUS`](registers.md#status) register is set to `LOCKED`. +- After reset, ACC is busy with the internal secure wipe and the [`STATUS`](registers.md#status) register is set to `BUSY_SEC_WIPE_INT`. +- If ACC is idle, the [`STATUS`](registers.md#status) register is set to `IDLE`. +- If ACC is busy, the [`STATUS`](registers.md#status) register is set to one of the values starting with `BUSY_`. +- If ACC is locked, the [`STATUS`](registers.md#status) register is set to `LOCKED`. -OTBN transitions into the busy state as result of host software [issuing a command](#operations-and-commands); OTBN is then said to perform an operation. -OTBN transitions out of the busy state whenever the operation has completed. +ACC transitions into the busy state as result of host software [issuing a command](#operations-and-commands); ACC is then said to perform an operation. +ACC transitions out of the busy state whenever the operation has completed. In the [`STATUS`](registers.md#status) register the different `BUSY_*` values represent the operation that is currently being performed. A transition out of the busy state is signaled by the `done` interrupt ([`INTR_STATE.done`](registers.md#intr_state)). -The locked state is a terminal state; transitioning out of it requires an OTBN reset. +The locked state is a terminal state; transitioning out of it requires an ACC reset. ### Operations and Commands -OTBN understands a set of commands to perform certain operations. +ACC understands a set of commands to perform certain operations. Commands are issued by writing to the [`CMD`](registers.md#cmd) register. -The `EXECUTE` command starts the [execution of the application](#software-execution) contained in OTBN's instruction memory. +The `EXECUTE` command starts the [execution of the application](#software-execution) contained in ACC's instruction memory. The `SEC_WIPE_DMEM` command [securely wipes the data memory](#secure-wipe). @@ -126,30 +128,30 @@ The `SEC_WIPE_IMEM` command [securely wipes the instruction memory](#secure-wipe ### Software Execution -Software execution on OTBN is triggered by host software by [issuing the `EXECUTE` command](#operations-and-commands). +Software execution on ACC is triggered by host software by [issuing the `EXECUTE` command](#operations-and-commands). The software then runs to completion, without the ability for host software to interrupt or inspect the execution. -- OTBN transitions into the busy state, and reflects this by setting [`STATUS`](registers.md#status) to `BUSY_EXECUTE`. +- ACC transitions into the busy state, and reflects this by setting [`STATUS`](registers.md#status) to `BUSY_EXECUTE`. - The internal randomness source, which provides random numbers to the `URND` CSR and WSR, is re-seeded from the EDN. - The instruction at address zero is fetched and executed. -- From this point on, all subsequent instructions are executed according to their semantics until either an {{#otbn-insn-ref ECALL}} instruction is executed, or an error is detected. +- From this point on, all subsequent instructions are executed according to their semantics until either an {{#acc-insn-ref ECALL}} instruction is executed, or an error is detected. - A [secure wipe of internal state](#internal-state-secure-wipe) is performed. - The [`ERR_BITS`](registers.md#err_bits) register is set to indicate either a successful execution (value `0`), or to indicate the error that was observed (a non-zero value). -- OTBN transitions into the [idle state](#operational-states) (in case of a successful execution, or a recoverable error) or the locked state (in case of a fatal error). +- ACC transitions into the [idle state](#operational-states) (in case of a successful execution, or a recoverable error) or the locked state (in case of a fatal error). This transition is signaled by raising the `done` interrupt ([`INTR_STATE.done`](registers.md#intr_state)), and reflected in the [`STATUS`](registers.md#status) register. ### Errors -OTBN is able to detect a range of errors, which are classified as *software errors* or *fatal errors*. -A software error is an error in the code that OTBN executes. +ACC is able to detect a range of errors, which are classified as *software errors* or *fatal errors*. +A software error is an error in the code that ACC executes. In the absence of an attacker, these errors are due to a programmer's mistake. A fatal error is typically the violation of a security property. All errors and their classification are listed in the [List of Errors](#list-of-errors). -Whenever an error is detected, OTBN reacts locally, and informs the OpenTitan system about it by raising an alert. -OTBN generally does not try to recover from errors itself, and provides no error handling support to code that runs on it. +Whenever an error is detected, ACC reacts locally, and informs the system about it by raising an alert. +ACC generally does not try to recover from errors itself, and provides no error handling support to code that runs on it. -OTBN gives host software the option to recover from some errors by restarting the operation. +ACC gives host software the option to recover from some errors by restarting the operation. All software errors are treated as recoverable, unless [`CTRL.software_errs_fatal`](registers.md#ctrl) is set, and are handled as described in the section [Reaction to Recoverable Errors](#reaction-to-recoverable-errors). When [`CTRL.software_errs_fatal`](registers.md#ctrl) is set, software errors become fatal errors. @@ -157,12 +159,12 @@ Fatal errors are treated as described in the section [Reaction to Fatal Errors]( ### Reaction to Recoverable Errors -Recoverable errors can be the result of a programming error in OTBN software. -Recoverable errors can only occur during the execution of software on OTBN, and not in other situations in which OTBN might be busy. +Recoverable errors can be the result of a programming error in ACC software. +Recoverable errors can only occur during the execution of software on ACC, and not in other situations in which ACC might be busy. -The following actions are taken when OTBN detects a recoverable error: +The following actions are taken when ACC detects a recoverable error: -1. The currently running operation is terminated, similar to the way an {{#otbn-insn-ref ECALL}} instruction [is executed](#returning-from-an-application): +1. The currently running operation is terminated, similar to the way an {{#acc-insn-ref ECALL}} instruction [is executed](#returning-from-an-application): - No more instructions are fetched or executed. - A [secure wipe of internal state](#internal-state-secure-wipe) is performed. - The [`ERR_BITS`](registers.md#err_bits) register is set to a non-zero value that describes the error. @@ -170,17 +172,17 @@ The following actions are taken when OTBN detects a recoverable error: - The [`STATUS`](registers.md#status) register is set to `IDLE`. 2. A [recoverable alert](#alerts) is raised. -The host software can start another operation on OTBN after a recoverable error was detected. +The host software can start another operation on ACC after a recoverable error was detected. ### Reaction to Fatal Errors -Fatal errors are generally seen as a sign of an intrusion, resulting in more drastic measures to protect the secrets stored within OTBN. -Fatal errors can occur at any time, even when an OTBN operation isn't in progress. +Fatal errors are generally seen as a sign of an intrusion, resulting in more drastic measures to protect the secrets stored within ACC. +Fatal errors can occur at any time, even when an ACC operation isn't in progress. -The following actions are taken when OTBN detects a fatal error: +The following actions are taken when ACC detects a fatal error: 1. A [secure wipe of the data memory](#data-memory-dmem-secure-wipe) and a [secure wipe of the instruction memory](#instruction-memory-imem-secure-wipe) is initiated. -2. If OTBN [is not idle](#operational-states), then the currently running operation is terminated, similarly to how an operation ends after an {{#otbn-insn-ref ECALL}} instruction [is executed](#returning-from-an-application): +2. If ACC [is not idle](#operational-states), then the currently running operation is terminated, similarly to how an operation ends after an {{#acc-insn-ref ECALL}} instruction [is executed](#returning-from-an-application): - No more instructions are fetched or executed. - A [secure wipe of internal state](#internal-state-secure-wipe) is performed. - The [`ERR_BITS`](registers.md#err_bits) register is set to a non-zero value that describes the error. @@ -188,11 +190,11 @@ The following actions are taken when OTBN detects a fatal error: 3. The [`STATUS`](registers.md#status) register is set to `LOCKED`. 4. A [fatal alert](#alerts) is raised. -Note that OTBN can detect some errors even when it isn't running. -One example of this is an error caused by an integrity error when reading or writing OTBN's memories over the bus. +Note that ACC can detect some errors even when it isn't running. +One example of this is an error caused by an integrity error when reading or writing ACC's memories over the bus. In this case, the [`ERR_BITS`](registers.md#err_bits) register will not change. This avoids race conditions with the host processor's error handling software. -However, every error that OTBN detects when it isn't running is fatal. +However, every error that ACC detects when it isn't running is fatal. This means that the cause will be reflected in [`FATAL_ALERT_CAUSE`](registers.md#fatal_alert_cause), as described below in [Alerts](#alerts). This way, no alert is generated without setting an error code somewhere. @@ -280,7 +282,7 @@ This way, no alert is generated without setting an error code somewhere. BAD_INTERNAL_STATE fatal - The internal state of OTBN has become corrupt. + The internal state of ACC has become corrupt. ILLEGAL_BUS_ACCESS @@ -302,41 +304,41 @@ This way, no alert is generated without setting an error code somewhere. ### Alerts -An alert is a reaction to an error that OTBN detected. -OTBN has two alerts, one recoverable and one fatal. +An alert is a reaction to an error that ACC detected. +ACC has two alerts, one recoverable and one fatal. A **recoverable alert** is a one-time triggered alert caused by [recoverable errors](#reaction-to-recoverable-errors). The error that caused the alert can be determined by reading the [`ERR_BITS`](registers.md#err_bits) register. A **fatal alert** is a continuously triggered alert caused by [fatal errors](#reaction-to-fatal-errors). The error that caused the alert can be determined by reading the [`FATAL_ALERT_CAUSE`](registers.md#fatal_alert_cause) register. -If OTBN was running, this value will also be reflected in the [`ERR_BITS`](registers.md#err_bits) register. -A fatal alert can only be cleared by resetting OTBN through the `rst_ni` line. +If ACC was running, this value will also be reflected in the [`ERR_BITS`](registers.md#err_bits) register. +A fatal alert can only be cleared by resetting ACC through the `rst_ni` line. -The host CPU can clear the [`ERR_BITS`](registers.md#err_bits) when OTBN is not running. +The host CPU can clear the [`ERR_BITS`](registers.md#err_bits) when ACC is not running. Writing any value to [`ERR_BITS`](registers.md#err_bits) clears this register to zero. -Write attempts while OTBN is running are ignored. +Write attempts while ACC is running are ignored. ### Reaction to Life Cycle Escalation Requests -OTBN receives and reacts to escalation signals from the [life cycle controller](../../lc_ctrl/README.md#security-escalation). +ACC receives and reacts to escalation signals from the [life cycle controller](../../lc_ctrl/README.md#security-escalation). An incoming life cycle escalation is a fatal error of type `lifecycle_escalation` and treated as described in the section [Fatal Errors](#reaction-to-fatal-errors). ### Idle -OTBN exposes a single-bit `idle_o` signal, intended to be used by the clock manager to clock-gate the block when it is not in use. +ACC exposes a single-bit `idle_o` signal, intended to be used by the clock manager to clock-gate the block when it is not in use. This signal is in the same clock domain as `clk_i`. -The `idle_o` signal is high when OTBN [is idle](#operational-states), and low otherwise. +The `idle_o` signal is high when ACC [is idle](#operational-states), and low otherwise. -OTBN also exposes another version of the idle signal as `idle_otp_o`. +ACC also exposes another version of the idle signal as `idle_otp_o`. This works analogously, but is in the same clock domain as `clk_otp_i`. TODO: Specify interactions between `idle_o`, `idle_otp_o` and the clock manager fully. ### Data Integrity Protection -OTBN stores and operates on data (state) in its dedicated memories, register files, and internal registers. -OTBN's data integrity protection is designed to protect all data stored and transmitted within OTBN from modifications through physical attacks. +ACC stores and operates on data (state) in its dedicated memories, register files, and internal registers. +ACC's data integrity protection is designed to protect all data stored and transmitted within ACC from modifications through physical attacks. During transmission, the integrity of data is protected with an integrity protection code. Data at rest in the instruction and data memories is additionally scrambled. @@ -345,7 +347,7 @@ In the following, the Integrity Protection Code and the scrambling algorithm are #### Integrity Protection Code -OTBN uses the same integrity protection code everywhere to provide overarching data protection without regular re-encoding. +ACC uses the same integrity protection code everywhere to provide overarching data protection without regular re-encoding. The code is applied to 32b data words, and produces 39b of encoded data. The code used is an (39,32) Hsiao "single error correction, double error detection" (SECDED) error correction code (ECC) [[CHEN08](#ref-chen08)]. @@ -354,18 +356,18 @@ The code is used for error detection only; no error correction is performed. #### Memory Scrambling -Contents of OTBN's instruction and data memories are scrambled while at rest. +Contents of ACC's instruction and data memories are scrambled while at rest. The data is bound to the address and scrambled before being stored in memory. The addresses are randomly remapped. -Note that data stored in other temporary memories within OTBN, including the register files, is not scrambled. +Note that data stored in other temporary memories within ACC, including the register files, is not scrambled. Scrambling is used to obfuscate the memory contents and to diffuse the data. Obfuscation makes passive probing more difficult, while diffusion makes active fault injection attacks more difficult. The scrambling mechanism is described in detail in the [section "Scrambling Primitive" of the SRAM Controller Technical Specification](../../sram_ctrl/README.md#scrambling-primitive). -When OTBN comes out of reset, its memories have default scrambling keys. +When ACC comes out of reset, its memories have default scrambling keys. The host processor can request new keys for each memory by issuing a [secure wipe of DMEM](#data-memory-dmem-secure-wipe) and a [secure wipe of IMEM](#instruction-memory-imem-secure-wipe). #### Actions on Integrity Errors @@ -375,7 +377,7 @@ The section [Error Handling and Reporting](#design-details-error-handling-and-re #### Register File Integrity Protection -OTBN contains two register files: the 32b GPRs and the 256b WDRs. +ACC contains two register files: the 32b GPRs and the 256b WDRs. The data stored in both register files is protected with the [Integrity Protection Code](#integrity-protection-code). Neither the register file contents nor register addresses are scrambled. @@ -389,8 +391,8 @@ The register files can consume data protected with the Integrity Protection Code Whenever possible the Integrity Protection Code is preserved from its source and written directly to the register files without recalculation, in particular in the following cases: * Data coming from the data memory (DMEM) through the load-store unit to a GPR or WDR. -* Data copied between WDRs using the {{#otbn-insn-ref BN.MOV}} or {{#otbn-insn-ref BN.MOVR}} instructions. -* Data conditionally copied between WDRs using the {{#otbn-insn-ref BN.SEL}} instruction. +* Data copied between WDRs using the {{#acc-insn-ref BN.MOV}} or {{#acc-insn-ref BN.MOVR}} instructions. +* Data conditionally copied between WDRs using the {{#acc-insn-ref BN.SEL}} instruction. * Data copied between the `ACC` and `MOD` WSRs and a WDR. * Data copied between any of the `MOD0` to `MOD7` CSRs and a GPR. (TODO: Not yet implemented.) @@ -403,7 +405,7 @@ Detected integrity violations in a register file raise a fatal `reg_error`. #### Data Memory (DMEM) Integrity Protection -OTBN's data memory is 256b wide, but allows for 32b word accesses. +ACC's data memory is 256b wide, but allows for 32b word accesses. To facilitate such accesses, all integrity protection in the data memory is done on a 32b word granularity. All data entering or leaving the data memory block is protected with the [Integrity Protection Code](#integrity-protection-code); @@ -413,7 +415,7 @@ Before being stored in SRAM, the data word with the attached Integrity Protectio The scrambling is reversed on a read. The ephemeral memory scrambling key and the nonce are provided by the OTP block. -They are set once when OTBN block is reset, and changed whenever a [secure wipe](#data-memory-dmem-secure-wipe) of the data memory is performed. +They are set once when ACC block is reset, and changed whenever a [secure wipe](#data-memory-dmem-secure-wipe) of the data memory is performed. For example, see earlgrey's [OTP block](../../../top_earlgrey/ip_autogen/otp_ctrl/doc/theory_of_operation.md#scrambling-key-derivation). The Integrity Protection Code is checked on every memory read, even though the code remains attached to the data. @@ -429,7 +431,7 @@ Before being stored in SRAM, the instruction word with the attached Integrity Pr The scrambling is reversed on a read. The ephemeral memory scrambling key and the nonce are provided by the OTP block (for example, see earlgrey's [scrambling specification](../../../top_earlgrey/ip_autogen/otp_ctrl/doc/theory_of_operation.md#scrambling-key-derivation)). -They are set once when OTBN block is reset, and changed whenever a [secure wipe](#instruction-memory-imem-secure-wipe) of the instruction memory is performed. +They are set once when ACC block is reset, and changed whenever a [secure wipe](#instruction-memory-imem-secure-wipe) of the instruction memory is performed. The Integrity Protection Code is checked on every memory read, even though the code remains attached to the data. A further check must be performed when the data is consumed. @@ -437,13 +439,13 @@ Detected integrity violations in the data memory raise a fatal `imem_error`. ### Memory Load Integrity -As well as the integrity protection discussed above for the memories and bus interface, OTBN has a second layer of integrity checking to allow a host processor to ensure that a program has been loaded correctly. +As well as the integrity protection discussed above for the memories and bus interface, ACC has a second layer of integrity checking to allow a host processor to ensure that a program has been loaded correctly. This is visible through the [`LOAD_CHECKSUM`](registers.md#load_checksum) register. The register exposes a cumulative CRC checksum which is updated on every write to either memory. This is intended as a light-weight way to implement a more efficient "write and read back" check. It isn't a cryptographically secure MAC, so cannot spot an attacker who can completely control the bus. -However, in this case the attacker would be equally able to control responses from OTBN, so any such check could be subverted. +However, in this case the attacker would be equally able to control responses from ACC, so any such check could be subverted. The CRC used is the 32-bit CRC-32-IEEE checksum. This standard choice of generating polynomial makes it compatible with other tooling and libraries, such as the [crc32 function](https://docs.python.org/3/library/binascii.html#binascii.crc32) in the python 'binascii' module and the crc instructions in the RISC-V bitmanip specification [[SYMBIOTIC21]](#ref-symbiotic21). @@ -460,13 +462,13 @@ Note the internal representation of the CRC is inverted from the register visibl This is done to maintain compatibility with existing CRC-32-IEEE tooling and libraries. To use this functionality, the host processor should set [`LOAD_CHECKSUM`](registers.md#load_checksum) to a known value (traditionally, `32'h00000000`). -Next, it should write the program to be loaded to OTBN's IMEM and DMEM over the bus. +Next, it should write the program to be loaded to ACC's IMEM and DMEM over the bus. Finally, it should read back the value of [`LOAD_CHECKSUM`](registers.md#load_checksum) and compare it with an expected value. ### Secure Wipe -Applications running on OTBN may store sensitive data in the internal registers or the memory. -In order to prevent an untrusted application from reading any leftover data, OTBN provides the secure wipe operation. +Applications running on ACC may store sensitive data in the internal registers or the memory. +In order to prevent an untrusted application from reading any leftover data, ACC provides the secure wipe operation. This operation can be applied to: - [Data memory](#data-memory-dmem-secure-wipe) - [Instruction memory](#instruction-memory-imem-secure-wipe) @@ -478,13 +480,13 @@ A secure wipe of either the instruction or the data memory can be triggered from A secure wipe of instruction memory, data memory, and all internal state is performed automatically when handling a [fatal error](#reaction-to-fatal-errors). In addition, it can be triggered by the [Life Cycle Controller](../../lc_ctrl/README.md) before RMA entry using the `lc_rma_req/ack` interface. -In both cases OTBN enters the locked state afterwards and needs to be reset. +In both cases ACC enters the locked state afterwards and needs to be reset. -A secure wipe of the internal state only is triggered automatically after reset and when OTBN [ends the software execution](#software-execution), either successfully, or unsuccessfully due to a [recoverable error](#reaction-to-recoverable-errors). +A secure wipe of the internal state only is triggered automatically after reset and when ACC [ends the software execution](#software-execution), either successfully, or unsuccessfully due to a [recoverable error](#reaction-to-recoverable-errors). -If OTBN cannot complete a secure wipe of the internal state (e.g., due to failing to obtain the required randomness), it immediately becomes locked. -In this case, OTBN must be reset and will then retry the secure wipe. -The secure wipe after reset must succeed before OTBN can be used. +If ACC cannot complete a secure wipe of the internal state (e.g., due to failing to obtain the required randomness), it immediately becomes locked. +In this case, ACC must be reset and will then retry the secure wipe. +The secure wipe after reset must succeed before ACC can be used. #### Data Memory (DMEM) Secure Wipe @@ -512,7 +514,7 @@ Host software can initiate a data memory secure wipe by [issuing the `SEC_WIPE_I #### Internal State Secure Wipe -OTBN provides a mechanism to securely wipe all internal state, excluding the instruction and data memories. +ACC provides a mechanism to securely wipe all internal state, excluding the instruction and data memories. The following state is wiped: * Register files: GPRs and WDRs @@ -533,11 +535,16 @@ Host software cannot explicitly trigger an internal secure wipe; it is performed ### KMAC Application Interface -The OTBN has an application interface connection to the KMAC block allowing for function calls directly to SHA3 and SHAKE algorithms. +The ACC has an application interface side-load connection to the KMAC IP allowing for accelerated hashing with the SHA3 and SHAKE algorithms. For KMAC specific implementation details of the AppIntf view the [`KMAC Theory of Operation`](../../kmac/doc/theory_of_operation.md#application-interface). -The first word written from KMAC on the application interface is used to dynamically configure the algorithm executed within the KMAC block. +The first word written from KMAC on the application interface is used to dynamically configure the algorithm executed within KMAC. Bits [1:0] select the appropriate SHA3/cSHAKE/SHAKE algorithm and bits [4:2] select the appropriate Keccak drive strength. -The CSR for configuring the KMAC operation can be found at 0x7D9. +The CSR for configuring the KMAC operation can be found at `0x7D9`. +After configuring the transaction, writes to the `kmac_msg` WSR register are used to send data over the AppIntf. +Reading from the `kmac_digest` WSR will contain the valid digest from KMAC. +ACC supports a partial word write through the `kmac_partial_write` CSR register. +This register applies a byte-mask to the `kmac_msg` WSR such that a word less than 32B can be written to the internal FIFO and sent over the AppIntf. +For register descriptions refer to the [csr.yml](../data/csr.yml) and [wsr.yml](../data/wsr.yml). @@ -552,14 +559,3 @@ The CSR for configuring the KMAC operation can be found at 0x7D9.
CsrKmacPartialWrite0x7F3
- -#### Partial Word Support - -To reduce additional complexity and code size in the OTBN when initializing a SHA3/SHAKE algorithm the OTBN supports partial word writes. -Writing to the `Send to KMAC` register is used to transfer data over the AppIntf. -The optimization provides a reduced code size for the following reason. -If software wanted to compute SHAKE128(a || b) where a is 2 bytes and b is 32 bytes, without partial write support, software is required to compute a || b[29:0]. -Then write the result and follow with the last two bytes, b[31:30]. -A `_KMAC_WRITE_LEN` register is used to write the size of the next word being transferred, if it is not 32B in size. -After writing the partial word to the KMAC register, the `_KMAC_WRITE_LEN` register will clear itself unless a new value is written. -The OTBN should be able to make requests to the KMAC block back-to-back. diff --git a/hw/ip/otbn/dv/README.md b/hw/ip/acc/dv/README.md similarity index 64% rename from hw/ip/otbn/dv/README.md rename to hw/ip/acc/dv/README.md index 1a1f04454eb..9a4419ace59 100644 --- a/hw/ip/otbn/dv/README.md +++ b/hw/ip/acc/dv/README.md @@ -1,8 +1,8 @@ -# OTBN DV document +# ACC DV document ## Goals * **DV** - * Verify the OTBN processor by running dynamic simulations with a SV/UVM based testbench + * Verify the ACC processor by running dynamic simulations with a SV/UVM based testbench * These simulations are grouped in tests listed in the [testplan](#testplan) below. * Close code and functional coverage on the IP and all of its sub-modules * **FPV** @@ -11,35 +11,35 @@ ## Current status * [Design & verification stage](../../../README.md) * [HW development stages](../../../../doc/project_governance/development_stages.md) -* [Simulation results](https://reports.opentitan.org/hw/ip/otbn/dv/uvm/latest/report.html) +* [Simulation results](https://reports.opentitan.org/hw/ip/acc/dv/uvm/latest/report.html) ## Design features -OTBN, the OpenTitan Big Number accelerator, is a cryptographic accelerator. -For detailed information on OTBN design features, see the [OTBN HWIP technical specification](../README.md). +ACC, the OpenTitan Big Number accelerator, is a cryptographic accelerator. +For detailed information on ACC design features, see the [ACC HWIP technical specification](../README.md). ## Testbench architecture -The OTBN testbench is based on the [CIP testbench architecture](../../../dv/sv/cip_lib/README.md). +The ACC testbench is based on the [CIP testbench architecture](../../../dv/sv/cip_lib/README.md). It builds on the [dv_utils](../../../dv/sv/dv_utils/README.md) and [csr_utils](../../../dv/sv/csr_utils/README.md) packages. ### Block diagram -OTBN testing makes use of a DPI-based model called `otbn_core_model`. +ACC testing makes use of a DPI-based model called `acc_core_model`. This is shown in the block diagram. -The dotted interfaces in the `otbn` block are bound in by the model to access internal signals (register file and memory contents). +The dotted interfaces in the `acc` block are bound in by the model to access internal signals (register file and memory contents). ![Block diagram](./doc/tb.svg) ### Top level testbench -The top-level testbench is located at `hw/ip/otbn/dv/uvm/tb.sv`. -This instantiates the OTBN DUT module `hw/ip/otbn/rtl/otbn.sv`. +The top-level testbench is located at `hw/ip/acc/dv/uvm/tb.sv`. +This instantiates the ACC DUT module `hw/ip/acc/rtl/acc.sv`. -OTBN has the following interfaces: +ACC has the following interfaces: - A [Clock and reset interface](../../../dv/sv/common_ifs/README.md#clk_rst_if) - A [TileLink interface](../../../dv/sv/tl_agent/README.md). - OTBN is a TL-UL device, which expects to communicate with a TL-UL host. + ACC is a TL-UL device, which expects to communicate with a TL-UL host. In the OpenTitan SoC, this will be the Ibex core. - Idle signals in each clock domain, `idle_o`, and `idle_otp_o` - One interrupt @@ -52,17 +52,17 @@ OTBN has the following interfaces: The idle and interrupt signals are modelled with the basic [`pins_if`](../../../dv/sv/common_ifs/README.md#pins_if) interface. -As well as instantiating OTBN, the testbench also instantiates an `otbn_core_model`. -This module wraps an ISS (instruction set simulator) subprocess and performs checks to make sure that OTBN behaves the same as the ISS. -The `otbn_core_model` module communicates with test sequences through an `otbn_model_if` interface, which is monitored by the `otbn_model_agent`, described below. +As well as instantiating ACC, the testbench also instantiates an `acc_core_model`. +This module wraps an ISS (instruction set simulator) subprocess and performs checks to make sure that ACC behaves the same as the ISS. +The `acc_core_model` module communicates with test sequences through an `acc_model_if` interface, which is monitored by the `acc_model_agent`, described below. The module communicates with the Python subprocess as shown in the diagram below. ![Model communication](./doc/model.svg) -### OTBN model agent +### ACC model agent -The model agent is instantiated by the testbench to monitor the OTBN model. +The model agent is instantiated by the testbench to monitor the ACC model. It is a passive agent (essentially just a monitor): the inputs to the model are set in `tb.sv`. The monitor for the agent generates transactions when it sees a start signal or a done signal. @@ -71,12 +71,12 @@ To make sure that the processor is starting when we expect, we check start trans ### Reference models -The main reference model for OTBN is the instruction set simulator (ISS), which is run as a subprocess by DPI code inside `otbn_core_model`. -This Python-based simulator can be found at `hw/ip/otbn/dv/otbnsim`. +The main reference model for ACC is the instruction set simulator (ISS), which is run as a subprocess by DPI code inside `acc_core_model`. +This Python-based simulator can be found at `hw/ip/acc/dv/accsim`. ## Stimulus strategy -When testing OTBN, we are careful to distinguish between +When testing ACC, we are careful to distinguish between - behaviour that can be triggered by particular instruction streams - behaviour that is triggered by particular external stimuli (register writes; surprise resets etc.) @@ -86,7 +86,7 @@ The idea is that this is much quicker for designers to use to smoke-test propose This pre-DV phase cannot drive sign-off, but it does use much of the same tooling. Once we are running full DV tests, we re-use this work, by using the same collection of randomised instruction streams and randomly picking from them for most of the sequences. -At the moment, the full DV tests create binaries on the fly by running `hw/ip/otbn/dv/uvm/gen-binaries.py`. +At the moment, the full DV tests create binaries on the fly by running `hw/ip/acc/dv/uvm/gen-binaries.py`. This results in one or more ELF files in a directory, which the simulation then picks from at random. The pre-DV testing doesn't address external stimuli like resets or TileLink-based register accesses. @@ -94,13 +94,13 @@ These are driven by specialised test sequences, described below. ### Functional coverage -As a complicated IP block, OTBN has a lot of functional coverage points defined. -To avoid overwhelming this document, these are described in [OTBN functional coverage](./doc/fcov.md). +As a complicated IP block, ACC has a lot of functional coverage points defined. +To avoid overwhelming this document, these are described in [ACC functional coverage](./doc/fcov.md). ### Test sequences -The test sequences can be found in `hw/ip/otbn/dv/uvm/env/seq_lib`. -The basic test sequence (`otbn_base_vseq`) loads the instruction stream from a randomly chosen binary (see above), configures OTBN and then lets it run to completion. +The test sequences can be found in `hw/ip/acc/dv/uvm/env/seq_lib`. +The basic test sequence (`acc_base_vseq`) loads the instruction stream from a randomly chosen binary (see above), configures ACC and then lets it run to completion. More specialized sequences include things like multiple runs, register accesses during operation (which should fail) and memory corruption. We also check things like the correct operation of the interrupt registers. @@ -108,7 +108,7 @@ We also check things like the correct operation of the interrupt registers. ## Self-checking strategy ### Scoreboard -Much of the checking for these tests is actually performed in `otbn_core_model`, which ensures that the RTL and ISS have the same behaviour. +Much of the checking for these tests is actually performed in `acc_core_model`, which ensures that the RTL and ISS have the same behaviour. However, the scoreboard does have some checks, to ensure that interrupt and idle signals are high at the expected times. ### Assertions @@ -118,7 +118,7 @@ Core TLUL protocol assertions are checked by binding the [TL-UL protocol checker Outputs are also checked for `'X` values by assertions in the design RTL. The design RTL contains other assertions defined by the designers, which will be checked in simulation (and won't have been checked by the pre-DV Verilator simulations). -Finally, the `otbn_idle_checker` checks that the `idle_o` output correctly matches the running state that you'd expect, based on writes to the `CMD` register and responses that will appear in the `DONE` interrupt. +Finally, the `acc_idle_checker` checks that the `idle_o` output correctly matches the running state that you'd expect, based on writes to the `CMD` register and responses that will appear in the `DONE` interrupt. ## Building and running tests @@ -126,8 +126,8 @@ Tests can be run with [`dvsim.py`](../../../../util/dvsim/README.md). The link gives details of the tool's features and command line arguments. To run a basic smoke test, go to the top of the repository and run: ```console -$ util/dvsim/dvsim.py hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson -i otbn_smoke +$ util/dvsim/dvsim.py hw/ip/acc/dv/uvm/acc_sim_cfg.hjson -i acc_smoke ``` ## Testplan -[Testplan](../data/otbn_testplan.hjson) +[Testplan](../data/acc_testplan.hjson) diff --git a/hw/ip/otbn/dv/otbnsim/BUILD b/hw/ip/acc/dv/accsim/BUILD similarity index 74% rename from hw/ip/otbn/dv/otbnsim/BUILD rename to hw/ip/acc/dv/accsim/BUILD index bef51563dfc..c1e7fdd341b 100644 --- a/hw/ip/otbn/dv/otbnsim/BUILD +++ b/hw/ip/acc/dv/accsim/BUILD @@ -15,8 +15,8 @@ py_binary( name = "standalone", srcs = ["standalone.py"], deps = [ - "//hw/ip/otbn/dv/otbnsim/sim:load_elf", - "//hw/ip/otbn/dv/otbnsim/sim:standalonesim", - "//hw/ip/otbn/dv/otbnsim/sim:stats", + "//hw/ip/acc/dv/accsim/sim:load_elf", + "//hw/ip/acc/dv/accsim/sim:standalonesim", + "//hw/ip/acc/dv/accsim/sim:stats", ], ) diff --git a/hw/ip/otbn/dv/otbnsim/Makefile b/hw/ip/acc/dv/accsim/Makefile similarity index 84% rename from hw/ip/otbn/dv/otbnsim/Makefile rename to hw/ip/acc/dv/accsim/Makefile index 0d2b90c88e5..2c0fa793c3f 100644 --- a/hw/ip/otbn/dv/otbnsim/Makefile +++ b/hw/ip/acc/dv/accsim/Makefile @@ -5,10 +5,10 @@ .PHONY: all all: lint -# We need a directory to build stuff and use the "otbn/otbnsim" namespace +# We need a directory to build stuff and use the "acc/accsim" namespace # in the top-level build-bin directory. repo-top := ../../../.. -build-dir := $(repo-top)/build-bin/otbn/otbnsim +build-dir := $(repo-top)/build-bin/acc/accsim $(build-dir): mkdir -p $@ diff --git a/hw/ip/otbn/dv/otbnsim/README.md b/hw/ip/acc/dv/accsim/README.md similarity index 62% rename from hw/ip/otbn/dv/otbnsim/README.md rename to hw/ip/acc/dv/accsim/README.md index e34d4561ace..4c99bf7ca0f 100644 --- a/hw/ip/otbn/dv/otbnsim/README.md +++ b/hw/ip/acc/dv/accsim/README.md @@ -1,20 +1,20 @@ -# OTBNSim - OTBN Simulation Software +# ACCSim - ACC Simulation Software -`OTBNSim` class represents a simulator that models the whole OTBN block. +`ACCSim` class represents a simulator that models the whole ACC block. Therefore it includes abstract models for the state of the core, its memory modules, and also the register modules. It has methods for starting the execution, cycle-accurate simulation tracing, and for injecting errors and reacting to those errors with a secure wipe. -As explained in the overall [OTBN DV documentation](../README.md), this simulator is driven essentially from the SystemVerilog model of the OTBN module. +As explained in the overall [ACC DV documentation](../README.md), this simulator is driven essentially from the SystemVerilog model of the ACC module. -The simulator works in a step-by-step fashion and it has multiple methods to apply external stimuli to OTBN. +The simulator works in a step-by-step fashion and it has multiple methods to apply external stimuli to ACC. In a typical run without errors, the ISS does the following: 1. Decode the program on the path given by `iss_wrapper.cc` by the `decode_file` method in `decode.py`. 2. Load the decoded program to a local list in `sim.py`. 3. With each `step` command from the SystemVerilog side, update the simulated state of the core (`state.py`), registers (`wsr.py`, `csr.py` and `gpr.py`) and data memory (`dmem.py`). - 4. Once the step is done, pass the generated trace to `iss_wrapper.cc`, which to then passes it on to `OTBNTraceChecker`. + 4. Once the step is done, pass the generated trace to `iss_wrapper.cc`, which to then passes it on to `ACCTraceChecker`. ## Co-Simulation with RTL -For co-simulation of RTL and ISS, the `otbn_tracer` module logs state changes of the RTL, and the ISS logs state changes of the Python model. -Trace entries from the simulated core (aka. from RTL) appear as a result of DPI callbacks while ISS trace entries appear in the trace checker through `ISSWrapper` using `OnIssTrace` method after sending a step command to `OTBNSim`. +For co-simulation of RTL and ISS, the `acc_tracer` module logs state changes of the RTL, and the ISS logs state changes of the Python model. +Trace entries from the simulated core (aka. from RTL) appear as a result of DPI callbacks while ISS trace entries appear in the trace checker through `ISSWrapper` using `OnIssTrace` method after sending a step command to `ACCSim`. To check correct behaviour, the two separate logs generated by the model and the RTL are compared. -For more information about how OTBN RTL produces traces see the [Tracer README](../tracer/README.md). -To see the C++ program that compares both traces, check the method `otbn_trace_checker.cc` in `../model/otbn_trace_entry`. +For more information about how ACC RTL produces traces see the [Tracer README](../tracer/README.md). +To see the C++ program that compares both traces, check the method `acc_trace_checker.cc` in `../model/acc_trace_entry`. diff --git a/hw/ip/otbn/dv/otbnsim/mypy.ini b/hw/ip/acc/dv/accsim/mypy.ini similarity index 76% rename from hw/ip/otbn/dv/otbnsim/mypy.ini rename to hw/ip/acc/dv/accsim/mypy.ini index 76db64b4560..93f74e399f6 100644 --- a/hw/ip/otbn/dv/otbnsim/mypy.ini +++ b/hw/ip/acc/dv/accsim/mypy.ini @@ -1,5 +1,5 @@ [mypy] -# Add OTBN and OpenTitan util dirs to MYPYPATH +# Add ACC and OpenTitan util dirs to MYPYPATH mypy_path = $MYPY_CONFIG_FILE_DIR/../../util, $MYPY_CONFIG_FILE_DIR/../../../../../util [mypy-semantic_version] ignore_missing_imports = True diff --git a/hw/ip/otbn/dv/otbnsim/sim/BUILD b/hw/ip/acc/dv/accsim/sim/BUILD similarity index 92% rename from hw/ip/otbn/dv/otbnsim/sim/BUILD rename to hw/ip/acc/dv/accsim/sim/BUILD index e7fab4e9d1d..a2c2b6bf5a2 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/BUILD +++ b/hw/ip/acc/dv/accsim/sim/BUILD @@ -37,7 +37,7 @@ py_library( srcs = ["dmem.py"], deps = [ ":trace", - "//hw/ip/otbn/util/shared:mem_layout", + "//hw/ip/acc/util/shared:mem_layout", ], ) @@ -52,7 +52,7 @@ py_library( deps = [ ":edn_client", ":trace", - "//hw/ip/otbn/util/shared:otbn_reggen", + "//hw/ip/acc/util/shared:acc_reggen", "//util/reggen:field", "//util/reggen:reg_block", "//util/reggen:register", @@ -92,7 +92,7 @@ py_library( srcs = ["isa.py"], deps = [ ":state", - "//hw/ip/otbn/util/shared:insn_yaml", + "//hw/ip/acc/util/shared:insn_yaml", ], ) @@ -102,7 +102,7 @@ py_library( deps = [ ":decode", ":sim", - "//hw/ip/otbn/util/shared:elf", + "//hw/ip/acc/util/shared:elf", ], ) @@ -159,7 +159,7 @@ py_library( ":reg", ":trace", ":wsr", - "//hw/ip/otbn/util/shared:mem_layout", + "//hw/ip/acc/util/shared:mem_layout", ], ) diff --git a/hw/ip/otbn/dv/otbnsim/sim/__init__.py b/hw/ip/acc/dv/accsim/sim/__init__.py similarity index 71% rename from hw/ip/otbn/dv/otbnsim/sim/__init__.py rename to hw/ip/acc/dv/accsim/sim/__init__.py index 4d215cd298c..a2e2ecf9436 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/__init__.py +++ b/hw/ip/acc/dv/accsim/sim/__init__.py @@ -6,7 +6,7 @@ import sys -# Ensure that the OTBN util directory is on sys.path. This allows us to import -# modules "shared.foo" to get the OTBN shared code. +# Ensure that the ACC util directory is on sys.path. This allows us to import +# modules "shared.foo" to get the ACC shared code. sys.path.append(os.path.normpath(os.path.join(os.path.dirname(__file__), '../../../util'))) diff --git a/hw/ip/otbn/dv/otbnsim/sim/constants.py b/hw/ip/acc/dv/accsim/sim/constants.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/sim/constants.py rename to hw/ip/acc/dv/accsim/sim/constants.py diff --git a/hw/ip/otbn/dv/otbnsim/sim/csr.py b/hw/ip/acc/dv/accsim/sim/csr.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/sim/csr.py rename to hw/ip/acc/dv/accsim/sim/csr.py diff --git a/hw/ip/otbn/dv/otbnsim/sim/decode.py b/hw/ip/acc/dv/accsim/sim/decode.py similarity index 88% rename from hw/ip/otbn/dv/otbnsim/sim/decode.py rename to hw/ip/acc/dv/accsim/sim/decode.py index ab93c9aac6a..312793e54f5 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/decode.py +++ b/hw/ip/acc/dv/accsim/sim/decode.py @@ -8,17 +8,17 @@ from typing import Iterator, List, Optional, Tuple from .constants import ErrBits -from .isa import INSNS_FILE, OTBNInsn +from .isa import INSNS_FILE, ACCInsn from .insn import INSN_CLASSES -from .state import OTBNState +from .state import ACCState MNEM_TO_CLASS = {cls.insn.mnemonic: cls for cls in INSN_CLASSES} -class IllegalInsn(OTBNInsn): +class IllegalInsn(ACCInsn): '''A catch-all subclass of Instruction for bad data - This handles anything that doesn't decode correctly. Doing so for OTBN is + This handles anything that doesn't decode correctly. Doing so for ACC is much easier than if we wanted to support compressed-mode (RV32IC), because we don't need to worry about whether we have 16 or 32 bits of rubbish. @@ -35,12 +35,12 @@ def __init__(self, pc: int, raw: int, msg: str) -> None: # disassembling the underlying DummyInsn. self._disasm = (pc, '?? 0x{:08x}'.format(raw)) - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) return None -class EmptyInsn(OTBNInsn): +class EmptyInsn(ACCInsn): '''A subclass of Instruction that represents non-existent data This is what we generate on a fetch error, where we don't really have any @@ -57,12 +57,12 @@ def __init__(self, pc: int) -> None: # disassembling the underlying DummyInsn. self._disasm = (pc, '?? (no instruction data)') - def execute(self, state: 'OTBNState') -> Optional[Iterator[None]]: + def execute(self, state: 'ACCState') -> Optional[Iterator[None]]: state.stop_at_end_of_cycle(ErrBits.IMEM_INTG_VIOLATION) return None -def _decode_word(pc: int, word: int) -> OTBNInsn: +def _decode_word(pc: int, word: int) -> ACCInsn: mnem = INSNS_FILE.mnem_for_word(word) if mnem is None: return IllegalInsn(pc, word, 'No legal decoding') @@ -84,7 +84,7 @@ def _decode_word(pc: int, word: int) -> OTBNInsn: def decode_words(base_addr: int, - data: List[Tuple[bool, int]]) -> List[OTBNInsn]: + data: List[Tuple[bool, int]]) -> List[ACCInsn]: '''Decode instruction bytes as instructions''' ret = [] for idx, (vld, w32) in enumerate(data): @@ -93,7 +93,7 @@ def decode_words(base_addr: int, return ret -def decode_file(base_addr: int, path: str) -> List[OTBNInsn]: +def decode_file(base_addr: int, path: str) -> List[ACCInsn]: with open(path, 'rb') as handle: raw_bytes = handle.read() diff --git a/hw/ip/otbn/dv/otbnsim/sim/dmem.py b/hw/ip/acc/dv/accsim/sim/dmem.py similarity index 97% rename from hw/ip/otbn/dv/otbnsim/sim/dmem.py rename to hw/ip/acc/dv/accsim/sim/dmem.py index 0375f0cc405..921eea403e7 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/dmem.py +++ b/hw/ip/acc/dv/accsim/sim/dmem.py @@ -26,10 +26,10 @@ def trace(self) -> str: class Dmem: - '''An object representing OTBN's DMEM. + '''An object representing ACC's DMEM. Memory is stored as an array of 32-byte words (the native width for the - OTBN wide side). These words are stored as 256-bit unsigned integers. This + ACC wide side). These words are stored as 256-bit unsigned integers. This is the same width as the wide-side registers (to avoid unnecessary packing/unpacking work), but the unsigned values simplify tracing. @@ -44,7 +44,7 @@ def __init__(self) -> None: raise RuntimeError('Implausibly large DMEM size: {}' .format(dmem_size)) - # The native width for the OTBN wide side is 256 bits. This means that + # The native width for the ACC wide side is 256 bits. This means that # dmem_size needs to be divisible by 32. if dmem_size % 32: raise RuntimeError('DMEM size ({}) is not divisible by 32.' diff --git a/hw/ip/otbn/dv/otbnsim/sim/edn_client.py b/hw/ip/acc/dv/accsim/sim/edn_client.py similarity index 98% rename from hw/ip/otbn/dv/otbnsim/sim/edn_client.py rename to hw/ip/acc/dv/accsim/sim/edn_client.py index d50ed978f11..97c1be8880e 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/edn_client.py +++ b/hw/ip/acc/dv/accsim/sim/edn_client.py @@ -44,7 +44,7 @@ def request(self) -> None: self._acc = [] elif self._poisoned: # This is a request when there was a RND fetch pending (from the - # previous OTBN run), but we now actually want the results. + # previous ACC run), but we now actually want the results. self._retry = True def poison(self) -> None: diff --git a/hw/ip/otbn/dv/otbnsim/sim/ext_regs.py b/hw/ip/acc/dv/accsim/sim/ext_regs.py similarity index 96% rename from hw/ip/otbn/dv/otbnsim/sim/ext_regs.py rename to hw/ip/acc/dv/accsim/sim/ext_regs.py index 55cc8259d36..1df20d9286b 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/ext_regs.py +++ b/hw/ip/acc/dv/accsim/sim/ext_regs.py @@ -8,7 +8,7 @@ from reggen.register import Register from reggen.reg_block import RegBlock -from shared.otbn_reggen import load_registers +from shared.acc_reggen import load_registers from .edn_client import EdnClient from .trace import Trace @@ -31,7 +31,7 @@ def trace(self) -> str: suff = ('' if self.erc.new_value == self.erc.written else ' (now {:#010x})'.format(self.erc.new_value)) - return ("otbn.{} {} {:#010x}{}{}" + return ("acc.{} {} {:#010x}{}{}" .format(self.name, self.erc.op, self.erc.written, @@ -39,7 +39,7 @@ def trace(self) -> str: suff)) def rtl_trace(self) -> str: - return '! otbn.{}: {:#010x}'.format(self.name, self.erc.new_value) + return '! acc.{}: {:#010x}'.format(self.name, self.erc.new_value) class RGField: @@ -152,7 +152,7 @@ def write(self, immediately: bool = False) -> None: '''Stage the effects of writing a value. - If from_hw is true, this write is from OTBN hardware (rather than the + If from_hw is true, this write is from ACC hardware (rather than the bus). ''' @@ -241,8 +241,8 @@ def make_flag_reg(name: str, double_flopped: bool) -> RGReg: return RGReg([RGField(name, 32, 0, 0, 'ro')], double_flopped) -class OTBNExtRegs: - '''A class representing OTBN's externally visible CSRs +class ACCExtRegs: + '''A class representing ACC's externally visible CSRs This models an extra flop between the core and some of the externally visible registers by ensuring that a write only becomes visible after an @@ -274,7 +274,7 @@ def __init__(self) -> None: # finish. self.regs['STOP_PC'] = make_flag_reg('STOP_PC', True) - # Add a fake "RND_REQ" register to allow us to tell otbn_core_model to + # Add a fake "RND_REQ" register to allow us to tell acc_core_model to # generate an EDN request. Expose it as a field so that the state # object can poke it directly. self._rnd_req = RndReq('RND_REQ') diff --git a/hw/ip/otbn/dv/otbnsim/sim/flags.py b/hw/ip/acc/dv/accsim/sim/flags.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/sim/flags.py rename to hw/ip/acc/dv/accsim/sim/flags.py diff --git a/hw/ip/otbn/dv/otbnsim/sim/gpr.py b/hw/ip/acc/dv/accsim/sim/gpr.py similarity index 98% rename from hw/ip/otbn/dv/otbnsim/sim/gpr.py rename to hw/ip/acc/dv/accsim/sim/gpr.py index 556e951e184..5980238fef1 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/gpr.py +++ b/hw/ip/acc/dv/accsim/sim/gpr.py @@ -67,7 +67,7 @@ def start(self) -> None: class GPRs(RegFile): - '''The narrow OTBN register file''' + '''The narrow ACC register file''' def __init__(self) -> None: super().__init__('x', 32, 32) diff --git a/hw/ip/otbn/dv/otbnsim/sim/insn.py b/hw/ip/acc/dv/accsim/sim/insn.py similarity index 93% rename from hw/ip/otbn/dv/otbnsim/sim/insn.py rename to hw/ip/acc/dv/accsim/sim/insn.py index 5bb50469057..4c466a5b922 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/insn.py +++ b/hw/ip/acc/dv/accsim/sim/insn.py @@ -3,7 +3,7 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028). # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. # Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -15,11 +15,11 @@ from .constants import ErrBits from .flags import FlagReg -from .isa import (OTBNInsn, RV32RegReg, RV32RegImm, +from .isa import (ACCInsn, RV32RegReg, RV32RegImm, RV32ImmShift, insn_for_mnemonic, logical_byte_shift, bit_shift, extract_quarter_word, extract_sub_word) -from .state import OTBNState +from .state import ACCState DEBUG_MEM = False DEBUG_BRANCH = False @@ -59,7 +59,7 @@ def cmod_single_subv(n: int, q: int) -> int: class ADD(RV32RegReg): insn = insn_for_mnemonic('add', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() if state.gprs.call_stack_err: @@ -89,7 +89,7 @@ def execute(self, state: OTBNState) -> None: class ADDI(RV32RegImm): insn = insn_for_mnemonic('addi', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() if state.gprs.call_stack_err: state.stop_at_end_of_cycle(ErrBits.CALL_STACK) @@ -115,7 +115,7 @@ def execute(self, state: OTBNState) -> None: state.gprs.get_reg(self.grd).write_unsigned(result) -class LUI(OTBNInsn): +class LUI(ACCInsn): insn = insn_for_mnemonic('lui', 2) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -123,14 +123,14 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grd = op_vals['grd'] self.imm = op_vals['imm'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: state.gprs.get_reg(self.grd).write_unsigned(self.imm << 12) class SUB(RV32RegReg): insn = insn_for_mnemonic('sub', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() if state.gprs.call_stack_err: @@ -146,7 +146,7 @@ def execute(self, state: OTBNState) -> None: class SLL(RV32RegReg): insn = insn_for_mnemonic('sll', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() & 0x1f if state.gprs.call_stack_err: @@ -162,7 +162,7 @@ def execute(self, state: OTBNState) -> None: class SLLI(RV32ImmShift): insn = insn_for_mnemonic('slli', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() if state.gprs.call_stack_err: state.stop_at_end_of_cycle(ErrBits.CALL_STACK) @@ -176,7 +176,7 @@ def execute(self, state: OTBNState) -> None: class SRL(RV32RegReg): insn = insn_for_mnemonic('srl', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() & 0x1f if state.gprs.call_stack_err: @@ -192,7 +192,7 @@ def execute(self, state: OTBNState) -> None: class SRLI(RV32ImmShift): insn = insn_for_mnemonic('srli', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() if state.gprs.call_stack_err: state.stop_at_end_of_cycle(ErrBits.CALL_STACK) @@ -206,7 +206,7 @@ def execute(self, state: OTBNState) -> None: class SRA(RV32RegReg): insn = insn_for_mnemonic('sra', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_signed() val2 = state.gprs.get_reg(self.grs2).read_unsigned() & 0x1f if state.gprs.call_stack_err: @@ -222,7 +222,7 @@ def execute(self, state: OTBNState) -> None: class SRAI(RV32ImmShift): insn = insn_for_mnemonic('srai', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_signed() val2 = self.shamt if state.gprs.call_stack_err: @@ -236,7 +236,7 @@ def execute(self, state: OTBNState) -> None: class AND(RV32RegReg): insn = insn_for_mnemonic('and', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() if state.gprs.call_stack_err: @@ -252,7 +252,7 @@ def execute(self, state: OTBNState) -> None: class ANDI(RV32RegImm): insn = insn_for_mnemonic('andi', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = self.to_2s_complement(self.imm) if state.gprs.call_stack_err: @@ -267,7 +267,7 @@ def execute(self, state: OTBNState) -> None: class OR(RV32RegReg): insn = insn_for_mnemonic('or', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() if state.gprs.call_stack_err: @@ -282,7 +282,7 @@ def execute(self, state: OTBNState) -> None: class ORI(RV32RegImm): insn = insn_for_mnemonic('ori', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = self.to_2s_complement(self.imm) if state.gprs.call_stack_err: @@ -296,7 +296,7 @@ def execute(self, state: OTBNState) -> None: class XOR(RV32RegReg): insn = insn_for_mnemonic('xor', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() if state.gprs.call_stack_err: @@ -310,7 +310,7 @@ def execute(self, state: OTBNState) -> None: class XORI(RV32RegImm): insn = insn_for_mnemonic('xori', 3) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = self.to_2s_complement(self.imm) if state.gprs.call_stack_err: @@ -321,7 +321,7 @@ def execute(self, state: OTBNState) -> None: state.gprs.get_reg(self.grd).write_unsigned(result) -class LW(OTBNInsn): +class LW(ACCInsn): insn = insn_for_mnemonic('lw', 3) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -330,7 +330,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.offset = op_vals['offset'] self.grs1 = op_vals['grs1'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: # LW executes over two cycles. On the first cycle, we read the base # address, compute the load address and check it for correctness, then # perform the load itself, returning the result. @@ -369,7 +369,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: return None -class SW(OTBNInsn): +class SW(ACCInsn): insn = insn_for_mnemonic('sw', 3) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -378,7 +378,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.offset = op_vals['offset'] self.grs1 = op_vals['grs1'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: base = state.gprs.get_reg(self.grs1).read_unsigned() addr = (base + self.offset) & ((1 << 32) - 1) value = state.gprs.get_reg(self.grs2).read_unsigned() @@ -402,7 +402,7 @@ def execute(self, state: OTBNState) -> None: state.dmem.store_u32(addr, value) -class BEQ(OTBNInsn): +class BEQ(ACCInsn): insn = insn_for_mnemonic('beq', 3) affects_control = True has_fetch_stall = True @@ -413,7 +413,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs2 = op_vals['grs2'] self.offset = op_vals['offset'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() if state.gprs.call_stack_err: @@ -434,7 +434,7 @@ def execute(self, state: OTBNState) -> None: eprint("not taken") -class BNE(OTBNInsn): +class BNE(ACCInsn): insn = insn_for_mnemonic('bne', 3) affects_control = True has_fetch_stall = True @@ -445,7 +445,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs2 = op_vals['grs2'] self.offset = op_vals['offset'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() val2 = state.gprs.get_reg(self.grs2).read_unsigned() @@ -467,7 +467,7 @@ def execute(self, state: OTBNState) -> None: eprint("not taken") -class JAL(OTBNInsn): +class JAL(ACCInsn): insn = insn_for_mnemonic('jal', 2) affects_control = True has_fetch_stall = True @@ -477,7 +477,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grd = op_vals['grd'] self.offset = op_vals['offset'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: mask32 = ((1 << 32) - 1) link_pc = (state.pc + 4) & mask32 state.gprs.get_reg(self.grd).write_unsigned(link_pc) @@ -490,7 +490,7 @@ def execute(self, state: OTBNState) -> None: state.set_next_pc(next_pc) -class JALR(OTBNInsn): +class JALR(ACCInsn): insn = insn_for_mnemonic('jalr', 3) affects_control = True has_fetch_stall = True @@ -501,7 +501,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs1 = op_vals['grs1'] self.offset = op_vals['offset'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: val1 = state.gprs.get_reg(self.grs1).read_unsigned() if state.gprs.call_stack_err: state.stop_at_end_of_cycle(ErrBits.CALL_STACK) @@ -519,7 +519,7 @@ def execute(self, state: OTBNState) -> None: state.set_next_pc(next_pc) -class CSRRS(OTBNInsn): +class CSRRS(ACCInsn): insn = insn_for_mnemonic('csrrs', 3) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -528,7 +528,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.csr = op_vals['csr'] self.grs1 = op_vals['grs1'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: if not state.csrs.check_idx(self.csr): # Invalid CSR index. Stop with an illegal instruction error. state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) @@ -557,7 +557,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: return None -class CSRRW(OTBNInsn): +class CSRRW(ACCInsn): insn = insn_for_mnemonic('csrrw', 3) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -566,7 +566,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.csr = op_vals['csr'] self.grs1 = op_vals['grs1'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: # eprint("csrrw") if not state.csrs.check_idx(self.csr): # Invalid CSR index. Stop with an illegal instruction error. @@ -588,7 +588,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: if self.csr == 0x7f3: # A write to KMAC_PW might stall, if there is a pending write - # to the AppIntf FIFO inside OTBN Bignum ALU + # to the AppIntf FIFO inside ACC Bignum ALU if DEBUG_KMAC: eprint("\tBNWSRW FOR KMAC PARTIAL WRITE REGISTER") while state.wsrs.KMAC_MSG.pending_write_pw(): @@ -607,15 +607,15 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: return None -class ECALL(OTBNInsn): +class ECALL(ACCInsn): insn = insn_for_mnemonic('ecall', 0) - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: # Set INTR_STATE.done and STATUS, reflecting the fact we've stopped. state.stop_at_end_of_cycle(err_bits=0) -class LOOP(OTBNInsn): +class LOOP(ACCInsn): insn = insn_for_mnemonic('loop', 2) affects_control = True @@ -624,7 +624,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs = op_vals['grs'] self.bodysize = op_vals['bodysize'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: num_iters = state.gprs.get_reg(self.grs).read_unsigned() if state.gprs.call_stack_err: state.stop_at_end_of_cycle(ErrBits.CALL_STACK) @@ -636,7 +636,7 @@ def execute(self, state: OTBNState) -> None: state.loop_start(num_iters, self.bodysize) -class LOOPI(OTBNInsn): +class LOOPI(ACCInsn): insn = insn_for_mnemonic('loopi', 2) affects_control = True @@ -645,7 +645,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.iterations = op_vals['iterations'] self.bodysize = op_vals['bodysize'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: if DEBUG_FLOW: eprint("LOOPI") if self.iterations == 0: @@ -654,7 +654,7 @@ def execute(self, state: OTBNState) -> None: state.loop_start(self.iterations, self.bodysize) -class BNADD(OTBNInsn): +class BNADD(ACCInsn): insn = insn_for_mnemonic('bn.add', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -666,7 +666,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -685,7 +685,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNADDC(OTBNInsn): +class BNADDC(ACCInsn): insn = insn_for_mnemonic('bn.addc', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -697,7 +697,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -713,7 +713,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNADDI(OTBNInsn): +class BNADDI(ACCInsn): insn = insn_for_mnemonic('bn.addi', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -723,7 +723,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.imm = op_vals['imm'] self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs).read_unsigned() b = self.imm @@ -740,7 +740,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNADDM(OTBNInsn): +class BNADDM(ACCInsn): insn = insn_for_mnemonic('bn.addm', 3) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -749,7 +749,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs1 = op_vals['wrs1'] self.wrs2 = op_vals['wrs2'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() mod_val = state.wsrs.MOD.read_unsigned() @@ -770,7 +770,7 @@ def execute(self, state: OTBNState) -> None: state.wdrs.get_reg(self.wrd).write_unsigned(result) -class BNADDV(OTBNInsn): +class BNADDV(ACCInsn): insn = insn_for_mnemonic('bn.addv', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -780,7 +780,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs2 = op_vals['wrs2'] self.type = op_vals['type'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: if not state.EN_PQC: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) @@ -807,7 +807,7 @@ def execute(self, state: OTBNState) -> None: state.wdrs.get_reg(self.wrd).write_unsigned(result) -class BNMULV(OTBNInsn): +class BNMULV(ACCInsn): insn = insn_for_mnemonic('bn.mulv', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -817,7 +817,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs2 = op_vals['wrs2'] self.type = op_vals['type'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: if not state.EN_PQC: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) @@ -917,7 +917,7 @@ def execute(self, state: OTBNState) -> None: eprint(f"acch at the end = {hex(acch)}") -class BNMULVL(OTBNInsn): +class BNMULVL(ACCInsn): insn = insn_for_mnemonic('bn.mulv.l', 5) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -928,7 +928,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.lane_reg = op_vals['lane_reg'] self.lane_index = op_vals['lane_index'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: if not state.EN_PQC: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) @@ -1031,7 +1031,7 @@ def execute(self, state: OTBNState) -> None: eprint(f"acch at the end = {hex(acch)}") -class BNMULQACC(OTBNInsn): +class BNMULQACC(ACCInsn): insn = insn_for_mnemonic('bn.mulqacc', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1043,7 +1043,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs2_qwsel = op_vals['wrs2_qwsel'] self.acc_shift_imm = op_vals['acc_shift_imm'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() @@ -1066,7 +1066,7 @@ def execute(self, state: OTBNState) -> None: state.wsrs.ACC.write_unsigned(truncated) -class BNMULQACCWO(OTBNInsn): +class BNMULQACCWO(ACCInsn): insn = insn_for_mnemonic('bn.mulqacc.wo', 8) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1080,7 +1080,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.acc_shift_imm = op_vals['acc_shift_imm'] self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() @@ -1103,7 +1103,7 @@ def execute(self, state: OTBNState) -> None: state.set_mlz_flags(self.flag_group, truncated) -class BNMULQACCSO(OTBNInsn): +class BNMULQACCSO(ACCInsn): insn = insn_for_mnemonic('bn.mulqacc.so', 9) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1118,7 +1118,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.acc_shift_imm = op_vals['acc_shift_imm'] self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() @@ -1165,7 +1165,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, new_flags) -class BNSUB(OTBNInsn): +class BNSUB(ACCInsn): insn = insn_for_mnemonic('bn.sub', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1177,7 +1177,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -1196,7 +1196,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNSUBB(OTBNInsn): +class BNSUBB(ACCInsn): insn = insn_for_mnemonic('bn.subb', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1208,7 +1208,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -1224,7 +1224,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNSUBI(OTBNInsn): +class BNSUBI(ACCInsn): insn = insn_for_mnemonic('bn.subi', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1234,7 +1234,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.imm = op_vals['imm'] self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs).read_unsigned() b = self.imm @@ -1248,7 +1248,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNSUBM(OTBNInsn): +class BNSUBM(ACCInsn): insn = insn_for_mnemonic('bn.subm', 3) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1257,7 +1257,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs1 = op_vals['wrs1'] self.wrs2 = op_vals['wrs2'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() mod_val = state.wsrs.MOD.read_unsigned() @@ -1275,7 +1275,7 @@ def execute(self, state: OTBNState) -> None: state.wdrs.get_reg(self.wrd).write_unsigned(result) -class BNSUBV(OTBNInsn): +class BNSUBV(ACCInsn): insn = insn_for_mnemonic('bn.subv', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1285,7 +1285,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs2 = op_vals['wrs2'] self.type = op_vals['type'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: if not state.EN_PQC: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) @@ -1312,7 +1312,7 @@ def execute(self, state: OTBNState) -> None: state.wdrs.get_reg(self.wrd).write_unsigned(result) -class BNAND(OTBNInsn): +class BNAND(ACCInsn): insn = insn_for_mnemonic('bn.and', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1324,7 +1324,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -1339,7 +1339,7 @@ def execute(self, state: OTBNState) -> None: state.set_mlz_flags(self.flag_group, result) -class BNOR(OTBNInsn): +class BNOR(ACCInsn): insn = insn_for_mnemonic('bn.or', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1351,7 +1351,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -1366,7 +1366,7 @@ def execute(self, state: OTBNState) -> None: state.set_mlz_flags(self.flag_group, result) -class BNNOT(OTBNInsn): +class BNNOT(ACCInsn): insn = insn_for_mnemonic('bn.not', 5) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1377,7 +1377,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs).read_unsigned() a_shifted = logical_byte_shift(a, self.shift_type, self.shift_bytes) @@ -1386,7 +1386,7 @@ def execute(self, state: OTBNState) -> None: state.set_mlz_flags(self.flag_group, result) -class BNXOR(OTBNInsn): +class BNXOR(ACCInsn): insn = insn_for_mnemonic('bn.xor', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1398,7 +1398,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -1411,7 +1411,7 @@ def execute(self, state: OTBNState) -> None: state.set_mlz_flags(self.flag_group, result) -class BNRSHI(OTBNInsn): +class BNRSHI(ACCInsn): insn = insn_for_mnemonic('bn.rshi', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1421,7 +1421,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs2 = op_vals['wrs2'] self.imm = op_vals['imm'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() @@ -1431,7 +1431,7 @@ def execute(self, state: OTBNState) -> None: state.wdrs.get_reg(self.wrd).write_unsigned(result) -class BNSHV(OTBNInsn): +class BNSHV(ACCInsn): insn = insn_for_mnemonic('bn.shv', 6) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1443,7 +1443,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bits = op_vals['shift_bits'] self.shift_arith = op_vals['shift_arith'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: if not state.EN_PQC: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) @@ -1463,7 +1463,7 @@ def execute(self, state: OTBNState) -> None: state.wdrs.get_reg(self.wrd).write_unsigned(result) -class BNSEL(OTBNInsn): +class BNSEL(ACCInsn): insn = insn_for_mnemonic('bn.sel', 5) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1474,7 +1474,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.flag_group = op_vals['flag_group'] self.flag = op_vals['flag'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: flag_is_set = state.csrs.flags[self.flag_group].get_by_idx(self.flag) wrs = self.wrs1 if flag_is_set else self.wrs2 value = state.wdrs.get_reg(wrs).read_unsigned() @@ -1483,7 +1483,7 @@ def execute(self, state: OTBNState) -> None: state.wdrs.get_reg(self.wrd).write_unsigned(value) -class BNCMP(OTBNInsn): +class BNCMP(ACCInsn): insn = insn_for_mnemonic('bn.cmp', 5) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1494,7 +1494,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -1513,7 +1513,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNCMPB(OTBNInsn): +class BNCMPB(ACCInsn): insn = insn_for_mnemonic('bn.cmpb', 5) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1524,7 +1524,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.shift_bytes = op_vals['shift_bits'] // 8 self.flag_group = op_vals['flag_group'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: a = state.wdrs.get_reg(self.wrs1).read_unsigned() b = state.wdrs.get_reg(self.wrs2).read_unsigned() b_shifted = logical_byte_shift(b, self.shift_type, self.shift_bytes) @@ -1539,7 +1539,7 @@ def execute(self, state: OTBNState) -> None: state.set_flags(self.flag_group, flags) -class BNLID(OTBNInsn): +class BNLID(ACCInsn): insn = insn_for_mnemonic('bn.lid', 5) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1550,7 +1550,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs1 = op_vals['grs1'] self.grs1_inc = op_vals['grs1_inc'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: # BN.LID executes over two cycles. On the first cycle, we read the base # address, compute the load address and check it for correctness, # increment any GPRs, then perform the load itself. On the second @@ -1610,7 +1610,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: return None -class BNSID(OTBNInsn): +class BNSID(ACCInsn): insn = insn_for_mnemonic('bn.sid', 5) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1621,7 +1621,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs1 = op_vals['grs1'] self.grs1_inc = op_vals['grs1_inc'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: if self.grs1_inc and self.grs2_inc: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) return None @@ -1669,7 +1669,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: return None -class BNMOV(OTBNInsn): +class BNMOV(ACCInsn): insn = insn_for_mnemonic('bn.mov', 2) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1677,12 +1677,12 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrd = op_vals['wrd'] self.wrs = op_vals['wrs'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: value = state.wdrs.get_reg(self.wrs).read_unsigned() state.wdrs.get_reg(self.wrd).write_unsigned(value) -class BNMOVR(OTBNInsn): +class BNMOVR(ACCInsn): insn = insn_for_mnemonic('bn.movr', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1692,7 +1692,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs = op_vals['grs'] self.grs_inc = op_vals['grs_inc'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: if DEBUG_ARITH: eprint("MOVR") if self.grs_inc and self.grd_inc: @@ -1740,7 +1740,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: return None -class BNWSRR(OTBNInsn): +class BNWSRR(ACCInsn): insn = insn_for_mnemonic('bn.wsrr', 2) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1748,7 +1748,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrd = op_vals['wrd'] self.wsr = op_vals['wsr'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: # The first, and possibly only, cycle of execution. if not state.wsrs.check_idx(self.wsr): # Invalid WSR index. Stop with an illegal instruction error. @@ -1786,7 +1786,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: return None -class BNWSRW(OTBNInsn): +class BNWSRW(ACCInsn): insn = insn_for_mnemonic('bn.wsrw', 2) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1794,7 +1794,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wsr = op_vals['wsr'] self.wrs = op_vals['wrs'] - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: if DEBUG_KMAC: eprint(f"\tRun BNWSRW Address {self.wsr}") if not state.wsrs.check_idx(self.wsr): @@ -1816,7 +1816,7 @@ def execute(self, state: OTBNState) -> Optional[Iterator[None]]: state.wsrs.write_at_idx(self.wsr, val) -class BNTRN(OTBNInsn): +class BNTRN(ACCInsn): insn = insn_for_mnemonic('bn.trn', 4) def __init__(self, raw: int, op_vals: Dict[str, int]): @@ -1826,7 +1826,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.wrs2 = op_vals['wrs2'] self.type = op_vals['type'] - def execute(self, state: OTBNState) -> None: + def execute(self, state: ACCState) -> None: if not state.EN_PQC: state.stop_at_end_of_cycle(ErrBits.ILLEGAL_INSN) diff --git a/hw/ip/otbn/dv/otbnsim/sim/isa.py b/hw/ip/acc/dv/accsim/sim/isa.py similarity index 94% rename from hw/ip/otbn/dv/otbnsim/sim/isa.py rename to hw/ip/acc/dv/accsim/sim/isa.py index c1cb6149911..15d49439cdb 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/isa.py +++ b/hw/ip/acc/dv/accsim/sim/isa.py @@ -10,13 +10,13 @@ from shared.insn_yaml import Insn, DummyInsn, load_insns_yaml -from .state import OTBNState +from .state import ACCState # Load the insns.yml file at module load time: we'll use its data while -# declaring the classes. The point is that an OTBNInsn below is an instance of +# declaring the classes. The point is that an ACCInsn below is an instance of # a particular Insn object from shared.insn_yaml, so we want a class variable -# on the OTBNInsn that points at the corresponding Insn. +# on the ACCInsn that points at the corresponding Insn. try: INSNS_FILE = load_insns_yaml() except RuntimeError as err: @@ -50,8 +50,8 @@ def insn_for_mnemonic(mnemonic: str, num_operands: int) -> Insn: return insn -class OTBNInsn: - '''A decoded OTBN instruction. +class ACCInsn: + '''A decoded ACC instruction. ''' @@ -81,14 +81,14 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): # it can't hurt to check). self._disasm: Optional[Tuple[int, str]] = None - def execute(self, state: OTBNState) -> Optional[Iterator[None]]: + def execute(self, state: ACCState) -> Optional[Iterator[None]]: '''Execute the instruction This may yield (returning an iterator object) if the instruction has stalled the processor and will take multiple cycles. ''' - raise NotImplementedError('OTBNInsn.execute') + raise NotImplementedError('ACCInsn.execute') def disassemble(self, pc: int) -> str: '''Generate an assembly listing for this instruction''' @@ -127,7 +127,7 @@ def rtl_trace(self, pc: int) -> str: f'# @{pc:#010x}: ??') -class RV32RegReg(OTBNInsn): +class RV32RegReg(ACCInsn): '''A general class for register-register insns from the RV32I ISA''' def __init__(self, raw: int, op_vals: Dict[str, int]): super().__init__(raw, op_vals) @@ -136,7 +136,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.grs2 = op_vals['grs2'] -class RV32RegImm(OTBNInsn): +class RV32RegImm(ACCInsn): '''A general class for register-immediate insns from the RV32I ISA''' def __init__(self, raw: int, op_vals: Dict[str, int]): super().__init__(raw, op_vals) @@ -145,7 +145,7 @@ def __init__(self, raw: int, op_vals: Dict[str, int]): self.imm = op_vals['imm'] -class RV32ImmShift(OTBNInsn): +class RV32ImmShift(ACCInsn): '''A general class for immediate shift insns from the RV32I ISA''' def __init__(self, raw: int, op_vals: Dict[str, int]): super().__init__(raw, op_vals) diff --git a/hw/ip/otbn/dv/otbnsim/sim/kmac.py b/hw/ip/acc/dv/accsim/sim/kmac.py similarity index 99% rename from hw/ip/otbn/dv/otbnsim/sim/kmac.py rename to hw/ip/acc/dv/accsim/sim/kmac.py index fb7ce36a0f6..b80e02ef387 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/kmac.py +++ b/hw/ip/acc/dv/accsim/sim/kmac.py @@ -4,7 +4,7 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028) # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. @@ -67,7 +67,7 @@ class KmacBlock: # interface. _APP_INTF_BYTES_PER_CYCLE = 8 - # FIFO within OTBN that waits to send message data over the application + # FIFO within ACC that waits to send message data over the application # interface. Without this we'd have to stall on every message WSR write # while we wait to send data to KMAC. _APP_INTF_FIFO_SIZE_BYTES = 64 diff --git a/hw/ip/otbn/dv/otbnsim/sim/load_elf.py b/hw/ip/acc/dv/accsim/sim/load_elf.py similarity index 95% rename from hw/ip/otbn/dv/otbnsim/sim/load_elf.py rename to hw/ip/acc/dv/accsim/sim/load_elf.py index 9e8b55eb236..96086112cbe 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/load_elf.py +++ b/hw/ip/acc/dv/accsim/sim/load_elf.py @@ -5,7 +5,7 @@ # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. -'''OTBN ELF file handling''' +'''ACC ELF file handling''' import re import struct @@ -14,7 +14,7 @@ from shared.elf import read_elf from .decode import decode_words -from .sim import LoopWarps, OTBNSim +from .sim import LoopWarps, ACCSim def _get_exp_end_addr(symbols: Dict[str, int]) -> Optional[int]: @@ -72,7 +72,7 @@ def _get_loop_warps(symbols: Dict[str, int]) -> LoopWarps: return ret -def load_elf(sim: OTBNSim, path: str, dump_rtl_sim: bool = False) -> Optional[int]: +def load_elf(sim: ACCSim, path: str, dump_rtl_sim: bool = False) -> Optional[int]: '''Load ELF file at path and inject its contents into sim Returns the expected end address, if set, otherwise None. diff --git a/hw/ip/otbn/dv/otbnsim/sim/loop.py b/hw/ip/acc/dv/accsim/sim/loop.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/sim/loop.py rename to hw/ip/acc/dv/accsim/sim/loop.py diff --git a/hw/ip/otbn/dv/otbnsim/sim/reg.py b/hw/ip/acc/dv/accsim/sim/reg.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/sim/reg.py rename to hw/ip/acc/dv/accsim/sim/reg.py diff --git a/hw/ip/otbn/dv/otbnsim/sim/sim.py b/hw/ip/acc/dv/accsim/sim/sim.py similarity index 98% rename from hw/ip/otbn/dv/otbnsim/sim/sim.py rename to hw/ip/acc/dv/accsim/sim/sim.py index 6fccede7746..f9b94e7b103 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/sim.py +++ b/hw/ip/acc/dv/accsim/sim/sim.py @@ -9,8 +9,8 @@ from .constants import ErrBits, LcTx, Status, read_lc_tx_t from .decode import EmptyInsn -from .isa import OTBNInsn -from .state import OTBNState, FsmState +from .isa import ACCInsn +from .state import ACCState, FsmState from .stats import ExecutionStats from .trace import Trace @@ -22,21 +22,21 @@ # The return type of the Step function: a possible instruction that was # executed, together with a list of changes. -StepRes = Tuple[Optional[OTBNInsn], List[Trace]] +StepRes = Tuple[Optional[ACCInsn], List[Trace]] -class OTBNSim: +class ACCSim: def __init__(self, pqc: bool) -> None: self.EN_PQC = pqc - self.state = OTBNState(self.EN_PQC) - self.program: List[OTBNInsn] = [] + self.state = ACCState(self.EN_PQC) + self.program: List[ACCInsn] = [] self.loop_warps: LoopWarps = {} self.stats: Optional[ExecutionStats] = None self.symbols: Dict[str, int] = {} self._execute_generator: Optional[Iterator[None]] = None - self._next_insn: Optional[OTBNInsn] = None + self._next_insn: Optional[ACCInsn] = None - def load_program(self, program: List[OTBNInsn]) -> None: + def load_program(self, program: List[ACCInsn]) -> None: self.program = program.copy() self.state.clear_imem_invalidation() @@ -81,7 +81,7 @@ def start_mem_wipe(self, is_imem: bool) -> None: self.state.set_fsm_state(FsmState.MEM_SEC_WIPE) self.state.ext_regs.write('STATUS', new_status, True) - def _fetch(self, pc: int) -> OTBNInsn: + def _fetch(self, pc: int) -> ACCInsn: word_pc = pc >> 2 if word_pc >= len(self.program): raise RuntimeError('Trying to execute instruction at address ' @@ -117,7 +117,7 @@ def _on_stall(self, def _on_retire(self, verbose: bool, - insn: OTBNInsn) -> List[Trace]: + insn: ACCInsn) -> List[Trace]: '''This is run when an instruction completes''' assert self._execute_generator is None self.state.post_insn(self.loop_warps.get(self.state.pc, {})) @@ -212,7 +212,7 @@ def step(self, verbose: bool) -> StepRes: return stepper(verbose) def _step_idle(self, verbose: bool) -> StepRes: - '''Step the simulation when OTBN is IDLE or LOCKED''' + '''Step the simulation when ACC is IDLE or LOCKED''' self.state.stop_if_pending_halt() is_locked = self.state.get_fsm_state() == FsmState.LOCKED diff --git a/hw/ip/otbn/dv/otbnsim/sim/standalonesim.py b/hw/ip/acc/dv/accsim/sim/standalonesim.py similarity index 98% rename from hw/ip/otbn/dv/otbnsim/sim/standalonesim.py rename to hw/ip/acc/dv/accsim/sim/standalonesim.py index ba231e1b560..d7b6713674e 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/standalonesim.py +++ b/hw/ip/acc/dv/accsim/sim/standalonesim.py @@ -5,7 +5,7 @@ from itertools import cycle from typing import Dict, Optional, TextIO -from .sim import OTBNSim +from .sim import ACCSim from .state import FsmState _TEST_RND_DATA = cycle([ @@ -22,7 +22,7 @@ ] -class StandaloneSim(OTBNSim): +class StandaloneSim(ACCSim): def __init__(self, pqc: bool) -> None: super().__init__(pqc=pqc) diff --git a/hw/ip/otbn/dv/otbnsim/sim/state.py b/hw/ip/acc/dv/accsim/sim/state.py similarity index 95% rename from hw/ip/otbn/dv/otbnsim/sim/state.py rename to hw/ip/acc/dv/accsim/sim/state.py index 40d65a46936..0e00aeb4cdd 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/state.py +++ b/hw/ip/acc/dv/accsim/sim/state.py @@ -12,7 +12,7 @@ from .dmem import Dmem from .constants import ErrBits, LcTx, Status from .edn_client import EdnClient -from .ext_regs import OTBNExtRegs +from .ext_regs import ACCExtRegs from .flags import FlagReg from .gpr import GPRs from .loop import LoopStack @@ -40,7 +40,7 @@ class FsmState(IntEnum): | LOCKED <--------/ - PRE_WIPE is the initial state. OTBN is requesting a URND seed from the EDN. + PRE_WIPE is the initial state. ACC is requesting a URND seed from the EDN. Once it arrives, we jump to WIPING and perform an actual round of wiping internal state. Once that wipe is finished, we normally jump back to PRE_WIPE and then back to WIPING again. @@ -52,13 +52,13 @@ class FsmState(IntEnum): fatal errors. It matches Status.IDLE. LOCKED represents the state when there has been a fatal error. It matches Status.LOCKED. - MEM_SEC_WIPE only represents the state where OTBN is busy operating on + MEM_SEC_WIPE only represents the state where ACC is busy operating on secure wipe of DMEM/IMEM to perform the SEC_WIPE_I(D)MEM command. Secure wipe of the memories also happen when we encounter a fatal error while on Status.BUSY_EXECUTE. However, if we are getting a fatal error Status would be LOCKED. - PRE_EXEC is the period after starting OTBN where we're still waiting for an + PRE_EXEC is the period after starting ACC where we're still waiting for an EDN value to seed URND. EXEC is the period where we start fetching and executing instructions. ''' @@ -77,13 +77,13 @@ class InitSecWipeState(IntEnum): DONE = 2 -class OTBNState: +class ACCState: def __init__(self, pqc: bool) -> None: self.EN_PQC = pqc self.gprs = GPRs() self.wdrs = RegFile('w', 256, 32) - self.ext_regs = OTBNExtRegs() + self.ext_regs = ACCExtRegs() self.kmac = KmacBlock() self.wsrs = WSRFile(self.ext_regs, self.kmac, self.EN_PQC) self.csrs = CSRFile(self.EN_PQC) @@ -143,7 +143,7 @@ def __init__(self, pqc: bool) -> None: self.injected_err_bits = 0 self.lock_immediately = False - # OTBN might zero its insn_cnt register during a secure wipe. The + # ACC might zero its insn_cnt register during a secure wipe. The # precise cycle that this happens depends slightly on how we decide to # do so. If this is not None, it is a counter of the number of cycles # before the zeroing should happen. @@ -160,13 +160,13 @@ def __init__(self, pqc: bool) -> None: # An RMA request is seen if the rma_req_i signal (tracked as rma_req # here) is ON at a particular time. # - # The signal is observed by OTBN at a few specific times: + # The signal is observed by ACC at a few specific times: # - # - When OTBN is idle (the 'initial' and 'halt' states in - # otbn_start_stop_control) + # - When ACC is idle (the 'initial' and 'halt' states in + # acc_start_stop_control) # # - At the end of a secure wipe (the 'wipe complete' state in - # otbn_start_stop_control). It gets sampled at that particular + # acc_start_stop_control). It gets sampled at that particular # point to allow an RMA to be chosen after triggering an error but # before the secure wipe is completed and the module locks # completely. @@ -177,7 +177,7 @@ def __init__(self, pqc: bool) -> None: # This flag gets set as soon as we leave the Idle state for the first # time. It reflects the behaviour of wipe_after_urnd_refresh_q in - # otbn_start_stop_control.sv, which skips a round of secure wiping + # acc_start_stop_control.sv, which skips a round of secure wiping self.has_state_to_wipe = False # If this flag is set, jump straight to the LOCKED state when we step @@ -210,7 +210,7 @@ def edn_rnd_step(self, rnd_data: int, fips_err: bool) -> None: def edn_flush(self) -> None: self.ext_regs.rnd_reset() self._urnd_client.edn_reset() - # If the initial secure wipe is running, OTBN will directly request a + # If the initial secure wipe is running, ACC will directly request a # new URND value. if self.init_sec_wipe_is_running(): self._urnd_client.request() @@ -239,7 +239,7 @@ def urnd_completed(self) -> None: def start_init_sec_wipe(self) -> None: self._init_sec_wipe_state = InitSecWipeState.IN_PROGRESS - # OTBN will request a new URND value, so the model has to do the same. + # ACC will request a new URND value, so the model has to do the same. self._urnd_client.request() def init_sec_wipe_is_running(self) -> bool: diff --git a/hw/ip/otbn/dv/otbnsim/sim/stats.py b/hw/ip/acc/dv/accsim/sim/stats.py similarity index 97% rename from hw/ip/otbn/dv/otbnsim/sim/stats.py rename to hw/ip/acc/dv/accsim/sim/stats.py index fd2417f92d9..b8bb776f1b1 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/stats.py +++ b/hw/ip/acc/dv/accsim/sim/stats.py @@ -16,12 +16,12 @@ from operator import add from .insn import BEQ, BNE, ECALL, JAL, JALR, LOOP, LOOPI -from .isa import OTBNInsn -from .state import OTBNState +from .isa import ACCInsn +from .state import ACCState class ExecutionStats: - def __init__(self, program: List[OTBNInsn]) -> None: + def __init__(self, program: List[ACCInsn]) -> None: # Executed program (the contents of the instruction memory). self.program = program @@ -45,7 +45,7 @@ def get_insn_count(self) -> int: '''Get the number of executed instructions.''' return sum(self.insn_histo.values()) - def record_stall(self, state_bc: OTBNState) -> None: + def record_stall(self, state_bc: ACCState) -> None: '''Record a single stall cycle.''' self.stall_count += 1 @@ -63,7 +63,7 @@ def record_stall(self, state_bc: OTBNState) -> None: self.func_instrs[state_bc.pc] = {} self.func_instrs[state_bc.pc][mnemonic] = [0, 1] - def _insn_at_addr(self, addr: int) -> Optional[OTBNInsn]: + def _insn_at_addr(self, addr: int) -> Optional[ACCInsn]: '''Get the instruction at a given address.''' assert addr % 4 == 0 assert addr >= 0 @@ -71,12 +71,12 @@ def _insn_at_addr(self, addr: int) -> Optional[OTBNInsn]: return self.program[word_addr] def record_insn(self, - insn: OTBNInsn, - state_bc: OTBNState) -> None: + insn: ACCInsn, + state_bc: ACCState) -> None: '''Record the execution of an instruction. insn is the currently executed instruction. state_bc is the state of - OTBN before the instruction is committed. + ACC before the instruction is committed. ''' pc = state_bc.pc @@ -213,7 +213,7 @@ def _get_addr_symbol_map(elf_file: ELFFile) -> Dict[int, str]: class ExecutionStatAnalyzer: - # Assumed clock frequency of OTBN, in MHz. + # Assumed clock frequency of ACC, in MHz. FREQ_MHZ = 100 def __init__(self, stats: ExecutionStats, elf_file_path: str): @@ -311,7 +311,7 @@ def _dump_execution_time(self) -> str: cycles = insn_count + stall_count time_ms = cycles / (self.FREQ_MHZ * 1e6) * 1e3 - out = f"OTBN executed {insn_count} instructions in {cycles} cycles.\n" + out = f"ACC executed {insn_count} instructions in {cycles} cycles.\n" out += f"The execution stalled for {stall_count} cycles " out += f"({stall_percent:.01f} percent).\n" diff --git a/hw/ip/otbn/dv/otbnsim/sim/trace.py b/hw/ip/acc/dv/accsim/sim/trace.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/sim/trace.py rename to hw/ip/acc/dv/accsim/sim/trace.py diff --git a/hw/ip/otbn/dv/otbnsim/sim/wsr.py b/hw/ip/acc/dv/accsim/sim/wsr.py similarity index 97% rename from hw/ip/otbn/dv/otbnsim/sim/wsr.py rename to hw/ip/acc/dv/accsim/sim/wsr.py index 77475dc5ec8..c4e9e882822 100644 --- a/hw/ip/otbn/dv/otbnsim/sim/wsr.py +++ b/hw/ip/acc/dv/accsim/sim/wsr.py @@ -3,7 +3,7 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028). # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. # Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -13,7 +13,7 @@ import sys from typing import List, Optional, Sequence, Tuple from .trace import Trace -from .ext_regs import OTBNExtRegs +from .ext_regs import ACCExtRegs from .kmac import KmacBlock DEBUG_KMAC = False @@ -128,14 +128,14 @@ def changes(self) -> List[TraceWSR]: class RandWSR(WSR): '''The magic RND WSR - RND is special as OTBN can stall on reads to it. A read from RND either + RND is special as ACC can stall on reads to it. A read from RND either immediately returns data from a cache of a previous EDN request (triggered by writing to the RND_PREFETCH CSR) or waits for data from the EDN. To model this, anything reading from RND must first call `request_value` which returns True if the value is available. ''' - def __init__(self, name: str, ext_regs: OTBNExtRegs): + def __init__(self, name: str, ext_regs: ACCExtRegs): super().__init__(name) self._random_value: Optional[int] = None @@ -517,7 +517,7 @@ def commit(self) -> None: kmac_debug_print(f"\tREG -> KMAC_MSG reg: {hex(self._next_value)}") if self._value == (1 << 31): # config value to release KMAC app intf - # should be done once before OTBN yiels + # should be done once before ACC yiels # to Ibex self._kmac._reset() else: @@ -568,14 +568,14 @@ class KmacDigestWSR(WSR): If KMAC is in the "idle" state, reads always return 0. When KMAC is in the "absorb" state, reading from this register will issue a `process` command; KMAC will move into the "squeeze" state and begin computing the digest. - OTBN will stall until the digest computation finishes, and KMAC sends the + ACC will stall until the digest computation finishes, and KMAC sends the first 256 bits of the digest as the read result. Reads from this register in the "squeeze" state will pull 256-bit slices of the digest sequentially from KMAC. The amount of digest available after `process` depends on the rate of the specific Keccak instantiation. If 256 bits of digest are not available, a read from this register will issue the - `run` command to KMAC and again OTBN will stall until the full 256 bits is + `run` command to KMAC and again ACC will stall until the full 256 bits is ready. ''' def __init__(self, name: str, kmac: KmacBlock): @@ -591,7 +591,7 @@ def has_value(self) -> bool: def request_value(self) -> bool: '''Returns true if the full register value is ready, but only one cycle after digest_ready() is asserted, - modeling the OTBN app_req.next behavior''' + modeling the ACC app_req.next behavior''' self._has_value = self._kmac.digest_ready() kmac_debug_print(f"\tKMAC_DIGEST - Request value: {self._has_value}") @@ -619,7 +619,7 @@ def commit(self) -> None: class WSRFile: '''A model of the WSR file''' - def __init__(self, ext_regs: OTBNExtRegs, kmac: KmacBlock, pqc: bool) -> None: + def __init__(self, ext_regs: ACCExtRegs, kmac: KmacBlock, pqc: bool) -> None: self.EN_PQC = pqc self.KeyS0 = SideloadKey('KeyS0') self.KeyS1 = SideloadKey('KeyS1') diff --git a/hw/ip/otbn/dv/otbnsim/standalone.py b/hw/ip/acc/dv/accsim/standalone.py similarity index 94% rename from hw/ip/otbn/dv/otbnsim/standalone.py rename to hw/ip/acc/dv/accsim/standalone.py index 8d5304d2880..0d2b33ea48a 100755 --- a/hw/ip/otbn/dv/otbnsim/standalone.py +++ b/hw/ip/acc/dv/accsim/standalone.py @@ -14,7 +14,7 @@ from sim.load_elf import load_elf from sim.standalonesim import StandaloneSim from sim.stats import ExecutionStatAnalyzer -from shared.testcase import OtbnTestCase +from shared.testcase import AccTestCase def main() -> int: @@ -52,7 +52,7 @@ def main() -> int: parser.add_argument( '--pqc', type=bool, - help=("set otbnsim to PQC feature mode for ML-KEM and ML-DSA.") + help=("set accsim to PQC feature mode for ML-KEM and ML-DSA.") ) args = parser.parse_args() @@ -69,7 +69,7 @@ def main() -> int: testcase = None if args.testcase: - testcase = OtbnTestCase.from_hjson(args.testcase.read(), sim.symbols) + testcase = AccTestCase.from_hjson(args.testcase.read(), sim.symbols) key0 = int((str("deadbeef") * 12), 16) key1 = int((str("baadf00d") * 12), 16) diff --git a/hw/ip/otbn/dv/otbnsim/stepped.py b/hw/ip/acc/dv/accsim/stepped.py similarity index 85% rename from hw/ip/otbn/dv/otbnsim/stepped.py rename to hw/ip/acc/dv/accsim/stepped.py index 57acd0ddb2f..f78893fdb31 100755 --- a/hw/ip/otbn/dv/otbnsim/stepped.py +++ b/hw/ip/acc/dv/accsim/stepped.py @@ -80,7 +80,7 @@ from sim.decode import decode_file from sim.load_elf import load_elf -from sim.sim import OTBNSim +from sim.sim import ACCSim def read_word(arg_name: str, word_data: str, bits: int) -> int: @@ -117,7 +117,7 @@ def check_arg_count(cmd: str, cnt: int, args: List[str]) -> None: raise ValueError(f'{cmd} expects {txt_cnt} arguments. Got {args}.') -def on_start_operation(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_start_operation(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('start_operation', 1, args) command = args[0] @@ -134,7 +134,7 @@ def on_start_operation(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_step(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_step(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Step one instruction''' check_arg_count('step', 0, args) @@ -184,7 +184,7 @@ def on_step(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_load_elf(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_load_elf(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Load contents of ELF at path given by only argument''' check_arg_count('load_elf', 1, args) @@ -196,7 +196,7 @@ def on_load_elf(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_add_loop_warp(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_add_loop_warp(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Add a loop warp to the simulation''' check_arg_count('add_loop_warp', 3, args) @@ -220,7 +220,7 @@ def on_add_loop_warp(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_clear_loop_warps(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_clear_loop_warps(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Run until ecall or error''' check_arg_count('clear_loop_warps', 0, args) @@ -229,7 +229,7 @@ def on_clear_loop_warps(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_load_d(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_load_d(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Load contents of data memory from file at path given by only argument''' check_arg_count('load_d', 1, args) @@ -242,7 +242,7 @@ def on_load_d(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_load_i(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_load_i(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Load contents of insn memory from file at path given by only argument''' check_arg_count('load_i', 1, args) @@ -254,7 +254,7 @@ def on_load_i(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_dump_d(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_dump_d(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Dump contents of data memory to file at path given by only argument''' check_arg_count('dump_d', 1, args) @@ -268,7 +268,7 @@ def on_dump_d(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_print_regs(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_print_regs(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Print registers to stdout''' check_arg_count('print_regs', 0, args) @@ -281,7 +281,7 @@ def on_print_regs(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_print_call_stack(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_print_call_stack(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: '''Print call stack to stdout. First element is the bottom of the stack''' check_arg_count('print_call_stack', 0, args) @@ -292,12 +292,12 @@ def on_print_call_stack(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_reset(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_reset(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('reset', 0, args) - return OTBNSim(get_pqc_mode()) + return ACCSim(get_pqc_mode()) -def on_edn_rnd_step(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_edn_rnd_step(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('edn_rnd_step', 2, args) edn_rnd_data = read_word('edn_rnd_step', args[0], 32) fips_err = read_word('fips_err', args[1], 1) @@ -305,47 +305,47 @@ def on_edn_rnd_step(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_edn_urnd_step(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_edn_urnd_step(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('edn_urnd_step', 1, args) edn_urnd_data = read_word('edn_urnd_step', args[0], 32) sim.state.edn_urnd_step(edn_urnd_data) return None -def on_edn_flush(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_edn_flush(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('edn_flush', 0, args) sim.state.edn_flush() return None -def on_edn_urnd_cdc_done(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_edn_urnd_cdc_done(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('urnd_cdc_done', 0, args) sim.urnd_completed() return None -def on_edn_rnd_cdc_done(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_edn_rnd_cdc_done(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('edn_rnd_cdc_done', 0, args) sim.state.rnd_completed() return None -def on_invalidate_imem(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_invalidate_imem(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('invalidate_imem', 0, args) sim.state.invalidate_imem() return None -def on_invalidate_dmem(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_invalidate_dmem(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('invalidate_dmem', 0, args) sim.state.dmem.empty_dmem() return None -def on_set_software_errs_fatal(sim: OTBNSim, - args: List[str]) -> Optional[OTBNSim]: +def on_set_software_errs_fatal(sim: ACCSim, + args: List[str]) -> Optional[ACCSim]: check_arg_count('set_software_errs_fatal', 1, args) new_val = read_word('error', args[0], 1) assert new_val in [0, 1] @@ -354,7 +354,7 @@ def on_set_software_errs_fatal(sim: OTBNSim, return None -def on_set_keymgr_value(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_set_keymgr_value(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('set_keymgr_value', 3, args) key0 = read_word('key0', args[0], 384) key1 = read_word('key1', args[1], 384) @@ -365,19 +365,19 @@ def on_set_keymgr_value(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_step_crc(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_step_crc(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('step_crc', 2, args) item = read_word('item', args[0], 48) state = read_word('state', args[1], 32) new_state = binascii.crc32(item.to_bytes(6, 'little'), state) - print(f'! otbn.LOAD_CHECKSUM: 0x{new_state:08x}') + print(f'! acc.LOAD_CHECKSUM: 0x{new_state:08x}') return None -def on_send_err_escalation(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_send_err_escalation(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('send_err_escalation', 2, args) err_val = read_word('err_val', args[0], 32) lock_immediately = bool(read_word('lock_immediately', args[1], 1)) @@ -385,20 +385,20 @@ def on_send_err_escalation(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: return None -def on_set_rma_req(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_set_rma_req(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('set_rma_req', 1, args) rma_req = read_word('rma_req', args[0], 4) sim.set_rma_req(rma_req) return None -def on_initial_secure_wipe(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_initial_secure_wipe(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('initial_secure_wipe', 0, args) sim.initial_secure_wipe() return None -def on_otp_cdc_done(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: +def on_otp_cdc_done(sim: ACCSim, args: List[str]) -> Optional[ACCSim]: check_arg_count('otp_key_cdc_done', 0, args) sim.on_otp_cdc_done() @@ -434,7 +434,7 @@ def on_otp_cdc_done(sim: OTBNSim, args: List[str]) -> Optional[OTBNSim]: } -def on_input(sim: OTBNSim, line: str) -> Optional[OTBNSim]: +def on_input(sim: ACCSim, line: str) -> Optional[ACCSim]: '''Process an input command''' words = line.split() @@ -459,7 +459,7 @@ def get_pqc_mode() -> bool: def main() -> int: - sim = OTBNSim(get_pqc_mode()) + sim = ACCSim(get_pqc_mode()) try: for line in sys.stdin: ret = on_input(sim, line) @@ -467,7 +467,7 @@ def main() -> int: sim = ret except KeyboardInterrupt: - print("Received shutdown request, ending OTBN simulation.") + print("Received shutdown request, ending ACC simulation.") return 0 return 0 diff --git a/hw/ip/otbn/dv/otbnsim/test/conftest.py b/hw/ip/acc/dv/accsim/test/conftest.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/conftest.py rename to hw/ip/acc/dv/accsim/test/conftest.py diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/insns/add.exp b/hw/ip/acc/dv/accsim/test/simple/insns/add.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/insns/add.exp rename to hw/ip/acc/dv/accsim/test/simple/insns/add.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/insns/add.s b/hw/ip/acc/dv/accsim/test/simple/insns/add.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/insns/add.s rename to hw/ip/acc/dv/accsim/test/simple/insns/add.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/insns/addi.exp b/hw/ip/acc/dv/accsim/test/simple/insns/addi.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/insns/addi.exp rename to hw/ip/acc/dv/accsim/test/simple/insns/addi.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/insns/addi.s b/hw/ip/acc/dv/accsim/test/simple/insns/addi.s similarity index 90% rename from hw/ip/otbn/dv/otbnsim/test/simple/insns/addi.s rename to hw/ip/acc/dv/accsim/test/simple/insns/addi.s index e9cc9316dc4..210eb17ed91 100644 --- a/hw/ip/otbn/dv/otbnsim/test/simple/insns/addi.s +++ b/hw/ip/acc/dv/accsim/test/simple/insns/addi.s @@ -6,7 +6,7 @@ Simple tests of the addi instruction This test also uses a comment syntax that broke the parser in a - previous version of otbn_as.py: if editing it, keep the block + previous version of acc_as.py: if editing it, keep the block comments on the same lines as instructions to keep that test in place. diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/insns/bnlid.exp b/hw/ip/acc/dv/accsim/test/simple/insns/bnlid.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/insns/bnlid.exp rename to hw/ip/acc/dv/accsim/test/simple/insns/bnlid.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/insns/bnlid.s b/hw/ip/acc/dv/accsim/test/simple/insns/bnlid.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/insns/bnlid.s rename to hw/ip/acc/dv/accsim/test/simple/insns/bnlid.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-end-loop.exp b/hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-end-loop.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-end-loop.exp rename to hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-end-loop.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-end-loop.s b/hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-end-loop.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-end-loop.s rename to hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-end-loop.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-overflow.exp b/hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-overflow.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-overflow.exp rename to hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-overflow.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-overflow.s b/hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-overflow.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-overflow.s rename to hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-overflow.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-zero.exp b/hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-zero.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-zero.exp rename to hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-zero.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-zero.s b/hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-zero.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loop-errs/loop-zero.s rename to hw/ip/acc/dv/accsim/test/simple/loop-errs/loop-zero.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loops/loops.exp b/hw/ip/acc/dv/accsim/test/simple/loops/loops.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loops/loops.exp rename to hw/ip/acc/dv/accsim/test/simple/loops/loops.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/loops/loops.s b/hw/ip/acc/dv/accsim/test/simple/loops/loops.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/loops/loops.s rename to hw/ip/acc/dv/accsim/test/simple/loops/loops.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/README b/hw/ip/acc/dv/accsim/test/simple/multi/README similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/README rename to hw/ip/acc/dv/accsim/test/simple/multi/README diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/beq-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/beq-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/beq-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/beq-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/beq-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/beq-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/beq-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/beq-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/beq-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bne-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bne-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/bne-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bne-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bne-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bne-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/bne-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bne-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bne-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-2.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-2.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-2.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-2.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-2.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-2.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-2.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-2.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-3.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-3.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-3.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-3.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-3.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-3.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-3.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-3.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-4.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-4.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-4.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-4.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-4.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-4.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-4.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-4.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-5.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-5.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-5.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-5.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-5.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-5.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-5.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-5.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-6.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-6.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-6.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-6.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-6.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-6.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-6.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-6.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-7.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-7.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-7.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-7.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-7.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-7.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-7.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-7.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-8.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-8.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-8.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-8.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-8.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnlid-8.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnlid-8.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnlid-8.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-2.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-2.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-2.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-2.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-2.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-2.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-2.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-2.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-3.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-3.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-3.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-3.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-3.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-3.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-3.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-3.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-4.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-4.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-4.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-4.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-4.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-4.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-4.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-4.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-5.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-5.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-5.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-5.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-5.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-5.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnmovr-5.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnmovr-5.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-2.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-2.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-2.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-2.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-2.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-2.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-2.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-2.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-3.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-3.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-3.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-3.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-3.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-3.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-3.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-3.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-4.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-4.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-4.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-4.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-4.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-4.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-4.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-4.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-5.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-5.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-5.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-5.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-5.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-5.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-5.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-5.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-6.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-6.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-6.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-6.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-6.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-6.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-6.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-6.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-7.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-7.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-7.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-7.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-7.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-7.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-7.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-7.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-8.exp b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-8.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-8.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-8.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-8.s b/hw/ip/acc/dv/accsim/test/simple/multi/bnsid-8.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/bnsid-8.s rename to hw/ip/acc/dv/accsim/test/simple/multi/bnsid-8.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/csrrs-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrs-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/csrrs-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrs-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/csrrs-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrs-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/csrrs-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrs-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrs-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/csrrw-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrw-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/csrrw-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrw-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/csrrw-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrw-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/csrrw-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/csrrw-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/csrrw-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jal-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/jal-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jal-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/jal-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-2.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jal-2.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-2.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-2.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-2.s b/hw/ip/acc/dv/accsim/test/simple/multi/jal-2.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-2.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-2.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-3.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jal-3.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-3.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-3.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-3.s b/hw/ip/acc/dv/accsim/test/simple/multi/jal-3.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jal-3.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jal-3.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-2.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-2.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-2.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-2.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-2.s b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-2.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-2.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-2.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-3.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-3.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-3.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-3.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-3.s b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-3.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-3.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-3.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-4.exp b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-4.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-4.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-4.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-4.s b/hw/ip/acc/dv/accsim/test/simple/multi/jalr-4.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/jalr-4.s rename to hw/ip/acc/dv/accsim/test/simple/multi/jalr-4.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/loop-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/loop-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/loop-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/loop-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-1.exp b/hw/ip/acc/dv/accsim/test/simple/multi/loop-1.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-1.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/loop-1.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-1.s b/hw/ip/acc/dv/accsim/test/simple/multi/loop-1.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/loop-1.s rename to hw/ip/acc/dv/accsim/test/simple/multi/loop-1.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/loopi-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/loopi-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/loopi-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/loopi-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/loopi-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/loopi-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/loopi-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/loopi-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/lw-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/lw-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/lw-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/lw-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/lw-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/lw-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/lw-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/lw-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/sw-0.exp b/hw/ip/acc/dv/accsim/test/simple/multi/sw-0.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/sw-0.exp rename to hw/ip/acc/dv/accsim/test/simple/multi/sw-0.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/multi/sw-0.s b/hw/ip/acc/dv/accsim/test/simple/multi/sw-0.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/multi/sw-0.s rename to hw/ip/acc/dv/accsim/test/simple/multi/sw-0.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/pseudos/bigla.exp b/hw/ip/acc/dv/accsim/test/simple/pseudos/bigla.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/pseudos/bigla.exp rename to hw/ip/acc/dv/accsim/test/simple/pseudos/bigla.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/pseudos/bigla.s b/hw/ip/acc/dv/accsim/test/simple/pseudos/bigla.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/pseudos/bigla.s rename to hw/ip/acc/dv/accsim/test/simple/pseudos/bigla.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/pseudos/la.exp b/hw/ip/acc/dv/accsim/test/simple/pseudos/la.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/pseudos/la.exp rename to hw/ip/acc/dv/accsim/test/simple/pseudos/la.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/pseudos/la.s b/hw/ip/acc/dv/accsim/test/simple/pseudos/la.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/pseudos/la.s rename to hw/ip/acc/dv/accsim/test/simple/pseudos/la.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/pseudos/li.exp b/hw/ip/acc/dv/accsim/test/simple/pseudos/li.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/pseudos/li.exp rename to hw/ip/acc/dv/accsim/test/simple/pseudos/li.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/pseudos/li.s b/hw/ip/acc/dv/accsim/test/simple/pseudos/li.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/pseudos/li.s rename to hw/ip/acc/dv/accsim/test/simple/pseudos/li.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/relocs/hilo.exp b/hw/ip/acc/dv/accsim/test/simple/relocs/hilo.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/relocs/hilo.exp rename to hw/ip/acc/dv/accsim/test/simple/relocs/hilo.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/relocs/hilo.s b/hw/ip/acc/dv/accsim/test/simple/relocs/hilo.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/relocs/hilo.s rename to hw/ip/acc/dv/accsim/test/simple/relocs/hilo.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/subroutines/direct-call.exp b/hw/ip/acc/dv/accsim/test/simple/subroutines/direct-call.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/subroutines/direct-call.exp rename to hw/ip/acc/dv/accsim/test/simple/subroutines/direct-call.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/subroutines/direct-call.s b/hw/ip/acc/dv/accsim/test/simple/subroutines/direct-call.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/subroutines/direct-call.s rename to hw/ip/acc/dv/accsim/test/simple/subroutines/direct-call.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/subroutines/indirect-call.exp b/hw/ip/acc/dv/accsim/test/simple/subroutines/indirect-call.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/subroutines/indirect-call.exp rename to hw/ip/acc/dv/accsim/test/simple/subroutines/indirect-call.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/subroutines/indirect-call.s b/hw/ip/acc/dv/accsim/test/simple/subroutines/indirect-call.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/subroutines/indirect-call.s rename to hw/ip/acc/dv/accsim/test/simple/subroutines/indirect-call.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/x1/overflow.exp b/hw/ip/acc/dv/accsim/test/simple/x1/overflow.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/x1/overflow.exp rename to hw/ip/acc/dv/accsim/test/simple/x1/overflow.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/x1/overflow.s b/hw/ip/acc/dv/accsim/test/simple/x1/overflow.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/x1/overflow.s rename to hw/ip/acc/dv/accsim/test/simple/x1/overflow.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/x1/underflow.exp b/hw/ip/acc/dv/accsim/test/simple/x1/underflow.exp similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/x1/underflow.exp rename to hw/ip/acc/dv/accsim/test/simple/x1/underflow.exp diff --git a/hw/ip/otbn/dv/otbnsim/test/simple/x1/underflow.s b/hw/ip/acc/dv/accsim/test/simple/x1/underflow.s similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple/x1/underflow.s rename to hw/ip/acc/dv/accsim/test/simple/x1/underflow.s diff --git a/hw/ip/otbn/dv/otbnsim/test/simple_test.py b/hw/ip/acc/dv/accsim/test/simple_test.py similarity index 100% rename from hw/ip/otbn/dv/otbnsim/test/simple_test.py rename to hw/ip/acc/dv/accsim/test/simple_test.py diff --git a/hw/ip/otbn/dv/otbnsim/test/state_test.py b/hw/ip/acc/dv/accsim/test/state_test.py similarity index 97% rename from hw/ip/otbn/dv/otbnsim/test/state_test.py rename to hw/ip/acc/dv/accsim/test/state_test.py index 5f01047e2bc..fc51fd1f552 100644 --- a/hw/ip/otbn/dv/otbnsim/test/state_test.py +++ b/hw/ip/acc/dv/accsim/test/state_test.py @@ -2,7 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''Test the implementation of OTBNState.''' +'''Test the implementation of ACCState.''' import py diff --git a/hw/ip/otbn/dv/otbnsim/test/stats_test.py b/hw/ip/acc/dv/accsim/test/stats_test.py similarity index 98% rename from hw/ip/otbn/dv/otbnsim/test/stats_test.py rename to hw/ip/acc/dv/accsim/test/stats_test.py index 238c33fdd5a..33c07d8e068 100644 --- a/hw/ip/otbn/dv/otbnsim/test/stats_test.py +++ b/hw/ip/acc/dv/accsim/test/stats_test.py @@ -22,7 +22,7 @@ def _run_sim_for_stats(sim: StandaloneSim) -> ExecutionStats: def _simulate_asm_file(asm_file: str, tmpdir: py.path.local) -> ExecutionStats: - '''Run the OTBN simulator, collect statistics, and return them.''' + '''Run the ACC simulator, collect statistics, and return them.''' sim = testutil.prepare_sim_for_asm_file(asm_file, tmpdir, True) return _run_sim_for_stats(sim) diff --git a/hw/ip/otbn/dv/otbnsim/test/testutil.py b/hw/ip/acc/dv/accsim/test/testutil.py similarity index 82% rename from hw/ip/otbn/dv/otbnsim/test/testutil.py rename to hw/ip/acc/dv/accsim/test/testutil.py index 5648f487b32..1c812a37564 100644 --- a/hw/ip/otbn/dv/otbnsim/test/testutil.py +++ b/hw/ip/acc/dv/accsim/test/testutil.py @@ -10,8 +10,8 @@ from sim.load_elf import load_elf from sim.standalonesim import StandaloneSim -OTBN_DIR = os.path.join(os.path.dirname(__file__), '../../..') -UTIL_DIR = os.path.join(OTBN_DIR, 'util') +ACC_DIR = os.path.join(os.path.dirname(__file__), '../../..') +UTIL_DIR = os.path.join(ACC_DIR, 'util') SIM_DIR = os.path.join(os.path.dirname(__file__), '..') @@ -21,13 +21,13 @@ def asm_and_link_one_file(asm_path: str, work_dir: py.path.local) -> str: Returns the path to the resulting ELF ''' - otbn_as = os.path.join(UTIL_DIR, 'otbn_as.py') - otbn_ld = os.path.join(UTIL_DIR, 'otbn_ld.py') + acc_as = os.path.join(UTIL_DIR, 'acc_as.py') + acc_ld = os.path.join(UTIL_DIR, 'acc_ld.py') obj_path = os.path.join(work_dir, 'tst.o') elf_path = os.path.join(work_dir, 'tst') - subprocess.run([otbn_as, '-o', obj_path, asm_path], check=True) - subprocess.run([otbn_ld, '-o', elf_path, obj_path], check=True) + subprocess.run([acc_as, '-o', obj_path, asm_path], check=True) + subprocess.run([acc_ld, '-o', elf_path, obj_path], check=True) return elf_path diff --git a/hw/ip/otbn/dv/doc/fcov.md b/hw/ip/acc/dv/doc/fcov.md similarity index 97% rename from hw/ip/otbn/dv/doc/fcov.md rename to hw/ip/acc/dv/doc/fcov.md index 50dde00d044..7b2a17f271b 100644 --- a/hw/ip/otbn/dv/doc/fcov.md +++ b/hw/ip/acc/dv/doc/fcov.md @@ -1,4 +1,4 @@ -# OTBN functional coverage +# ACC functional coverage We distinguish between *architectural* and *micro-architectural* functional coverage. The idea is that the points that go into architectural coverage are those that a DV engineer could derive by reading the block specification. @@ -33,7 +33,7 @@ All four of these events should be crossed with the three states of the call sta The [loop stack](../README.md#loop-stack) is accessed by executing `LOOP` and `LOOPI` instructions. Events concerning the start of loops are tracked at those instructions, but we can't track things like loop completion there. -> Coverage for these points is tracked with cover properties in the `otbn_loop_if` interface. +> Coverage for these points is tracked with cover properties in the `acc_loop_if` interface. We expect to: - Complete a loop. @@ -60,13 +60,13 @@ See [CSRRS](#csrrs) and [CSRRW](#csrrw) for CSRs; [BN.WSRR](#bnwsrr) and [BN.WSR ## Random numbers -Random numbers are exposed to OTBN code through the `RND` and `URND` CSRs and WSRs. +Random numbers are exposed to ACC code through the `RND` and `URND` CSRs and WSRs. A new random number can be prefetched for `RND` with the `RND_PREFETCH` CSR. We track uses of each of these CSRs and WSRs in the instructions that access them. See [CSRRS](#csrrs) and [CSRRW](#csrrw) for CSRs; [BN.WSRR](#bnwsrr) and [BN.WSRW](#bnwsrw) for WSRs. However, we also want to see some interactions between `RND` and `RND_PREFETCH`. -These are all tracked with cover properties in `otbn_rnd_if.sv`. +These are all tracked with cover properties in `acc_rnd_if.sv`. Specifically, we expect to see: @@ -114,7 +114,7 @@ See the `mem_integrity` and `internal_integrity` entries in the testplan for mor ## Lifecycle escalation -The lifecycle controller can send a "lifecycle escalation" signal to tell OTBN to clear its internal state and to raise its own fatal error. +The lifecycle controller can send a "lifecycle escalation" signal to tell ACC to clear its internal state and to raise its own fatal error. We expect to see this happen. However, we don't track coverage for this explicitly since it's handled at the testplan level (with the `lc_escalation` testpoint). @@ -132,16 +132,16 @@ CSRs](#external-bus-accessible-csrs) section below. ## Scratchpad memory A portion of DMEM is inaccessible from the bus. -We want to see accesses (read and write) to both endpoints of the inaccessible portion of DMEM when OTBN is in an idle state (so would otherwise allow them). +We want to see accesses (read and write) to both endpoints of the inaccessible portion of DMEM when ACC is in an idle state (so would otherwise allow them). These are tracked in the `addr_cp` coverpoint in `scratchpad_writes_cg`. We also want to see a successful write to the top word of accessible DMEM. -We don't track that explicitly, since it is covered by the `otbn_mem_walk` test. +We don't track that explicitly, since it is covered by the `acc_mem_walk` test. ## External (bus-accessible) CSRs -The OTBN block exposes functionality to a bus host through bus-accessible CSRs. -Behavior of some CSRs depends on [OTBN's operational state](../../doc/theory_of_operation.md#operational-states). +The ACC block exposes functionality to a bus host through bus-accessible CSRs. +Behavior of some CSRs depends on [ACC's operational state](../../doc/theory_of_operation.md#operational-states). For every CSR (no matter its access restrictions), we want to see an attempt to read it and an attempt to write it. The CSRs are tracked in covergroups based on the CSR name, with the format: `ext_csr__cg`. @@ -157,7 +157,7 @@ We track the last write state for a CSR and then sample that covergroup when the Coverage is tracked in the `ext_csr_cmd_cg` covergroup. We want to see all valid commands (plus at least one invalid command) being written in each operational state. -This ensures commands are ignored as expected when OTBN is busy or locked. +This ensures commands are ignored as expected when ACC is busy or locked. It also ensures that bad commands are ignored as expected. The `cmd_cp` bin covers the different types of commands. @@ -240,8 +240,8 @@ This is tracked in the `ext_csr_wr_operational_state_cg` covergroup. # Instruction-based coverage -As a processor, much of OTBN's coverage points are described in terms of instructions being executed. -Because OTBN doesn't have a complicated multi-stage pipeline or any real exception handling, we don't track much temporal information (such as sequences of instructions). +As a processor, much of ACC's coverage points are described in terms of instructions being executed. +Because ACC doesn't have a complicated multi-stage pipeline or any real exception handling, we don't track much temporal information (such as sequences of instructions). As well as instruction-specific coverage points detailed below, we include a requirement that each instruction is executed at least once. @@ -250,7 +250,7 @@ That is, we expect to see execution with each bit of each immediate field being We also expect to see each field with values `'0` and `'1` (all zeros and all ones). If the field is treated as a signed number, we also expect to see it with the extremal values for its range (just the MSB set, for the most negative value; all but the MSB set, for the most positive value). -> The code to track this is split by encoding schema in `otbn_env_cov`. +> The code to track this is split by encoding schema in `acc_env_cov`. > Each instruction listed below will specify its encoding schema. > Each encoding schema then has its own covergroup. > Rather than tracking toggle coverage as described above, we just track extremal values in a coverpoint. @@ -265,7 +265,7 @@ If the field is treated as a signed number, we also expect to see it with the ex For any instruction that reads from or writes to a GPR, we expect to see that operand equal to `x0`, `x1` and an arbitrary register in the range `x2 .. x31`. We don't have any particular coverage requirements for WDRs (since all of them work essentially the same). -> As for immediates, the code to track this is split by encoding schema in `otbn_env_cov`. +> As for immediates, the code to track this is split by encoding schema in `acc_env_cov`. > Each register field gets a coverpoint with the same name, defined with the `DEF_GPR_CP` helper macro. > If the encoding schema has more than one instruction, the coverpoint is then crossed with the mnemonic, using the `DEF_MNEM_CROSS` helper macro. > For example, `add` is in the `enc_bnr_cg` covergroup. @@ -278,7 +278,7 @@ We want to see each of the 32 bits of that operand set and unset (giving 64 cove Similarly, `BN.ADD` reads from its `wrs1` operand. We want to see each of the 256 bits of that operand set and unset (giving 512 coverage points). -> Again, the code to track this is split by encoding schema in `otbn_env_cov`. +> Again, the code to track this is split by encoding schema in `acc_env_cov`. > The trace interface takes a copy of GPR and WDR read data. > The relevant register read data are then passed to the encoding schema's covergroup in the `on_insn` method. > To avoid extremely repetitive code, the actual coverpoints and crosses are defined with the help of macros. @@ -290,7 +290,7 @@ This needn't be crossed with the two flag groups (that's tracked separately in t For example, `BN.ADD` can write to each of the flags `C`, `M`, `L` and `Z`. This paragraph implies eight coverage points (four flags times two values) for that instruction. -> Again, the code to track this is split by encoding schema in `otbn_env_cov`. +> Again, the code to track this is split by encoding schema in `acc_env_cov`. > The trace interface takes a copy of flag write data. > It doesn't bother storing the flag write flags, since these are implied by the instruction anyway. > There is a coverage coverpoint tracking both values for each of the flags that can be written. diff --git a/hw/ip/otbn/dv/doc/model.svg b/hw/ip/acc/dv/doc/model.svg similarity index 98% rename from hw/ip/otbn/dv/doc/model.svg rename to hw/ip/acc/dv/doc/model.svg index 9f7018b2d89..ffe8e1627cf 100644 --- a/hw/ip/otbn/dv/doc/model.svg +++ b/hw/ip/acc/dv/doc/model.svg @@ -263,7 +263,7 @@ id="tspan839" x="105.76097" y="70.315781" - style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:4.93889px;font-family:'Liberation Mono';-inkscape-font-specification:'Liberation Mono';text-align:center;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.79375">otbn_core_model.sv + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:4.93889px;font-family:'Liberation Mono';-inkscape-font-specification:'Liberation Mono';text-align:center;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.79375">acc_core_model.sv otbn_model.cc + id="tspan848">acc_model.cc match the otbn modulematch the acc modulein otbn.sv + id="tspan1192">in acc.sv The code in otbn_core_model.sv is designed to beThe code in acc_core_model.sv is designed to beotbn_model.cc translates from DPI calls to a moreacc_model.cc translates from DPI calls to a moreiss_wrapper.cc doesn't know much about OTBN.iss_wrapper.cc doesn't know much about ACC.for OTBN. + id="tspan2269">for ACC. otbn_base_test + id="tspan861">acc_base_test otbn_env_cfg + id="tspan867">acc_env_cfg otbn_core_if + id="tspan875">acc_core_if otbn_model_agent_cfg + id="tspan883">acc_model_agent_cfg otbn_mem_if + id="tspan891">acc_mem_if otbn_base_test class derives) creates and runs the sequence acc_base_test class derives) creates and runs the sequence otbn_base_vseq + id="tspan941">acc_base_vseq otbn_env + id="tspan983">acc_env otbn_env_cov + id="tspan989">acc_env_cov otbn_scoreboard + id="tspan997">acc_scoreboard otbn_virtual_sequencer + id="tspan1005">acc_virtual_sequencer otbn_model_agent + id="tspan1013">acc_model_agent otbn + id="tspan1095">acc @@ -1182,7 +1182,7 @@ id="text1123">u_otbn_core + id="tspan1121">u_acc_core otbn_core_model + id="tspan1163">acc_core_model otbn_env_cfg object. To denote this, those classes are acc_env_cfg object. To denote this, those classes are connected by a dotted line to the otbn_env_cfg class. + style="shape-inside:url(#rect1653)">dotted line to the acc_env_cfg class. p_sequencer handle to the otbn_virtual_sequencer inside p_sequencer handle to the acc_virtual_sequencer inside the environment otbn_env inside the object of type otbn_base_test.acc_env inside the object of type acc_base_test.otbn_model_if + id="tspan1190">acc_model_if #include @@ -18,7 +18,7 @@ #include "sv_scoped.h" #include "sv_utils.h" -OtbnMemUtil::OtbnMemUtil(const std::string &top_scope) +AccMemUtil::AccMemUtil(const std::string &top_scope) : imem_(SVScoped::join_sv_scopes(top_scope, "u_imem"), 32768 / 4, 4 / 4), dmem_(SVScoped::join_sv_scopes(top_scope, "u_dmem"), 32768 / 32, 32 / 4), expected_end_addr_(-1) { @@ -26,21 +26,21 @@ OtbnMemUtil::OtbnMemUtil(const std::string &top_scope) RegisterMemoryArea("dmem", 0x18000, &dmem_); } -void OtbnMemUtil::LoadElf(const std::string &elf_path) { +void AccMemUtil::LoadElf(const std::string &elf_path) { LoadElfToMemories(false, elf_path); } -const StagedMem::SegMap &OtbnMemUtil::GetSegs(bool is_imem) const { +const StagedMem::SegMap &AccMemUtil::GetSegs(bool is_imem) const { return GetMemoryData(is_imem ? "imem" : "dmem").GetSegs(); } -uint32_t OtbnMemUtil::GetLoopWarp(uint32_t addr, uint32_t from_cnt) const { +uint32_t AccMemUtil::GetLoopWarp(uint32_t addr, uint32_t from_cnt) const { auto key = std::make_pair(addr, from_cnt); auto it = loop_warp_.find(key); return (it == loop_warp_.end()) ? from_cnt : it->second; } -void OtbnMemUtil::OnElfLoaded(Elf *elf_file) { +void AccMemUtil::OnElfLoaded(Elf *elf_file) { assert(elf_file); expected_end_addr_ = -1; @@ -73,7 +73,7 @@ void OtbnMemUtil::OnElfLoaded(Elf *elf_file) { } } -void OtbnMemUtil::OnSymbol(const std::string &name, uint32_t value) { +void AccMemUtil::OnSymbol(const std::string &name, uint32_t value) { // Expected end address if (name == "_expected_end_addr") { expected_end_addr_ = value; @@ -111,8 +111,8 @@ void OtbnMemUtil::OnSymbol(const std::string &name, uint32_t value) { } } -void OtbnMemUtil::AddLoopWarp(uint32_t addr, uint32_t from_cnt, - uint32_t to_cnt) { +void AccMemUtil::AddLoopWarp(uint32_t addr, uint32_t from_cnt, + uint32_t to_cnt) { auto key = std::make_pair(addr, from_cnt); auto pr = loop_warp_.insert(std::make_pair(key, to_cnt)); if (!pr.second) { @@ -127,19 +127,18 @@ void OtbnMemUtil::AddLoopWarp(uint32_t addr, uint32_t from_cnt, } } -extern "C" OtbnMemUtil *OtbnMemUtilMake(const char *top_scope) { +extern "C" AccMemUtil *AccMemUtilMake(const char *top_scope) { try { - return new OtbnMemUtil(top_scope); + return new AccMemUtil(top_scope); } catch (const std::exception &err) { - std::cerr << "Failed to create OtbnMemUtil: " << err.what() << "\n"; + std::cerr << "Failed to create AccMemUtil: " << err.what() << "\n"; return nullptr; } } -extern "C" void OtbnMemUtilFree(OtbnMemUtil *mem_util) { delete mem_util; } +extern "C" void AccMemUtilFree(AccMemUtil *mem_util) { delete mem_util; } -extern "C" svBit OtbnMemUtilLoadElf(OtbnMemUtil *mem_util, - const char *elf_path) { +extern "C" svBit AccMemUtilLoadElf(AccMemUtil *mem_util, const char *elf_path) { assert(mem_util); assert(elf_path); try { @@ -152,8 +151,8 @@ extern "C" svBit OtbnMemUtilLoadElf(OtbnMemUtil *mem_util, } } -extern "C" svBit OtbnMemUtilStageElf(OtbnMemUtil *mem_util, - const char *elf_path) { +extern "C" svBit AccMemUtilStageElf(AccMemUtil *mem_util, + const char *elf_path) { assert(mem_util); assert(elf_path); try { @@ -166,7 +165,7 @@ extern "C" svBit OtbnMemUtilStageElf(OtbnMemUtil *mem_util, } } -extern "C" int OtbnMemUtilGetSegCount(OtbnMemUtil *mem_util, svBit is_imem) { +extern "C" int AccMemUtilGetSegCount(AccMemUtil *mem_util, svBit is_imem) { assert(mem_util); const StagedMem::SegMap &segs = mem_util->GetSegs(is_imem); size_t num_segs = segs.size(); @@ -181,9 +180,9 @@ extern "C" int OtbnMemUtilGetSegCount(OtbnMemUtil *mem_util, svBit is_imem) { return num_segs; } -extern "C" svBit OtbnMemUtilGetSegInfo(OtbnMemUtil *mem_util, svBit is_imem, - int seg_idx, svBitVecVal *seg_off, - svBitVecVal *seg_size) { +extern "C" svBit AccMemUtilGetSegInfo(AccMemUtil *mem_util, svBit is_imem, + int seg_idx, svBitVecVal *seg_off, + svBitVecVal *seg_size) { assert(mem_util); assert(seg_off); assert(seg_size); @@ -228,8 +227,8 @@ extern "C" svBit OtbnMemUtilGetSegInfo(OtbnMemUtil *mem_util, svBit is_imem, return sv_1; } -extern "C" svBit OtbnMemUtilGetSegData( - OtbnMemUtil *mem_util, svBit is_imem, int word_off, +extern "C" svBit AccMemUtilGetSegData( + AccMemUtil *mem_util, svBit is_imem, int word_off, /* output bit[31:0] */ svBitVecVal *data_value) { assert(mem_util); assert(data_value); @@ -273,15 +272,15 @@ extern "C" svBit OtbnMemUtilGetSegData( return sv_1; } -int OtbnMemUtilGetExpEndAddr(OtbnMemUtil *mem_util) { +int AccMemUtilGetExpEndAddr(AccMemUtil *mem_util) { assert(mem_util); return mem_util->GetExpEndAddr(); } -svBit OtbnMemUtilGetLoopWarp(OtbnMemUtil *mem_util, - /* bit [31:0] */ const svBitVecVal *addr, - /* bit [31:0] */ const svBitVecVal *from_cnt, - /* output bit [31:0] */ svBitVecVal *to_cnt) { +svBit AccMemUtilGetLoopWarp(AccMemUtil *mem_util, + /* bit [31:0] */ const svBitVecVal *addr, + /* bit [31:0] */ const svBitVecVal *from_cnt, + /* output bit [31:0] */ svBitVecVal *to_cnt) { assert(mem_util); uint32_t addr32 = get_sv_u32(addr); uint32_t from32 = get_sv_u32(from_cnt); @@ -290,7 +289,7 @@ svBit OtbnMemUtilGetLoopWarp(OtbnMemUtil *mem_util, return to32 != from32; } -int OtbnMemUtilGetNumLoopWarps(OtbnMemUtil *mem_util) { +int AccMemUtilGetNumLoopWarps(AccMemUtil *mem_util) { assert(mem_util); size_t sz = mem_util->GetLoopWarps().size(); @@ -299,11 +298,10 @@ int OtbnMemUtilGetNumLoopWarps(OtbnMemUtil *mem_util) { return sz; } -void OtbnMemUtilGetLoopWarpByIndex( - OtbnMemUtil *mem_util, int idx, - /* output bit [31:0] */ svBitVecVal *addr, - /* output bit [31:0] */ svBitVecVal *from_cnt, - /* output bit [31:0] */ svBitVecVal *to_cnt) { +void AccMemUtilGetLoopWarpByIndex(AccMemUtil *mem_util, int idx, + /* output bit [31:0] */ svBitVecVal *addr, + /* output bit [31:0] */ svBitVecVal *from_cnt, + /* output bit [31:0] */ svBitVecVal *to_cnt) { assert(mem_util); assert(0 <= idx); diff --git a/hw/ip/otbn/dv/memutil/otbn_memutil.core b/hw/ip/acc/dv/memutil/acc_memutil.core similarity index 64% rename from hw/ip/otbn/dv/memutil/otbn_memutil.core rename to hw/ip/acc/dv/memutil/acc_memutil.core index 4a63b793567..52df30e64d9 100644 --- a/hw/ip/otbn/dv/memutil/otbn_memutil.core +++ b/hw/ip/acc/dv/memutil/acc_memutil.core @@ -3,17 +3,17 @@ CAPI=2: # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_memutil" -description: "A wrapper around memutil_verilator for OTBN" +name: "lowrisc:dv:acc_memutil" +description: "A wrapper around memutil_verilator for ACC" filesets: files_cpp: depend: - lowrisc:dv_verilator:memutil_dpi_scrambled files: - - otbn_memutil.cc - - otbn_memutil.h: { is_include_file: true } - - otbn_memutil_pkg.sv: { file_type: systemVerilogSource } + - acc_memutil.cc + - acc_memutil.h: { is_include_file: true } + - acc_memutil_pkg.sv: { file_type: systemVerilogSource } - sv_utils.h: { file_type: cppSource, is_include_file: true } file_type: cppSource diff --git a/hw/ip/otbn/dv/memutil/otbn_memutil.h b/hw/ip/acc/dv/memutil/acc_memutil.h similarity index 67% rename from hw/ip/otbn/dv/memutil/otbn_memutil.h rename to hw/ip/acc/dv/memutil/acc_memutil.h index 8cefc2fb6e3..cb48994ef9e 100644 --- a/hw/ip/otbn/dv/memutil/otbn_memutil.h +++ b/hw/ip/acc/dv/memutil/acc_memutil.h @@ -1,8 +1,8 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_MEMUTIL_OTBN_MEMUTIL_H_ -#define OPENTITAN_HW_IP_OTBN_DV_MEMUTIL_OTBN_MEMUTIL_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_MEMUTIL_ACC_MEMUTIL_H_ +#define OPENTITAN_HW_IP_ACC_DV_MEMUTIL_ACC_MEMUTIL_H_ #include #include @@ -11,13 +11,13 @@ #include "dpi_memutil.h" #include "scrambled_ecc32_mem_area.h" -class OtbnMemUtil : public DpiMemUtil { +class AccMemUtil : public DpiMemUtil { public: typedef std::map, uint32_t> LoopWarps; // Constructor. top_scope is the SV scope that contains IMEM and // DMEM memories as u_imem and u_dmem, respectively. - OtbnMemUtil(const std::string &top_scope); + AccMemUtil(const std::string &top_scope); // Load an ELF file at the given path and backdoor load it into the // attached memories. @@ -59,27 +59,27 @@ class OtbnMemUtil : public DpiMemUtil { // DPI-accessible wrappers extern "C" { -OtbnMemUtil *OtbnMemUtilMake(const char *top_scope); -void OtbnMemUtilFree(OtbnMemUtil *mem_util); +AccMemUtil *AccMemUtilMake(const char *top_scope); +void AccMemUtilFree(AccMemUtil *mem_util); // Loads an ELF file into memory via the backdoor. Returns 1'b1 on success. // Prints a message to stderr and returns 1'b0 on failure. -svBit OtbnMemUtilLoadElf(OtbnMemUtil *mem_util, const char *elf_path); +svBit AccMemUtilLoadElf(AccMemUtil *mem_util, const char *elf_path); -// Loads an ELF file into the OtbnMemUtil object, but doesn't touch the +// Loads an ELF file into the AccMemUtil object, but doesn't touch the // simulated memory. Returns 1'b1 on success. Prints a message to stderr and // returns 1'b0 on failure. -svBit OtbnMemUtilStageElf(OtbnMemUtil *mem_util, const char *elf_path); +svBit AccMemUtilStageElf(AccMemUtil *mem_util, const char *elf_path); // Returns the number of segments currently staged in imem/dmem. -int OtbnMemUtilGetSegCount(OtbnMemUtil *mem_util, svBit is_imem); +int AccMemUtilGetSegCount(AccMemUtil *mem_util, svBit is_imem); // Gets offset and size (both in 32-bit words) for a segment currently staged // in imem/dmem. Both are returned with output arguments. Returns 1'b1 on // success. Prints a message to stderr and returns 1'b0 on failure. -svBit OtbnMemUtilGetSegInfo(OtbnMemUtil *mem_util, svBit is_imem, int seg_idx, - /* output bit[31:0] */ svBitVecVal *seg_off, - /* output bit[31:0] */ svBitVecVal *seg_size); +svBit AccMemUtilGetSegInfo(AccMemUtil *mem_util, svBit is_imem, int seg_idx, + /* output bit[31:0] */ svBitVecVal *seg_off, + /* output bit[31:0] */ svBitVecVal *seg_size); // Gets a word of data from segments currently staged in imem/dmem. If there // is a word at that address, the function writes its value to the output @@ -88,8 +88,8 @@ svBit OtbnMemUtilGetSegInfo(OtbnMemUtil *mem_util, svBit is_imem, int seg_idx, // // If word_off is invalid (negative or enormous), the function writes a // message to stderr and returns 1'b0. -svBit OtbnMemUtilGetSegData(OtbnMemUtil *mem_util, svBit is_imem, int word_off, - /* output bit[31:0] */ svBitVecVal *data_value); +svBit AccMemUtilGetSegData(AccMemUtil *mem_util, svBit is_imem, int word_off, + /* output bit[31:0] */ svBitVecVal *data_value); // Get an "expected end address". This is a belt-and-braces check, where the // producer of the ELF file knows what address they expect to finish at (either @@ -97,34 +97,33 @@ svBit OtbnMemUtilGetSegData(OtbnMemUtil *mem_util, svBit is_imem, int word_off, // symbol in the ELF file and then we check at simulation time that we really // did stop there. // -// Note: This functionality doesn't provide any extra check of OTBN itself. +// Note: This functionality doesn't provide any extra check of ACC itself. // Rather, it's helpful for debugging the random instruction generator, which // is supposed to be able to predict (roughly) what its instruction streams // will do. // // Returns the output address as an integer. A negative result means that no // such address is present in the ELF file. -int OtbnMemUtilGetExpEndAddr(OtbnMemUtil *mem_util); +int AccMemUtilGetExpEndAddr(AccMemUtil *mem_util); // Get a loop warp entry, if there is one. // // Returns 1'b0 if there is no matching entry. On a matching entry, // returns 1'b1 and writes the new count to to_cnt. -svBit OtbnMemUtilGetLoopWarp(OtbnMemUtil *mem_util, - /* bit [31:0] */ const svBitVecVal *addr, - /* bit [31:0] */ const svBitVecVal *from_cnt, - /* output bit [31:0] */ svBitVecVal *to_cnt); +svBit AccMemUtilGetLoopWarp(AccMemUtil *mem_util, + /* bit [31:0] */ const svBitVecVal *addr, + /* bit [31:0] */ const svBitVecVal *from_cnt, + /* output bit [31:0] */ svBitVecVal *to_cnt); // Get the number of loop warps -int OtbnMemUtilGetNumLoopWarps(OtbnMemUtil *mem_util); +int AccMemUtilGetNumLoopWarps(AccMemUtil *mem_util); // Get a loop warp by index (should be less than returned by -// OtbnMemUtilGetNumLoopWarps). -void OtbnMemUtilGetLoopWarpByIndex( - OtbnMemUtil *mem_util, int idx, - /* output bit [31:0] */ svBitVecVal *addr, - /* output bit [31:0] */ svBitVecVal *from_cnt, - /* output bit [31:0] */ svBitVecVal *to_cnt); +// AccMemUtilGetNumLoopWarps). +void AccMemUtilGetLoopWarpByIndex(AccMemUtil *mem_util, int idx, + /* output bit [31:0] */ svBitVecVal *addr, + /* output bit [31:0] */ svBitVecVal *from_cnt, + /* output bit [31:0] */ svBitVecVal *to_cnt); } -#endif // OPENTITAN_HW_IP_OTBN_DV_MEMUTIL_OTBN_MEMUTIL_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_MEMUTIL_ACC_MEMUTIL_H_ diff --git a/hw/ip/otbn/dv/memutil/otbn_memutil_pkg.sv b/hw/ip/acc/dv/memutil/acc_memutil_pkg.sv similarity index 51% rename from hw/ip/otbn/dv/memutil/otbn_memutil_pkg.sv rename to hw/ip/acc/dv/memutil/acc_memutil_pkg.sv index a9365b7d8c4..84b6a98c7c5 100644 --- a/hw/ip/otbn/dv/memutil/otbn_memutil_pkg.sv +++ b/hw/ip/acc/dv/memutil/acc_memutil_pkg.sv @@ -2,38 +2,38 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// Imports for the functions defined in otbn_memutil.h. There are documentation comments explaining +// Imports for the functions defined in acc_memutil.h. There are documentation comments explaining // what the functions do there. `ifndef SYNTHESIS -package otbn_memutil_pkg; +package acc_memutil_pkg; - import "DPI-C" function chandle OtbnMemUtilMake(string top_scope); + import "DPI-C" function chandle AccMemUtilMake(string top_scope); - import "DPI-C" function void OtbnMemUtilFree(chandle mem_util); + import "DPI-C" function void AccMemUtilFree(chandle mem_util); - import "DPI-C" context function bit OtbnMemUtilLoadElf(chandle mem_util, string elf_path); + import "DPI-C" context function bit AccMemUtilLoadElf(chandle mem_util, string elf_path); - import "DPI-C" function bit OtbnMemUtilStageElf(chandle mem_util, string elf_path); + import "DPI-C" function bit AccMemUtilStageElf(chandle mem_util, string elf_path); - import "DPI-C" function int OtbnMemUtilGetSegCount(chandle mem_util, bit is_imem); + import "DPI-C" function int AccMemUtilGetSegCount(chandle mem_util, bit is_imem); - import "DPI-C" function bit OtbnMemUtilGetSegInfo(chandle mem_util, bit is_imem, int seg_idx, + import "DPI-C" function bit AccMemUtilGetSegInfo(chandle mem_util, bit is_imem, int seg_idx, output bit [31:0] seg_off, output bit [31:0] seg_size); - import "DPI-C" function bit OtbnMemUtilGetSegData(chandle mem_util, bit is_imem, int word_off, + import "DPI-C" function bit AccMemUtilGetSegData(chandle mem_util, bit is_imem, int word_off, output bit [31:0] data_value); - import "DPI-C" function int OtbnMemUtilGetExpEndAddr(chandle mem_util); + import "DPI-C" function int AccMemUtilGetExpEndAddr(chandle mem_util); - import "DPI-C" function bit OtbnMemUtilGetLoopWarp(chandle mem_util, + import "DPI-C" function bit AccMemUtilGetLoopWarp(chandle mem_util, bit [31:0] addr, bit [31:0] from_cnt, output bit [31:0] to_cnt); - import "DPI-C" function int OtbnMemUtilGetNumLoopWarps(chandle mem_util); + import "DPI-C" function int AccMemUtilGetNumLoopWarps(chandle mem_util); - import "DPI-C" function void OtbnMemUtilGetLoopWarpByIndex(chandle mem_util, + import "DPI-C" function void AccMemUtilGetLoopWarpByIndex(chandle mem_util, int idx, output bit [31:0] addr, output bit [31:0] from_cnt, diff --git a/hw/ip/acc/dv/memutil/acc_memutil_sim_opts.hjson b/hw/ip/acc/dv/memutil/acc_memutil_sim_opts.hjson new file mode 100644 index 00000000000..a48cc477594 --- /dev/null +++ b/hw/ip/acc/dv/memutil/acc_memutil_sim_opts.hjson @@ -0,0 +1,29 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Additional build-time options needed to compile C++ sources in + // simulators such as VCS and Xcelium for anything that uses + // acc_memutil. + // In addition to the build options here the user also must include the + // hw/dv/verilator/memutil_dpi_scrambled_opts.hjson file. + acc_memutil_core: "lowrisc:dv:acc_memutil:0" + acc_memutil_src_dir: "{eval_cmd} echo \"{acc_memutil_core}\" | tr ':' '_'" + + build_modes: [ + { + name: vcs_acc_memutil_build_opts + build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{acc_memutil_src_dir}"] + } + + { + name: xcelium_acc_memutil_build_opts + build_opts: ["-I{build_dir}/fusesoc-work/src/{acc_memutil_src_dir}"] + } + + { + name: dsim_acc_memutil_build_opts + build_opts: ["-c-opts -I{build_dir}/fusesoc-work/src/{acc_memutil_src_dir}"] + } + ] +} diff --git a/hw/ip/otbn/dv/memutil/sv_utils.h b/hw/ip/acc/dv/memutil/sv_utils.h similarity index 86% rename from hw/ip/otbn/dv/memutil/sv_utils.h rename to hw/ip/acc/dv/memutil/sv_utils.h index d7e07539383..aaaba1356ee 100644 --- a/hw/ip/otbn/dv/memutil/sv_utils.h +++ b/hw/ip/acc/dv/memutil/sv_utils.h @@ -1,8 +1,8 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_MEMUTIL_SV_UTILS_H_ -#define OPENTITAN_HW_IP_OTBN_DV_MEMUTIL_SV_UTILS_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_MEMUTIL_SV_UTILS_H_ +#define OPENTITAN_HW_IP_ACC_DV_MEMUTIL_SV_UTILS_H_ #include @@ -34,4 +34,4 @@ inline uint32_t get_sv_u32(const svBitVecVal *src) { return ret; } -#endif // OPENTITAN_HW_IP_OTBN_DV_MEMUTIL_SV_UTILS_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_MEMUTIL_SV_UTILS_H_ diff --git a/hw/ip/otbn/dv/model/otbn_core_model.sv b/hw/ip/acc/dv/model/acc_core_model.sv similarity index 77% rename from hw/ip/otbn/dv/model/otbn_core_model.sv rename to hw/ip/acc/dv/model/acc_core_model.sv index e8631f379e6..fc41419f8a3 100644 --- a/hw/ip/otbn/dv/model/otbn_core_model.sv +++ b/hw/ip/acc/dv/model/acc_core_model.sv @@ -6,20 +6,20 @@ `include "prim_assert.sv" /** - * OpenTitan Big Number Accelerator (OTBN) Core + * OpenTitan Big Number Accelerator (ACC) Core * - * This module is the top-level of the OTBN processing core. + * This module is the top-level of the ACC processing core. */ -module otbn_core_model - import otbn_pkg::*; +module acc_core_model + import acc_pkg::*; import edn_pkg::*; - import keymgr_pkg::otbn_key_req_t; + import keymgr_pkg::acc_key_req_t; #( // The scope that contains the instruction and data memory (for DPI) parameter string MemScope = "", - // Scope of an RTL OTBN implementation (for DPI). This should be give the scope for the top-level + // Scope of an RTL ACC implementation (for DPI). This should be give the scope for the top-level // of a real implementation running alongside. We will use it to check DMEM and register file // contents on completion of an operation. parameter string DesignScope = "" @@ -29,8 +29,8 @@ module otbn_core_model input logic rst_ni, input logic rst_edn_ni, - input logic [7:0] cmd_i, // CMD register for OTBN commands - input logic cmd_en_i, // CMD register enable for OTBN commands + input logic [7:0] cmd_i, // CMD register for ACC commands + input logic cmd_en_i, // CMD register enable for ACC commands input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, input lc_ctrl_pkg::lc_tx_t lc_rma_req_i, @@ -52,23 +52,23 @@ module otbn_core_model output bit [7:0] status_o, // STATUS register output bit [31:0] insn_cnt_o, // INSN_CNT register - input keymgr_pkg::otbn_key_req_t keymgr_key_i, + input keymgr_pkg::acc_key_req_t keymgr_key_i, output bit done_rr_o, output bit err_o // something went wrong ); -`include "otbn_model_dpi.svh" +`include "acc_model_dpi.svh" // Create and destroy an object through which we can talk to the ISS. chandle model_handle; initial begin - model_handle = otbn_model_init(MemScope, DesignScope); + model_handle = acc_model_init(MemScope, DesignScope); assert(model_handle != null); end final begin - otbn_model_destroy(model_handle); + acc_model_destroy(model_handle); end // A packed set of bits representing the state of the model. This gets assigned by DPI function @@ -134,12 +134,12 @@ module otbn_core_model assign new_escalation = escalate_fifo[1] & ~escalate_fifo[2]; assign rma_req_changed = rma_req_fifo[1] != rma_req_fifo[2]; - // Currently, the OTBN core model doesn't ever set the lock_immediately_d/q signals. However, - // the OTBN model agent provides a function (see lock_immediately() in otbn_model_if.sv) to + // Currently, the ACC core model doesn't ever set the lock_immediately_d/q signals. However, + // the ACC model agent provides a function (see lock_immediately() in acc_model_if.sv) to // tell the model to lock immediately. This is used by sequences testing FI countermeasures. assign lock_immediately_d = lock_immediately_q; - // RND Request starts if OTBN Model raises rnd_req_start while we are not + // RND Request starts if ACC Model raises rnd_req_start while we are not // finishing up processing RND. assign edn_rnd_req_d = ~edn_rnd_cdc_done_q & (edn_rnd_req_q | rnd_req_start_q); @@ -162,19 +162,19 @@ module otbn_core_model bit is_idle; assign start_d = (cmd == CmdExecute) & is_idle; - assign is_idle = otbn_pkg::status_e'(status_o) == StatusIdle; + assign is_idle = acc_pkg::status_e'(status_o) == StatusIdle; // URND Reseeding is done twice as part of every secure wipe: once before the secure wipe and once - // after a first wipe with random data. A secure wipe happens after reset and when OTBN receives + // after a first wipe with random data. A secure wipe happens after reset and when ACC receives // the `EXECUTE` command. typedef enum logic [2:0] { - OtbnCoreModelUrndStateReset, - OtbnCoreModelUrndStateAwaitInitialAck, - OtbnCoreModelUrndStateAwaitWipe, - OtbnCoreModelUrndStateAwaitSecondAck, - OtbnCoreModelUrndStateAwaitStart, - OtbnCoreModelUrndStateAwaitPostStartAck, - OtbnCoreModelUrndStateAwaitPostExecSecWipe + AccCoreModelUrndStateReset, + AccCoreModelUrndStateAwaitInitialAck, + AccCoreModelUrndStateAwaitWipe, + AccCoreModelUrndStateAwaitSecondAck, + AccCoreModelUrndStateAwaitStart, + AccCoreModelUrndStateAwaitPostStartAck, + AccCoreModelUrndStateAwaitPostExecSecWipe } urnd_state_e; urnd_state_e urnd_state_q, urnd_state_d; @@ -188,67 +188,67 @@ module otbn_core_model wipe_cyc_cnt_d = wipe_cyc_cnt_q; unique case (urnd_state_q) - OtbnCoreModelUrndStateReset: begin - urnd_state_d = OtbnCoreModelUrndStateAwaitInitialAck; + AccCoreModelUrndStateReset: begin + urnd_state_d = AccCoreModelUrndStateAwaitInitialAck; end - OtbnCoreModelUrndStateAwaitInitialAck: begin + AccCoreModelUrndStateAwaitInitialAck: begin edn_urnd_o = 1'b1; if (edn_urnd_cdc_done_i) begin wipe_cyc_cnt_d = wipe_cyc_cnt_t'(WIPE_CYCLES); - urnd_state_d = OtbnCoreModelUrndStateAwaitWipe; + urnd_state_d = AccCoreModelUrndStateAwaitWipe; end end - OtbnCoreModelUrndStateAwaitWipe: begin + AccCoreModelUrndStateAwaitWipe: begin wipe_cyc_cnt_d = wipe_cyc_cnt_q - 1; if (wipe_cyc_cnt_q == '0) begin edn_urnd_o = 1'b1; - urnd_state_d = OtbnCoreModelUrndStateAwaitSecondAck; + urnd_state_d = AccCoreModelUrndStateAwaitSecondAck; end end - OtbnCoreModelUrndStateAwaitSecondAck: begin + AccCoreModelUrndStateAwaitSecondAck: begin edn_urnd_o = 1'b1; if (edn_urnd_cdc_done_i) begin - urnd_state_d = OtbnCoreModelUrndStateAwaitStart; + urnd_state_d = AccCoreModelUrndStateAwaitStart; end end - OtbnCoreModelUrndStateAwaitStart: begin + AccCoreModelUrndStateAwaitStart: begin if (start_q) begin - urnd_state_d = OtbnCoreModelUrndStateAwaitPostStartAck; + urnd_state_d = AccCoreModelUrndStateAwaitPostStartAck; end end - OtbnCoreModelUrndStateAwaitPostStartAck: begin + AccCoreModelUrndStateAwaitPostStartAck: begin edn_urnd_o = 1'b1; if (edn_urnd_cdc_done_i) begin - urnd_state_d = OtbnCoreModelUrndStateAwaitPostExecSecWipe; + urnd_state_d = AccCoreModelUrndStateAwaitPostExecSecWipe; end end - OtbnCoreModelUrndStateAwaitPostExecSecWipe: begin + AccCoreModelUrndStateAwaitPostExecSecWipe: begin if (status_q == StatusBusySecWipeInt) begin // This wipe is three clock cycles shorter, because it does starts directly after // execution and not directly after an URND reseed. wipe_cyc_cnt_d = wipe_cyc_cnt_t'(WIPE_CYCLES) - 3; - urnd_state_d = OtbnCoreModelUrndStateAwaitWipe; + urnd_state_d = AccCoreModelUrndStateAwaitWipe; end end - default: urnd_state_d = OtbnCoreModelUrndStateReset; + default: urnd_state_d = AccCoreModelUrndStateReset; endcase if (lock_immediately_q) begin - urnd_state_d = OtbnCoreModelUrndStateReset; + urnd_state_d = AccCoreModelUrndStateReset; end end always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin start_q <= 1'b0; - urnd_state_q <= OtbnCoreModelUrndStateReset; + urnd_state_q <= AccCoreModelUrndStateReset; wipe_cyc_cnt_q <= '0; end else begin start_q <= start_d; @@ -263,14 +263,14 @@ module otbn_core_model if (!rst_edn_ni) begin failed_rnd_step <= 0; failed_urnd_step <= 0; - failed_edn_flush <= (otbn_model_edn_flush(model_handle) != 0); + failed_edn_flush <= (acc_model_edn_flush(model_handle) != 0); end else begin if (edn_rnd_i.edn_ack) begin - failed_rnd_step <= (otbn_model_edn_rnd_step(model_handle, edn_rnd_i.edn_bus, + failed_rnd_step <= (acc_model_edn_rnd_step(model_handle, edn_rnd_i.edn_bus, ~edn_rnd_i.edn_fips) != 0); end if (edn_urnd_i.edn_ack) begin - failed_urnd_step <= (otbn_model_edn_urnd_step(model_handle, edn_urnd_i.edn_bus) != 0); + failed_urnd_step <= (acc_model_edn_urnd_step(model_handle, edn_urnd_i.edn_bus) != 0); end end end @@ -320,7 +320,7 @@ module otbn_core_model bit failed_initial_secure_wipe, initial_secure_wipe_started; always @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - failed_reset <= (otbn_model_reset(model_handle, + failed_reset <= (acc_model_reset(model_handle, status_q, insn_cnt_q, rnd_req_start_q, @@ -337,36 +337,36 @@ module otbn_core_model model_state <= 0; end else begin if (!initial_secure_wipe_started) begin - failed_initial_secure_wipe <= (otbn_model_initial_secure_wipe(model_handle) != 0); + failed_initial_secure_wipe <= (acc_model_initial_secure_wipe(model_handle) != 0); initial_secure_wipe_started <= 1; end if (new_escalation) begin // Setting LIFECYCLE_ESCALATION bit - failed_lc_escalate <= (otbn_model_send_err_escalation(model_handle, + failed_lc_escalate <= (acc_model_send_err_escalation(model_handle, 32'd1 << 22, 1'b0) != 0); end if (rma_req_changed) begin - failed_lc_rma_req <= (otbn_model_set_rma_req(model_handle, rma_req_fifo[1]) != 0); + failed_lc_rma_req <= (acc_model_set_rma_req(model_handle, rma_req_fifo[1]) != 0); end if (!$stable(keymgr_key_i) || $rose(rst_ni)) begin - failed_keymgr_value <= (otbn_model_set_keymgr_value(model_handle, + failed_keymgr_value <= (acc_model_set_keymgr_value(model_handle, keymgr_key_i.key[0], keymgr_key_i.key[1], keymgr_key_i.valid) != 0); end if (edn_urnd_cdc_done_i) begin - failed_urnd_cdc <= (otbn_model_urnd_cdc_done(model_handle) != 0); + failed_urnd_cdc <= (acc_model_urnd_cdc_done(model_handle) != 0); end if (edn_rnd_cdc_done_i) begin - failed_rnd_cdc <= (otbn_model_rnd_cdc_done(model_handle) != 0); + failed_rnd_cdc <= (acc_model_rnd_cdc_done(model_handle) != 0); end if (otp_key_cdc_done_i) begin - failed_otp_key_cdc <= (otbn_model_otp_key_cdc_done(model_handle) != 0); + failed_otp_key_cdc <= (acc_model_otp_key_cdc_done(model_handle) != 0); end if (step_iss) begin - model_state <= otbn_model_step(model_handle, + model_state <= acc_model_step(model_handle, model_state, cmd, status_q, @@ -388,7 +388,7 @@ module otbn_core_model check_mismatch_q <= 0; end else begin if (check_due) begin - failed_check <= (otbn_model_check(model_handle, check_mismatch_d) == 0); + failed_check <= (acc_model_check(model_handle, check_mismatch_d) == 0); check_mismatch_q <= check_mismatch_d; end end @@ -408,8 +408,8 @@ module otbn_core_model // TODO: This bind is by module, rather than by instance, because I couldn't get the by-instance // syntax plus upwards name referencing to work with Verilator. Obviously, this won't work with - // multiple OTBN instances, so it would be nice to get it right. - bind otbn_rf_base_ff otbn_rf_snooper_if #( + // multiple ACC instances, so it would be nice to get it right. + bind acc_rf_base_ff acc_rf_snooper_if #( .Width (BaseIntgWidth), .Depth (NGpr), .IntegrityEnabled(1) @@ -417,7 +417,7 @@ module otbn_core_model .rf (rf_reg) ); - bind otbn_rf_bignum_ff otbn_rf_snooper_if #( + bind acc_rf_bignum_ff acc_rf_snooper_if #( .Width (ExtWLEN), .Depth (NWdr), .IntegrityEnabled(1) @@ -425,7 +425,7 @@ module otbn_core_model .rf (rf) ); - bind otbn_rf_base otbn_stack_snooper_if #(.StackIntgWidth(39), .StackWidth(32), .StackDepth(8)) + bind acc_rf_base acc_stack_snooper_if #(.StackIntgWidth(39), .StackWidth(32), .StackDepth(8)) u_call_stack_snooper ( .stack_storage(u_call_stack.stack_storage), .stack_wr_ptr_q(u_call_stack.stack_wr_ptr) @@ -437,24 +437,24 @@ module otbn_core_model failed_urnd_cdc, failed_rnd_cdc, failed_otp_key_cdc, failed_initial_secure_wipe, failed_lc_rma_req}; - // Derive a "done" signal. This should trigger for a single cycle when OTBN finishes its work. - // It's analogous to the done_o signal on otbn_core, but this signal is delayed by a single cycle + // Derive a "done" signal. This should trigger for a single cycle when ACC finishes its work. + // It's analogous to the done_o signal on acc_core, but this signal is delayed by a single cycle // (hence its name is done_r_o). - bit otbn_model_busy, otbn_model_busy_r; - assign otbn_model_busy = !(status_q inside {StatusIdle, StatusLocked}) & init_sec_wipe_done_i; + bit acc_model_busy, acc_model_busy_r; + assign acc_model_busy = !(status_q inside {StatusIdle, StatusLocked}) & init_sec_wipe_done_i; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - otbn_model_busy_r <= 1'b0; + acc_model_busy_r <= 1'b0; end else begin - otbn_model_busy_r <= otbn_model_busy; + acc_model_busy_r <= acc_model_busy; end end - assign done_rr_o = otbn_model_busy_r & ~otbn_model_busy; + assign done_rr_o = acc_model_busy_r & ~acc_model_busy; // Make stop_pc available over DPI. This is handy for Verilator simulations (where the top-level // is in C++). - export "DPI-C" function otbn_core_get_stop_pc; - function automatic int otbn_core_get_stop_pc(); + export "DPI-C" function acc_core_get_stop_pc; + function automatic int acc_core_get_stop_pc(); return stop_pc_q; endfunction diff --git a/hw/ip/otbn/dv/model/otbn_model.cc b/hw/ip/acc/dv/model/acc_model.cc similarity index 79% rename from hw/ip/otbn/dv/model/otbn_model.cc rename to hw/ip/acc/dv/model/acc_model.cc index 44cb1092b31..84a10f2fd03 100644 --- a/hw/ip/otbn/dv/model/otbn_model.cc +++ b/hw/ip/acc/dv/model/acc_model.cc @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "otbn_model.h" +#include "acc_model.h" #include #include @@ -12,27 +12,27 @@ #include #include +#include "acc_model_dpi.h" +#include "acc_trace_checker.h" #include "iss_wrapper.h" -#include "otbn_model_dpi.h" -#include "otbn_trace_checker.h" #include "sv_scoped.h" #include "sv_utils.h" extern "C" { -int otbn_rf_peek(int index, svBitVecVal *val); -int otbn_stack_element_peek(int index, svBitVecVal *val); +int acc_rf_peek(int index, svBitVecVal *val); +int acc_stack_element_peek(int index, svBitVecVal *val); } #define RUNNING_BIT (1U << 0) #define CHECK_DUE_BIT (1U << 1) #define FAILED_STEP_BIT (1U << 2) -// Values come from otbn_pkg to signify the value for specific operations. +// Values come from acc_pkg to signify the value for specific operations. #define CMD_EXECUTE 0xD8 #define CMD_SECWIPE_DMEM 0xC3 #define CMD_SECWIPE_IMEM 0x1E -// Values of the `STATUS` register, as defined in `otbn.hjson`. +// Values of the `STATUS` register, as defined in `acc.hjson`. #define STATUS_IDLE 0x00 #define STATUS_BUSY_EXECUTE 0x01 #define STATUS_BUSY_SEC_WIPE_DMEM 0x02 @@ -126,13 +126,13 @@ static std::array get_rtl_regs(const std::string ®_scope) { SVScoped scoped(reg_scope); - // otbn_rf_peek passes data as a packed array of svBitVecVal words (for a + // acc_rf_peek passes data as a packed array of svBitVecVal words (for a // "bit [255:0]" argument). Allocate 256 bits (= 32 bytes) as // 32/sizeof(svBitVecVal) words on the stack. svBitVecVal buf[256 / 8 / sizeof(svBitVecVal)]; for (int i = 0; i < 32; ++i) { - if (!otbn_rf_peek(i, buf)) { + if (!acc_rf_peek(i, buf)) { std::ostringstream oss; oss << "Failed to peek into RTL to get value of register " << i << " at scope `" << reg_scope << "'."; @@ -151,7 +151,7 @@ static std::vector get_stack(const std::string &stack_scope) { SVScoped scoped(stack_scope); - // otbn_stack_element_peek passes data as a packed array of svBitVecVal words + // acc_stack_element_peek passes data as a packed array of svBitVecVal words // (for a "bit [255:0]" argument). Allocate 256 bits (= 32 bytes) as // 32/sizeof(svBitVecVal) words on the stack. svBitVecVal buf[256 / 8 / sizeof(svBitVecVal)]; @@ -159,9 +159,9 @@ static std::vector get_stack(const std::string &stack_scope) { int i = 0; while (1) { - int peek_result = otbn_stack_element_peek(i, buf); + int peek_result = acc_stack_element_peek(i, buf); - // otbn_stack_element_peek is defined in otbn_stack_snooper_if.sv. Possible + // acc_stack_element_peek is defined in acc_stack_snooper_if.sv. Possible // return values are: 0 on success, if we've returned an element. 1 if the // stack doesn't have an element at index i. 2 if something terrible has // gone wrong (such as a completely bogus index). @@ -189,15 +189,15 @@ static std::vector get_stack(const std::string &stack_scope) { return ret; } -OtbnModel::OtbnModel(const std::string &mem_scope, - const std::string &design_scope) +AccModel::AccModel(const std::string &mem_scope, + const std::string &design_scope) : mem_util_(mem_scope), design_scope_(design_scope) { assert(mem_scope.size() && design_scope.size()); } -OtbnModel::~OtbnModel() {} +AccModel::~AccModel() {} -int OtbnModel::take_loop_warps(const OtbnMemUtil &memutil) { +int AccModel::take_loop_warps(const AccMemUtil &memutil) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -226,7 +226,7 @@ int OtbnModel::take_loop_warps(const OtbnMemUtil &memutil) { return 0; } -int OtbnModel::start_operation(command_t command) { +int AccModel::start_operation(command_t command) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -273,7 +273,7 @@ int OtbnModel::start_operation(command_t command) { return 0; } -int OtbnModel::edn_flush() { +int AccModel::edn_flush() { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -288,8 +288,8 @@ int OtbnModel::edn_flush() { return 0; } -int OtbnModel::edn_rnd_step(svLogicVecVal *edn_rnd_data /* logic [31:0] */, - unsigned char fips_err) { +int AccModel::edn_rnd_step(svLogicVecVal *edn_rnd_data /* logic [31:0] */, + unsigned char fips_err) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -305,7 +305,7 @@ int OtbnModel::edn_rnd_step(svLogicVecVal *edn_rnd_data /* logic [31:0] */, return 0; } -int OtbnModel::edn_urnd_step(svLogicVecVal *edn_urnd_data /* logic [31:0] */) { +int AccModel::edn_urnd_step(svLogicVecVal *edn_urnd_data /* logic [31:0] */) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -320,7 +320,7 @@ int OtbnModel::edn_urnd_step(svLogicVecVal *edn_urnd_data /* logic [31:0] */) { return 0; } -int OtbnModel::edn_rnd_cdc_done() { +int AccModel::edn_rnd_cdc_done() { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -336,7 +336,7 @@ int OtbnModel::edn_rnd_cdc_done() { return 0; } -int OtbnModel::edn_urnd_cdc_done() { +int AccModel::edn_urnd_cdc_done() { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -352,7 +352,7 @@ int OtbnModel::edn_urnd_cdc_done() { return 0; } -int OtbnModel::otp_key_cdc_done() { +int AccModel::otp_key_cdc_done() { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -368,9 +368,9 @@ int OtbnModel::otp_key_cdc_done() { return 0; } -int OtbnModel::set_keymgr_value(svLogicVecVal *key0 /* logic [383:0] */, - svLogicVecVal *key1 /* logic [383:0] */, - unsigned char valid) { +int AccModel::set_keymgr_value(svLogicVecVal *key0 /* logic [383:0] */, + svLogicVecVal *key1 /* logic [383:0] */, + unsigned char valid) { ISSWrapper *iss = ensure_wrapper(); std::array key0_arr; @@ -391,11 +391,11 @@ int OtbnModel::set_keymgr_value(svLogicVecVal *key0 /* logic [383:0] */, return 0; } -int OtbnModel::step(svBitVecVal *status /* bit [7:0] */, - svBitVecVal *insn_cnt /* bit [31:0] */, - svBitVecVal *rnd_req /* bit [0:0] */, - svBitVecVal *err_bits /* bit [31:0] */, - svBitVecVal *stop_pc /* bit [31:0] */) { +int AccModel::step(svBitVecVal *status /* bit [7:0] */, + svBitVecVal *insn_cnt /* bit [31:0] */, + svBitVecVal *rnd_req /* bit [0:0] */, + svBitVecVal *err_bits /* bit [31:0] */, + svBitVecVal *stop_pc /* bit [31:0] */) { assert(insn_cnt && err_bits && stop_pc); ISSWrapper *iss = ensure_wrapper(); @@ -448,19 +448,19 @@ int OtbnModel::step(svBitVecVal *status /* bit [7:0] */, return finished ? 1 : 0; } -int OtbnModel::check() const { +int AccModel::check() const { if (!has_rtl()) return 1; ISSWrapper *iss = iss_.get(); if (!iss) { - std::cerr << "Cannot check OTBN model: ISS has not started.\n"; + std::cerr << "Cannot check ACC model: ISS has not started.\n"; return -1; } bool good = true; - good &= OtbnTraceChecker::get().Finish(); + good &= AccTraceChecker::get().Finish(); // Check DMEM only when we are about to start Secure Wipe because otherwise // we would not have a valid scrambling key anymore. That would result with @@ -493,10 +493,10 @@ int OtbnModel::check() const { return good ? 1 : 0; } -int OtbnModel::load_dmem() { +int AccModel::load_dmem() { ISSWrapper *iss = iss_.get(); if (!iss) { - std::cerr << "Cannot load dmem from OTBN model: ISS has not started.\n"; + std::cerr << "Cannot load dmem from ACC model: ISS has not started.\n"; return -1; } @@ -515,7 +515,7 @@ int OtbnModel::load_dmem() { return 0; } -int OtbnModel::invalidate_imem() { +int AccModel::invalidate_imem() { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -530,7 +530,7 @@ int OtbnModel::invalidate_imem() { return 0; } -int OtbnModel::invalidate_dmem() { +int AccModel::invalidate_dmem() { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -545,7 +545,7 @@ int OtbnModel::invalidate_dmem() { return 0; } -int OtbnModel::set_software_errs_fatal(unsigned char new_val) { +int AccModel::set_software_errs_fatal(unsigned char new_val) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -561,18 +561,18 @@ int OtbnModel::set_software_errs_fatal(unsigned char new_val) { return 0; } -int OtbnModel::set_no_sec_wipe_chk() { - OtbnTraceChecker::get().set_no_sec_wipe_chk(); +int AccModel::set_no_sec_wipe_chk() { + AccTraceChecker::get().set_no_sec_wipe_chk(); return 0; } -int OtbnModel::disable_stack_check() { +int AccModel::disable_stack_check() { stack_check_enabled_ = false; return 0; } -int OtbnModel::step_crc(const svBitVecVal *item /* bit [47:0] */, - svBitVecVal *state /* bit [31:0] */) { +int AccModel::step_crc(const svBitVecVal *item /* bit [47:0] */, + svBitVecVal *state /* bit [31:0] */) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -596,11 +596,11 @@ int OtbnModel::step_crc(const svBitVecVal *item /* bit [47:0] */, return 0; } -int OtbnModel::reset(svBitVecVal *status /* bit [7:0] */, - svBitVecVal *insn_cnt /* bit [31:0] */, - svBitVecVal *rnd_req /* bit [0:0] */, - svBitVecVal *err_bits /* bit [31:0] */, - svBitVecVal *stop_pc /* bit [31:0] */) { +int AccModel::reset(svBitVecVal *status /* bit [7:0] */, + svBitVecVal *insn_cnt /* bit [31:0] */, + svBitVecVal *rnd_req /* bit [0:0] */, + svBitVecVal *err_bits /* bit [31:0] */, + svBitVecVal *stop_pc /* bit [31:0] */) { ISSWrapper *iss = iss_.get(); if (!iss) return 0; @@ -621,8 +621,8 @@ int OtbnModel::reset(svBitVecVal *status /* bit [7:0] */, return 0; } -int OtbnModel::send_err_escalation(svBitVecVal *err_val /* bit [31:0] */, - svBit lock_immediately) { +int AccModel::send_err_escalation(svBitVecVal *err_val /* bit [31:0] */, + svBit lock_immediately) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -638,7 +638,7 @@ int OtbnModel::send_err_escalation(svBitVecVal *err_val /* bit [31:0] */, return 0; } -int OtbnModel::set_rma_req(svBitVecVal *rma_req /* bit [3:0] */) { +int AccModel::set_rma_req(svBitVecVal *rma_req /* bit [3:0] */) { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -653,12 +653,12 @@ int OtbnModel::set_rma_req(svBitVecVal *rma_req /* bit [3:0] */) { return 0; } -bool OtbnModel::is_at_start_of_wipe() const { +bool AccModel::is_at_start_of_wipe() const { ISSWrapper *iss = iss_.get(); return iss && iss->get_mirrored().wipe_start; } -ISSWrapper *OtbnModel::ensure_wrapper() { +ISSWrapper *AccModel::ensure_wrapper() { if (!iss_) { try { iss_.reset(new ISSWrapper()); @@ -672,17 +672,17 @@ ISSWrapper *OtbnModel::ensure_wrapper() { return iss_.get(); } -Ecc32MemArea::EccWords OtbnModel::get_sim_memory(bool is_imem) const { +Ecc32MemArea::EccWords AccModel::get_sim_memory(bool is_imem) const { auto &mem_area = mem_util_.GetMemArea(is_imem); return mem_area.ReadWithIntegrity(0, mem_area.GetSizeWords()); } -void OtbnModel::set_sim_memory(bool is_imem, - const Ecc32MemArea::EccWords &words) { +void AccModel::set_sim_memory(bool is_imem, + const Ecc32MemArea::EccWords &words) { mem_util_.GetMemArea(is_imem).WriteWithIntegrity(0, words); } -bool OtbnModel::check_dmem(ISSWrapper &iss) const { +bool AccModel::check_dmem(ISSWrapper &iss) const { const MemArea &dmem = mem_util_.GetMemArea(false); uint32_t dmem_bytes = dmem.GetSizeBytes(); @@ -748,13 +748,13 @@ bool OtbnModel::check_dmem(ISSWrapper &iss) const { return bad_count == 0; } -bool OtbnModel::check_regs(ISSWrapper &iss) const { +bool AccModel::check_regs(ISSWrapper &iss) const { std::string base_scope = design_scope_ + - ".u_otbn_rf_base.gen_rf_base_ff.u_otbn_rf_base_inner.u_snooper"; + ".u_acc_rf_base.gen_rf_base_ff.u_acc_rf_base_inner.u_snooper"; std::string wide_scope = design_scope_ + - ".u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.u_snooper"; + ".u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.u_snooper"; auto rtl_gprs = get_rtl_regs(base_scope); auto rtl_wdrs = get_rtl_regs(wide_scope); @@ -807,9 +807,9 @@ bool OtbnModel::check_regs(ISSWrapper &iss) const { return good; } -bool OtbnModel::check_call_stack(ISSWrapper &iss) const { +bool AccModel::check_call_stack(ISSWrapper &iss) const { std::string call_stack_snooper_scope = - design_scope_ + ".u_otbn_rf_base.u_call_stack_snooper"; + design_scope_ + ".u_acc_rf_base.u_call_stack_snooper"; auto rtl_call_stack = get_stack(call_stack_snooper_scope); @@ -843,7 +843,7 @@ bool OtbnModel::check_call_stack(ISSWrapper &iss) const { return good; } -int OtbnModel::initial_secure_wipe() { +int AccModel::initial_secure_wipe() { ISSWrapper *iss = ensure_wrapper(); if (!iss) return -1; @@ -853,69 +853,69 @@ int OtbnModel::initial_secure_wipe() { return 0; } -OtbnModel *otbn_model_init(const char *mem_scope, const char *design_scope) { +AccModel *acc_model_init(const char *mem_scope, const char *design_scope) { assert(mem_scope && design_scope); - return new OtbnModel(mem_scope, design_scope); + return new AccModel(mem_scope, design_scope); } -void otbn_model_destroy(OtbnModel *model) { delete model; } +void acc_model_destroy(AccModel *model) { delete model; } -void otbn_take_loop_warps(OtbnModel *model, OtbnMemUtil *memutil) { +void acc_take_loop_warps(AccModel *model, AccMemUtil *memutil) { assert(model && memutil); model->take_loop_warps(*memutil); } -int otbn_has_loop_warps(OtbnMemUtil *memutil) { +int acc_has_loop_warps(AccMemUtil *memutil) { assert(memutil); return memutil->GetLoopWarps().size() != 0; } -int otbn_model_edn_flush(OtbnModel *model) { +int acc_model_edn_flush(AccModel *model) { assert(model); return model->edn_flush(); } -int otbn_model_edn_rnd_step(OtbnModel *model, - svLogicVecVal *edn_rnd_data /* logic [31:0] */, - unsigned char fips_err) { +int acc_model_edn_rnd_step(AccModel *model, + svLogicVecVal *edn_rnd_data /* logic [31:0] */, + unsigned char fips_err) { assert(model && edn_rnd_data); return model->edn_rnd_step(edn_rnd_data, fips_err); } -int otbn_model_edn_urnd_step(OtbnModel *model, - svLogicVecVal *edn_urnd_data /* logic [31:0] */) { +int acc_model_edn_urnd_step(AccModel *model, + svLogicVecVal *edn_urnd_data /* logic [31:0] */) { assert(model && edn_urnd_data); return model->edn_urnd_step(edn_urnd_data); } -int otbn_model_rnd_cdc_done(OtbnModel *model) { +int acc_model_rnd_cdc_done(AccModel *model) { assert(model); return model->edn_rnd_cdc_done(); } -int otbn_model_urnd_cdc_done(OtbnModel *model) { +int acc_model_urnd_cdc_done(AccModel *model) { assert(model); return model->edn_urnd_cdc_done(); } -int otbn_model_otp_key_cdc_done(OtbnModel *model) { +int acc_model_otp_key_cdc_done(AccModel *model) { assert(model); return model->otp_key_cdc_done(); } -int otbn_model_set_keymgr_value(OtbnModel *model, svLogicVecVal *key0, - svLogicVecVal *key1, unsigned char valid) { +int acc_model_set_keymgr_value(AccModel *model, svLogicVecVal *key0, + svLogicVecVal *key1, unsigned char valid) { assert(model && key0 && key1); return model->set_keymgr_value(key0, key1, valid); } -unsigned otbn_model_step(OtbnModel *model, unsigned model_state, - svBitVecVal *cmd /* bit [7:0] */, - svBitVecVal *status /* bit [7:0] */, - svBitVecVal *insn_cnt /* bit [31:0] */, - svBitVecVal *rnd_req /* bit [0:0] */, - svBitVecVal *err_bits /* bit [31:0] */, - svBitVecVal *stop_pc /* bit [31:0] */) { +unsigned acc_model_step(AccModel *model, unsigned model_state, + svBitVecVal *cmd /* bit [7:0] */, + svBitVecVal *status /* bit [7:0] */, + svBitVecVal *insn_cnt /* bit [31:0] */, + svBitVecVal *rnd_req /* bit [0:0] */, + svBitVecVal *err_bits /* bit [31:0] */, + svBitVecVal *stop_pc /* bit [31:0] */) { assert(model && status && insn_cnt && err_bits && stop_pc); // Clear any check due bit (we hopefully ran the check on the previous @@ -926,18 +926,18 @@ unsigned otbn_model_step(OtbnModel *model, unsigned model_state, unsigned new_state_bits = 0; if (*status == STATUS_IDLE) { - // OTBN only executes commands if STATUS is IDLE. + // ACC only executes commands if STATUS is IDLE. switch (*cmd) { case CMD_EXECUTE: - result = model->start_operation(OtbnModel::Execute); + result = model->start_operation(AccModel::Execute); new_state_bits = RUNNING_BIT; break; case CMD_SECWIPE_DMEM: - result = model->start_operation(OtbnModel::DmemWipe); + result = model->start_operation(AccModel::DmemWipe); new_state_bits = RUNNING_BIT; break; case CMD_SECWIPE_IMEM: - result = model->start_operation(OtbnModel::ImemWipe); + result = model->start_operation(AccModel::ImemWipe); new_state_bits = RUNNING_BIT; break; } @@ -981,7 +981,7 @@ unsigned otbn_model_step(OtbnModel *model, unsigned model_state, return model_state; } -int otbn_model_check(OtbnModel *model, svBitVecVal *mismatch /* bit [0:0] */) { +int acc_model_check(AccModel *model, svBitVecVal *mismatch /* bit [0:0] */) { assert(model && mismatch); // Run model checks if needed. This usually happens just after an operation @@ -1013,61 +1013,60 @@ int otbn_model_check(OtbnModel *model, svBitVecVal *mismatch /* bit [0:0] */) { return 1; } -int otbn_model_invalidate_imem(OtbnModel *model) { +int acc_model_invalidate_imem(AccModel *model) { assert(model); return model->invalidate_imem(); } -int otbn_model_invalidate_dmem(OtbnModel *model) { +int acc_model_invalidate_dmem(AccModel *model) { assert(model); return model->invalidate_dmem(); } -int otbn_model_set_software_errs_fatal(OtbnModel *model, - unsigned char new_val) { +int acc_model_set_software_errs_fatal(AccModel *model, unsigned char new_val) { assert(model); return model->set_software_errs_fatal(new_val); } -int otbn_set_no_sec_wipe_chk(OtbnModel *model) { +int acc_set_no_sec_wipe_chk(AccModel *model) { assert(model); return model->set_no_sec_wipe_chk(); } -int otbn_disable_stack_check(OtbnModel *model) { +int acc_disable_stack_check(AccModel *model) { assert(model); return model->disable_stack_check(); } -int otbn_model_step_crc(OtbnModel *model, svBitVecVal *item /* bit [47:0] */, - svBitVecVal *state /* inout bit [31:0] */) { +int acc_model_step_crc(AccModel *model, svBitVecVal *item /* bit [47:0] */, + svBitVecVal *state /* inout bit [31:0] */) { assert(model && item && state); return model->step_crc(item, state); } -int otbn_model_reset(OtbnModel *model, svBitVecVal *status /* bit [7:0] */, - svBitVecVal *insn_cnt /* bit [31:0] */, - svBitVecVal *rnd_req /* bit [0:0] */, - svBitVecVal *err_bits /* bit [31:0] */, - svBitVecVal *stop_pc /* bit [31:0] */) { +int acc_model_reset(AccModel *model, svBitVecVal *status /* bit [7:0] */, + svBitVecVal *insn_cnt /* bit [31:0] */, + svBitVecVal *rnd_req /* bit [0:0] */, + svBitVecVal *err_bits /* bit [31:0] */, + svBitVecVal *stop_pc /* bit [31:0] */) { assert(model); return model->reset(status, insn_cnt, rnd_req, err_bits, stop_pc); } -int otbn_model_send_err_escalation(OtbnModel *model, - svBitVecVal *err_val /* bit [31:0] */, - svBit lock_immediately) { +int acc_model_send_err_escalation(AccModel *model, + svBitVecVal *err_val /* bit [31:0] */, + svBit lock_immediately) { assert(model); return model->send_err_escalation(err_val, lock_immediately); } -int otbn_model_set_rma_req(OtbnModel *model, - svBitVecVal *rma_req /* bit [3:0] */) { +int acc_model_set_rma_req(AccModel *model, + svBitVecVal *rma_req /* bit [3:0] */) { assert(model); return model->set_rma_req(rma_req); } -int otbn_model_initial_secure_wipe(OtbnModel *model) { +int acc_model_initial_secure_wipe(AccModel *model) { assert(model); return model->initial_secure_wipe(); } diff --git a/hw/ip/acc/dv/model/acc_model.core b/hw/ip/acc/dv/model/acc_model.core new file mode 100644 index 00000000000..d37307de7e9 --- /dev/null +++ b/hw/ip/acc/dv/model/acc_model.core @@ -0,0 +1,35 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:acc_model:0.1" +description: "OpenTitan Big Number Accelerator (ACC)" + +filesets: + files_model: + depend: + - lowrisc:ip:acc_pkg + - lowrisc:dv_verilator:memutil_dpi + - lowrisc:dv:acc_memutil + - lowrisc:ip:acc_tracer + files: + - acc_model.cc: { file_type: cppSource } + - acc_model.h: { file_type: cppSource, is_include_file: true } + - acc_model_dpi.h: { file_type: cppSource, is_include_file: true } + - acc_model_dpi.svh: { is_include_file: true } + - iss_wrapper.cc: { file_type: cppSource } + - iss_wrapper.h: { file_type: cppSource, is_include_file: true } + - acc_trace_checker.h: { file_type: cppSource, is_include_file: true } + - acc_trace_checker.cc: { file_type: cppSource } + - acc_trace_entry.h: { file_type: cppSource, is_include_file: true } + - acc_trace_entry.cc: { file_type: cppSource } + - acc_core_model.sv + - acc_rf_snooper_if.sv + - acc_stack_snooper_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_model + toplevel: acc_core_model diff --git a/hw/ip/otbn/dv/model/otbn_model.h b/hw/ip/acc/dv/model/acc_model.h similarity index 92% rename from hw/ip/otbn/dv/model/otbn_model.h rename to hw/ip/acc/dv/model/acc_model.h index f89326ec2ec..a8ad4a73f62 100644 --- a/hw/ip/otbn/dv/model/otbn_model.h +++ b/hw/ip/acc/dv/model/acc_model.h @@ -1,8 +1,8 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_MODEL_H_ -#define OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_MODEL_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_MODEL_H_ +#define OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_MODEL_H_ #include #include @@ -10,21 +10,21 @@ #include #include -#include "otbn_memutil.h" +#include "acc_memutil.h" struct ISSWrapper; -class OtbnModel { +class AccModel { public: enum command_t { Execute, DmemWipe, ImemWipe }; - OtbnModel(const std::string &mem_scope, const std::string &design_scope); - ~OtbnModel(); + AccModel(const std::string &mem_scope, const std::string &design_scope); + ~AccModel(); // Replace any current loop warps with those from memutil. Returns 0 // on success or -1 on failure. In the latter case, a message will // already have been written to stderr. - int take_loop_warps(const OtbnMemUtil &memutil); + int take_loop_warps(const AccMemUtil &memutil); // True if this model is running in a simulation that has an RTL // implementation too (which needs checking). @@ -65,7 +65,7 @@ class OtbnModel { // Step once in the model. Returns 1 if the model has finished, 0 if not and // -1 on failure. If gen_trace is true, pass trace entries to the trace - // checker. If the model has finished, writes otbn.ERR_BITS to *err_bits. + // checker. If the model has finished, writes acc.ERR_BITS to *err_bits. int step(svBitVecVal *status /* bit [7:0] */, svBitVecVal *insn_cnt /* bit [31:0] */, svBitVecVal *rnd_req /* bit [0:0] */, @@ -100,7 +100,7 @@ class OtbnModel { // Step CRC by consuming 48 bits of data. // // This doesn't actually update any internal state: we're just using the - // otbn_model framework as a convenient connection between SystemVerilog and + // acc_model framework as a convenient connection between SystemVerilog and // Python. Returns 0 on success; -1 on failure. int step_crc(const svBitVecVal *item /* bit [47:0] */, svBitVecVal *state /* bit [31:0] */); @@ -163,10 +163,10 @@ class OtbnModel { // time it's actually needed. Use ensure_wrapper() to create as needed. std::unique_ptr iss_; - OtbnMemUtil mem_util_; + AccMemUtil mem_util_; std::string design_scope_; bool stack_check_enabled_ = true; }; -#endif // OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_MODEL_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_MODEL_H_ diff --git a/hw/ip/acc/dv/model/acc_model_dpi.h b/hw/ip/acc/dv/model/acc_model_dpi.h new file mode 100644 index 00000000000..e1da4f5e7da --- /dev/null +++ b/hw/ip/acc/dv/model/acc_model_dpi.h @@ -0,0 +1,150 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +#ifndef OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_MODEL_DPI_H_ +#define OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_MODEL_DPI_H_ + +// The DPI exports for AccModel. See also acc_model_dpi.svh, where +// they are declared for the SystemVerilog side. +// +// These are defined in a separate file from acc_model.h because otherwise +// something like acc_top_sim.cc will see both these defines and the +// auto-generated ones that Verilator produces in e.g. Vacc_top_sim__Dpi.h. The +// latter use void* for all the chandle arguments and some versions of GCC treat +// the resulting signatures as incompatible. + +extern "C" { + +// Create an AccModel object. Will always succeed. +AccModel *acc_model_init(const char *mem_scope, const char *design_scope); + +// Delete an AccModel +void acc_model_destroy(AccModel *model); + +// Take loop warps from an AccMemUtil +void acc_take_loop_warps(AccModel *model, AccMemUtil *memutil); + +// Returns non-zero if an AccMemUtil contains loop warps +int acc_has_loop_warps(AccMemUtil *memutil); + +// Flush URND and RND EDN data from model because of edn_rst_n signal. Returns +// 0 on success; -1 on error. +int acc_model_edn_flush(AccModel *model); + +// Call edn_rnd_step function of AccModel. Returns 0 on success; -1 on error. +int acc_model_edn_rnd_step(AccModel *model, + svLogicVecVal *edn_rnd_data /* logic [31:0] */, + unsigned char fips_err); + +// Call edn_urnd_step function of AccModel. Returns 0 on success; -1 on error. +int acc_model_edn_urnd_step(AccModel *model, + svLogicVecVal *edn_urnd_data /* logic [31:0] */); + +// Signal RTL is finished processing RND data to Model. Returns 0 on success; +// -1 on error. +int acc_model_rnd_cdc_done(AccModel *model); + +// Signal RTL is finished processing EDN data for URND to Model. Returns 0 on +// success; -1 on error. +int acc_model_urnd_cdc_done(AccModel *model); + +// Signal RTL is finished processing OTP key to the Model. Returns 0 on +// success; -1 on error. +int acc_model_otp_key_cdc_done(AccModel *model); + +// Pass keymgr data to model. Returns 0 on success; -1 on error. +int acc_model_set_keymgr_value(AccModel *model, svLogicVecVal *key0, + svLogicVecVal *key1, unsigned char valid); + +// The main entry point to the ACC model, exported from here and used in +// acc_core_model.sv. +// +// This communicates state with acc_core_model.sv through the model_state +// parameter, which has the following bits: +// +// Bit 0: running True if the model is currently running +// Bit 1: check_due True if the model finished running last cycle +// Bit 2: failed_step Something failed when trying to start/step ISS +// +// The acc_model_step function should only be called when either the model is +// running (bit 0 of model_state), has a check due (bit 1 of model_state), or +// when start is asserted. At other times, it will return immediately (but +// wastes a DPI call). +// +// If the model is running and start is false, acc_model_step steps the ISS by +// a single cycle. If something goes wrong, it will set failed_step to true and +// running to false. Otherwise, it writes the new value of acc.INSN_CNT to +// *insn_cnt. +// +// If nothing goes wrong and the ISS finishes its run, we set running to false, +// write out err_bits and stop_pc and set check_due to ensure acc_model_check +// runs on the next negedge of the clock. +// +unsigned acc_model_step(AccModel *model, unsigned model_state, + svBitVecVal *cmd /* bit [7:0] */, + svBitVecVal *status /* bit [7:0] */, + svBitVecVal *insn_cnt /* bit [31:0] */, + svBitVecVal *rnd_req /* bit [0:0] */, + svBitVecVal *err_bits /* bit [31:0] */, + svBitVecVal *stop_pc /* bit [31:0] */); + +// This gets run if the acc_model_step function sets the check_due bit in its +// model_state bitfield (see above). If the model's design_scope is non-empty, +// it should be the scope of an RTL implementation. In that case, we compare +// register and memory contents with that implementation, printing to stderr +// and setting the failed_cmp bit if there are any mismatches. If the model's +// design_scope is the empty string, we grab the contents of DMEM from the ISS +// and inject them into the simulation memory. +// +// Returns 1 on success; 0 on failure. +int acc_model_check(AccModel *model, svBitVecVal *mismatch /* bit [0:0] */); + +// Tell the model to mark all of IMEM as invalid so that any fetch causes an +// integrity error. Returns 0 on success or -1 on failure. +int acc_model_invalidate_imem(AccModel *model); + +// Tell the model to mark all of DMEM as invalid so that any load causes an +// integrity error. Returns 0 on success or -1 on failure. +int acc_model_invalidate_dmem(AccModel *model); + +// Tell the model to set software_errs_fatal bit in ctrl register. Once this bit +// is set, any software error will be elevated to fatal error from recoverable +// error. +int acc_model_set_software_errs_fatal(AccModel *model, unsigned char new_val); + +// Tell the model to not execute checks to see if secure wiping has written +// random data to all registers before wiping them with zeroes. +int acc_set_no_sec_wipe_chk(AccModel *model); + +// Disable stack integrity checks +int acc_disable_stack_check(AccModel *model); + +// Step the CRC calculation for item +// +// state is an inout parameter and should be updated in-place. This is +// a "pure" function: there isn't actually any model state that gets +// updated by calling it. Returns 0 on success or -1 on failure. +int acc_model_step_crc(AccModel *model, svBitVecVal *item /* bit [47:0] */, + svBitVecVal *state /* inout bit [31:0] */); + +// Flush any information in the model. Returns 0 on success; -1 on error. +int acc_model_reset(AccModel *model, svBitVecVal *status /* bit [7:0] */, + svBitVecVal *insn_cnt /* bit [31:0] */, + svBitVecVal *rnd_req /* bit [0:0] */, + svBitVecVal *err_bits /* bit [31:0] */, + svBitVecVal *stop_pc /* bit [31:0] */); + +// React to an error escalation. Returns 0 on success or -1 on failure. +int acc_model_send_err_escalation(AccModel *model, + svBitVecVal *err_val /* bit [31:0] */, + svBit lock_immediately); + +// Send an RMA request value to the model +int acc_model_set_rma_req(AccModel *model, + svBitVecVal *rma_req /* bit [3:0] */); + +// Trigger initial secure wipe. +int acc_model_initial_secure_wipe(AccModel *model); +} + +#endif // OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_MODEL_DPI_H_ diff --git a/hw/ip/otbn/dv/model/otbn_model_dpi.svh b/hw/ip/acc/dv/model/acc_model_dpi.svh similarity index 51% rename from hw/ip/otbn/dv/model/otbn_model_dpi.svh rename to hw/ip/acc/dv/model/acc_model_dpi.svh index ffe9b67165d..0ef7b8e6ec4 100644 --- a/hw/ip/otbn/dv/model/otbn_model_dpi.svh +++ b/hw/ip/acc/dv/model/acc_model_dpi.svh @@ -2,41 +2,41 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// Imports for the functions defined in otbn_model.h. There are documentation comments explaining -// what the functions do there. This needs to be included into otbn_core_model (because we need +// Imports for the functions defined in acc_model.h. There are documentation comments explaining +// what the functions do there. This needs to be included into acc_core_model (because we need // svGetScope() to point at the model instance). `ifndef SYNTHESIS -import "DPI-C" context function chandle otbn_model_init(string mem_scope, +import "DPI-C" context function chandle acc_model_init(string mem_scope, string design_scope); -import "DPI-C" function void otbn_model_destroy(chandle model); +import "DPI-C" function void acc_model_destroy(chandle model); -import "DPI-C" function void otbn_take_loop_warps(chandle model, chandle memutil); +import "DPI-C" function void acc_take_loop_warps(chandle model, chandle memutil); -import "DPI-C" function int otbn_has_loop_warps(chandle memutil); +import "DPI-C" function int acc_has_loop_warps(chandle memutil); -import "DPI-C" function int otbn_model_edn_flush(chandle model); +import "DPI-C" function int acc_model_edn_flush(chandle model); -import "DPI-C" function int otbn_model_edn_rnd_step(chandle model, +import "DPI-C" function int acc_model_edn_rnd_step(chandle model, logic [31:0] edn_rnd_data, bit fips_err); -import "DPI-C" function int otbn_model_edn_urnd_step(chandle model, +import "DPI-C" function int acc_model_edn_urnd_step(chandle model, logic [31:0] edn_urnd_data); -import "DPI-C" function int otbn_model_rnd_cdc_done(chandle model); +import "DPI-C" function int acc_model_rnd_cdc_done(chandle model); -import "DPI-C" function int otbn_model_urnd_cdc_done(chandle model); +import "DPI-C" function int acc_model_urnd_cdc_done(chandle model); -import "DPI-C" function int otbn_model_otp_key_cdc_done(chandle model); +import "DPI-C" function int acc_model_otp_key_cdc_done(chandle model); import "DPI-C" function - int otbn_model_set_keymgr_value(chandle model, logic [383:0] key0, + int acc_model_set_keymgr_value(chandle model, logic [383:0] key0, logic [383:0] key1, bit valid); import "DPI-C" context function - int unsigned otbn_model_step(chandle model, + int unsigned acc_model_step(chandle model, int unsigned model_state, bit [7:0] cmd, inout bit [7:0] status, @@ -45,36 +45,36 @@ import "DPI-C" context function inout bit [31:0] err_bits, inout bit [31:0] stop_pc); -import "DPI-C" context function int otbn_model_check(chandle model, inout bit mismatch); +import "DPI-C" context function int acc_model_check(chandle model, inout bit mismatch); -import "DPI-C" function int otbn_model_invalidate_imem(chandle model); +import "DPI-C" function int acc_model_invalidate_imem(chandle model); -import "DPI-C" function int otbn_model_invalidate_dmem(chandle model); +import "DPI-C" function int acc_model_invalidate_dmem(chandle model); -import "DPI-C" function int otbn_model_set_software_errs_fatal(chandle model, bit new_val); +import "DPI-C" function int acc_model_set_software_errs_fatal(chandle model, bit new_val); -import "DPI-C" function int otbn_set_no_sec_wipe_chk(chandle model); +import "DPI-C" function int acc_set_no_sec_wipe_chk(chandle model); -import "DPI-C" function int otbn_model_step_crc(chandle model, +import "DPI-C" function int acc_model_step_crc(chandle model, bit [47:0] item, inout bit [31:0] state); -import "DPI-C" context function int otbn_model_reset(chandle model, +import "DPI-C" context function int acc_model_reset(chandle model, inout bit [7:0] status, inout bit [31:0] insn_cnt, inout bit rnd_req, inout bit [31:0] err_bits, inout bit [31:0] stop_pc); -import "DPI-C" function int otbn_model_send_err_escalation(chandle model, +import "DPI-C" function int acc_model_send_err_escalation(chandle model, bit [31:0] err_val, bit lock_immediately); -import "DPI-C" function int otbn_model_set_rma_req(chandle model, +import "DPI-C" function int acc_model_set_rma_req(chandle model, bit [3:0] rma_req); -import "DPI-C" function int otbn_model_initial_secure_wipe(chandle model); +import "DPI-C" function int acc_model_initial_secure_wipe(chandle model); -import "DPI-C" function int otbn_disable_stack_check(chandle model); +import "DPI-C" function int acc_disable_stack_check(chandle model); `endif // SYNTHESIS diff --git a/hw/ip/otbn/dv/model/otbn_rf_snooper_if.sv b/hw/ip/acc/dv/model/acc_rf_snooper_if.sv similarity index 84% rename from hw/ip/otbn/dv/model/otbn_rf_snooper_if.sv rename to hw/ip/acc/dv/model/acc_rf_snooper_if.sv index fb65e44d35e..05e09d28ed5 100644 --- a/hw/ip/otbn/dv/model/otbn_rf_snooper_if.sv +++ b/hw/ip/acc/dv/model/acc_rf_snooper_if.sv @@ -2,11 +2,11 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// Backdoor interface that can be bound into an OTBN register file and exports a function to peek at +// Backdoor interface that can be bound into an ACC register file and exports a function to peek at // the memory contents. `ifndef SYNTHESIS -interface otbn_rf_snooper_if #( +interface acc_rf_snooper_if #( parameter int Width = 39, // Memory width in bits (including integrity bits) parameter int Depth = 32, // Number of registers parameter bit IntegrityEnabled = 1 // Does the RF include integrity bits? @@ -14,7 +14,7 @@ interface otbn_rf_snooper_if #( input logic [Width-1:0] rf [Depth] ); - export "DPI-C" function otbn_rf_peek; + export "DPI-C" function acc_rf_peek; // Number of data bits per integrity code localparam int IntgGranule = IntegrityEnabled ? 32 : Width; @@ -25,7 +25,7 @@ interface otbn_rf_snooper_if #( localparam int DataWidth = IntgGranules * IntgGranule; localparam int IntgWidth = IntgGranule + IntgBitsPerGranule; - function automatic int otbn_rf_peek(input int index, output bit [255:0] val); + function automatic int acc_rf_peek(input int index, output bit [255:0] val); // Function only works for register files with 256 data bits or fewer if (DataWidth > 256) begin return 0; diff --git a/hw/ip/otbn/dv/model/otbn_stack_snooper_if.sv b/hw/ip/acc/dv/model/acc_stack_snooper_if.sv similarity index 73% rename from hw/ip/otbn/dv/model/otbn_stack_snooper_if.sv rename to hw/ip/acc/dv/model/acc_stack_snooper_if.sv index 6040cb69f27..e5a363c4874 100644 --- a/hw/ip/otbn/dv/model/otbn_stack_snooper_if.sv +++ b/hw/ip/acc/dv/model/acc_stack_snooper_if.sv @@ -2,11 +2,11 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// Backdoor interface that can be bound into an OTBN stack and exports a function to peek at +// Backdoor interface that can be bound into an ACC stack and exports a function to peek at // the stack contents. `ifndef SYNTHESIS -interface otbn_stack_snooper_if #( +interface acc_stack_snooper_if #( parameter int StackIntgWidth = 39, parameter int StackWidth = 32, parameter int StackDepth = 4, @@ -16,10 +16,10 @@ interface otbn_stack_snooper_if #( input logic [StackDepthW:0] stack_wr_ptr_q ); - export "DPI-C" function otbn_stack_element_peek; + export "DPI-C" function acc_stack_element_peek; - function automatic int otbn_stack_element_peek(input int index, output bit [255:0] val); - // Return 2 for issues indicating a broken usage of otbn_stack_element_peek + function automatic int acc_stack_element_peek(input int index, output bit [255:0] val); + // Return 2 for issues indicating a broken usage of acc_stack_element_peek // Function only works for stacks <= 256 bits wide if ((StackWidth > 256) || (index > StackDepth)) begin return 2; diff --git a/hw/ip/otbn/dv/model/otbn_trace_checker.cc b/hw/ip/acc/dv/model/acc_trace_checker.cc similarity index 84% rename from hw/ip/otbn/dv/model/otbn_trace_checker.cc rename to hw/ip/acc/dv/model/acc_trace_checker.cc index 51499232802..911c642a6ae 100644 --- a/hw/ip/otbn/dv/model/otbn_trace_checker.cc +++ b/hw/ip/acc/dv/model/acc_trace_checker.cc @@ -2,19 +2,19 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "otbn_trace_checker.h" +#include "acc_trace_checker.h" #include #include #include #include -#include "otbn_trace_source.h" +#include "acc_trace_source.h" #include "sv_utils.h" -static std::unique_ptr trace_checker; +static std::unique_ptr trace_checker; -OtbnTraceChecker::OtbnTraceChecker() +AccTraceChecker::AccTraceChecker() : rtl_started_(false), rtl_pending_(false), iss_started_(false), @@ -22,38 +22,38 @@ OtbnTraceChecker::OtbnTraceChecker() done_(true), seen_err_(false), last_data_vld_(false) { - OtbnTraceSource::get().AddListener(this); + AccTraceSource::get().AddListener(this); } -OtbnTraceChecker::~OtbnTraceChecker() { +AccTraceChecker::~AccTraceChecker() { if (!done_) { std::cerr - << ("WARNING: Destroying OtbnTraceChecker object with an " + << ("WARNING: Destroying AccTraceChecker object with an " "unfinished operation.\n"); } } -OtbnTraceChecker &OtbnTraceChecker::get() { +AccTraceChecker &AccTraceChecker::get() { if (!trace_checker) { - trace_checker.reset(new OtbnTraceChecker()); + trace_checker.reset(new AccTraceChecker()); } return *trace_checker; } -void OtbnTraceChecker::AcceptTraceString(const std::string &trace, - unsigned int cycle_count) { +void AccTraceChecker::AcceptTraceString(const std::string &trace, + unsigned int cycle_count) { assert(!(rtl_pending_ && iss_pending_)); if (seen_err_) return; done_ = false; - OtbnTraceEntry trace_entry; + AccTraceEntry trace_entry; if (!trace_entry.from_rtl_trace(trace)) { seen_err_ = true; return; } - if (trace_entry.trace_type() == OtbnTraceEntry::Invalid) { + if (trace_entry.trace_type() == AccTraceEntry::Invalid) { std::cerr << "ERROR: Invalid RTL trace entry with invalid header:\n"; trace_entry.print(" ", std::cerr); seen_err_ = true; @@ -66,7 +66,7 @@ void OtbnTraceChecker::AcceptTraceString(const std::string &trace, // // To avoid things being really mysterious, write this to stderr as well. It // shouldn't happen very often, so we won't generate much text. - if (trace_entry.trace_type() == OtbnTraceEntry::Stray) { + if (trace_entry.trace_type() == AccTraceEntry::Stray) { std::cerr << "INFO: RTL trace entry with header 'Z':\n"; trace_entry.print(" ", std::cerr); std::cerr << "Discarding the entry: " @@ -153,14 +153,14 @@ void OtbnTraceChecker::AcceptTraceString(const std::string &trace, } } -bool OtbnTraceChecker::OnIssTrace(const std::vector &lines) { +bool AccTraceChecker::OnIssTrace(const std::vector &lines) { assert(!(rtl_pending_ && iss_pending_)); if (seen_err_) { return false; } - OtbnIssTraceEntry trace_entry; + AccIssTraceEntry trace_entry; if (!trace_entry.from_iss_trace(lines)) { // Error parsing ISS trace. This has already printed a message to stderr. // Just return false to pass the error code along. @@ -202,7 +202,7 @@ bool OtbnTraceChecker::OnIssTrace(const std::vector &lines) { return MatchPair(); } -void OtbnTraceChecker::Flush() { +void AccTraceChecker::Flush() { rtl_pending_ = false; rtl_started_ = false; iss_pending_ = false; @@ -210,7 +210,7 @@ void OtbnTraceChecker::Flush() { no_sec_wipe_data_chk_ = false; } -bool OtbnTraceChecker::Finish() { +bool AccTraceChecker::Finish() { assert(!(rtl_pending_ && iss_pending_)); done_ = true; if (seen_err_) { @@ -235,7 +235,7 @@ bool OtbnTraceChecker::Finish() { return true; } -const OtbnIssTraceEntry::IssData *OtbnTraceChecker::PopIssData() { +const AccIssTraceEntry::IssData *AccTraceChecker::PopIssData() { if (!last_data_vld_) return nullptr; @@ -243,9 +243,9 @@ const OtbnIssTraceEntry::IssData *OtbnTraceChecker::PopIssData() { return &last_data_; } -void OtbnTraceChecker::set_no_sec_wipe_chk() { no_sec_wipe_data_chk_ = true; } +void AccTraceChecker::set_no_sec_wipe_chk() { no_sec_wipe_data_chk_ = true; } -bool OtbnTraceChecker::MatchPair() { +bool AccTraceChecker::MatchPair() { if (!(rtl_pending_ && iss_pending_)) { return true; } @@ -263,13 +263,13 @@ bool OtbnTraceChecker::MatchPair() { iss_entry_.print(" ", std::cerr); seen_err_ = true; return false; - if (rtl_entry_.trace_type() == OtbnTraceEntry::WipeComplete) { + if (rtl_entry_.trace_type() == AccTraceEntry::WipeComplete) { no_sec_wipe_data_chk_ = false; } } // We've got a matching pair of entries. Move the ISS data out of the (now // defunct) iss_entry_ and into last_data_. - if (rtl_entry_.trace_type() == OtbnTraceEntry::Exec) { + if (rtl_entry_.trace_type() == AccTraceEntry::Exec) { last_data_ = std::move(iss_entry_.data_); last_data_vld_ = true; } @@ -280,18 +280,18 @@ bool OtbnTraceChecker::MatchPair() { // Exposed over DPI as: // // import "DPI-C" function bit -// otbn_trace_checker_pop_iss_insn(output bit [31:0] insn_addr, +// acc_trace_checker_pop_iss_insn(output bit [31:0] insn_addr, // output string mnemonic); // // Any string output argument will stay unchanged until the next call to this // function. -extern "C" unsigned char otbn_trace_checker_pop_iss_insn( - svBitVecVal *insn_addr, const char **mnemonic) { +extern "C" unsigned char acc_trace_checker_pop_iss_insn(svBitVecVal *insn_addr, + const char **mnemonic) { static char mnemonic_buf[16]; - const OtbnIssTraceEntry::IssData *iss_data = - OtbnTraceChecker::get().PopIssData(); + const AccIssTraceEntry::IssData *iss_data = + AccTraceChecker::get().PopIssData(); if (!iss_data) return 0; diff --git a/hw/ip/otbn/dv/model/otbn_trace_checker.h b/hw/ip/acc/dv/model/acc_trace_checker.h similarity index 83% rename from hw/ip/otbn/dv/model/otbn_trace_checker.h rename to hw/ip/acc/dv/model/acc_trace_checker.h index 321814bca38..48a68450ca3 100644 --- a/hw/ip/otbn/dv/model/otbn_trace_checker.h +++ b/hw/ip/acc/dv/model/acc_trace_checker.h @@ -1,11 +1,11 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_TRACE_CHECKER_H_ -#define OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_TRACE_CHECKER_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_TRACE_CHECKER_H_ +#define OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_TRACE_CHECKER_H_ // A singleton class that listens to trace entries from the simulated core (as -// an OtbnTraceListener) and compares them with the trace coming out of the +// an AccTraceListener) and compares them with the trace coming out of the // stepped ISS process. // // Trace entries from the simulated core appear as a result of DPI callbacks, @@ -39,16 +39,16 @@ #include #include -#include "otbn_trace_entry.h" -#include "otbn_trace_listener.h" +#include "acc_trace_entry.h" +#include "acc_trace_listener.h" -class OtbnTraceChecker : public OtbnTraceListener { +class AccTraceChecker : public AccTraceListener { public: - OtbnTraceChecker(); - ~OtbnTraceChecker(); + AccTraceChecker(); + ~AccTraceChecker(); // Get the singleton object - static OtbnTraceChecker &get(); + static AccTraceChecker &get(); // Take a trace entry from the wrapped RTL. Any mismatch error is stored // until the next call to an API function that can respond with the error. @@ -73,7 +73,7 @@ class OtbnTraceChecker : public OtbnTraceListener { // Return and clear the ISS data for the last pair of trace entries that went // through MatchPair if there is any. - const OtbnIssTraceEntry::IssData *PopIssData(); + const AccIssTraceEntry::IssData *PopIssData(); // Tell the model not to execute checks to see if secure wiping has written // random data to all registers before wiping them with zeroes on the next @@ -89,11 +89,11 @@ class OtbnTraceChecker : public OtbnTraceListener { bool rtl_started_; bool rtl_pending_; - OtbnTraceEntry rtl_entry_; + AccTraceEntry rtl_entry_; bool iss_started_; bool iss_pending_; - OtbnIssTraceEntry iss_entry_; + AccIssTraceEntry iss_entry_; bool done_; bool seen_err_; @@ -101,8 +101,8 @@ class OtbnTraceChecker : public OtbnTraceListener { // The ISS entry for the last pair of trace entries that went through // MatchPair. bool last_data_vld_; - OtbnIssTraceEntry::IssData last_data_; + AccIssTraceEntry::IssData last_data_; bool no_sec_wipe_data_chk_; }; -#endif // OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_TRACE_CHECKER_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_TRACE_CHECKER_H_ diff --git a/hw/ip/otbn/dv/model/otbn_trace_entry.cc b/hw/ip/acc/dv/model/acc_trace_entry.cc similarity index 84% rename from hw/ip/otbn/dv/model/otbn_trace_entry.cc rename to hw/ip/acc/dv/model/acc_trace_entry.cc index 24d94e675f2..8c10bb6f2ad 100644 --- a/hw/ip/otbn/dv/model/otbn_trace_entry.cc +++ b/hw/ip/acc/dv/model/acc_trace_entry.cc @@ -2,21 +2,21 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "otbn_trace_entry.h" +#include "acc_trace_entry.h" #include #include #include #include -bool OtbnTraceBodyLine::fill_from_string(const std::string &src, - const std::string &line) { +bool AccTraceBodyLine::fill_from_string(const std::string &src, + const std::string &line) { // A valid line matches the following regex std::regex re("(.) ([^:]+): (.+)"); std::smatch match; if (!std::regex_match(line, match, re)) { - std::cerr << "OTBN trace body line from " << src + std::cerr << "ACC trace body line from " << src << " does not have expected format. Saw: `" << line << "'.\n"; return false; } @@ -30,7 +30,7 @@ bool OtbnTraceBodyLine::fill_from_string(const std::string &src, return true; } -bool OtbnTraceBodyLine::operator==(const OtbnTraceBodyLine &other) const { +bool AccTraceBodyLine::operator==(const AccTraceBodyLine &other) const { // If the raw lines are identical, the two objects are identical and no // further checks are required. if (raw_ == other.raw_) { @@ -63,7 +63,7 @@ bool OtbnTraceBodyLine::operator==(const OtbnTraceBodyLine &other) const { return true; } -bool OtbnTraceEntry::from_rtl_trace(const std::string &trace) { +bool AccTraceEntry::from_rtl_trace(const std::string &trace) { size_t eol = trace.find('\n'); hdr_ = trace.substr(0, eol); trace_type_ = hdr_to_trace_type(hdr_); @@ -79,7 +79,7 @@ bool OtbnTraceEntry::from_rtl_trace(const std::string &trace) { if (!(line.size() > 0 && line[0] == '>')) continue; - OtbnTraceBodyLine parsed_line; + AccTraceBodyLine parsed_line; if (!parsed_line.fill_from_string("RTL", line)) { return false; } @@ -88,9 +88,9 @@ bool OtbnTraceEntry::from_rtl_trace(const std::string &trace) { return true; } -bool OtbnTraceEntry::compare_rtl_iss_entries(const OtbnTraceEntry &other, - bool no_sec_wipe_data_chk, - std::string *err_desc) const { +bool AccTraceEntry::compare_rtl_iss_entries(const AccTraceEntry &other, + bool no_sec_wipe_data_chk, + std::string *err_desc) const { assert(err_desc); if (hdr_ != other.hdr_) { @@ -125,7 +125,7 @@ bool OtbnTraceEntry::compare_rtl_iss_entries(const OtbnTraceEntry &other, return true; } -void OtbnTraceEntry::print(const std::string &indent, std::ostream &os) const { +void AccTraceEntry::print(const std::string &indent, std::ostream &os) const { os << indent << hdr_ << "\n"; for (const auto &pr : writes_) { for (const auto &line : pr.second) { @@ -134,15 +134,14 @@ void OtbnTraceEntry::print(const std::string &indent, std::ostream &os) const { } } -void OtbnTraceEntry::take_writes(const OtbnTraceEntry &other, - bool other_first) { +void AccTraceEntry::take_writes(const AccTraceEntry &other, bool other_first) { for (const auto &pr : other.writes_) { - std::vector &so_far = writes_[pr.first]; + std::vector &so_far = writes_[pr.first]; if (other_first) { // If other_first is true, we should prepend the writes from other. We do // so by creating a temporary vector (with a copy of the writes from // other) and then appending any writes we had before. - std::vector tmp(pr.second); + std::vector tmp(pr.second); tmp.insert(tmp.end(), so_far.begin(), so_far.end()); writes_[pr.first] = tmp; } else { @@ -153,7 +152,7 @@ void OtbnTraceEntry::take_writes(const OtbnTraceEntry &other, } } -bool OtbnTraceEntry::is_compatible(const OtbnTraceEntry &prev) const { +bool AccTraceEntry::is_compatible(const AccTraceEntry &prev) const { // Two entries are compatible if they might both come from the multi-cycle // execution of one instruction. For example, you might expect to see these // two lines: @@ -210,21 +209,21 @@ bool OtbnTraceEntry::is_compatible(const OtbnTraceEntry &prev) const { return 0 == hdr_.compare(1, first_qm - 1, prev.hdr_, 1, first_qm - 1); } -bool OtbnTraceEntry::is_partial() const { - return ((trace_type_ == OtbnTraceEntry::Stall) || - (trace_type_ == OtbnTraceEntry::WipeInProgress)); +bool AccTraceEntry::is_partial() const { + return ((trace_type_ == AccTraceEntry::Stall) || + (trace_type_ == AccTraceEntry::WipeInProgress)); } -bool OtbnTraceEntry::is_final() const { - return ((trace_type_ == OtbnTraceEntry::Exec) || - (trace_type_ == OtbnTraceEntry::WipeComplete) || - (trace_type_ == OtbnTraceEntry::Stray)); +bool AccTraceEntry::is_final() const { + return ((trace_type_ == AccTraceEntry::Exec) || + (trace_type_ == AccTraceEntry::WipeComplete) || + (trace_type_ == AccTraceEntry::Stray)); } -bool OtbnTraceEntry::check_entries_compatible( +bool AccTraceEntry::check_entries_compatible( trace_type_t type, const std::string &key, - const std::vector &rtl_lines, - const std::vector &iss_lines, bool no_sec_wipe_data_chk, + const std::vector &rtl_lines, + const std::vector &iss_lines, bool no_sec_wipe_data_chk, std::string *err_desc) { assert(rtl_lines.size() && iss_lines.size()); assert(type == WipeComplete || type == Exec); @@ -272,7 +271,7 @@ bool OtbnTraceEntry::check_entries_compatible( return true; } -OtbnTraceEntry::trace_type_t OtbnTraceEntry::hdr_to_trace_type( +AccTraceEntry::trace_type_t AccTraceEntry::hdr_to_trace_type( const std::string &hdr) { if (hdr.empty()) { return Invalid; @@ -294,7 +293,7 @@ OtbnTraceEntry::trace_type_t OtbnTraceEntry::hdr_to_trace_type( } } -bool OtbnIssTraceEntry::from_iss_trace(const std::vector &lines) { +bool AccIssTraceEntry::from_iss_trace(const std::vector &lines) { // Read FSM. state 0 = read header; state 1 = read mnemonic (for E // lines); state 2 = read writes int state = 0; @@ -336,7 +335,7 @@ bool OtbnIssTraceEntry::from_iss_trace(const std::vector &lines) { // external register changes, not tracked by the RTL core simulation) bool is_bang = (line.size() > 0 && line[0] == '!'); if (!is_bang) { - OtbnTraceBodyLine parsed_line; + AccTraceBodyLine parsed_line; if (!parsed_line.fill_from_string("ISS", line)) { return false; } diff --git a/hw/ip/otbn/dv/model/otbn_trace_entry.h b/hw/ip/acc/dv/model/acc_trace_entry.h similarity index 73% rename from hw/ip/otbn/dv/model/otbn_trace_entry.h rename to hw/ip/acc/dv/model/acc_trace_entry.h index 9926e4d6aff..7081f6ce0c3 100644 --- a/hw/ip/otbn/dv/model/otbn_trace_entry.h +++ b/hw/ip/acc/dv/model/acc_trace_entry.h @@ -1,15 +1,15 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_TRACE_ENTRY_H_ -#define OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_TRACE_ENTRY_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_TRACE_ENTRY_H_ +#define OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_TRACE_ENTRY_H_ #include #include #include #include -// This models a body line in an OTBN trace entry (type '<', '>', 'R' or 'W'). +// This models a body line in an ACC trace entry (type '<', '>', 'R' or 'W'). // Each of these lines is of the format // // TYPE ' ' LOC ': ' VALUE @@ -17,14 +17,14 @@ // and we parse them accordingly here. The point is that we want to merge // successive writes to the same location and thus need to unpack things enough // to see them. -class OtbnTraceBodyLine { +class AccTraceBodyLine { public: // Parse a line into this object, based on the format above. On success, // return true. On failure, write an error message to stderr (using src to // say where the line came from) and return false. bool fill_from_string(const std::string &src, const std::string &line); - bool operator==(const OtbnTraceBodyLine &other) const; + bool operator==(const AccTraceBodyLine &other) const; // Return the location that is being read or written const std::string &get_loc() const { return loc_; } @@ -39,7 +39,7 @@ class OtbnTraceBodyLine { std::string value_; }; -class OtbnTraceEntry { +class AccTraceEntry { public: enum trace_type_t { Invalid, @@ -50,25 +50,25 @@ class OtbnTraceEntry { Stray, }; - virtual ~OtbnTraceEntry(){}; + virtual ~AccTraceEntry(){}; // Parse a trace entry from the RTL into this object. On an error, print a // message to stderr and return false. bool from_rtl_trace(const std::string &trace); - bool compare_rtl_iss_entries(const OtbnTraceEntry &other, + bool compare_rtl_iss_entries(const AccTraceEntry &other, bool no_sec_wipe_data_chk, std::string *err_desc) const; void print(const std::string &indent, std::ostream &os) const; - void take_writes(const OtbnTraceEntry &other, bool other_first); + void take_writes(const AccTraceEntry &other, bool other_first); trace_type_t trace_type() const { return trace_type_; } // True if this is an acceptable line to follow other (assumed to // have been of type Stall or WipeInProgress) - bool is_compatible(const OtbnTraceEntry &other) const; + bool is_compatible(const AccTraceEntry &other) const; // True if this entry is "partial" (Stall or WipeInProgress) bool is_partial() const; @@ -79,19 +79,19 @@ class OtbnTraceEntry { protected: static bool check_entries_compatible( trace_type_t type, const std::string &key, - const std::vector &rtl_lines, - const std::vector &iss_lines, - bool no_sec_wipe_data_chk, std::string *err_desc); + const std::vector &rtl_lines, + const std::vector &iss_lines, bool no_sec_wipe_data_chk, + std::string *err_desc); static trace_type_t hdr_to_trace_type(const std::string &hdr); trace_type_t trace_type_; std::string hdr_; // The register writes for this trace entry, keyed by destination - std::map> writes_; + std::map> writes_; }; -class OtbnIssTraceEntry : public OtbnTraceEntry { +class AccIssTraceEntry : public AccTraceEntry { public: bool from_iss_trace(const std::vector &lines); @@ -104,4 +104,4 @@ class OtbnIssTraceEntry : public OtbnTraceEntry { IssData data_; }; -#endif // OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_TRACE_ENTRY_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_MODEL_ACC_TRACE_ENTRY_H_ diff --git a/hw/ip/otbn/dv/model/iss_wrapper.cc b/hw/ip/acc/dv/model/iss_wrapper.cc similarity index 95% rename from hw/ip/otbn/dv/model/iss_wrapper.cc rename to hw/ip/acc/dv/model/iss_wrapper.cc index b972b46f0df..421adc45d15 100644 --- a/hw/ip/otbn/dv/model/iss_wrapper.cc +++ b/hw/ip/acc/dv/model/iss_wrapper.cc @@ -20,7 +20,7 @@ #include #include -#include "otbn_trace_checker.h" +#include "acc_trace_checker.h" // Guard class to safely delete C strings namespace { @@ -45,11 +45,11 @@ struct TmpDir { tmpdir = "/tmp"; std::string tmp_template(tmpdir); - tmp_template += "/otbn_XXXXXX"; + tmp_template += "/acc_XXXXXX"; if (!mkdtemp(&tmp_template.at(0))) { std::ostringstream oss; - oss << ("Cannot create temporary directory for OTBN simulation " + oss << ("Cannot create temporary directory for ACC simulation " "with template ") << tmp_template << ": " << strerror(errno); throw std::runtime_error(oss.str()); @@ -59,9 +59,9 @@ struct TmpDir { return tmp_template; } - // Return true if the OTBN_MODEL_KEEP_TMP environment variable is set to 1. + // Return true if the ACC_MODEL_KEEP_TMP environment variable is set to 1. static bool should_keep_tmp() { - const char *keep_str = getenv("OTBN_MODEL_KEEP_TMP"); + const char *keep_str = getenv("ACC_MODEL_KEEP_TMP"); if (!keep_str) return false; return (strcmp(keep_str, "1") == 0) ? true : false; @@ -86,7 +86,7 @@ struct TmpDir { if (TmpDir::should_keep_tmp()) { std::cerr << "Keeping temporary directory at " << path - << " because OTBN_MODEL_KEEP_TMP=1.\n"; + << " because ACC_MODEL_KEEP_TMP=1.\n"; return; } @@ -99,8 +99,8 @@ struct TmpDir { // stderr to tell the user what's going on. struct stat statbuf; if (stat(path.c_str(), &statbuf) == 0) { - std::cerr << "ERROR: Failed to delete OTBN temporary directory at " - << path << ".\n"; + std::cerr << "ERROR: Failed to delete ACC temporary directory at " << path + << ".\n"; } } }; @@ -160,7 +160,7 @@ static std::string find_repo_top() { std::ostringstream oss; oss << "Cannot find a git top-level directory containing " << self_path.get() - << (". To run the OTBN model outside of the repo, " + << (". To run the ACC model outside of the repo, " "set the $REPO_TOP environment variable."); throw std::runtime_error(oss.str()); } @@ -188,14 +188,14 @@ static std::string find_repo_top() { return path_buf; } -// Find the otbn Python model. On failure, throw a std::runtime_error with a +// Find the acc Python model. On failure, throw a std::runtime_error with a // description of what went wrong. -static std::string find_otbn_model() { - std::string path = find_repo_top() + "/hw/ip/otbn/dv/otbnsim/stepped.py"; +static std::string find_acc_model() { + std::string path = find_repo_top() + "/hw/ip/acc/dv/accsim/stepped.py"; c_str_ptr abs_path(realpath(path.c_str(), NULL)); if (!abs_path) { std::ostringstream oss; - oss << "Cannot find otbnsim.py, at '" << path << "'.\n"; + oss << "Cannot find accsim.py, at '" << path << "'.\n"; throw std::runtime_error(oss.str()); } @@ -220,8 +220,8 @@ static void read_ext_reg(const std::string ®_name, // We're interested in lines that show an update to the external register // called reg_name. These look something like this: // - // ! otbn.$REG_NAME: 0x00000000 - std::regex re("! otbn\\." + reg_name + ": 0x([0-9a-f]{8})"); + // ! acc.$REG_NAME: 0x00000000 + std::regex re("! acc\\." + reg_name + ": 0x([0-9a-f]{8})"); std::smatch match; for (const auto &line : lines) { @@ -267,7 +267,7 @@ void MirroredRegs::reset() { } ISSWrapper::ISSWrapper() : tmpdir(new TmpDir()) { - std::string model_path(find_otbn_model()); + std::string model_path(find_acc_model()); // We want two pipes: one for writing to the child process, and the other for // reading from it. We set the O_CLOEXEC flag so that the child process will @@ -455,7 +455,7 @@ int ISSWrapper::step(bool gen_trace) { run_command("step\n", &lines); if (gen_trace && lines.size()) { - if (!OtbnTraceChecker::get().OnIssTrace(lines)) { + if (!AccTraceChecker::get().OnIssTrace(lines)) { return -1; } } @@ -521,7 +521,7 @@ uint32_t ISSWrapper::step_crc(const std::array &item, void ISSWrapper::reset(bool gen_trace) { if (gen_trace) - OtbnTraceChecker::get().Flush(); + AccTraceChecker::get().Flush(); run_command("reset\n", nullptr); diff --git a/hw/ip/otbn/dv/model/iss_wrapper.h b/hw/ip/acc/dv/model/iss_wrapper.h similarity index 93% rename from hw/ip/otbn/dv/model/iss_wrapper.h rename to hw/ip/acc/dv/model/iss_wrapper.h index 46c2278f04b..68cdf678c3d 100644 --- a/hw/ip/otbn/dv/model/iss_wrapper.h +++ b/hw/ip/acc/dv/model/iss_wrapper.h @@ -1,8 +1,8 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_MODEL_ISS_WRAPPER_H_ -#define OPENTITAN_HW_IP_OTBN_DV_MODEL_ISS_WRAPPER_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_MODEL_ISS_WRAPPER_H_ +#define OPENTITAN_HW_IP_ACC_DV_MODEL_ISS_WRAPPER_H_ #include #include @@ -15,7 +15,7 @@ // Forward declaration (the implementation is private in iss_wrapper.cc) struct TmpDir; -// OTBN has some externally visible CSRs that can be updated by hardware +// ACC has some externally visible CSRs that can be updated by hardware // (without explicit writes from software). The ISSWrapper mirrors the ISS's // versions of these registers in this structure. class MirroredRegs { @@ -101,7 +101,7 @@ struct ISSWrapper { // Run simulation for a single cycle. // - // If gen_trace is true, pass trace data to the (singleton) OtbnTraceChecker + // If gen_trace is true, pass trace data to the (singleton) AccTraceChecker // object. // // The return code describes the state of the simulation. It is 1 if the @@ -131,7 +131,7 @@ struct ISSWrapper { // Reset simulation // // This doesn't actually send anything to the ISS, but instead tells the - // OtbnTraceChecker to clear out any partial instructions. It also resets + // AccTraceChecker to clear out any partial instructions. It also resets // mirrored registers to their initial states. void reset(bool gen_trace); @@ -175,4 +175,4 @@ struct ISSWrapper { MirroredRegs mirrored_; }; -#endif // OPENTITAN_HW_IP_OTBN_DV_MODEL_ISS_WRAPPER_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_MODEL_ISS_WRAPPER_H_ diff --git a/hw/ip/otbn/dv/rig/Makefile b/hw/ip/acc/dv/rig/Makefile similarity index 83% rename from hw/ip/otbn/dv/rig/Makefile rename to hw/ip/acc/dv/rig/Makefile index 6175c3044cc..6c72189681b 100644 --- a/hw/ip/otbn/dv/rig/Makefile +++ b/hw/ip/acc/dv/rig/Makefile @@ -5,10 +5,10 @@ .PHONY: all all: lint -# We need a directory to build stuff and use the "otbn/rig" namespace +# We need a directory to build stuff and use the "acc/rig" namespace # in the top-level build-bin directory. repo-top := ../../../.. -build-dir := $(repo-top)/build-bin/otbn/rig +build-dir := $(repo-top)/build-bin/acc/rig cs-build-dir := $(build-dir)/code-snippets lint-build-dir := $(build-dir)/lint @@ -16,7 +16,7 @@ $(build-dir) $(lint-build-dir): mkdir -p $@ pylibs := $(wildcard ../../util/shared/*.py rig/*.py rig/gens/*.py) -pyscripts := otbn-rig +pyscripts := acc-rig lint-stamps := $(foreach s,$(pyscripts),$(lint-build-dir)/$(s).stamp) $(lint-build-dir)/%.stamp: % $(pylibs) | $(lint-build-dir) diff --git a/hw/ip/otbn/dv/rig/README.md b/hw/ip/acc/dv/rig/README.md similarity index 87% rename from hw/ip/otbn/dv/rig/README.md rename to hw/ip/acc/dv/rig/README.md index 1def062a03e..fdb84438578 100644 --- a/hw/ip/otbn/dv/rig/README.md +++ b/hw/ip/acc/dv/rig/README.md @@ -1,7 +1,7 @@ -# OTBN Random Instruction Generator +# ACC Random Instruction Generator -This directory contains a random instruction generator for OTBN called -`otbn-rig`. This is intended to be run in multiple phases. If you just +This directory contains a random instruction generator for ACC called +`acc-rig`. This is intended to be run in multiple phases. If you just want to generate some random binaries, it might be easier to call the wrapper at `../uvm/gen-binaries.py`. @@ -17,7 +17,7 @@ command. Example usage: ``` -hw/ip/otbn/dv/rig/otbn-rig gen --seed 123 --size 1000 >foo.json +hw/ip/acc/dv/rig/acc-rig gen --seed 123 --size 1000 >foo.json ``` To control random generation, there is a `--seed` parameter. The @@ -69,7 +69,7 @@ words of (randomly) initialised data, scattered around dmem. Once a random program has been generated, the `asm` command can be used to convert it to an assembly listing. This, in turn, can be -assembled and linked using the toolchain in `hw/ip/otbn/util`. +assembled and linked using the toolchain in `hw/ip/acc/util`. Unlike the `gen` command, this step does no random generation: it's a deterministic translation from the JSON input to assembly and linker @@ -77,7 +77,7 @@ script output. Example usage: ``` -hw/ip/otbn/dv/rig/otbn-rig asm --output foo foo.json +hw/ip/acc/dv/rig/acc-rig asm --output foo foo.json ``` When given the `--output` parameter, this command generates two output @@ -86,8 +86,8 @@ are an assembly listing and a linker script, respectively. To assemble and link, use commands like: ``` -hw/ip/otbn/util/otbn_as.py -o foo.o foo.s -hw/ip/otbn/util/otbn_ld.py -o foo.elf -T foo.ld foo.o +hw/ip/acc/util/acc_as.py -o foo.o foo.s +hw/ip/acc/util/acc_ld.py -o foo.elf -T foo.ld foo.o ``` This is automated in the `gen-binaries.py` wrapper described above. diff --git a/hw/ip/otbn/dv/rig/otbn-rig b/hw/ip/acc/dv/rig/acc-rig similarity index 93% rename from hw/ip/otbn/dv/rig/otbn-rig rename to hw/ip/acc/dv/rig/acc-rig index cc2b1eecb60..fa3dbf328a3 100755 --- a/hw/ip/otbn/dv/rig/otbn-rig +++ b/hw/ip/acc/dv/rig/acc-rig @@ -4,7 +4,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''Wrapper script to run the OTBN random instruction generator''' +'''Wrapper script to run the ACC random instruction generator''' import argparse import json @@ -13,12 +13,12 @@ import random import sys from typing import Optional, cast -# Ensure that the OTBN utils directory is on sys.path. This means that RIG code -# can import modules like "shared.foo" and get the OTBN shared code. +# Ensure that the ACC utils directory is on sys.path. This means that RIG code +# can import modules like "shared.foo" and get the ACC shared code. _RIG_DIR = os.path.dirname(__file__) -_OTBN_DIR = os.path.normpath(os.path.join(_RIG_DIR, '../..')) -_OTBN_UTIL_DIR = os.path.join(_OTBN_DIR, 'util') -sys.path.append(_OTBN_UTIL_DIR) +_ACC_DIR = os.path.normpath(os.path.join(_RIG_DIR, '../..')) +_ACC_UTIL_DIR = os.path.join(_ACC_DIR, 'util') +sys.path.append(_ACC_UTIL_DIR) from shared.insn_yaml import InsnsFile, load_insns_yaml # noqa: E402 @@ -179,7 +179,7 @@ def main() -> int: asm.add_argument('snippets', metavar='path.json', type=argparse.FileType('r'), nargs='?', default=sys.stdin, help=('A JSON file of snippets, as generated by ' - 'otbn-rig gen.')) + 'acc-rig gen.')) asm.set_defaults(func=asm_main) args = parser.parse_args() diff --git a/hw/ip/otbn/dv/rig/mypy.ini b/hw/ip/acc/dv/rig/mypy.ini similarity index 76% rename from hw/ip/otbn/dv/rig/mypy.ini rename to hw/ip/acc/dv/rig/mypy.ini index 76db64b4560..71da3304aeb 100644 --- a/hw/ip/otbn/dv/rig/mypy.ini +++ b/hw/ip/acc/dv/rig/mypy.ini @@ -1,5 +1,5 @@ [mypy] -# Add OTBN and OpenTitan util dirs to MYPYPATH +# Add ACC and repo util dirs to MYPYPATH mypy_path = $MYPY_CONFIG_FILE_DIR/../../util, $MYPY_CONFIG_FILE_DIR/../../../../../util [mypy-semantic_version] ignore_missing_imports = True diff --git a/hw/ip/otbn/dv/rig/rig/README.md b/hw/ip/acc/dv/rig/rig/README.md similarity index 90% rename from hw/ip/otbn/dv/rig/rig/README.md rename to hw/ip/acc/dv/rig/rig/README.md index d476cd7fc7e..1579cfe0198 100644 --- a/hw/ip/otbn/dv/rig/rig/README.md +++ b/hw/ip/acc/dv/rig/rig/README.md @@ -1,4 +1,4 @@ -# OTBN Random Instruction Generator - Internals +# ACC Random Instruction Generator - Internals This directory contains the internal part of the random instruction generator (RIG). This document aims to help with the general understanding of the inner workings of RIG. @@ -11,7 +11,7 @@ The `SnippetGens` class involves a list of these smaller snippet generators defi This main script also constructs a `Program` and a `Model`. `Program` reflects both data memory that gets initialised and also the instruction memory that gets set with the generated snippets. -The generated program then gets used in `otbn-rig` (which lives in the parent directory) to create proper output files to simulate the generated instructions. +The generated program then gets used in `acc-rig` (which lives in the parent directory) to create proper output files to simulate the generated instructions. ## Snippet Generators These generators are split up into two lists. @@ -31,7 +31,7 @@ Picks a configuration file at random from below with specified weights. - `straight-line.yaml`: A custom configuration that does not generate any branches, hence the name. ## Abstract Models in RIG -In order to generate concise programs that don't run into architectural problems RIG needs to have an idea about how OTBN works, what's a memory, a register etc. +In order to generate concise programs that don't run into architectural problems RIG needs to have an idea about how ACC works, what's a memory, a register etc. This is all handled in `model.py` in which different classes for different models exists. A list of them includes: - `CallStack`: Abstract model of the `x1` call stack diff --git a/hw/ip/otbn/dv/rig/rig/config.py b/hw/ip/acc/dv/rig/rig/config.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/config.py rename to hw/ip/acc/dv/rig/rig/config.py diff --git a/hw/ip/otbn/dv/rig/rig/configs/README.md b/hw/ip/acc/dv/rig/rig/configs/README.md similarity index 100% rename from hw/ip/otbn/dv/rig/rig/configs/README.md rename to hw/ip/acc/dv/rig/rig/configs/README.md diff --git a/hw/ip/otbn/dv/rig/rig/configs/base.yml b/hw/ip/acc/dv/rig/rig/configs/base.yml similarity index 100% rename from hw/ip/otbn/dv/rig/rig/configs/base.yml rename to hw/ip/acc/dv/rig/rig/configs/base.yml diff --git a/hw/ip/otbn/dv/rig/rig/configs/default.yml b/hw/ip/acc/dv/rig/rig/configs/default.yml similarity index 100% rename from hw/ip/otbn/dv/rig/rig/configs/default.yml rename to hw/ip/acc/dv/rig/rig/configs/default.yml diff --git a/hw/ip/otbn/dv/rig/rig/configs/loopy.yml b/hw/ip/acc/dv/rig/rig/configs/loopy.yml similarity index 100% rename from hw/ip/otbn/dv/rig/rig/configs/loopy.yml rename to hw/ip/acc/dv/rig/rig/configs/loopy.yml diff --git a/hw/ip/otbn/dv/rig/rig/configs/safe.yml b/hw/ip/acc/dv/rig/rig/configs/safe.yml similarity index 100% rename from hw/ip/otbn/dv/rig/rig/configs/safe.yml rename to hw/ip/acc/dv/rig/rig/configs/safe.yml diff --git a/hw/ip/otbn/dv/rig/rig/configs/straight-line.yml b/hw/ip/acc/dv/rig/rig/configs/straight-line.yml similarity index 100% rename from hw/ip/otbn/dv/rig/rig/configs/straight-line.yml rename to hw/ip/acc/dv/rig/rig/configs/straight-line.yml diff --git a/hw/ip/otbn/dv/rig/rig/gens/app_req.py b/hw/ip/acc/dv/rig/rig/gens/app_req.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/app_req.py rename to hw/ip/acc/dv/rig/rig/gens/app_req.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_at_end.py b/hw/ip/acc/dv/rig/rig/gens/bad_at_end.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_at_end.py rename to hw/ip/acc/dv/rig/rig/gens/bad_at_end.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_bnmovr.py b/hw/ip/acc/dv/rig/rig/gens/bad_bnmovr.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_bnmovr.py rename to hw/ip/acc/dv/rig/rig/gens/bad_bnmovr.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_branch.py b/hw/ip/acc/dv/rig/rig/gens/bad_branch.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_branch.py rename to hw/ip/acc/dv/rig/rig/gens/bad_branch.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py b/hw/ip/acc/dv/rig/rig/gens/bad_deep_loop.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py rename to hw/ip/acc/dv/rig/rig/gens/bad_deep_loop.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_giant_loop.py b/hw/ip/acc/dv/rig/rig/gens/bad_giant_loop.py similarity index 99% rename from hw/ip/otbn/dv/rig/rig/gens/bad_giant_loop.py rename to hw/ip/acc/dv/rig/rig/gens/bad_giant_loop.py index 3988fba0d02..ca552b57c96 100644 --- a/hw/ip/otbn/dv/rig/rig/gens/bad_giant_loop.py +++ b/hw/ip/acc/dv/rig/rig/gens/bad_giant_loop.py @@ -22,7 +22,7 @@ class BadGiantLoop(Loop): This generator has "ends_program = True", but doesn't end the program in itself. Instead, it sets up a loop with an endpoint that doesn't fit in memory (so the loop body will never actually terminate) and then generates - a sequence for the rest of the program, to go inside the body. OTBN will + a sequence for the rest of the program, to go inside the body. ACC will complete its operation without popping the loop off the stack. ''' diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_insn.py b/hw/ip/acc/dv/rig/rig/gens/bad_insn.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_insn.py rename to hw/ip/acc/dv/rig/rig/gens/bad_insn.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_ispr.py b/hw/ip/acc/dv/rig/rig/gens/bad_ispr.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_ispr.py rename to hw/ip/acc/dv/rig/rig/gens/bad_ispr.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_load_store.py b/hw/ip/acc/dv/rig/rig/gens/bad_load_store.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_load_store.py rename to hw/ip/acc/dv/rig/rig/gens/bad_load_store.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/bad_zero_loop.py b/hw/ip/acc/dv/rig/rig/gens/bad_zero_loop.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/bad_zero_loop.py rename to hw/ip/acc/dv/rig/rig/gens/bad_zero_loop.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/branch.py b/hw/ip/acc/dv/rig/rig/gens/branch.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/branch.py rename to hw/ip/acc/dv/rig/rig/gens/branch.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/branch_gen.py b/hw/ip/acc/dv/rig/rig/gens/branch_gen.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/branch_gen.py rename to hw/ip/acc/dv/rig/rig/gens/branch_gen.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/call_stack_rw.py b/hw/ip/acc/dv/rig/rig/gens/call_stack_rw.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/call_stack_rw.py rename to hw/ip/acc/dv/rig/rig/gens/call_stack_rw.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/clear_wsr.py b/hw/ip/acc/dv/rig/rig/gens/clear_wsr.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/clear_wsr.py rename to hw/ip/acc/dv/rig/rig/gens/clear_wsr.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/ecall.py b/hw/ip/acc/dv/rig/rig/gens/ecall.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/ecall.py rename to hw/ip/acc/dv/rig/rig/gens/ecall.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/edge_load_store.py b/hw/ip/acc/dv/rig/rig/gens/edge_load_store.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/edge_load_store.py rename to hw/ip/acc/dv/rig/rig/gens/edge_load_store.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/jump.py b/hw/ip/acc/dv/rig/rig/gens/jump.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/jump.py rename to hw/ip/acc/dv/rig/rig/gens/jump.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/known_wdr.py b/hw/ip/acc/dv/rig/rig/gens/known_wdr.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/known_wdr.py rename to hw/ip/acc/dv/rig/rig/gens/known_wdr.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/loop.py b/hw/ip/acc/dv/rig/rig/gens/loop.py similarity index 99% rename from hw/ip/otbn/dv/rig/rig/gens/loop.py rename to hw/ip/acc/dv/rig/rig/gens/loop.py index 48026046f8d..247f8390e2f 100644 --- a/hw/ip/otbn/dv/rig/rig/gens/loop.py +++ b/hw/ip/acc/dv/rig/rig/gens/loop.py @@ -630,7 +630,7 @@ def _gen_pieces(self, # Update model to take the loop body into account. For the loop stack # state, we just take whatever's in body_model. If everything was well # balanced, this will match anyway (and, if not, it's the state that - # OTBN will be in at the end of the loop). + # ACC will be in at the end of the loop). # # For registers, if we know we have exactly one iteration through the # body, we can just take them from body_model. Otherwise, we merge the diff --git a/hw/ip/otbn/dv/rig/rig/gens/loop_dup_end.py b/hw/ip/acc/dv/rig/rig/gens/loop_dup_end.py similarity index 96% rename from hw/ip/otbn/dv/rig/rig/gens/loop_dup_end.py rename to hw/ip/acc/dv/rig/rig/gens/loop_dup_end.py index 43a509a0254..a719ac8eb31 100644 --- a/hw/ip/otbn/dv/rig/rig/gens/loop_dup_end.py +++ b/hw/ip/acc/dv/rig/rig/gens/loop_dup_end.py @@ -66,7 +66,7 @@ class LoopDupEnd(Loop): pop off the rest of the loop stack. But we've got some coverage points for this happening, so we need to be able to generate it. Note that, unlike most "bad behaviour" generators, this doesn't set the ends_program flag: - OTBN won't spot any error, we'll just use up some of the loop stack. + ACC won't spot any error, we'll just use up some of the loop stack. ''' def __init__(self, cfg: Config, insns_file: InsnsFile) -> None: @@ -128,7 +128,7 @@ def _gen_tail(self, # Add a bogus extra copy of the loop end address to model's loop stack # here. Then Loop's _gen_body implementation will pop the top one off, - # getting to the state that OTBN is actually in (where we've popped one + # getting to the state that ACC is actually in (where we've popped one # already, but can't pop the second). model.loop_stack.push(loop_end) diff --git a/hw/ip/otbn/dv/rig/rig/gens/misaligned_load_store.py b/hw/ip/acc/dv/rig/rig/gens/misaligned_load_store.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/misaligned_load_store.py rename to hw/ip/acc/dv/rig/rig/gens/misaligned_load_store.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/small_val.py b/hw/ip/acc/dv/rig/rig/gens/small_val.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/small_val.py rename to hw/ip/acc/dv/rig/rig/gens/small_val.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/straight_line_insn.py b/hw/ip/acc/dv/rig/rig/gens/straight_line_insn.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/straight_line_insn.py rename to hw/ip/acc/dv/rig/rig/gens/straight_line_insn.py diff --git a/hw/ip/otbn/dv/rig/rig/gens/untaken_branch.py b/hw/ip/acc/dv/rig/rig/gens/untaken_branch.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/gens/untaken_branch.py rename to hw/ip/acc/dv/rig/rig/gens/untaken_branch.py diff --git a/hw/ip/otbn/dv/rig/rig/init_data.py b/hw/ip/acc/dv/rig/rig/init_data.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/init_data.py rename to hw/ip/acc/dv/rig/rig/init_data.py diff --git a/hw/ip/otbn/dv/rig/rig/known_mem.py b/hw/ip/acc/dv/rig/rig/known_mem.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/known_mem.py rename to hw/ip/acc/dv/rig/rig/known_mem.py diff --git a/hw/ip/otbn/dv/rig/rig/model.py b/hw/ip/acc/dv/rig/rig/model.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/model.py rename to hw/ip/acc/dv/rig/rig/model.py diff --git a/hw/ip/otbn/dv/rig/rig/program.py b/hw/ip/acc/dv/rig/rig/program.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/program.py rename to hw/ip/acc/dv/rig/rig/program.py diff --git a/hw/ip/otbn/dv/rig/rig/rig.py b/hw/ip/acc/dv/rig/rig/rig.py similarity index 98% rename from hw/ip/otbn/dv/rig/rig/rig.py rename to hw/ip/acc/dv/rig/rig/rig.py index 79e78f9a6e9..d850409330b 100644 --- a/hw/ip/otbn/dv/rig/rig/rig.py +++ b/hw/ip/acc/dv/rig/rig/rig.py @@ -20,7 +20,7 @@ def gen_program(config: Config, fuel: int, pqc: bool, insns_file: InsnsFile) -> Tuple[InitData, Snippet, int]: - '''Generate a random program for OTBN + '''Generate a random program for ACC fuel gives a rough upper bound for the number of instructions that will be executed by the generated program. diff --git a/hw/ip/otbn/dv/rig/rig/snippet.py b/hw/ip/acc/dv/rig/rig/snippet.py similarity index 100% rename from hw/ip/otbn/dv/rig/rig/snippet.py rename to hw/ip/acc/dv/rig/rig/snippet.py diff --git a/hw/ip/otbn/dv/rig/rig/snippet_gen.py b/hw/ip/acc/dv/rig/rig/snippet_gen.py similarity index 99% rename from hw/ip/otbn/dv/rig/rig/snippet_gen.py rename to hw/ip/acc/dv/rig/rig/snippet_gen.py index ec09dcae9f7..55a6c7e3ce5 100644 --- a/hw/ip/otbn/dv/rig/rig/snippet_gen.py +++ b/hw/ip/acc/dv/rig/rig/snippet_gen.py @@ -33,7 +33,7 @@ # A continuation type that allows a generator to recursively generate some more # stuff. If the boolean argument is true, the continuation will try to generate -# a snippet that causes OTBN to stop. In this case, the Snippet term in the +# a snippet that causes ACC to stop. In this case, the Snippet term in the # GensRet will not be None. GenCont = Callable[[Model, Program, bool, bool], GensRet] diff --git a/hw/ip/otbn/dv/rig/rig/snippet_gens.py b/hw/ip/acc/dv/rig/rig/snippet_gens.py similarity index 99% rename from hw/ip/otbn/dv/rig/rig/snippet_gens.py rename to hw/ip/acc/dv/rig/rig/snippet_gens.py index 6d56ca6aa8b..edcaf798c09 100644 --- a/hw/ip/otbn/dv/rig/rig/snippet_gens.py +++ b/hw/ip/acc/dv/rig/rig/snippet_gens.py @@ -269,7 +269,7 @@ def gens(self, This will try to run down model.fuel and program.size. When it runs out of one or the other, it stops and returns any snippet it generated plus the updated model. If end is true, the generated snippet should cause - OTBN to stop. + ACC to stop. ''' snippets, next_model = self._gens(model, program, start, end) diff --git a/hw/ip/otbn/dv/smoke_pqc/BUILD b/hw/ip/acc/dv/smoke/BUILD similarity index 87% rename from hw/ip/otbn/dv/smoke_pqc/BUILD rename to hw/ip/acc/dv/smoke/BUILD index f4756eac94b..7712427353e 100644 --- a/hw/ip/otbn/dv/smoke_pqc/BUILD +++ b/hw/ip/acc/dv/smoke/BUILD @@ -2,11 +2,11 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_binary") +load("//rules:acc.bzl", "acc_binary") package(default_visibility = ["//visibility:public"]) -otbn_binary( +acc_binary( name = "smoke_test", srcs = [ "smoke_test.s", diff --git a/hw/ip/otbn/dv/smoke/run_smoke.sh b/hw/ip/acc/dv/smoke/run_smoke.sh similarity index 68% rename from hw/ip/otbn/dv/smoke/run_smoke.sh rename to hw/ip/acc/dv/smoke/run_smoke.sh index 311ad9d521b..44d97a8071a 100755 --- a/hw/ip/otbn/dv/smoke/run_smoke.sh +++ b/hw/ip/acc/dv/smoke/run_smoke.sh @@ -3,11 +3,11 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# Runs the OTBN smoke test (builds software, build simulation, runs simulation +# Runs the ACC smoke test (builds software, build simulation, runs simulation # and checks expected output) fail() { - echo >&2 "OTBN SMOKE FAILURE: $*" + echo >&2 "ACC SMOKE FAILURE: $*" exit 1 } @@ -20,21 +20,21 @@ UTIL_DIR="$(readlink -e "$SCRIPT_DIR/../../../../../util")" || \ source "$UTIL_DIR/build_consts.sh" -SMOKE_BIN_DIR=$BIN_DIR/otbn/smoke_test -SMOKE_SRC_DIR=$REPO_TOP/hw/ip/otbn/dv/smoke +SMOKE_BIN_DIR=$BIN_DIR/acc/smoke_test +SMOKE_SRC_DIR=$REPO_TOP/hw/ip/acc/dv/smoke mkdir -p $SMOKE_BIN_DIR -OTBN_UTIL=$REPO_TOP/hw/ip/otbn/util +ACC_UTIL=$REPO_TOP/hw/ip/acc/util -$OTBN_UTIL/otbn_as.py -o $SMOKE_BIN_DIR/smoke_test.o $SMOKE_SRC_DIR/smoke_test.s || \ +$ACC_UTIL/acc_as.py -o $SMOKE_BIN_DIR/smoke_test.o $SMOKE_SRC_DIR/smoke_test.s || \ fail "Failed to assemble smoke_test.s" -$OTBN_UTIL/otbn_ld.py -o $SMOKE_BIN_DIR/smoke.elf $SMOKE_BIN_DIR/smoke_test.o || \ +$ACC_UTIL/acc_ld.py -o $SMOKE_BIN_DIR/smoke.elf $SMOKE_BIN_DIR/smoke_test.o || \ fail "Failed to link smoke_test.o" (cd $REPO_TOP; fusesoc --cores-root=. run --target=sim --setup --build \ - --mapping=lowrisc:prim_generic:all:0.1 lowrisc:ip:otbn_top_sim \ + --mapping=lowrisc:prim_generic:all:0.1 lowrisc:ip:acc_top_sim \ --make_options="-j$(nproc)" || fail "HW Sim build failed") RUN_LOG=`mktemp` @@ -43,7 +43,7 @@ readonly RUN_LOG trap "rm -rf $RUN_LOG" EXIT timeout 5s \ - $REPO_TOP/build/lowrisc_ip_otbn_top_sim_0.1/sim-verilator/Votbn_top_sim \ + $REPO_TOP/build/lowrisc_ip_acc_top_sim_0.1/sim-verilator/Vacc_top_sim \ --load-elf=$SMOKE_BIN_DIR/smoke.elf -t | tee $RUN_LOG if [ $? -eq 124 ]; then @@ -58,7 +58,7 @@ had_diff=0 grep -A 74 "Call Stack:" $RUN_LOG | diff -U3 $SMOKE_SRC_DIR/smoke_expected.txt - || had_diff=1 if [ $had_diff == 0 ]; then - echo "OTBN SMOKE PASS" + echo "ACC SMOKE PASS" else fail "Simulator output does not match expected output" fi diff --git a/hw/ip/otbn/dv/smoke/smoke_expected.txt b/hw/ip/acc/dv/smoke/smoke_expected.txt similarity index 100% rename from hw/ip/otbn/dv/smoke/smoke_expected.txt rename to hw/ip/acc/dv/smoke/smoke_expected.txt diff --git a/hw/ip/otbn/dv/smoke/smoke_test.s b/hw/ip/acc/dv/smoke/smoke_test.s similarity index 99% rename from hw/ip/otbn/dv/smoke/smoke_test.s rename to hw/ip/acc/dv/smoke/smoke_test.s index 4ad17c3190b..ee03756c607 100644 --- a/hw/ip/otbn/dv/smoke/smoke_test.s +++ b/hw/ip/acc/dv/smoke/smoke_test.s @@ -2,7 +2,7 @@ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ /* SPDX-License-Identifier: Apache-2.0 */ -# OTBN Smoke test, runs various instructions which are expected to produce the +# ACC Smoke test, runs various instructions which are expected to produce the # final register state see in smoke_expected.txt .section .text.start diff --git a/hw/ip/otbn/dv/smoke/BUILD b/hw/ip/acc/dv/smoke_pqc/BUILD similarity index 87% rename from hw/ip/otbn/dv/smoke/BUILD rename to hw/ip/acc/dv/smoke_pqc/BUILD index f4756eac94b..7712427353e 100644 --- a/hw/ip/otbn/dv/smoke/BUILD +++ b/hw/ip/acc/dv/smoke_pqc/BUILD @@ -2,11 +2,11 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_binary") +load("//rules:acc.bzl", "acc_binary") package(default_visibility = ["//visibility:public"]) -otbn_binary( +acc_binary( name = "smoke_test", srcs = [ "smoke_test.s", diff --git a/hw/ip/otbn/dv/smoke_pqc/run_smoke.sh b/hw/ip/acc/dv/smoke_pqc/run_smoke.sh similarity index 68% rename from hw/ip/otbn/dv/smoke_pqc/run_smoke.sh rename to hw/ip/acc/dv/smoke_pqc/run_smoke.sh index a416ba140fe..0980dac4750 100755 --- a/hw/ip/otbn/dv/smoke_pqc/run_smoke.sh +++ b/hw/ip/acc/dv/smoke_pqc/run_smoke.sh @@ -4,11 +4,11 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# Runs the OTBN smoke test (builds software, build simulation, runs simulation +# Runs the ACC smoke test (builds software, build simulation, runs simulation # and checks expected output) fail() { - echo >&2 "OTBN SMOKE FAILURE: $*" + echo >&2 "ACC SMOKE FAILURE: $*" exit 1 } @@ -21,21 +21,21 @@ UTIL_DIR="$(readlink -e "$SCRIPT_DIR/../../../../../util")" || \ source "$UTIL_DIR/build_consts.sh" -SMOKE_BIN_DIR=$BIN_DIR/otbn/smoke_test -SMOKE_SRC_DIR=$REPO_TOP/hw/ip/otbn/dv/smoke_pqc +SMOKE_BIN_DIR=$BIN_DIR/acc/smoke_test +SMOKE_SRC_DIR=$REPO_TOP/hw/ip/acc/dv/smoke_pqc mkdir -p $SMOKE_BIN_DIR -OTBN_UTIL=$REPO_TOP/hw/ip/otbn/util +ACC_UTIL=$REPO_TOP/hw/ip/acc/util -$OTBN_UTIL/otbn_as.py -o $SMOKE_BIN_DIR/smoke_test.o $SMOKE_SRC_DIR/smoke_test.s || \ +$ACC_UTIL/acc_as.py -o $SMOKE_BIN_DIR/smoke_test.o $SMOKE_SRC_DIR/smoke_test.s || \ fail "Failed to assemble smoke_test.s" -$OTBN_UTIL/otbn_ld.py -o $SMOKE_BIN_DIR/smoke.elf $SMOKE_BIN_DIR/smoke_test.o || \ +$ACC_UTIL/acc_ld.py -o $SMOKE_BIN_DIR/smoke.elf $SMOKE_BIN_DIR/smoke_test.o || \ fail "Failed to link smoke_test.o" (cd $REPO_TOP; fusesoc --cores-root=. run --target=sim --setup --build \ - --mapping=lowrisc:prim_generic:all:0.1 lowrisc:ip:otbn_top_sim \ + --mapping=lowrisc:prim_generic:all:0.1 lowrisc:ip:acc_top_sim \ --make_options="-j$(nproc)" || fail "HW Sim build failed") RUN_LOG=`mktemp` @@ -44,7 +44,7 @@ readonly RUN_LOG trap "rm -rf $RUN_LOG" EXIT timeout 5s \ - $REPO_TOP/build/lowrisc_ip_otbn_top_sim_0.1/sim-verilator/Votbn_top_sim \ + $REPO_TOP/build/lowrisc_ip_acc_top_sim_0.1/sim-verilator/Vacc_top_sim \ --load-elf=$SMOKE_BIN_DIR/smoke.elf -t | tee $RUN_LOG if [ $? -eq 124 ]; then @@ -59,7 +59,7 @@ had_diff=0 grep -A 74 "Call Stack:" $RUN_LOG | diff -U3 $SMOKE_SRC_DIR/smoke_expected.txt - || had_diff=1 if [ $had_diff == 0 ]; then - echo "OTBN SMOKE PASS" + echo "ACC SMOKE PASS" else fail "Simulator output does not match expected output" fi diff --git a/hw/ip/otbn/dv/smoke_pqc/smoke_expected.txt b/hw/ip/acc/dv/smoke_pqc/smoke_expected.txt similarity index 100% rename from hw/ip/otbn/dv/smoke_pqc/smoke_expected.txt rename to hw/ip/acc/dv/smoke_pqc/smoke_expected.txt diff --git a/hw/ip/otbn/dv/smoke_pqc/smoke_test.s b/hw/ip/acc/dv/smoke_pqc/smoke_test.s similarity index 99% rename from hw/ip/otbn/dv/smoke_pqc/smoke_test.s rename to hw/ip/acc/dv/smoke_pqc/smoke_test.s index 849f6f3dd4a..27d5a6a507e 100644 --- a/hw/ip/otbn/dv/smoke_pqc/smoke_test.s +++ b/hw/ip/acc/dv/smoke_pqc/smoke_test.s @@ -1,13 +1,13 @@ /* Copyright lowRISC contributors (OpenTitan project). */ /* Copyright zeroRISC Inc. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ /* SPDX-License-Identifier: Apache-2.0 */ -# OTBN Smoke test, runs various instructions which are expected to produce the +# ACC Smoke test, runs various instructions which are expected to produce the # final register state see in smoke_expected.txt .section .text.start diff --git a/hw/ip/otbn/dv/tracer/README.md b/hw/ip/acc/dv/tracer/README.md similarity index 86% rename from hw/ip/otbn/dv/tracer/README.md rename to hw/ip/acc/dv/tracer/README.md index 730cf5db087..aef5796d79f 100644 --- a/hw/ip/otbn/dv/tracer/README.md +++ b/hw/ip/acc/dv/tracer/README.md @@ -1,20 +1,20 @@ -# OTBN Tracer +# ACC Tracer -The tracer consists of a module (`otbn_tracer.sv`) and an interface -(`otbn_trace_if.sv`). The interface is responsible for directly probing the +The tracer consists of a module (`acc_tracer.sv`) and an interface +(`acc_trace_if.sv`). The interface is responsible for directly probing the design and implementing any basic tracking logic that is required. The module takes an instance of this interface and uses it to produce trace data. Trace output is provided to the simulation environment by calling the -`accept_otbn_trace_string` function which is imported via DPI (the simulator +`accept_acc_trace_string` function which is imported via DPI (the simulator environment provides its implementation). Each call to -`accept_otbn_trace_string` provides a trace record and a cycle count. There is +`accept_acc_trace_string` provides a trace record and a cycle count. There is at most one call per cycle. Further details are below. -A typical setup would bind an instantiation of `otbn_trace_if` and -`otbn_tracer` into `otbn_core` passing the `otbn_trace_if` instance into the -`otbn_tracer` instance. However this is no need for `otbn_tracer` to be bound -into `otbn_core` provided it is given a `otbn_trace_if` instance. +A typical setup would bind an instantiation of `acc_trace_if` and +`acc_tracer` into `acc_core` passing the `acc_trace_if` instance into the +`acc_tracer` instance. However this is no need for `acc_tracer` to be bound +into `acc_core` provided it is given a `acc_trace_if` instance. ## Trace Format @@ -27,7 +27,7 @@ types for header lines are as follows: - `S`: **Instruction stall**. An instruction is stalled. - `E`: **Instruction execute**. An instruction completed its execution. -- `U`: **Wipe in progress**. OTBN is in the middle of an internal wipe. +- `U`: **Wipe in progress**. ACC is in the middle of an internal wipe. - `V`: **Wipe complete**. An internal wipe has completed. The possible types for body lines are: @@ -47,7 +47,7 @@ should flag these as errors in a suitable way. An instruction execution will be represented by zero or more `S` records, followed by one `E` record that represents the retirement of the instruction. -The secure wipe phase at the end of OTBN's operation will be represented by +The secure wipe phase at the end of ACC's operation will be represented by zero or more `U` records, followed by a final `V` record. Whilst the tracer does not aim to detect bugs, there may be instances where the @@ -118,7 +118,7 @@ Register x26 was read and contained value 0x00000018: ``` Register w24 had value -`0xcccccccc_bbbbbbbb_aaaaaaaa_facefeed_deadbeef_cafed00d_d0beb533_1234abcd` +`0xcccccccc_bbbbbbbb_aaaaaaaa_facefeed_deadbeef_cafed00d_d0beb533_1234abcd` written to it: ``` > w24: 0xcccccccc_bbbbbbbb_aaaaaaaa_facefeed_deadbeef_cafed00d_d0beb533_1234abcd @@ -157,7 +157,7 @@ Address `0x00000004` had value `0xd0beb533` written to it: W [0x00000004]: 0xd0beb533 ``` -In the event of an OTBN bug that produces bad memory masks on writes (where the +In the event of an ACC bug that produces bad memory masks on writes (where the write is neither to a full 256 bits nor a aligned 32-bit chunk), an error line is produced giving the full mask and data ``` @@ -167,6 +167,6 @@ W [0x00000080]: Mask ERR Mask: 0xfffff800_0000ffff_ffffffff_00000000_00000000_00 ## Using with dvsim To use this code, depend on the core file. If you're using dvsim, -you'll also need to include `otbn_tracer_sim_opts.hjson` in your -simulator configuration and add `"{tool}_otbn_tracer_build_opts"` to +you'll also need to include `acc_tracer_sim_opts.hjson` in your +simulator configuration and add `"{tool}_acc_tracer_build_opts"` to the `en_build_modes` variable. diff --git a/hw/ip/otbn/dv/tracer/otbn_tracer.core b/hw/ip/acc/dv/tracer/acc_tracer.core similarity index 52% rename from hw/ip/otbn/dv/tracer/otbn_tracer.core rename to hw/ip/acc/dv/tracer/acc_tracer.core index 40e04830181..d7ed280283c 100644 --- a/hw/ip/otbn/dv/tracer/otbn_tracer.core +++ b/hw/ip/acc/dv/tracer/acc_tracer.core @@ -2,24 +2,24 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:otbn_tracer" -description: "Tracer for OTBN" +name: "lowrisc:ip:acc_tracer" +description: "Tracer for ACC" filesets: files_tracer: depend: - - lowrisc:ip:otbn_pkg + - lowrisc:ip:acc_pkg files: - - cpp/otbn_trace_listener.h: { is_include_file: true, file_type: cppSource } - - cpp/otbn_trace_source.h: { is_include_file: true, file_type: cppSource } - - cpp/otbn_trace_source.cc: { file_type: cppSource } + - cpp/acc_trace_listener.h: { is_include_file: true, file_type: cppSource } + - cpp/acc_trace_source.h: { is_include_file: true, file_type: cppSource } + - cpp/acc_trace_source.cc: { file_type: cppSource } - cpp/log_trace_listener.h: { is_include_file: true, file_type: cppSource } - cpp/log_trace_listener.cc: { file_type: cppSource } - - rtl/otbn_tracer.sv: { file_type: systemVerilogSource } - - rtl/otbn_trace_if.sv: { file_type: systemVerilogSource } + - rtl/acc_tracer.sv: { file_type: systemVerilogSource } + - rtl/acc_trace_if.sv: { file_type: systemVerilogSource } files_verilator_waiver: files: - - lint/otbn_tracer_waivers.vlt + - lint/acc_tracer_waivers.vlt file_type: vlt targets: diff --git a/hw/ip/acc/dv/tracer/acc_tracer_sim_opts.hjson b/hw/ip/acc/dv/tracer/acc_tracer_sim_opts.hjson new file mode 100644 index 00000000000..b6ce7ba99c7 --- /dev/null +++ b/hw/ip/acc/dv/tracer/acc_tracer_sim_opts.hjson @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Additional build-time options needed to compile C++ sources in + // simulators such as VCS and Xcelium for anything that uses + // acc_tracer. + acc_tracer_inc_dir: "{build_dir}/fusesoc-work/src/lowrisc_ip_acc_tracer_0/cpp" + + build_modes: [ + { + name: vcs_acc_tracer_build_opts + build_opts: ["-CFLAGS -I{acc_tracer_inc_dir}"] + } + { + name: xcelium_acc_tracer_build_opts + build_opts: ["-I{acc_tracer_inc_dir}"] + } + { + name: dsim_acc_tracer_build_opts + build_opts: ["-c-opts -I{acc_tracer_inc_dir}"] + } + ] +} diff --git a/hw/ip/otbn/dv/tracer/cpp/otbn_trace_listener.h b/hw/ip/acc/dv/tracer/cpp/acc_trace_listener.h similarity index 63% rename from hw/ip/otbn/dv/tracer/cpp/otbn_trace_listener.h rename to hw/ip/acc/dv/tracer/cpp/acc_trace_listener.h index fad4989c963..f29508fb1a2 100644 --- a/hw/ip/otbn/dv/tracer/cpp/otbn_trace_listener.h +++ b/hw/ip/acc/dv/tracer/cpp/acc_trace_listener.h @@ -2,24 +2,24 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_OTBN_TRACE_LISTENER_H_ -#define OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_OTBN_TRACE_LISTENER_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_ACC_TRACE_LISTENER_H_ +#define OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_ACC_TRACE_LISTENER_H_ #include #include #include /** - * Base class for anything that wants to examine trace output from OTBN. The + * Base class for anything that wants to examine trace output from ACC. The * simulation that hosts the tracer is responsible for setting up listeners and - * routing the DPI `accept_otbn_trace_string` calls to them. + * routing the DPI `accept_acc_trace_string` calls to them. */ -class OtbnTraceListener { +class AccTraceListener { public: /** - * Helper function to split an OTBN trace output up into individual lines. + * Helper function to split an ACC trace output up into individual lines. * - * @param trace Trace output from OTBN + * @param trace Trace output from ACC * @return A vector of lines from the trace */ static std::vector SplitTraceLines(const std::string &trace) { @@ -36,14 +36,14 @@ class OtbnTraceListener { } /** - * Called to process an OTBN trace output, called a maximum of once per cycle + * Called to process an ACC trace output, called a maximum of once per cycle * - * @param trace Trace output from OTBN + * @param trace Trace output from ACC * @param cycle_count The cycle count associated with the trace output */ virtual void AcceptTraceString(const std::string &trace, unsigned int cycle_count) = 0; - virtual ~OtbnTraceListener() {} + virtual ~AccTraceListener() {} }; -#endif // OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_OTBN_TRACE_LISTENER_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_ACC_TRACE_LISTENER_H_ diff --git a/hw/ip/acc/dv/tracer/cpp/acc_trace_source.cc b/hw/ip/acc/dv/tracer/cpp/acc_trace_source.cc new file mode 100644 index 00000000000..01641b0e4bb --- /dev/null +++ b/hw/ip/acc/dv/tracer/cpp/acc_trace_source.cc @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "acc_trace_source.h" + +#include +#include +#include + +static std::unique_ptr trace_source; + +AccTraceSource &AccTraceSource::get() { + if (!trace_source) { + trace_source.reset(new AccTraceSource()); + } + return *trace_source; +} + +void AccTraceSource::AddListener(AccTraceListener *listener) { + listeners_.push_back(listener); +} + +void AccTraceSource::RemoveListener(const AccTraceListener *listener) { + auto it = std::find(listeners_.begin(), listeners_.end(), listener); + assert(it != listeners_.end()); + listeners_.erase(it); +} + +void AccTraceSource::Broadcast(const std::string &trace, unsigned cycle_count) { + for (AccTraceListener *listener : listeners_) { + listener->AcceptTraceString(trace, cycle_count); + } +} + +extern "C" void accept_acc_trace_string(const char *trace, + unsigned int cycle_count) { + assert(trace != nullptr); + AccTraceSource::get().Broadcast(trace, cycle_count); +} diff --git a/hw/ip/otbn/dv/tracer/cpp/otbn_trace_source.h b/hw/ip/acc/dv/tracer/cpp/acc_trace_source.h similarity index 55% rename from hw/ip/otbn/dv/tracer/cpp/otbn_trace_source.h rename to hw/ip/acc/dv/tracer/cpp/acc_trace_source.h index 674b85d8e0c..55b9248dd52 100644 --- a/hw/ip/otbn/dv/tracer/cpp/otbn_trace_source.h +++ b/hw/ip/acc/dv/tracer/cpp/acc_trace_source.h @@ -1,12 +1,12 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_OTBN_TRACE_SOURCE_H_ -#define OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_OTBN_TRACE_SOURCE_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_ACC_TRACE_SOURCE_H_ +#define OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_ACC_TRACE_SOURCE_H_ #include -#include "otbn_trace_listener.h" +#include "acc_trace_listener.h" // A source for simulation trace data. // @@ -14,25 +14,25 @@ // get() or the first trace data that comes back from the simulation. // // The object is in charge of taking trace data from the simulation (which is -// sent by calling the accept_otbn_trace_string DPI function) and passing it +// sent by calling the accept_acc_trace_string DPI function) and passing it // out to registered listeners. -class OtbnTraceSource { +class AccTraceSource { public: - // Get the (singleton) OtbnTraceSource object - static OtbnTraceSource &get(); + // Get the (singleton) AccTraceSource object + static AccTraceSource &get(); // Add a listener to the source - void AddListener(OtbnTraceListener *listener); + void AddListener(AccTraceListener *listener); // Remove a listener from the source - void RemoveListener(const OtbnTraceListener *listener); + void RemoveListener(const AccTraceListener *listener); // Send a trace string to all listeners void Broadcast(const std::string &trace, unsigned cycle_count); private: - std::vector listeners_; + std::vector listeners_; }; -#endif // OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_OTBN_TRACE_SOURCE_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_ACC_TRACE_SOURCE_H_ diff --git a/hw/ip/otbn/dv/tracer/cpp/log_trace_listener.cc b/hw/ip/acc/dv/tracer/cpp/log_trace_listener.cc similarity index 100% rename from hw/ip/otbn/dv/tracer/cpp/log_trace_listener.cc rename to hw/ip/acc/dv/tracer/cpp/log_trace_listener.cc diff --git a/hw/ip/otbn/dv/tracer/cpp/log_trace_listener.h b/hw/ip/acc/dv/tracer/cpp/log_trace_listener.h similarity index 75% rename from hw/ip/otbn/dv/tracer/cpp/log_trace_listener.h rename to hw/ip/acc/dv/tracer/cpp/log_trace_listener.h index b7dcbafa543..c967c009279 100644 --- a/hw/ip/otbn/dv/tracer/cpp/log_trace_listener.h +++ b/hw/ip/acc/dv/tracer/cpp/log_trace_listener.h @@ -2,16 +2,16 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_LOG_TRACE_LISTENER_H_ -#define OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_LOG_TRACE_LISTENER_H_ +#ifndef OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_LOG_TRACE_LISTENER_H_ +#define OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_LOG_TRACE_LISTENER_H_ #include #include -#include "otbn_trace_listener.h" +#include "acc_trace_listener.h" /** - * An OtbnTraceListener that dumps the trace to a log file, with some minimal + * An AccTraceListener that dumps the trace to a log file, with some minimal * pretty printing. * * It examines the first line of any trace output, expecting it to be an 'E' or @@ -23,7 +23,7 @@ * line that gives the cycle count and dumps the rest of the trace indented by * four spaces. */ -class LogTraceListener : public OtbnTraceListener { +class LogTraceListener : public AccTraceListener { private: std::ofstream trace_log; @@ -37,4 +37,4 @@ class LogTraceListener : public OtbnTraceListener { unsigned int cycle_count) override; }; -#endif // OPENTITAN_HW_IP_OTBN_DV_TRACER_CPP_LOG_TRACE_LISTENER_H_ +#endif // OPENTITAN_HW_IP_ACC_DV_TRACER_CPP_LOG_TRACE_LISTENER_H_ diff --git a/hw/ip/acc/dv/tracer/lint/acc_tracer_waivers.vlt b/hw/ip/acc/dv/tracer/lint/acc_tracer_waivers.vlt new file mode 100644 index 00000000000..18387a03a70 --- /dev/null +++ b/hw/ip/acc/dv/tracer/lint/acc_tracer_waivers.vlt @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +lint_off -rule BLKSEQ -file "*/acc_tracer.sv" -match "*Blocking assignments (=) in sequential (flop or latch) block*" + +// Flag ISPR (3) has its own trace signals due to special handling +lint_off -rule UNDRIVEN -file "*/acc_trace_if.sv" -match "*Bits of signal are not driven: 'ispr_*'[3]*" + +lint_off -rule UNUSED -file "*/acc_trace_if.sv" -match "*Bits of signal are not used: 'dmem_addr_o'*" +lint_off -rule UNUSED -file "*/acc_trace_if.sv" -match "*Bits of signal are not used: 'insn_dec_shared'*" +lint_off -rule UNUSED -file "*/acc_trace_if.sv" -match "*Bits of signal are not used: 'insn_dec_bignum'*" +lint_off -rule UNUSED -file "*/acc_trace_if.sv" -match "*Bits of signal are not used: 'alu_bignum_operation'*" diff --git a/hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv b/hw/ip/acc/dv/tracer/rtl/acc_trace_if.sv similarity index 73% rename from hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv rename to hw/ip/acc/dv/tracer/rtl/acc_trace_if.sv index b1b5bd28e3a..66c89b853a7 100644 --- a/hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv +++ b/hw/ip/acc/dv/tracer/rtl/acc_trace_if.sv @@ -1,7 +1,7 @@ // Copyright lowRISC contributors (OpenTitan project). // Copyright zeroRISC Inc. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -10,7 +10,7 @@ `ifndef SYNTHESIS /** - * Interface designed to be bound into otbn_core and extract out signals useful for the tracer. + * Interface designed to be bound into acc_core and extract out signals useful for the tracer. * * The tracer takes an instance of this interface as one of its module ports. The tracer will * examine both inputs to this interface as well as signals created within it. This interface is @@ -20,21 +20,21 @@ * process. Anything that is messy/fiddly should be confined to this file if at all possible so * the tracer itself can be cleanly written. * 2. Aim to provide signals from interface to the tracer with clear consistent naming, this may - * result in situations where this interface simply renames an existing otbn_core signal (by + * result in situations where this interface simply renames an existing acc_core signal (by * bringing it in via an input and then assigning it to an internal signal). - * 3. Hierarchical references can only refer to modules inside otbn_core, not otbn_core itself as - * this requires assuming the instance name of otbn_core (which could vary from environment to + * 3. Hierarchical references can only refer to modules inside acc_core, not acc_core itself as + * this requires assuming the instance name of acc_core (which could vary from environment to * environment). - * 4. To use a signal from the otbn_core module, name it as an input with the name used in - * otbn_core. Whatever binds the interface into otbn_core is responsible for connecting these + * 4. To use a signal from the acc_core module, name it as an input with the name used in + * acc_core. Whatever binds the interface into acc_core is responsible for connecting these * up, e.g. using a wildcard '.*'. */ -interface otbn_trace_if +interface acc_trace_if #( parameter int ImemAddrWidth = 15, parameter int DmemAddrWidth = 15, - parameter bit OtbnPQCEn = otbn_pqc_env_pkg::OtbnPQCEn, - parameter otbn_pkg::regfile_e RegFile = otbn_pkg::RegFileFF + parameter bit AccPQCEn = acc_pqc_env_pkg::AccPQCEn, + parameter acc_pkg::regfile_e RegFile = acc_pkg::RegFileFF )( input logic clk_i, input logic rst_ni, @@ -48,21 +48,21 @@ interface otbn_trace_if input logic rf_base_wr_en, input logic rf_base_wr_commit, - input logic [otbn_pkg::WdrAw-1:0] rf_bignum_rd_addr_a, - input logic [otbn_pkg::WdrAw-1:0] rf_bignum_rd_addr_b, - input logic [otbn_pkg::WdrAw-1:0] rf_bignum_wr_addr, + input logic [acc_pkg::WdrAw-1:0] rf_bignum_rd_addr_a, + input logic [acc_pkg::WdrAw-1:0] rf_bignum_rd_addr_b, + input logic [acc_pkg::WdrAw-1:0] rf_bignum_wr_addr, input logic rf_bignum_rd_en_a, input logic rf_bignum_rd_en_b, input logic [1:0] rf_bignum_wr_en, input logic rf_bignum_wr_commit, - input logic [otbn_pkg::WLEN-1:0] rf_bignum_wr_data_no_intg, - input logic [otbn_pkg::ExtWLEN-1:0] rf_bignum_wr_data_intg, + input logic [acc_pkg::WLEN-1:0] rf_bignum_wr_data_no_intg, + input logic [acc_pkg::ExtWLEN-1:0] rf_bignum_wr_data_intg, input logic rf_bignum_wr_data_intg_sel, - input logic [otbn_pkg::ExtWLEN-1:0] rf_bignum_rd_data_a_intg, - input logic [otbn_pkg::ExtWLEN-1:0] rf_bignum_rd_data_b_intg, + input logic [acc_pkg::ExtWLEN-1:0] rf_bignum_rd_data_a_intg, + input logic [acc_pkg::ExtWLEN-1:0] rf_bignum_rd_data_b_intg, input logic [31:0] insn_fetch_resp_data, input logic [ImemAddrWidth-1:0] insn_fetch_resp_addr, @@ -72,24 +72,24 @@ interface otbn_trace_if input logic dmem_req_o, input logic dmem_write_o, input logic [DmemAddrWidth-1:0] dmem_addr_o, - input logic [otbn_pkg::ExtWLEN-1:0] dmem_wdata_o, - input logic [otbn_pkg::ExtWLEN-1:0] dmem_wmask_o, - input logic [otbn_pkg::ExtWLEN-1:0] dmem_rdata_i, + input logic [acc_pkg::ExtWLEN-1:0] dmem_wdata_o, + input logic [acc_pkg::ExtWLEN-1:0] dmem_wmask_o, + input logic [acc_pkg::ExtWLEN-1:0] dmem_rdata_i, - input otbn_pkg::ispr_e ispr_addr, + input acc_pkg::ispr_e ispr_addr, input logic ispr_init, - input otbn_pkg::insn_dec_shared_t insn_dec_shared, - input otbn_pkg::insn_dec_bignum_t insn_dec_bignum, - input otbn_pkg::alu_bignum_operation_t alu_bignum_operation, + input acc_pkg::insn_dec_shared_t insn_dec_shared, + input acc_pkg::insn_dec_bignum_t insn_dec_bignum, + input acc_pkg::alu_bignum_operation_t alu_bignum_operation, input logic mac_bignum_en, - input logic [otbn_pkg::WLEN-1:0] rnd_data, + input logic [acc_pkg::WLEN-1:0] rnd_data, input logic rnd_req, input logic rnd_valid, - input logic [otbn_pkg::WLEN-1:0] urnd_data, + input logic [acc_pkg::WLEN-1:0] urnd_data, - input logic [1:0][otbn_pkg::SideloadKeyWidth-1:0] sideload_key_shares_i, + input logic [1:0][acc_pkg::SideloadKeyWidth-1:0] sideload_key_shares_i, input logic secure_wipe_req, input logic secure_wipe_ack, @@ -112,13 +112,13 @@ interface otbn_trace_if input logic alu_bignum_reg_intg_violation_err, input logic mac_bignum_reg_intg_violation_err ); - import otbn_pkg::*; + import acc_pkg::*; import prim_mubi_pkg::*; localparam int DmemSubWordAddrWidth = prim_util_pkg::vbits(WLEN/8); // `insn_stall` isn't a signal that exists in the design so needs creating here. To keep things - // consistent `insn_X` signals are provided here that are simply assigned to `otbn_core` signals. + // consistent `insn_X` signals are provided here that are simply assigned to `acc_core` signals. // To prevent the tracer needing to deal with differing Imem sizes the address is padded out to // 32-bits. logic insn_valid; @@ -129,7 +129,7 @@ interface otbn_trace_if assign insn_valid = insn_fetch_resp_valid; assign insn_addr = {{(32-ImemAddrWidth){1'b0}}, insn_fetch_resp_addr}; assign insn_data = insn_fetch_resp_data; - assign insn_stall = u_otbn_core.u_otbn_controller.state_d == OtbnStateStall; + assign insn_stall = u_acc_core.u_acc_controller.state_d == AccStateStall; logic [31:0] rf_base_rd_data_a; logic [31:0] rf_base_rd_data_b; @@ -138,12 +138,12 @@ interface otbn_trace_if logic [WLEN-1:0] rf_bignum_rd_data_a; logic [WLEN-1:0] rf_bignum_rd_data_b; - assign rf_base_rd_data_a = u_otbn_controller.rf_base_rd_data_a_no_intg; - assign rf_base_rd_data_b = u_otbn_controller.rf_base_rd_data_b_no_intg; - assign rf_base_wr_data = u_otbn_rf_base.wr_data_intg_mux_out[31:0]; + assign rf_base_rd_data_a = u_acc_controller.rf_base_rd_data_a_no_intg; + assign rf_base_rd_data_b = u_acc_controller.rf_base_rd_data_b_no_intg; + assign rf_base_wr_data = u_acc_rf_base.wr_data_intg_mux_out[31:0]; - assign rf_bignum_rd_data_a = u_otbn_controller.rf_bignum_rd_data_a_no_intg; - assign rf_bignum_rd_data_b = u_otbn_controller.rf_bignum_rd_data_b_no_intg; + assign rf_bignum_rd_data_a = u_acc_controller.rf_bignum_rd_data_a_no_intg; + assign rf_bignum_rd_data_b = u_acc_controller.rf_bignum_rd_data_b_no_intg; // The bignum register file is capable of half register writes. To avoid the tracer having to deal // with this, it should just OR together the bits of rf_bignum_wr_en to get a single "there was a @@ -162,9 +162,9 @@ interface otbn_trace_if for (genvar i = 0; i < NWdr; ++i) begin : g_probe_bignum_rf if (RegFile == RegFileFF) begin : g_rf_ff_probe - assign bignum_rf[i] = u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf[i]; + assign bignum_rf[i] = u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf[i]; end else if (RegFile == RegFileFPGA) begin : g_rf_fpga_probe - assign bignum_rf[i] = u_otbn_rf_bignum.gen_rf_bignum_fpga.u_otbn_rf_bignum_inner.rf[i]; + assign bignum_rf[i] = u_acc_rf_bignum.gen_rf_bignum_fpga.u_acc_rf_bignum_inner.rf[i]; end end @@ -260,29 +260,29 @@ interface otbn_trace_if (insn_dec_shared.ispr_rd_insn | insn_dec_shared.ispr_rs_insn) & insn_fetch_resp_valid; - assign ispr_write[IsprMod] = |u_otbn_alu_bignum.mod_wr_en & ~ispr_init; + assign ispr_write[IsprMod] = |u_acc_alu_bignum.mod_wr_en & ~ispr_init; generate - if (OtbnPQCEn) begin : gen_ispr_data_pqc + if (AccPQCEn) begin : gen_ispr_data_pqc for (genvar i_word = 0; i_word < BaseWordsPerWLEN; i_word++) begin : g_mod_and_acc_words assign ispr_write_data[IsprMod][i_word*32+:32] = - u_otbn_alu_bignum.mod_wr_en[i_word] ? u_otbn_alu_bignum.mod_intg_d[i_word*39+:32] : - u_otbn_alu_bignum.mod_intg_q[i_word*39+:32]; - assign ispr_read_data[IsprMod][i_word*32+:32] = u_otbn_alu_bignum.mod_intg_q[i_word*39+:32]; - assign ispr_write_data[IsprAcc][i_word*32+:32] = u_otbn_mac_bignum.acc_intg_d[i_word*39+:32]; + u_acc_alu_bignum.mod_wr_en[i_word] ? u_acc_alu_bignum.mod_intg_d[i_word*39+:32] : + u_acc_alu_bignum.mod_intg_q[i_word*39+:32]; + assign ispr_read_data[IsprMod][i_word*32+:32] = u_acc_alu_bignum.mod_intg_q[i_word*39+:32]; + assign ispr_write_data[IsprAcc][i_word*32+:32] = u_acc_mac_bignum.acc_intg_d[i_word*39+:32]; assign ispr_write_data[IsprKmacMsg][i_word*32+:32] = - u_otbn_alu_bignum.gen_pqc_wsr.kmac_msg_wr_en[i_word] ? u_otbn_alu_bignum.gen_pqc_wsr.kmac_msg_intg_d[i_word*39+:32] : - u_otbn_alu_bignum.gen_pqc_wsr.kmac_msg_intg_q[i_word*39+:32]; - assign ispr_read_data[IsprKmacMsg][i_word*32+:32] = u_otbn_alu_bignum.gen_pqc_wsr.kmac_msg_intg_q[i_word*39+:32]; - assign ispr_write_data[IsprAccH][i_word*32+:32] = u_otbn_mac_bignum.gen_acch_wr_en.acch_intg_d[i_word*39+:32]; + u_acc_alu_bignum.gen_pqc_wsr.kmac_msg_wr_en[i_word] ? u_acc_alu_bignum.gen_pqc_wsr.kmac_msg_intg_d[i_word*39+:32] : + u_acc_alu_bignum.gen_pqc_wsr.kmac_msg_intg_q[i_word*39+:32]; + assign ispr_read_data[IsprKmacMsg][i_word*32+:32] = u_acc_alu_bignum.gen_pqc_wsr.kmac_msg_intg_q[i_word*39+:32]; + assign ispr_write_data[IsprAccH][i_word*32+:32] = u_acc_mac_bignum.gen_acch_wr_en.acch_intg_d[i_word*39+:32]; end end else begin : gen_ispr_data for (genvar i_word = 0; i_word < BaseWordsPerWLEN; i_word++) begin : g_mod_and_acc_words assign ispr_write_data[IsprMod][i_word*32+:32] = - u_otbn_alu_bignum.mod_wr_en[i_word] ? u_otbn_alu_bignum.mod_intg_d[i_word*39+:32] : - u_otbn_alu_bignum.mod_intg_q[i_word*39+:32]; - assign ispr_read_data[IsprMod][i_word*32+:32] = u_otbn_alu_bignum.mod_intg_q[i_word*39+:32]; - assign ispr_write_data[IsprAcc][i_word*32+:32] = u_otbn_mac_bignum.acc_intg_d[i_word*39+:32]; + u_acc_alu_bignum.mod_wr_en[i_word] ? u_acc_alu_bignum.mod_intg_d[i_word*39+:32] : + u_acc_alu_bignum.mod_intg_q[i_word*39+:32]; + assign ispr_read_data[IsprMod][i_word*32+:32] = u_acc_alu_bignum.mod_intg_q[i_word*39+:32]; + assign ispr_write_data[IsprAcc][i_word*32+:32] = u_acc_mac_bignum.acc_intg_d[i_word*39+:32]; assign ispr_write_data[IsprKmacMsg][i_word*32+:32] = 32'b0; assign ispr_read_data[IsprKmacMsg][i_word*32+:32] = 32'b0; assign ispr_write_data[IsprAccH][i_word*32+:32] = 32'b0; @@ -296,29 +296,29 @@ interface otbn_trace_if (alu_bignum_operation.op inside {AluOpBignumAddm, AluOpBignumSubm})); generate - if (OtbnPQCEn) begin : gen_ispr_read_write_pqc + if (AccPQCEn) begin : gen_ispr_read_write_pqc // KMAC MSG assign ispr_read[IsprKmacMsg] = (any_ispr_read & (ispr_addr == IsprKmacMsg)); - assign ispr_write[IsprKmacMsg] = u_otbn_alu_bignum.gen_pqc_wsr.kmac_msg_wr_en & ~ispr_init; + assign ispr_write[IsprKmacMsg] = u_acc_alu_bignum.gen_pqc_wsr.kmac_msg_wr_en & ~ispr_init; // KMAC CFG assign ispr_read[IsprKmacCfg] = (any_ispr_read & (ispr_addr == IsprKmacCfg)); - assign ispr_read_data[IsprKmacCfg] = {224'b0, u_otbn_alu_bignum.gen_pqc_wsr.kmac_cfg_intg_q[31:0]}; - assign ispr_write[IsprKmacCfg] = u_otbn_alu_bignum.gen_pqc_wsr.kmac_cfg_wr_en & ~ispr_init; - assign ispr_write_data[IsprKmacCfg] = {224'b0, u_otbn_alu_bignum.gen_pqc_wsr.kmac_cfg_intg_d[31:0]}; + assign ispr_read_data[IsprKmacCfg] = {224'b0, u_acc_alu_bignum.gen_pqc_wsr.kmac_cfg_intg_q[31:0]}; + assign ispr_write[IsprKmacCfg] = u_acc_alu_bignum.gen_pqc_wsr.kmac_cfg_wr_en & ~ispr_init; + assign ispr_write_data[IsprKmacCfg] = {224'b0, u_acc_alu_bignum.gen_pqc_wsr.kmac_cfg_intg_d[31:0]}; // KMAC PARTIAL WRITE assign ispr_read[IsprKmacPartialW] = (any_ispr_read & (ispr_addr == IsprKmacPartialW)); - assign ispr_read_data[IsprKmacPartialW] = {224'b0, u_otbn_alu_bignum.gen_pqc_wsr.kmac_pw_intg_q[31:0]}; - assign ispr_write[IsprKmacPartialW] = u_otbn_alu_bignum.gen_pqc_wsr.kmac_pw_wr_en & ~ispr_init; - assign ispr_write_data[IsprKmacPartialW] = {224'b0, u_otbn_alu_bignum.gen_pqc_wsr.kmac_pw_intg_d[31:0]}; + assign ispr_read_data[IsprKmacPartialW] = {224'b0, u_acc_alu_bignum.gen_pqc_wsr.kmac_pw_intg_q[31:0]}; + assign ispr_write[IsprKmacPartialW] = u_acc_alu_bignum.gen_pqc_wsr.kmac_pw_wr_en & ~ispr_init; + assign ispr_write_data[IsprKmacPartialW] = {224'b0, u_acc_alu_bignum.gen_pqc_wsr.kmac_pw_intg_d[31:0]}; // ACCH - assign ispr_write[IsprAccH] = u_otbn_mac_bignum.gen_acch_wr_en.acch_en & ~ispr_init; + assign ispr_write[IsprAccH] = u_acc_mac_bignum.gen_acch_wr_en.acch_en & ~ispr_init; assign ispr_read[IsprAccH] = (any_ispr_read & (ispr_addr == IsprAccH)) | mac_bignum_en; assign ispr_read_data[IsprAccH] = - (any_ispr_read & (ispr_addr == IsprAccH)) ? u_otbn_mac_bignum.gen_acch_reg.acch_no_intg_q : - u_otbn_mac_bignum.gen_acch_blanker.acch_blanked; + (any_ispr_read & (ispr_addr == IsprAccH)) ? u_acc_mac_bignum.gen_acch_reg.acch_no_intg_q : + u_acc_mac_bignum.gen_acch_blanker.acch_blanked; end else begin : gen_ispr_read_write_blank // Need to drive unused signals for verilator linting // KMAC MSG @@ -352,14 +352,14 @@ interface otbn_trace_if endgenerate // ACC - assign ispr_write[IsprAcc] = u_otbn_mac_bignum.acc_en & ~ispr_init; + assign ispr_write[IsprAcc] = u_acc_mac_bignum.acc_en & ~ispr_init; assign ispr_read[IsprAcc] = (any_ispr_read & (ispr_addr == IsprAcc)) | mac_bignum_en; // For ISPR reads look at the ACC flops directly. For other ACC reads look at the `acc_blanked` // signal in order to read ACC as 0 for the BN.MULQACC.Z instruction variant. assign ispr_read_data[IsprAcc] = - (any_ispr_read & (ispr_addr == IsprAcc)) ? u_otbn_mac_bignum.acc_no_intg_q : - u_otbn_mac_bignum.acc_blanked; + (any_ispr_read & (ispr_addr == IsprAcc)) ? u_acc_mac_bignum.acc_no_intg_q : + u_acc_mac_bignum.acc_blanked; assign ispr_write[IsprRnd] = 1'b0; assign ispr_write_data[IsprRnd] = '0; @@ -412,17 +412,17 @@ interface otbn_trace_if for (genvar i_fg = 0; i_fg < NFlagGroups; i_fg++) begin : g_flag_group_acceses assign flags_write[i_fg] = (sec_wipe_zero | - ((u_otbn_alu_bignum.alu_predec_bignum_i.flags_adder_update[i_fg] | - u_otbn_alu_bignum.alu_predec_bignum_i.flags_logic_update[i_fg] | - u_otbn_alu_bignum.alu_predec_bignum_i.flags_mac_update[i_fg] | - (|u_otbn_alu_bignum.alu_predec_bignum_i.flags_ispr_wr)) & - u_otbn_alu_bignum.operation_commit_i)) & ~ispr_init; - assign flags_write_data[i_fg] = u_otbn_alu_bignum.flags_d[i_fg]; + ((u_acc_alu_bignum.alu_predec_bignum_i.flags_adder_update[i_fg] | + u_acc_alu_bignum.alu_predec_bignum_i.flags_logic_update[i_fg] | + u_acc_alu_bignum.alu_predec_bignum_i.flags_mac_update[i_fg] | + (|u_acc_alu_bignum.alu_predec_bignum_i.flags_ispr_wr)) & + u_acc_alu_bignum.operation_commit_i)) & ~ispr_init; + assign flags_write_data[i_fg] = u_acc_alu_bignum.flags_d[i_fg]; assign flags_read[i_fg] = (any_ispr_read & (ispr_addr == IsprFlags)) | (flag_group_read_op & (alu_bignum_operation.flag_group == i_fg) & insn_fetch_resp_valid); - assign flags_read_data[i_fg] = u_otbn_alu_bignum.flags_q[i_fg]; + assign flags_read_data[i_fg] = u_acc_alu_bignum.flags_q[i_fg]; end logic initial_secure_wipe_done; @@ -513,41 +513,41 @@ interface otbn_trace_if assign predec_err_i.rf_err = rf_bignum_predec_error; assign predec_err_i.rd_err = rd_predec_error; - assign start_stop_bad_int_i.state_err = u_otbn_start_stop_control.state_error_d; - assign start_stop_bad_int_i.spr_urnd_acks = u_otbn_rnd.edn_urnd_ack_i && - (!u_otbn_rnd.edn_urnd_req_o); - assign start_stop_bad_int_i.spr_rnd_acks = u_otbn_rnd.edn_rnd_ack_i && - (!u_otbn_rnd.edn_rnd_req_o); - assign start_stop_bad_int_i.spr_secwipe_reqs = u_otbn_start_stop_control.secure_wipe_error_q; + assign start_stop_bad_int_i.state_err = u_acc_start_stop_control.state_error_d; + assign start_stop_bad_int_i.spr_urnd_acks = u_acc_rnd.edn_urnd_ack_i && + (!u_acc_rnd.edn_urnd_req_o); + assign start_stop_bad_int_i.spr_rnd_acks = u_acc_rnd.edn_rnd_ack_i && + (!u_acc_rnd.edn_rnd_req_o); + assign start_stop_bad_int_i.spr_secwipe_reqs = u_acc_start_stop_control.secure_wipe_error_q; - assign start_stop_bad_int_i.mubi_rma_err = u_otbn_start_stop_control.mubi_err_d && - prim_mubi_pkg::mubi4_test_invalid(u_otbn_start_stop_control.rma_ack_q); - assign start_stop_bad_int_i.mubi_urnd_err = u_otbn_start_stop_control.mubi_err_d && - prim_mubi_pkg::mubi4_test_invalid(u_otbn_start_stop_control.wipe_after_urnd_refresh_q); + assign start_stop_bad_int_i.mubi_rma_err = u_acc_start_stop_control.mubi_err_d && + prim_mubi_pkg::mubi4_test_invalid(u_acc_start_stop_control.rma_ack_q); + assign start_stop_bad_int_i.mubi_urnd_err = u_acc_start_stop_control.mubi_err_d && + prim_mubi_pkg::mubi4_test_invalid(u_acc_start_stop_control.wipe_after_urnd_refresh_q); assign controller_bad_int_i.loop_hw_cnt_err = - (|u_otbn_controller.u_otbn_loop_controller.loop_counter_err); + (|u_acc_controller.u_acc_loop_controller.loop_counter_err); assign controller_bad_int_i.loop_hw_stack_cnt_err = - u_otbn_controller.u_otbn_loop_controller.loop_stack_cnt_err; + u_acc_controller.u_acc_loop_controller.loop_stack_cnt_err; assign controller_bad_int_i.loop_hw_intg_err = - ((|u_otbn_controller.u_otbn_loop_controller.current_loop_intg_err) && - u_otbn_controller.u_otbn_loop_controller.current_loop_valid); + ((|u_acc_controller.u_acc_loop_controller.current_loop_intg_err) && + u_acc_controller.u_acc_loop_controller.current_loop_valid); assign controller_bad_int_i.rf_base_call_stack_err = - u_otbn_controller.rf_base_call_stack_hw_err_i; - assign controller_bad_int_i.spr_secwipe_acks = u_otbn_controller.spurious_secure_wipe_ack_q; - assign controller_bad_int_i.state_err = u_otbn_controller.state_error; - assign controller_bad_int_i.controller_mubi_err = u_otbn_controller.mubi_err_q; + u_acc_controller.rf_base_call_stack_hw_err_i; + assign controller_bad_int_i.spr_secwipe_acks = u_acc_controller.spurious_secure_wipe_ack_q; + assign controller_bad_int_i.state_err = u_acc_controller.state_error; + assign controller_bad_int_i.controller_mubi_err = u_acc_controller.mubi_err_q; // Probe Start Stop Control module FSM to inject escalate signals in specific states. - otbn_start_stop_state_e otbn_start_stop_state; + acc_start_stop_state_e acc_start_stop_state; // Use this to mute Verilator unused errors. - otbn_start_stop_state_e unused_start_stop_state; + acc_start_stop_state_e unused_start_stop_state; - assign otbn_start_stop_state = u_otbn_start_stop_control.state_q; - assign unused_start_stop_state = otbn_start_stop_state; + assign acc_start_stop_state = u_acc_start_stop_control.state_q; + assign unused_start_stop_state = acc_start_stop_state; // Only define force/release functions if we're not running Verilator. This is because the version // we currently use does not support force/release. @@ -556,27 +556,27 @@ interface otbn_trace_if // Force the `rd_data_a_intg_o` signal to `should_val`. This function needs to be static because // its argument must live as least as long as the `force` statement is in effect. function static void force_rf_bignum_rd_data_a_intg( - input logic [otbn_pkg::ExtWLEN-1:0] should_val + input logic [acc_pkg::ExtWLEN-1:0] should_val ); - force u_otbn_rf_bignum.rd_data_a_intg_o = should_val; + force u_acc_rf_bignum.rd_data_a_intg_o = should_val; endfunction // Force the `rd_data_b_intg_o` signal to `should_val`. This function needs to be static because // its argument must live as least as long as the `force` statement is in effect. function static void force_rf_bignum_rd_data_b_intg( - input logic [otbn_pkg::ExtWLEN-1:0] should_val + input logic [acc_pkg::ExtWLEN-1:0] should_val ); - force u_otbn_rf_bignum.rd_data_b_intg_o = should_val; + force u_acc_rf_bignum.rd_data_b_intg_o = should_val; endfunction // Release the forcing of the `rd_data_a_intg_o` signal. function automatic void release_rf_bignum_rd_data_a_intg(); - release u_otbn_rf_bignum.rd_data_a_intg_o; + release u_acc_rf_bignum.rd_data_a_intg_o; endfunction // Release the forcing of the `rd_data_b_intg_o` signal. function automatic void release_rf_bignum_rd_data_b_intg(); - release u_otbn_rf_bignum.rd_data_b_intg_o; + release u_acc_rf_bignum.rd_data_b_intg_o; endfunction `endif // VERILATOR diff --git a/hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv b/hw/ip/acc/dv/tracer/rtl/acc_tracer.sv similarity index 62% rename from hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv rename to hw/ip/acc/dv/tracer/rtl/acc_tracer.sv index 02d8d8f7822..4f1c5ce46ed 100644 --- a/hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv +++ b/hw/ip/acc/dv/tracer/rtl/acc_tracer.sv @@ -1,7 +1,7 @@ // Copyright lowRISC contributors (OpenTitan project). // Copyright zeroRISC Inc. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -10,21 +10,21 @@ `ifndef SYNTHESIS /** - * Tracer module for OTBN. This produces a multi-line string as trace output at most once every - * cycle and provides it to the simulation environment via a DPI call. It uses `otbn_trace_if` to - * get the information it needs. For further information see `hw/ip/otbn/dv/tracer/README.md`. + * Tracer module for ACC. This produces a multi-line string as trace output at most once every + * cycle and provides it to the simulation environment via a DPI call. It uses `acc_trace_if` to + * get the information it needs. For further information see `hw/ip/acc/dv/tracer/README.md`. */ -module otbn_tracer #( - parameter bit OtbnPQCEn = otbn_pqc_env_pkg::OtbnPQCEn +module acc_tracer #( + parameter bit AccPQCEn = acc_pqc_env_pkg::AccPQCEn ) ( input logic clk_i, input logic rst_ni, - otbn_trace_if otbn_trace + acc_trace_if acc_trace ); - import otbn_pkg::*; + import acc_pkg::*; - // Prefixes used in trace lines. Formats are documented in `hw/ip/otbn/dv/tracer/README.md` + // Prefixes used in trace lines. Formats are documented in `hw/ip/acc/dv/tracer/README.md` parameter string InsnExecutePrefix = "E"; parameter string InsnStallPrefix = "S"; parameter string WipeInProgressPrefix = "U"; @@ -39,10 +39,10 @@ module otbn_tracer #( // Given a WLEN size word output a hex string with the data split into 32-bit chunks separated // with '_'. WLEN must be a multiple of 32. - function automatic string otbn_wlen_data_str(logic [WLEN-1:0] data); + function automatic string acc_wlen_data_str(logic [WLEN-1:0] data); string data_str; - assert ((WLEN % 32) == 0) else $error("WLEN must be a multiple of 32 in otbn_wlen_data_str"); + assert ((WLEN % 32) == 0) else $error("WLEN must be a multiple of 32 in acc_wlen_data_str"); for (int i = WLEN; i > 0; i-= 32) begin if (i != WLEN) begin @@ -60,7 +60,7 @@ module otbn_tracer #( // Produce trace output string for dmem writes. For a 256-bit write, the address and full data is // output. For 32-bit writes (determined by looking at the mask) only the relevant 32-bit chunk is // output along with the address modified so it refers to that chunk. - function automatic string otbn_dmem_write_str(logic [31:0] addr, + function automatic string acc_dmem_write_str(logic [31:0] addr, logic [WLEN-1:0] data, logic [WLEN-1:0] wmask); @@ -68,7 +68,7 @@ module otbn_tracer #( // For a full WLEN write output all of the data. if (wmask == '1) begin - return $sformatf("[0x%08x]: %s", addr, otbn_wlen_data_str(data)); + return $sformatf("[0x%08x]: %s", addr, acc_wlen_data_str(data)); end // Iterate through the possible 32-bit chunks @@ -85,32 +85,32 @@ module otbn_tracer #( // Fallback where mask isn't as expected, indicate ERR in the trace and provide both full mask // and data. - return $sformatf("[0x%08x]: Mask ERR Mask: %s Data: %s", addr, otbn_wlen_data_str(wmask), - otbn_wlen_data_str(data)); + return $sformatf("[0x%08x]: Mask ERR Mask: %s Data: %s", addr, acc_wlen_data_str(wmask), + acc_wlen_data_str(data)); endfunction // Determine name for an ISPR - function automatic string otbn_ispr_name_str(ispr_e ispr); + function automatic string acc_ispr_name_str(ispr_e ispr); unique case (ispr) IsprMod: return "MOD"; IsprAcc: return "ACC"; IsprAccH: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin return "ACCH"; end end IsprKmacMsg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin return "KMAC_MSG"; end end IsprKmacCfg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin return "KMAC_CFG"; end end IsprKmacPartialW: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin return "KMAC_PARTIAL_WRITE"; end end @@ -122,7 +122,7 @@ module otbn_tracer #( endfunction // Format flag information into a string - function automatic string otbn_flags_str(flags_t f); + function automatic string acc_flags_str(flags_t f); return $sformatf("{C: %d, M: %d, L: %d, Z: %d}", f.C, f.M, f.L, f.Z); endfunction @@ -137,62 +137,62 @@ module otbn_tracer #( endfunction function automatic string trace_base_rf(string work); - if (otbn_trace.rf_base_rd_en_a) begin + if (acc_trace.rf_base_rd_en_a) begin work = output_trace(work, RegReadPrefix, - $sformatf("x%02d: 0x%08x", otbn_trace.rf_base_rd_addr_a, - otbn_trace.rf_base_rd_data_a)); + $sformatf("x%02d: 0x%08x", acc_trace.rf_base_rd_addr_a, + acc_trace.rf_base_rd_data_a)); end - if (otbn_trace.rf_base_rd_en_b) begin + if (acc_trace.rf_base_rd_en_b) begin work = output_trace(work, RegReadPrefix, - $sformatf("x%02d: 0x%08x", otbn_trace.rf_base_rd_addr_b, - otbn_trace.rf_base_rd_data_b)); + $sformatf("x%02d: 0x%08x", acc_trace.rf_base_rd_addr_b, + acc_trace.rf_base_rd_data_b)); end - if (|otbn_trace.rf_base_wr_en && otbn_trace.rf_base_wr_commit && - otbn_trace.rf_base_wr_addr != '0) begin + if (|acc_trace.rf_base_wr_en && acc_trace.rf_base_wr_commit && + acc_trace.rf_base_wr_addr != '0) begin work = output_trace(work, RegWritePrefix, - $sformatf("x%02d: 0x%08x", otbn_trace.rf_base_wr_addr, - otbn_trace.rf_base_wr_data)); + $sformatf("x%02d: 0x%08x", acc_trace.rf_base_wr_addr, + acc_trace.rf_base_wr_data)); end return work; endfunction function automatic string trace_bignum_rf(string work); - if (otbn_trace.rf_bignum_rd_en_a) begin + if (acc_trace.rf_bignum_rd_en_a) begin work = output_trace(work, RegReadPrefix, - $sformatf("w%02d: %s", otbn_trace.rf_bignum_rd_addr_a, - otbn_wlen_data_str(otbn_trace.rf_bignum_rd_data_a))); + $sformatf("w%02d: %s", acc_trace.rf_bignum_rd_addr_a, + acc_wlen_data_str(acc_trace.rf_bignum_rd_data_a))); end - if (otbn_trace.rf_bignum_rd_en_b) begin + if (acc_trace.rf_bignum_rd_en_b) begin work = output_trace(work, RegReadPrefix, - $sformatf("w%02d: %s", otbn_trace.rf_bignum_rd_addr_b, - otbn_wlen_data_str(otbn_trace.rf_bignum_rd_data_b))); + $sformatf("w%02d: %s", acc_trace.rf_bignum_rd_addr_b, + acc_wlen_data_str(acc_trace.rf_bignum_rd_data_b))); end - if (|otbn_trace.rf_bignum_wr_en & otbn_trace.rf_bignum_wr_commit) begin + if (|acc_trace.rf_bignum_wr_en & acc_trace.rf_bignum_wr_commit) begin work = output_trace(work, RegWritePrefix, - $sformatf("w%02d: %s", otbn_trace.rf_bignum_wr_addr, - otbn_wlen_data_str(otbn_trace.rf_bignum_wr_data))); + $sformatf("w%02d: %s", acc_trace.rf_bignum_wr_addr, + acc_wlen_data_str(acc_trace.rf_bignum_wr_data))); end return work; endfunction function automatic string trace_bignum_mem(string work); - if (otbn_trace.dmem_write) begin + if (acc_trace.dmem_write) begin work = output_trace(work, MemWritePrefix, - otbn_dmem_write_str(otbn_trace.dmem_write_addr, - otbn_trace.dmem_write_data, - otbn_trace.dmem_write_mask)); + acc_dmem_write_str(acc_trace.dmem_write_addr, + acc_trace.dmem_write_data, + acc_trace.dmem_write_mask)); end - if (otbn_trace.dmem_read) begin + if (acc_trace.dmem_read) begin work = output_trace(work, MemReadPrefix, - $sformatf("[0x%08x]: %s", otbn_trace.dmem_read_addr, - otbn_wlen_data_str(otbn_trace.dmem_read_data))); + $sformatf("[0x%08x]: %s", acc_trace.dmem_read_addr, + acc_wlen_data_str(acc_trace.dmem_read_data))); end return work; @@ -204,30 +204,30 @@ module otbn_tracer #( if (ispr_e'(i_ispr) == IsprFlags) begin // Special handling for flags ISPR to provide per flag field output for (int i_fg = 0; i_fg < NFlagGroups; i_fg++) begin - if (otbn_trace.flags_read[i_fg]) begin + if (acc_trace.flags_read[i_fg]) begin work = output_trace(work, RegReadPrefix, - $sformatf("%s%1d: %s", otbn_ispr_name_str(ispr_e'(i_ispr)), i_fg, - otbn_flags_str(otbn_trace.flags_read_data[i_fg]))); + $sformatf("%s%1d: %s", acc_ispr_name_str(ispr_e'(i_ispr)), i_fg, + acc_flags_str(acc_trace.flags_read_data[i_fg]))); end - if (otbn_trace.flags_write[i_fg]) begin + if (acc_trace.flags_write[i_fg]) begin work = output_trace(work, RegWritePrefix, - $sformatf("%s%1d: %s", otbn_ispr_name_str(ispr_e'(i_ispr)), i_fg, - otbn_flags_str(otbn_trace.flags_write_data[i_fg]))); + $sformatf("%s%1d: %s", acc_ispr_name_str(ispr_e'(i_ispr)), i_fg, + acc_flags_str(acc_trace.flags_write_data[i_fg]))); end end end else begin // For all other ISPRs just dump out the full 256-bits of data being read/written - if (otbn_trace.ispr_read[i_ispr]) begin + if (acc_trace.ispr_read[i_ispr]) begin work = output_trace(work, RegReadPrefix, - $sformatf("%s: %s", otbn_ispr_name_str(ispr_e'(i_ispr)), - otbn_wlen_data_str(otbn_trace.ispr_read_data[i_ispr]))); + $sformatf("%s: %s", acc_ispr_name_str(ispr_e'(i_ispr)), + acc_wlen_data_str(acc_trace.ispr_read_data[i_ispr]))); end - if (otbn_trace.ispr_write[i_ispr]) begin + if (acc_trace.ispr_write[i_ispr]) begin work = output_trace(work, RegWritePrefix, - $sformatf("%s: %s", otbn_ispr_name_str(ispr_e'(i_ispr)), - otbn_wlen_data_str(otbn_trace.ispr_write_data[i_ispr]))); + $sformatf("%s: %s", acc_ispr_name_str(ispr_e'(i_ispr)), + acc_wlen_data_str(acc_trace.ispr_write_data[i_ispr]))); end end end @@ -237,25 +237,25 @@ module otbn_tracer #( function automatic string prepend_trace_header(string work); bit added_header = 1'b0; - if (otbn_trace.secure_wipe_ack_r) begin + if (acc_trace.secure_wipe_ack_r) begin work = prepend_trace(work, WipeCompletePrefix, ""); added_header = 1'b1; - end else if (otbn_trace.secure_wipe_req || !otbn_trace.initial_secure_wipe_done) begin + end else if (acc_trace.secure_wipe_req || !acc_trace.initial_secure_wipe_done) begin work = prepend_trace(work, WipeInProgressPrefix, ""); added_header = 1'b1; end - if (otbn_trace.insn_valid) begin - if (otbn_trace.insn_fetch_err) begin + if (acc_trace.insn_valid) begin + if (acc_trace.insn_fetch_err) begin // This means that we've seen an IMEM integrity error. Squash the reported instruction bits // and ignore any stall: this will be the last cycle of the instruction either way. work = prepend_trace(work, InsnExecutePrefix, - $sformatf("PC: 0x%08x, insn: ??", otbn_trace.insn_addr)); + $sformatf("PC: 0x%08x, insn: ??", acc_trace.insn_addr)); end else begin // We have a valid instruction, either stalled or completing its execution - work = prepend_trace(work, otbn_trace.insn_stall ? InsnStallPrefix : InsnExecutePrefix, - $sformatf("PC: 0x%08x, insn: 0x%08x", otbn_trace.insn_addr, - otbn_trace.insn_data)); + work = prepend_trace(work, acc_trace.insn_stall ? InsnStallPrefix : InsnExecutePrefix, + $sformatf("PC: 0x%08x, insn: 0x%08x", acc_trace.insn_addr, + acc_trace.insn_data)); end added_header = 1'b1; end @@ -267,7 +267,7 @@ module otbn_tracer #( return work; endfunction - import "DPI-C" function void accept_otbn_trace_string(string trace, int unsigned cycle_count); + import "DPI-C" function void accept_acc_trace_string(string trace, int unsigned cycle_count); function automatic void do_trace(); string work; @@ -280,7 +280,7 @@ module otbn_tracer #( work = prepend_trace_header(work); if (work != "") begin - accept_otbn_trace_string(work, cycle_count); + accept_acc_trace_string(work, cycle_count); end endfunction diff --git a/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent.core b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent.core new file mode 100644 index 00000000000..0e51a0f1218 --- /dev/null +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:acc_app_agent:0.1" +description: "acc_app DV UVM agent" +filesets: + files_dv: + depend: + - lowrisc:dv:dv_utils + - lowrisc:dv:dv_lib + - lowrisc:ip:keymgr_pkg + - lowrisc:ip:kmac_pkg + - lowrisc:dv:kmac_app_agent:0.1 + files: + - acc_app_agent_pkg.sv + - acc_app_intf.sv + - acc_app_item.sv: {is_include_file: true} + - acc_app_agent_cfg.sv: {is_include_file: true} + - acc_app_sequencer.sv: {is_include_file: true} + - acc_app_base_seq.sv: {is_include_file: true} + - acc_app_agent_cov.sv: {is_include_file: true} + - acc_app_driver.sv: {is_include_file: true} + - acc_app_monitor.sv: {is_include_file: true} + - acc_app_agent.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent.sv similarity index 63% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent.sv index 2fe58c2170a..d1b066f1ded 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent.sv @@ -2,15 +2,15 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_agent extends dv_base_agent #( - .CFG_T (otbn_app_agent_cfg), - .DRIVER_T (otbn_app_driver), - .SEQUENCER_T (otbn_app_sequencer), - .MONITOR_T (otbn_app_monitor), - .COV_T (otbn_app_agent_cov) +class acc_app_agent extends dv_base_agent #( + .CFG_T (acc_app_agent_cfg), + .DRIVER_T (acc_app_driver), + .SEQUENCER_T (acc_app_sequencer), + .MONITOR_T (acc_app_monitor), + .COV_T (acc_app_agent_cov) ); - `uvm_component_utils(otbn_app_agent) + `uvm_component_utils(acc_app_agent) `uvm_component_new @@ -19,9 +19,9 @@ class otbn_app_agent extends dv_base_agent #( cfg.has_req_fifo = 1; - // Get otbn_app_intf handle from uvm_config_db - if (!uvm_config_db#(virtual otbn_app_intf)::get(this, "", "vif", cfg.vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_app_intf handle from uvm_config_db") + // Get acc_app_intf handle from uvm_config_db + if (!uvm_config_db#(virtual acc_app_intf)::get(this, "", "vif", cfg.vif)) begin + `uvm_fatal(`gfn, "failed to get acc_app_intf handle from uvm_config_db") end endfunction @@ -41,10 +41,10 @@ class otbn_app_agent extends dv_base_agent #( virtual task run_phase(uvm_phase phase); if (cfg.is_active) begin - otbn_app_base_seq m_seq; + acc_app_base_seq m_seq; // Start a device sequence `uvm_info(`gfn, $sformatf("Starting AppIntf response sequence"), UVM_MEDIUM) - m_seq = otbn_app_base_seq::type_id::create("m_seq", this); + m_seq = acc_app_base_seq::type_id::create("m_seq", this); end endtask endclass diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_cfg.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_cfg.sv similarity index 73% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_cfg.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_cfg.sv index 3043c713cb2..86402750b31 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_cfg.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_cfg.sv @@ -2,19 +2,19 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_agent_cfg extends dv_base_agent_cfg; +class acc_app_agent_cfg extends dv_base_agent_cfg; // interface handle used by driver, monitor & the sequencer, via cfg handle - virtual otbn_app_intf vif; + virtual acc_app_intf vif; // Enable starting the device auto-response sequence by default if configured in Device mode. bit start_default_device_seq = 1; - `uvm_object_utils_begin(otbn_app_agent_cfg) + `uvm_object_utils_begin(acc_app_agent_cfg) `uvm_field_int(start_default_device_seq, UVM_DEFAULT) `uvm_object_utils_end - function new (string name = "otbn_app_agent_cfg"); + function new (string name = "acc_app_agent_cfg"); super.new(name); endfunction : new diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_cov.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_cov.sv similarity index 72% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_cov.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_cov.sv index ff50dfceb19..4092ccd39b1 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_cov.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_cov.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_agent_cov extends dv_base_agent_cov #(otbn_app_agent_cfg); - `uvm_component_utils(otbn_app_agent_cov) +class acc_app_agent_cov extends dv_base_agent_cov #(acc_app_agent_cfg); + `uvm_component_utils(acc_app_agent_cov) // covergroups diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_pkg.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_pkg.sv similarity index 85% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_pkg.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_pkg.sv index e3d365dc2dc..ea55cd50cad 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent_pkg.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_agent_pkg.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -package otbn_app_agent_pkg; +package acc_app_agent_pkg; // dep packages import uvm_pkg::*; import dv_utils_pkg::*; @@ -57,16 +57,16 @@ package otbn_app_agent_pkg; parameter int KECCAK_ABSORBED_LATENCY = KECCAK_CYCLES_PER_ROUND * KECCAK_NUM_ROUNDS + KECCAK_LATENCY_DIGEST_EXPOSED; - `define CONNECT_DATA_WIDTH .HostDataWidth(otbn_app_agent_pkg::KMAC_RSP_DATA_WIDTH) + `define CONNECT_DATA_WIDTH .HostDataWidth(acc_app_agent_pkg::KMAC_RSP_DATA_WIDTH) // package sources - `include "otbn_app_item.sv" - `include "otbn_app_agent_cfg.sv" - `include "otbn_app_sequencer.sv" - `include "otbn_app_base_seq.sv" - `include "otbn_app_agent_cov.sv" - `include "otbn_app_driver.sv" - `include "otbn_app_monitor.sv" - `include "otbn_app_agent.sv" - -endpackage: otbn_app_agent_pkg + `include "acc_app_item.sv" + `include "acc_app_agent_cfg.sv" + `include "acc_app_sequencer.sv" + `include "acc_app_base_seq.sv" + `include "acc_app_agent_cov.sv" + `include "acc_app_driver.sv" + `include "acc_app_monitor.sv" + `include "acc_app_agent.sv" + +endpackage: acc_app_agent_pkg diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_base_seq.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_base_seq.sv similarity index 96% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_base_seq.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_base_seq.sv index 3561f418e72..43231ba88ab 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_base_seq.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_base_seq.sv @@ -2,18 +2,18 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_base_seq extends dv_base_seq #( - .REQ (otbn_app_item), - .RSP (otbn_app_item), - .CFG_T (otbn_app_agent_cfg), - .SEQUENCER_T (otbn_app_sequencer) +class acc_app_base_seq extends dv_base_seq #( + .REQ (acc_app_item), + .RSP (acc_app_item), + .CFG_T (acc_app_agent_cfg), + .SEQUENCER_T (acc_app_sequencer) ); - `uvm_object_utils(otbn_app_base_seq) + `uvm_object_utils(acc_app_base_seq) `uvm_object_new virtual task body(); - otbn_app_item item; + acc_app_item item; // Status bits to determine response digest behavior bit finish_seq = 0; @@ -82,7 +82,7 @@ class otbn_app_base_seq extends dv_base_seq #( // If hold is dropped we should reset and drive ready low if (!item.req_hold && !saw_first_rsp) begin - otbn_app_item rsp = otbn_app_item::type_id::create("rsp_item"); + acc_app_item rsp = acc_app_item::type_id::create("rsp_item"); rsp.rsp_ready = 0; rsp.drive_rsp_ready = 1; rsp.rsp_ready_delay = 0; @@ -93,7 +93,7 @@ class otbn_app_base_seq extends dv_base_seq #( // Set ready to 1 at the start of a transaction if (!item.rsp_ready && item.drive_rsp_ready && !initial_ready_rsp) begin - otbn_app_item rsp = otbn_app_item::type_id::create("rsp_item"); + acc_app_item rsp = acc_app_item::type_id::create("rsp_item"); rsp.rsp_ready = 1; rsp.drive_rsp_ready = 1; @@ -129,7 +129,7 @@ class otbn_app_base_seq extends dv_base_seq #( kmac_msg_fifo_cnt += $countones(item.req_strb); if (kmac_msg_fifo_cnt == (MSG_FIFO_SIZE_BYTES + MSG_PACKER_SIZE_BYTES)) begin // Drop ready here now that msg_fifo is full - otbn_app_item rsp = otbn_app_item::type_id::create("rsp_item"); + acc_app_item rsp = acc_app_item::type_id::create("rsp_item"); rsp.rsp_ready_delay = 0; rsp.rsp_ready = 0; rsp.drive_rsp_ready = 1; @@ -140,7 +140,7 @@ class otbn_app_base_seq extends dv_base_seq #( end end else if (kmac_msg_fifo_cnt == (MSG_FIFO_SIZE_BYTES + MSG_PACKER_SIZE_BYTES)) begin // Assert ready to 1 after the appropriate delay - otbn_app_item rsp = otbn_app_item::type_id::create("rsp_item"); + acc_app_item rsp = acc_app_item::type_id::create("rsp_item"); rsp.rsp_ready_delay = rsp_ready_delay; rsp.rsp_ready = 1; msg_size = msg_size + 1; @@ -386,7 +386,7 @@ class otbn_app_base_seq extends dv_base_seq #( // Send the actual digest response if (should_send_rsp) begin - otbn_app_item rsp = otbn_app_item::type_id::create("rsp_item"); + acc_app_item rsp = acc_app_item::type_id::create("rsp_item"); // Add the rsp_delay; rsp.rsp_delay = keccak_delay; @@ -445,7 +445,7 @@ class otbn_app_base_seq extends dv_base_seq #( sha3_pkg::Sha3: begin case (strength) sha3_pkg::L224: begin - `uvm_fatal(`gfn, $sformatf("strength[%0s] is not allowed for OTBN sha3", strength.name())) + `uvm_fatal(`gfn, $sformatf("strength[%0s] is not allowed for ACC sha3", strength.name())) end sha3_pkg::L256: begin if (output_wrd_cnt > 1) begin @@ -454,7 +454,7 @@ class otbn_app_base_seq extends dv_base_seq #( digestpp_dpi_pkg::c_dpi_sha3_256(msg_arr, msg_arr.size(), digest_result); end sha3_pkg::L384: begin - `uvm_fatal(`gfn, $sformatf("strength[%0s] is not allowed for OTBN sha3", strength.name())) + `uvm_fatal(`gfn, $sformatf("strength[%0s] is not allowed for ACC sha3", strength.name())) end sha3_pkg::L512: begin if (output_wrd_cnt > 2) begin @@ -487,7 +487,7 @@ class otbn_app_base_seq extends dv_base_seq #( // CSHAKE // //////////// sha3_pkg::CShake: begin - `uvm_fatal(`gfn, $sformatf("mode[%0s] is not allowed for OTBN", hash_mode.name())) + `uvm_fatal(`gfn, $sformatf("mode[%0s] is not allowed for ACC", hash_mode.name())) end endcase endtask diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_driver.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_driver.sv similarity index 93% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_driver.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_driver.sv index 1c6ae0eb9b0..35cd83dec99 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_driver.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_driver.sv @@ -2,12 +2,12 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_driver extends dv_base_driver #( - .ITEM_T (otbn_app_item), - .CFG_T (otbn_app_agent_cfg) +class acc_app_driver extends dv_base_driver #( + .ITEM_T (acc_app_item), + .CFG_T (acc_app_agent_cfg) ); - `uvm_component_utils(otbn_app_driver) + `uvm_component_utils(acc_app_driver) `uvm_component_new virtual task run_phase(uvm_phase phase); @@ -38,7 +38,7 @@ class otbn_app_driver extends dv_base_driver #( // drive trans received from sequencer virtual task get_and_drive(); forever begin - otbn_app_item item; + acc_app_item item; seq_item_port.get_next_item(item); // TODO: This driver needs to be updated to use the random reset base class // which will fix the non-blocking call to the sequencer before the item has @@ -55,7 +55,7 @@ class otbn_app_driver extends dv_base_driver #( // Drives additional responses from next as long as hold is asserted while (cfg.vif.mon_cb.req_hold && ~item.drive_rsp_ready) begin - otbn_app_item next_item; + acc_app_item next_item; if (!cfg.vif.rst_n) begin break; end @@ -76,7 +76,7 @@ class otbn_app_driver extends dv_base_driver #( endtask // Drive rsp_ready signal - task automatic drive_rsp_ready(otbn_app_item item); + task automatic drive_rsp_ready(acc_app_item item); int remaining = 0; `uvm_info(`gfn, $sformatf("Item received by ready driver:\n%0s", item.sprint()), UVM_MEDIUM) @@ -99,7 +99,7 @@ class otbn_app_driver extends dv_base_driver #( endtask // Drive digest and rsp_done - task automatic drive_rsp_response(otbn_app_item item); + task automatic drive_rsp_response(acc_app_item item); int remaining = 0; cfg.vif.host_cb.rsp_ready <= 1'b0; diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_intf.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_intf.sv similarity index 98% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_intf.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_intf.sv index aaa03ec9e95..a6e6c86aee4 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_intf.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_intf.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -interface otbn_app_intf (input clk, input rst_n); +interface acc_app_intf (input clk, input rst_n); dv_utils_pkg::if_mode_e if_mode; // interface mode - Host or Device diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_item.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_item.sv similarity index 93% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_item.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_item.sv index 965522e88eb..d56c75b2c5e 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_item.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_item.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_item extends kmac_app_item; +class acc_app_item extends kmac_app_item; // request msg rand bit req_valid; @@ -16,7 +16,7 @@ class otbn_app_item extends kmac_app_item; rand bit drive_rsp_ready; rand int unsigned rsp_ready_delay; - `uvm_object_utils_begin(otbn_app_item) + `uvm_object_utils_begin(acc_app_item) `uvm_field_int(req_valid, UVM_DEFAULT) `uvm_field_int(req_hold, UVM_DEFAULT) `uvm_field_int(req_next, UVM_DEFAULT) diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_monitor.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_monitor.sv similarity index 90% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_monitor.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_monitor.sv index 6582d2ad06f..c9855294d94 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_monitor.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_monitor.sv @@ -2,13 +2,13 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_monitor extends dv_base_monitor #( - .ITEM_T (otbn_app_item), - .CFG_T (otbn_app_agent_cfg), - .COV_T (otbn_app_agent_cov) +class acc_app_monitor extends dv_base_monitor #( + .ITEM_T (acc_app_item), + .CFG_T (acc_app_agent_cfg), + .COV_T (acc_app_agent_cov) ); - `uvm_component_utils(otbn_app_monitor) + `uvm_component_utils(acc_app_monitor) `uvm_component_new function void build_phase(uvm_phase phase); @@ -36,9 +36,9 @@ class otbn_app_monitor extends dv_base_monitor #( // Capture the MSG payload forever begin - otbn_app_item base_item = otbn_app_item::type_id::create("base_item"); - otbn_app_item next_rsp; - otbn_app_item rst_rsp; + acc_app_item base_item = acc_app_item::type_id::create("base_item"); + acc_app_item next_rsp; + acc_app_item rst_rsp; // Wait for the first valid word in the message // Wait for reset to deassert @@ -61,7 +61,7 @@ class otbn_app_monitor extends dv_base_monitor #( base_item.drive_rsp_ready = 1; req_analysis_port.write(base_item); - `uvm_info(`gfn, $sformatf("Captured configuration request from OTBN (rsp_ready = 0):\n%0s", + `uvm_info(`gfn, $sformatf("Captured configuration request from ACC (rsp_ready = 0):\n%0s", base_item.sprint()), UVM_MEDIUM) // Collect the req from DUT @@ -112,7 +112,7 @@ class otbn_app_monitor extends dv_base_monitor #( // Start a rsp if we see a posedge on next if (new_next && !prev_next) begin - next_rsp = otbn_app_item::type_id::create("rsp_next"); + next_rsp = acc_app_item::type_id::create("rsp_next"); next_rsp.byte_data_q = base_item.byte_data_q; // Maintain msg payload next_rsp.req_next = 1; // Indicate we want a new rsp next_rsp.req_hold = new_hold; // Maintain hold value @@ -125,7 +125,7 @@ class otbn_app_monitor extends dv_base_monitor #( end while (cfg.vif.mon_cb.req_hold == 1); // Once hold is dropped transaction is over // Capture req_hold = 0 to stop sequence - rst_rsp = otbn_app_item::type_id::create("rst_rsp"); + rst_rsp = acc_app_item::type_id::create("rst_rsp"); rst_rsp.req_hold = cfg.vif.mon_cb.req_hold; req_analysis_port.write(rst_rsp); diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_sequencer.sv b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_sequencer.sv similarity index 52% rename from hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_sequencer.sv rename to hw/ip/acc/dv/uvm/acc_app_agent/acc_app_sequencer.sv index b94a197616b..1796eee4d8c 100644 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_sequencer.sv +++ b/hw/ip/acc/dv/uvm/acc_app_agent/acc_app_sequencer.sv @@ -2,11 +2,11 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_app_sequencer extends dv_base_sequencer #( - .ITEM_T (otbn_app_item), - .CFG_T (otbn_app_agent_cfg) +class acc_app_sequencer extends dv_base_sequencer #( + .ITEM_T (acc_app_item), + .CFG_T (acc_app_agent_cfg) ); - `uvm_component_param_utils(otbn_app_sequencer) + `uvm_component_param_utils(acc_app_sequencer) `uvm_component_new endclass diff --git a/hw/ip/acc/dv/uvm/acc_base_sim_cfg.hjson b/hw/ip/acc/dv/uvm/acc_base_sim_cfg.hjson new file mode 100644 index 00000000000..3659af01f89 --- /dev/null +++ b/hw/ip/acc/dv/uvm/acc_base_sim_cfg.hjson @@ -0,0 +1,409 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ +// Name of the sim cfg - typically same as the name of the DUT. +name: + acc + + // Top level dut name (sv module). + dut: acc + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: xcelium + + acc_dir: "{proj_root}/hw/ip/acc" + + // Testplan hjson file. + testplan: "{acc_dir}/data/acc_testplan.hjson" + + exports: [ + { REPO_TOP: "{proj_root}" }, + ] + + // Import additional common sim cfg files. + import_cfgs: [ + // Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Config files to get the correct flags for acc_memutil and acc_tracer + "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson", + "{acc_dir}/dv/memutil/acc_memutil_sim_opts.hjson", + "{acc_dir}/dv/tracer/acc_tracer_sim_opts.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson" + ] + + // Add options needed to compile against acc_memutil, acc_tracer, and + // memutil_dpi_scrambled. + en_build_modes: ["{tool}_acc_memutil_build_opts", + "{tool}_acc_tracer_build_opts", + "{tool}_memutil_dpi_scrambled_build_opts"] + + // Add additional tops for simulation. + sim_tops: ["acc_bind", "sec_cm_prim_sparse_fsm_flop_bind", "sec_cm_prim_onehot_check_bind", + "sec_cm_prim_count_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: acc_base_test + uvm_test_seq: acc_base_vseq + + // The default place to find and build ELF binaries. If you have + // some pre-built binaries, you can run the simulation with them by using + // --run-opts to override the acc_elf_dir plusarg in run_opts. + acc_elf_dir: "{run_dir}/acc-binaries" + + + // TODO(lowrisc/opentitan#16689): Enable cdc instrumentation + run_opts: ["+acc_elf_dir={acc_elf_dir}", + "+cdc_instrumentation_enabled=0"] + + // The default build mode, used for the tests explicitly listed below does not + // require any pre-build steps. + build_modes: [ + { + name: default + pre_build_cmds: [] + } + ] + + // The value to pass to the --size parameter for gen-binaries.py. This + // controls the number of instructions that are run before ECALL or error. + binary_size: 2000 + + // This runs bazel to locate the RV32 toolchain, needed by gen-binaries.py. + setup_env: "pushd {proj_root}; source hw/ip/acc/dv/uvm/get-toolchain-paths.sh; popd;" + gen_binaries_py: "{setup_env} {acc_dir}/dv/uvm/gen-binaries.py" + + rnd_args: "--seed {seed} --size {binary_size} --pqc {pqc_enable}" + gen_fixed: "{gen_binaries_py}" + gen_rnd: "{gen_binaries_py} {rnd_args}" + + multi_err_dir: "{acc_dir}/dv/accsim/test/simple/multi" + + run_modes: [ + // Run the random instruction generator and build the one resulting binary + // in {acc_elf_dir}. If you override the acc_elf_dir plusarg with + // --run-opts, we'll still build the binary (but will ignore it). + { + name: build_acc_rig_binary_mode + pre_run_cmds: [ + "{gen_rnd} --count 1 {acc_elf_dir}" + ] + } + + // Run the random instruction generator in a "safe mode" and build + // resulting binary in {acc_elf_dir}. Other than the choice of + // RIG config, this the same as build_acc_rig_binary_mode. + { + name: build_acc_rig_safe_binary_mode + pre_run_cmds: [ + "{gen_rnd} --count 1 {acc_elf_dir} --config safe" + ] + } + + // Run the random instruction generator several times and build the + // resulting binaries in {acc_elf_dir}. + { + name: build_acc_rig_binaries_mode + pre_run_cmds: [ + "{gen_rnd} --count 10 {acc_elf_dir}" + ] + } + + // Build the smoke test in {acc_elf_dir}. + { + name: build_acc_smoke_binary_mode + pre_run_cmds: [ + "{gen_fixed} --src-dir {smoke_dir} {acc_elf_dir}" + ] + } + + // Build the multi-error tests in {acc_elf_dir}. + { + name: build_acc_multi_err_binaries_mode + pre_run_cmds: [ + "{gen_fixed} --src-dir {multi_err_dir} {acc_elf_dir}" + ] + } + ] + + // List of test specifications. + tests: [ + { + name: "acc_smoke" + uvm_test_seq: "acc_smoke_vseq" + en_run_modes: ["build_acc_smoke_binary_mode"] + // Run just one smoke test: it's a fixed binary and there's not much + // interaction with the environment so there's probably not much point + // in running it loads of times. + reseed: 1 + } + + { + name: "acc_single" + uvm_test_seq: "acc_single_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 100 + } + + // This test runs 10 binaries each time, so we give it a reseed value + // that's much less than for acc_single: these tests should equally good + // at catching errors within a single run, so the coverage that they give + // is specifically to do with improper clearing of state when starting or + // ending an operation. + { + name: "acc_multi" + uvm_test_seq: "acc_multi_vseq" + en_run_modes: ["build_acc_rig_binaries_mode"] + reseed: 10 + } + + // This test asserts reset somewhere in the middle of an operation. It is + // good for flushing out testbench bugs that are triggered on a reset, but + // it will also catch incorrect initialisation of state and hit some + // FSM/toggle coverage points that need a reset. + { + name: "acc_reset" + uvm_test_seq: "acc_reset_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 10 + } + + // This test runs a fixed set of binaries, one after the other. Since this + // is essentially a directed test, there's probably no real benefit to + // running it more than once. + { + name: "acc_multi_err" + uvm_test_seq: "acc_sequential_vseq" + en_run_modes: ["build_acc_multi_err_binaries_mode"] + reseed: 1 + } + + // This test causes a fault in the middle of an execution by triggering an + // IMEM error. We run it several times because (historically) some of the + // bugs it has found have been depended on unfortunate timing coincidences, + // so we want to have a chance of seeing them. + { + name: "acc_imem_err" + uvm_test_seq: "acc_imem_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 10 + } + + // This test causes a fault in the middle of an execution by triggering an + // DMEM error. As with the IMEM case, we want a reasonable number of + // reseeds to see awkward timing corners. Also, there's a possibility of an + // acc_dmem_err test not actually generating an error (if we don't load + // from DMEM after invalidating it), so we bump things up slightly further + // to correct for that. + { + name: "acc_dmem_err" + uvm_test_seq: "acc_dmem_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 15 + } + + // This test sets the lc_escalate_en_i and lc_rma_req_i signals somewhere in + // the middle of an operation and makes sure that we see an alert. There's + // not much interesting that can happen here, so a small number of seeds should + // suffice. + { + name: "acc_escalate" + uvm_test_seq: "acc_escalate_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 60 + } + + { + name: "acc_alu_bignum_mod_err" + uvm_test_seq: "acc_alu_bignum_mod_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + + { + name: "acc_controller_ispr_rdata_err" + uvm_test_seq: "acc_controller_ispr_rdata_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + + { + name: "acc_mac_bignum_acc_err" + uvm_test_seq: "acc_mac_bignum_acc_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + + { + name: "acc_rf_bignum_intg_err" + uvm_test_seq: "acc_rf_bignum_intg_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 10 + } + + { + name: "acc_rf_base_intg_err" + uvm_test_seq: "acc_rf_base_intg_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 10 + } + + // This test runs several sequences back-to-back. Unlike acc_multi, these + // sequences can include imem or dmem error sequences. We shouldn't need + // many seeds here because each test runs several operations. + { + name: "acc_stress_all" + uvm_test_seq: "acc_stress_all_vseq" + en_run_modes: ["build_acc_rig_binaries_mode"] + reseed: 10 + } + + // A combination of acc_stress_all and acc_reset. + { + name: "acc_stress_all_with_rand_reset" + en_run_modes: ["build_acc_rig_binaries_mode"] + reseed: 10 + } + { + name: "acc_zero_state_err_urnd" + uvm_test_seq: "acc_zero_state_err_urnd_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + { + name: "acc_illegal_mem_acc" + uvm_test_seq: "acc_illegal_mem_acc_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + { + name: "acc_sw_errs_fatal_chk" + uvm_test_seq: "acc_sw_errs_fatal_chk_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 10 + } + { + name: "acc_pc_ctrl_flow_redun" + uvm_test_seq: "acc_pc_ctrl_flow_redun_vseq" + // Use a "safe" binary, in the hope that it will run for long + // enough that we can interrupt it with an error. + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + { + name: "acc_rnd_sec_cm" + uvm_test_seq: "acc_rnd_sec_cm_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + { + name: "acc_ctrl_redun" + uvm_test_seq: "acc_ctrl_redun_vseq" + en_run_modes: ["build_acc_rig_safe_binary_mode"] + reseed: 12 + } + { + name: "acc_sec_wipe_err" + uvm_test_seq: "acc_sec_wipe_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 7 + } + { + name: "acc_urnd_err" + uvm_test_seq: "acc_urnd_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 2 + } + { + name: "acc_sw_no_acc" + uvm_test_seq: "acc_sw_no_acc_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + { + name: "acc_mem_gnt_acc_err" + uvm_test_seq: "acc_mem_gnt_acc_err_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 2 + } + { + name: "acc_stack_addr_integ_chk" + uvm_test_seq: "acc_stack_addr_integ_chk_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 5 + } + { + name: "acc_partial_wipe" + uvm_test_seq: "acc_partial_wipe_vseq" + en_run_modes: ["build_acc_rig_binary_mode"] + reseed: 10 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["acc_smoke"] + } + + { + name: "core" + tests: [ + "acc_smoke", "acc_single", "acc_multi", "acc_reset", + "acc_multi_err", "acc_imem_err", "acc_dmem_err", + "acc_stress_all", "acc_escalate", "acc_illegal_mem_acc", + "acc_zero_state_err_urnd", "acc_sw_errs_fatal_chk", + "acc_rnd_sec_cm", "acc_mac_bignum_acc_err", "acc_rf_base_intg_err", + "acc_controller_ispr_rdata_err", "acc_alu_bignum_mod_err" + ] + + } + + { + name: "ci" + tests: [ + # V1 + "acc_smoke", "acc_single", "acc_csr_hw_reset", "acc_csr_rw", + "acc_csr_bit_bash", "acc_csr_aliasing", + "acc_csr_mem_rw_with_rand_reset", + "acc_mem_partial_access", + # V1 but known broken + # "acc_mem_walk", + # V2 + "acc_reset", "acc_multi", "acc_stress_all", + "acc_zero_state_err_urnd", "acc_sw_errs_fatal_chk", "acc_alert_test", + "acc_intr_test", "acc_tl_errors", + "acc_same_csr_outstanding" + # V2 but known broken + # "acc_multi_err", "acc_escalate", + # V2S + "acc_imem_err", "acc_dmem_err", "acc_illegal_mem_acc", + "acc_tl_intg_err", "acc_sec_cm", "acc_pc_ctrl_flow_redun", + "acc_rnd_sec_cm", "acc_alu_bignum_mod_err", + "acc_controller_ispr_rdata_err", "acc_mac_bignum_acc_err", + "acc_rf_base_intg_err", + "acc_sec_wipe_err", "acc_urnd_err", + # V2S but known broken + # "acc_passthru_mem_tl_intg_err", + # V3 thus not yet active + # "acc_stress_all_with_rand_reset", + ] + } + ] +} diff --git a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent.core b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent.core similarity index 50% rename from hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent.core rename to hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent.core index 838e1ece19b..a0556d92e39 100644 --- a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent.core +++ b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent.core @@ -2,24 +2,24 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_model_agent:0.1" -description: "Agent for OTBN model interface" +name: "lowrisc:dv:acc_model_agent:0.1" +description: "Agent for ACC model interface" filesets: files_dv: depend: - lowrisc:prim:assert - lowrisc:dv:dv_utils - lowrisc:dv:dv_lib - - lowrisc:dv:otbn_model - - lowrisc:ip:otbn_pkg + - lowrisc:dv:acc_model + - lowrisc:ip:acc_pkg - lowrisc:ip:keymgr_pkg files: - - otbn_model_if.sv - - otbn_model_agent_pkg.sv - - otbn_model_item.sv: {is_include_file: true} - - otbn_model_agent_cfg.sv: {is_include_file: true} - - otbn_model_monitor.sv: {is_include_file: true} - - otbn_model_agent.sv: {is_include_file: true} + - acc_model_if.sv + - acc_model_agent_pkg.sv + - acc_model_item.sv: {is_include_file: true} + - acc_model_agent_cfg.sv: {is_include_file: true} + - acc_model_monitor.sv: {is_include_file: true} + - acc_model_agent.sv: {is_include_file: true} file_type: systemVerilogSource targets: diff --git a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent.sv b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent.sv similarity index 53% rename from hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent.sv rename to hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent.sv index 95425b5aad9..ab93dca0e7d 100644 --- a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent.sv +++ b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent.sv @@ -2,14 +2,14 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_model_agent extends dv_base_agent #( - .CFG_T (otbn_model_agent_cfg), - .MONITOR_T (otbn_model_monitor), - .DRIVER_T (otbn_dummy_driver), - .SEQUENCER_T (otbn_dummy_sequencer) +class acc_model_agent extends dv_base_agent #( + .CFG_T (acc_model_agent_cfg), + .MONITOR_T (acc_model_monitor), + .DRIVER_T (acc_dummy_driver), + .SEQUENCER_T (acc_dummy_sequencer) ); - `uvm_component_utils(otbn_model_agent) + `uvm_component_utils(acc_model_agent) `uvm_component_new function void build_phase(uvm_phase phase); @@ -18,11 +18,11 @@ class otbn_model_agent extends dv_base_agent #( // This agent doesn't support active use (it's just for monitoring the model interface). `DV_CHECK_FATAL(!cfg.is_active) - // get otbn_model_if handle + // get acc_model_if handle if (!uvm_config_db#( - virtual otbn_model_if#(.ImemSizeByte(otbn_reg_pkg::OTBN_IMEM_SIZE)) + virtual acc_model_if#(.ImemSizeByte(acc_reg_pkg::ACC_IMEM_SIZE)) )::get(this, "", "vif", cfg.vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_model_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_model_if handle from uvm_config_db") end endfunction diff --git a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent_cfg.sv b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent_cfg.sv similarity index 70% rename from hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent_cfg.sv rename to hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent_cfg.sv index ff24ca1388f..7fe7ed8c52d 100644 --- a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent_cfg.sv +++ b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent_cfg.sv @@ -2,12 +2,12 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_model_agent_cfg extends dv_base_agent_cfg; +class acc_model_agent_cfg extends dv_base_agent_cfg; // interface handle used by driver, monitor & the sequencer, via cfg handle - virtual otbn_model_if#(.ImemSizeByte(otbn_reg_pkg::OTBN_IMEM_SIZE)) vif; + virtual acc_model_if#(.ImemSizeByte(acc_reg_pkg::ACC_IMEM_SIZE)) vif; - `uvm_object_utils_begin(otbn_model_agent_cfg) + `uvm_object_utils_begin(acc_model_agent_cfg) `uvm_object_utils_end function new (string name=""); diff --git a/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent_pkg.sv b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent_pkg.sv new file mode 100644 index 00000000000..ecd3b86c5f4 --- /dev/null +++ b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_agent_pkg.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package acc_model_agent_pkg; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + + import "DPI-C" function bit + acc_trace_checker_pop_iss_insn(output bit [31:0] insn_addr, output string mnemonic); + + typedef enum { + AccModelStatus, + AccModelInsn + } acc_model_item_type_e; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + typedef acc_model_item; + typedef acc_model_agent_cfg; + // driver and sequencer are not used in this agent. Create these dummy components to avoid compile + // error due to the TLM connection between monitor and sequencer in dv_base_*. + // Both TLM fifo/port need to use the same item object (acc_model_item) + typedef dv_base_sequencer #(acc_model_item, acc_model_agent_cfg) acc_dummy_sequencer; + typedef dv_base_driver #(acc_model_item, acc_model_agent_cfg) acc_dummy_driver; + + // package sources + `include "acc_model_item.sv" + + `include "acc_model_agent_cfg.sv" + `include "acc_model_monitor.sv" + `include "acc_model_agent.sv" + +endpackage: acc_model_agent_pkg diff --git a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_if.sv b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_if.sv similarity index 62% rename from hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_if.sv rename to hw/ip/acc/dv/uvm/acc_model_agent/acc_model_if.sv index ab23ade0233..fa770919841 100644 --- a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_if.sv +++ b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_if.sv @@ -3,12 +3,12 @@ // SPDX-License-Identifier: Apache-2.0 // If using this, instantiate it somewhere that "u_model" will resolve to the corresponding instance -// of the otbn_core_model module. For example, you might instantiate it in your testbench next to +// of the acc_core_model module. For example, you might instantiate it in your testbench next to // your model. In that case, SystemVerilog's symbol resolution rules ("go up until it works") should // do the right thing. -interface otbn_model_if - import keymgr_pkg::otbn_key_req_t; +interface acc_model_if + import keymgr_pkg::acc_key_req_t; #( // Size of the instruction memory, in bytes parameter int ImemSizeByte = 4096, @@ -17,7 +17,7 @@ interface otbn_model_if ) ( input logic clk_i, input logic rst_ni, - input otbn_key_req_t keymgr_key_i + input acc_key_req_t keymgr_key_i ); import uvm_pkg::*; @@ -28,7 +28,7 @@ interface otbn_model_if // Outputs from DUT bit err; // Something went wrong bit [31:0] stop_pc; // PC at end of operation - otbn_pkg::err_bits_t err_bits; // Error bits; updated when STATUS switches to idle + acc_pkg::err_bits_t err_bits; // Error bits; updated when STATUS switches to idle // Mirrored registers bit [7:0] status; // STATUS register @@ -48,22 +48,22 @@ interface otbn_model_if // Mark the entirety of IMEM as invalid // - // Call this on a negedge of clk_i to ensure sequencing with the otbn_model_step on the following + // Call this on a negedge of clk_i to ensure sequencing with the acc_model_step on the following // posedge. function automatic void invalidate_imem(); - `uvm_info("otbn_model_if", "Invalidating IMEM", UVM_HIGH) - `DV_CHECK_FATAL(u_model.otbn_model_invalidate_imem(handle) == 0, - "Failed to invalidate IMEM", "otbn_model_if") + `uvm_info("acc_model_if", "Invalidating IMEM", UVM_HIGH) + `DV_CHECK_FATAL(u_model.acc_model_invalidate_imem(handle) == 0, + "Failed to invalidate IMEM", "acc_model_if") endfunction // Mark the entirety of DMEM as invalid // - // Call this on a negedge of clk_i to ensure sequencing with the otbn_model_step on the following + // Call this on a negedge of clk_i to ensure sequencing with the acc_model_step on the following // posedge. function automatic void invalidate_dmem(); - `uvm_info("otbn_model_if", "Invalidating DMEM", UVM_HIGH) - `DV_CHECK_FATAL(u_model.otbn_model_invalidate_dmem(handle) == 0, - "Failed to invalidate DMEM", "otbn_model_if") + `uvm_info("acc_model_if", "Invalidating DMEM", UVM_HIGH) + `DV_CHECK_FATAL(u_model.acc_model_invalidate_dmem(handle) == 0, + "Failed to invalidate DMEM", "acc_model_if") endfunction // Ask the Python model to compute a CRC step for a memory write @@ -73,25 +73,25 @@ interface otbn_model_if // to write our own CRC function and ensures that the RTL matches the standardised CRC-32-IEEE // checksum. function automatic bit [31:0] step_crc(bit [47:0] item, bit [31:0] crc_state); - `DV_CHECK_FATAL(u_model.otbn_model_step_crc(handle, item, crc_state) == 0, - "Failed to update CRC", "otbn_model_if") + `DV_CHECK_FATAL(u_model.acc_model_step_crc(handle, item, crc_state) == 0, + "Failed to update CRC", "acc_model_if") return crc_state; endfunction // Pass loop warp rules to the model function automatic void take_loop_warps(chandle memutil); - u_model.otbn_take_loop_warps(handle, memutil); + u_model.acc_take_loop_warps(handle, memutil); endfunction function automatic bit has_loop_warps(chandle memutil); - return u_model.otbn_has_loop_warps(memutil) != 0; + return u_model.acc_has_loop_warps(memutil) != 0; endfunction task automatic send_err_escalation(bit [31:0] err_val); - `uvm_info("otbn_model_if", "Escalating errors", UVM_HIGH) + `uvm_info("acc_model_if", "Escalating errors", UVM_HIGH) force u_model.wakeup_iss = 1; - `DV_CHECK_FATAL(u_model.otbn_model_send_err_escalation(handle, err_val, 1'b0) == 0, - "Failed to escalate errors", "otbn_model_if") + `DV_CHECK_FATAL(u_model.acc_model_send_err_escalation(handle, err_val, 1'b0) == 0, + "Failed to escalate errors", "acc_model_if") @(posedge clk_i or negedge rst_ni); force u_model.wakeup_iss = 0; @@ -100,14 +100,14 @@ interface otbn_model_if task automatic lock_immediately(bit [31:0] err_val); string lock_path = "tb.u_model.lock_immediately_q"; - `uvm_info("otbn_model_if", "Locking immediately after error", UVM_HIGH) + `uvm_info("acc_model_if", "Locking immediately after error", UVM_HIGH) force u_model.wakeup_iss = 1; - `DV_CHECK_FATAL(u_model.otbn_model_send_err_escalation(handle, err_val, 1'b1) == 0, + `DV_CHECK_FATAL(u_model.acc_model_send_err_escalation(handle, err_val, 1'b1) == 0, "Failed to lock immediately", - "otbn_model_if") + "acc_model_if") `DV_CHECK_FATAL(uvm_hdl_deposit(lock_path, 1'b1) == 1, "Failed to let SV model know about locking", - "otbn_model_if") + "acc_model_if") @(posedge clk_i or negedge rst_ni); force u_model.wakeup_iss = 0; @@ -115,21 +115,21 @@ interface otbn_model_if endtask: lock_immediately function automatic void set_software_errs_fatal(bit new_val); - `uvm_info("otbn_model_if", "writing to software_errs_fatal", UVM_HIGH); - `DV_CHECK_FATAL(u_model.otbn_model_set_software_errs_fatal(handle, new_val) == 0, - "Failed to set software_errs_fatal", "otbn_model_if") + `uvm_info("acc_model_if", "writing to software_errs_fatal", UVM_HIGH); + `DV_CHECK_FATAL(u_model.acc_model_set_software_errs_fatal(handle, new_val) == 0, + "Failed to set software_errs_fatal", "acc_model_if") endfunction - function automatic void otbn_set_no_sec_wipe_chk(); - `uvm_info("otbn_model_if", "writing to no_sec_wipe_data_chk", UVM_HIGH); - `DV_CHECK_FATAL(u_model.otbn_set_no_sec_wipe_chk(handle) == 0, - "Failed to set no_sec_wipe_data_chk", "otbn_model_if") + function automatic void acc_set_no_sec_wipe_chk(); + `uvm_info("acc_model_if", "writing to no_sec_wipe_data_chk", UVM_HIGH); + `DV_CHECK_FATAL(u_model.acc_set_no_sec_wipe_chk(handle) == 0, + "Failed to set no_sec_wipe_data_chk", "acc_model_if") endfunction - function automatic void otbn_disable_stack_check(); - `uvm_info("otbn_model_if", "Disabling stack integrity checks", UVM_HIGH); - `DV_CHECK_FATAL(u_model.otbn_disable_stack_check(handle) == 0, - "Failed to disable stack integrity checks", "otbn_model_if") + function automatic void acc_disable_stack_check(); + `uvm_info("acc_model_if", "Disabling stack integrity checks", UVM_HIGH); + `DV_CHECK_FATAL(u_model.acc_disable_stack_check(handle) == 0, + "Failed to disable stack integrity checks", "acc_model_if") endfunction // The err signal is asserted by the model if it fails to find the DUT or if it finds a mismatch diff --git a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_item.sv b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_item.sv similarity index 68% rename from hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_item.sv rename to hw/ip/acc/dv/uvm/acc_model_agent/acc_model_item.sv index e89bc58fa98..716843d6373 100644 --- a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_item.sv +++ b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_item.sv @@ -2,23 +2,23 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_model_item extends uvm_sequence_item; +class acc_model_item extends uvm_sequence_item; // What sort of transaction is this? - otbn_model_item_type_e item_type; + acc_model_item_type_e item_type; - // Only valid when item_type == OtbnModelStatus. + // Only valid when item_type == AccModelStatus. bit [7:0] status; bit err; - otbn_pkg::err_bits_t err_bits; + acc_pkg::err_bits_t err_bits; bit rst_n; - // Only valid when item_type == OtbnModelInsn + // Only valid when item_type == AccModelInsn bit [31:0] insn_addr; string mnemonic; - `uvm_object_utils_begin(otbn_model_item) - `uvm_field_enum (otbn_model_item_type_e, item_type, UVM_DEFAULT) + `uvm_object_utils_begin(acc_model_item) + `uvm_field_enum (acc_model_item_type_e, item_type, UVM_DEFAULT) `uvm_field_int (status, UVM_DEFAULT) `uvm_field_int (err, UVM_DEFAULT) `uvm_field_int (err_bits, UVM_DEFAULT | UVM_HEX) diff --git a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_monitor.sv b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_monitor.sv similarity index 72% rename from hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_monitor.sv rename to hw/ip/acc/dv/uvm/acc_model_agent/acc_model_monitor.sv index e8be6e5ad30..d25810c5238 100644 --- a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_monitor.sv +++ b/hw/ip/acc/dv/uvm/acc_model_agent/acc_model_monitor.sv @@ -3,19 +3,19 @@ // SPDX-License-Identifier: Apache-2.0 // -// The monitor watches the otbn_model_if and reports responses from the model +// The monitor watches the acc_model_if and reports responses from the model // -class otbn_model_monitor extends dv_base_monitor #( - .ITEM_T (otbn_model_item), - .CFG_T (otbn_model_agent_cfg) +class acc_model_monitor extends dv_base_monitor #( + .ITEM_T (acc_model_item), + .CFG_T (acc_model_agent_cfg) ); - `uvm_component_utils(otbn_model_monitor) + `uvm_component_utils(acc_model_monitor) // the base class provides the following handles for use: - // otbn_model_agent_cfg: cfg - // otbn_model_agent_cov: cov - // uvm_analysis_port #(otbn_model_item): analysis_port + // acc_model_agent_cfg: cfg + // acc_model_agent_cov: cov + // uvm_analysis_port #(acc_model_item): analysis_port `uvm_component_new @@ -27,10 +27,10 @@ class otbn_model_monitor extends dv_base_monitor #( endtask protected task collect_status(); - otbn_model_item trans; + acc_model_item trans; forever begin - trans = otbn_model_item::type_id::create("trans"); + trans = acc_model_item::type_id::create("trans"); // Wait until vif signals a change in status (or we are in reset) cfg.vif.wait_status(); @@ -44,7 +44,7 @@ class otbn_model_monitor extends dv_base_monitor #( wait(cfg.vif.rst_ni); end - trans.item_type = OtbnModelStatus; + trans.item_type = AccModelStatus; trans.status = cfg.vif.status; trans.err = cfg.vif.err; trans.err_bits = cfg.vif.err_bits; @@ -54,12 +54,12 @@ class otbn_model_monitor extends dv_base_monitor #( endtask protected task collect_insns(); - otbn_model_item trans; + acc_model_item trans; bit [31:0] insn_addr; string insn_mnemonic; - // OtbnModelInsn items are only used for coverage collection; disable their detection if + // AccModelInsn items are only used for coverage collection; disable their detection if // coverage is not enabled. if (!cfg.en_cov) begin return; @@ -67,7 +67,7 @@ class otbn_model_monitor extends dv_base_monitor #( // Collect transactions on each clock edge when we are not in reset forever begin - // Use a clocking block to ensure we sample after the always_ff code in otbn_core_model.sv has + // Use a clocking block to ensure we sample after the always_ff code in acc_core_model.sv has // run. This means that we'll immediately see any instructions that executed. Without it, we'd // be racing against that logic, which might mean we saw the instructions a cycle later. In // that case, a final instruction gets spotted after we see the status go back to idle @@ -77,9 +77,9 @@ class otbn_model_monitor extends dv_base_monitor #( if (cfg.vif.rst_ni === 1'b1) begin // Ask the trace checker for any ISS instruction that has come in since last cycle. - if (otbn_trace_checker_pop_iss_insn(insn_addr, insn_mnemonic)) begin - trans = otbn_model_item::type_id::create("trans"); - trans.item_type = OtbnModelInsn; + if (acc_trace_checker_pop_iss_insn(insn_addr, insn_mnemonic)) begin + trans = acc_model_item::type_id::create("trans"); + trans.item_type = AccModelInsn; trans.status = 0; trans.err = 0; trans.insn_addr = insn_addr; diff --git a/hw/ip/otbn/dv/uvm/otbn_pqc_sim_cfg.hjson b/hw/ip/acc/dv/uvm/acc_pqc_sim_cfg.hjson similarity index 58% rename from hw/ip/otbn/dv/uvm/otbn_pqc_sim_cfg.hjson rename to hw/ip/acc/dv/uvm/acc_pqc_sim_cfg.hjson index e43aa5c0ba2..bfab6b74d7f 100644 --- a/hw/ip/otbn/dv/uvm/otbn_pqc_sim_cfg.hjson +++ b/hw/ip/acc/dv/uvm/acc_pqc_sim_cfg.hjson @@ -1,27 +1,27 @@ // Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// sim cfg file for the pqc version of OTBN +// sim cfg file for the pqc version of ACC { // Name of the sim cfg variant variant: pqc // Import additional common sim cfg files. - import_cfgs: ["{proj_root}/hw/ip/otbn/dv/uvm/otbn_base_sim_cfg.hjson"] + import_cfgs: ["{proj_root}/hw/ip/acc/dv/uvm/acc_base_sim_cfg.hjson"] - smoke_dir: "{otbn_dir}/dv/smoke_pqc" + smoke_dir: "{acc_dir}/dv/smoke_pqc" // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:dv:otbn_sim_pqc:0.1 + fusesoc_core: lowrisc:dv:acc_sim_pqc:0.1 // Used to generate pqc instructions with assembly gen pqc_enable: 1 - // Sets otbnsim to PQC mode + // Sets accsim to PQC mode exports: [ { PQC_EN: 1 }, ] // exclusion files - vcs_cov_excl_files: ["{proj_root}/hw/ip/otbn/dv/uvm/cov/otbn_pqc_cov_excl.el"] + vcs_cov_excl_files: ["{proj_root}/hw/ip/acc/dv/uvm/cov/acc_pqc_cov_excl.el"] } diff --git a/hw/ip/otbn/dv/uvm/otbn_sim.core b/hw/ip/acc/dv/uvm/acc_sim.core similarity index 69% rename from hw/ip/otbn/dv/uvm/otbn_sim.core rename to hw/ip/acc/dv/uvm/acc_sim.core index 32ae5e8cbb2..96274e0b31d 100644 --- a/hw/ip/otbn/dv/uvm/otbn_sim.core +++ b/hw/ip/acc/dv/uvm/acc_sim.core @@ -2,19 +2,19 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_sim:0.1" -description: "OTBN DV sim target" +name: "lowrisc:dv:acc_sim:0.1" +description: "ACC DV sim target" filesets: files_rtl: depend: - - lowrisc:dv:otbn_pqc_off_env_pkg - - lowrisc:ip:otbn - - lowrisc:dv:otbn_model + - lowrisc:dv:acc_pqc_off_env_pkg + - lowrisc:ip:acc + - lowrisc:dv:acc_model files_dv: depend: - - lowrisc:dv:otbn_test - - lowrisc:dv:otbn_sva + - lowrisc:dv:acc_test + - lowrisc:dv:acc_sva - lowrisc:dv:mem_bkdr_util - lowrisc:dv:sram_ctrl_bkdr_util - lowrisc:ip:edn_pkg diff --git a/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson b/hw/ip/acc/dv/uvm/acc_sim_cfg.hjson similarity index 58% rename from hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson rename to hw/ip/acc/dv/uvm/acc_sim_cfg.hjson index 3a5cb0e2c13..5bc1956844a 100644 --- a/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson +++ b/hw/ip/acc/dv/uvm/acc_sim_cfg.hjson @@ -1,27 +1,27 @@ // Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// sim cfg file for the standard version of OTBN +// sim cfg file for the standard version of ACC { // Name of the sim cfg variant variant: standard // Import additional common sim cfg files. - import_cfgs: ["{proj_root}/hw/ip/otbn/dv/uvm/otbn_base_sim_cfg.hjson"] + import_cfgs: ["{proj_root}/hw/ip/acc/dv/uvm/acc_base_sim_cfg.hjson"] - smoke_dir: "{otbn_dir}/dv/smoke" + smoke_dir: "{acc_dir}/dv/smoke" // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:dv:otbn_sim:0.1 + fusesoc_core: lowrisc:dv:acc_sim:0.1 // Used to disable generation of pqc instructions with assembly gen pqc_enable: 0 - // Sets otbnsim to standard mode + // Sets accsim to standard mode exports: [ { PQC_EN: 0 }, ] // exclusion files - vcs_cov_excl_files: ["{proj_root}/hw/ip/otbn/dv/uvm/cov/otbn_standard_cov_excl.el"] + vcs_cov_excl_files: ["{proj_root}/hw/ip/acc/dv/uvm/cov/acc_standard_cov_excl.el"] } diff --git a/hw/ip/otbn/dv/uvm/otbn_sim_pqc.core b/hw/ip/acc/dv/uvm/acc_sim_pqc.core similarity index 69% rename from hw/ip/otbn/dv/uvm/otbn_sim_pqc.core rename to hw/ip/acc/dv/uvm/acc_sim_pqc.core index 22212b57710..ccafe0d7fda 100644 --- a/hw/ip/otbn/dv/uvm/otbn_sim_pqc.core +++ b/hw/ip/acc/dv/uvm/acc_sim_pqc.core @@ -2,19 +2,19 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_sim_pqc:0.1" -description: "OTBN DV sim target" +name: "lowrisc:dv:acc_sim_pqc:0.1" +description: "ACC DV sim target" filesets: files_rtl: depend: - - lowrisc:dv:otbn_pqc_on_env_pkg - - lowrisc:ip:otbn - - lowrisc:dv:otbn_model + - lowrisc:dv:acc_pqc_on_env_pkg + - lowrisc:ip:acc + - lowrisc:dv:acc_model files_dv: depend: - - lowrisc:dv:otbn_test - - lowrisc:dv:otbn_sva + - lowrisc:dv:acc_test + - lowrisc:dv:acc_sva - lowrisc:dv:mem_bkdr_util - lowrisc:dv:sram_ctrl_bkdr_util - lowrisc:ip:edn_pkg diff --git a/hw/ip/otbn/dv/uvm/cov/otbn_pqc_cov_excl.el b/hw/ip/acc/dv/uvm/cov/acc_pqc_cov_excl.el similarity index 97% rename from hw/ip/otbn/dv/uvm/cov/otbn_pqc_cov_excl.el rename to hw/ip/acc/dv/uvm/cov/acc_pqc_cov_excl.el index d901352be9c..cdd6a255959 100644 --- a/hw/ip/otbn/dv/uvm/cov/otbn_pqc_cov_excl.el +++ b/hw/ip/acc/dv/uvm/cov/acc_pqc_cov_excl.el @@ -10,7 +10,7 @@ // ExclMode: default //================================================== CHECKSUM: "3838931634 1997345871" -INSTANCE: tb.dut.u_otbn_core.u_otbn_mac_bignum.gen_mac_adder_pqc.adder16 +INSTANCE: tb.dut.u_acc_core.u_acc_mac_bignum.gen_mac_adder_pqc.adder16 ANNOTATION: "vcs_gen_start:ALL:vcs_gen_end:[UNR]: Adder 16 can never have VecType_h16 mode as an input" Branch 29 "1327461312" "(word_mode == VecType_h16)" (0) "(word_mode == VecType_h16) 1,-,-" ANNOTATION: "vcs_gen_start:ALL:vcs_gen_end:[UNR]: Adder 16 can never have VecType_h16 mode as an input" @@ -72,7 +72,7 @@ Branch 26 "3962392675" "(word_mode == VecType_h16)" (0) "(word_mode == VecType_h ANNOTATION: "vcs_gen_start:i=15:vcs_gen_end:[UNR]: Adder 16 can never have VecType_h16 mode as an input" Branch 28 "1327461312" "(word_mode == VecType_h16)" (0) "(word_mode == VecType_h16) 1,-,-" CHECKSUM: "994428267 3945285972" -INSTANCE: tb.dut.u_otbn_core.u_otbn_alu_bignum.gen_pqc_wsr.u_kmac_cfg_secded_dec +INSTANCE: tb.dut.u_acc_core.u_acc_alu_bignum.gen_pqc_wsr.u_kmac_cfg_secded_dec ANNOTATION: "[UNSUPPORTED]: Bits [30:20] are unused in KMAC Cfg CSR" Toggle data_o [29] "logic data_o[31:0]" ANNOTATION: "[UNSUPPORTED]: Bits [30:20] are unused in KMAC Cfg CSR" @@ -118,7 +118,7 @@ Toggle data_i [20] "net data_i[38:0]" ANNOTATION: "[UNSUPPORTED]: Bits [30:20] are unused in KMAC Cfg CSR" Toggle data_i [30] "net data_i[38:0]" CHECKSUM: "994428267 3945285972" -INSTANCE: tb.dut.u_otbn_core.u_otbn_alu_bignum.gen_pqc_wsr.u_kmac_status_secded_dec +INSTANCE: tb.dut.u_acc_core.u_acc_alu_bignum.gen_pqc_wsr.u_kmac_status_secded_dec ANNOTATION: "[UNSUPPORTED]: Bits [31:5] of KMAC status CSR/WSR are unused" Toggle data_o [30] "logic data_o[31:0]" ANNOTATION: "[UNSUPPORTED]: Bits [31:5] of KMAC status CSR/WSR are unused" @@ -228,7 +228,7 @@ Toggle data_i [5] "net data_i[38:0]" ANNOTATION: "[UNSUPPORTED]: Bits [31:5] of KMAC status CSR/WSR are unused" Toggle data_i [31] "net data_i[38:0]" CHECKSUM: "3838931634 2094048665" -INSTANCE: tb.dut.u_otbn_core.u_otbn_mac_bignum.gen_mac_adder_pqc.adder16 +INSTANCE: tb.dut.u_acc_core.u_acc_mac_bignum.gen_mac_adder_pqc.adder16 ANNOTATION: "vcs_gen_start:i=1:vcs_gen_end:[UNR]: Adder 16 can never have VecType_h16 mode as an input" Condition 2 "1880076921" "(word_mode == VecType_h16) 1 -1" ANNOTATION: "vcs_gen_start:i=15:vcs_gen_end:[UNR]: Adder 16 can never have VecType_h16 mode as an input" @@ -290,40 +290,40 @@ Condition 14 "2634351077" "(word_mode == VecType_h16) 1 -1" ANNOTATION: "vcs_gen_start:i=1:vcs_gen_end:[UNR]: Adder 16 can never have VecType_h16 mode as an input" Condition 8 "3587187684" "(word_mode == VecType_h16) 1 -1" CHECKSUM: "127070474 927371340" -INSTANCE: tb.dut.u_otbn_core.u_otbn_decoder -ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static OtbnPQCEn is 1" +INSTANCE: tb.dut.u_acc_core.u_acc_decoder +ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static AccPQCEn is 1" Branch 4 "2344605462" "opcode_alu" (35) "opcode_alu InsnOpcodeBignumArith ,-,-,-,-,-,-,3'b101 ,-,1,1,0,-,-,-,-,-,-,-,-,-,-" -ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static AccPQCEn is 1" Branch 4 "2344605462" "opcode_alu" (59) "opcode_alu InsnOpcodeBignumTrn ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0" -ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static AccPQCEn is 1" Branch 4 "2344605462" "opcode_alu" (57) "opcode_alu InsnOpcodeBignumShiftv ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-" -ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Decoder else conditions not reachable for vector insntructions when static AccPQCEn is 1" Branch 4 "2344605462" "opcode_alu" (39) "opcode_alu InsnOpcodeBignumArith ,-,-,-,-,-,-,3'b101 ,-,0,-,-,-,1,0,-,-,-,-,-,-,-" CHECKSUM: "737333266 3782559018" -INSTANCE: tb.dut.u_otbn_core.u_otbn_instruction_fetch.u_otbn_predecode -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +INSTANCE: tb.dut.u_acc_core.u_acc_instruction_fetch.u_acc_predecode +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 0 "3102685083" "imem_rvalid_i" (20) "imem_rvalid_i 1,InsnOpcodeBignumArith ,-,-,-,-,-,-,-,3'b101 ,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 0 "3102685083" "imem_rvalid_i" (21) "imem_rvalid_i 1,InsnOpcodeBignumArith ,-,-,-,-,-,-,-,3'b101 ,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 0 "3102685083" "imem_rvalid_i" (54) "imem_rvalid_i 1,InsnOpcodeBignumTrn ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 0 "3102685083" "imem_rvalid_i" (52) "imem_rvalid_i 1,InsnOpcodeBignumShiftv ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 0 "3102685083" "imem_rvalid_i" (50) "imem_rvalid_i 1,InsnOpcodeBignumMulv ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 1 "2606768895" "csr_addr_sel" (2) "csr_addr_sel 1,CsrKmacCfg ,0,-,-,-,-,-,-,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 1 "2606768895" "csr_addr_sel" (22) "csr_addr_sel 0,-,-,-,-,WsrAccH ,-,-,-,0" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 1 "2606768895" "csr_addr_sel" (20) "csr_addr_sel 0,-,-,-,-,WsrKmacDigest ,-,-,0,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 1 "2606768895" "csr_addr_sel" (18) "csr_addr_sel 0,-,-,-,-,WsrKmacMsg ,-,0,-,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 1 "2606768895" "csr_addr_sel" (16) "csr_addr_sel 0,-,-,-,-,WsrKmacCfg ,0,-,-,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 1 "2606768895" "csr_addr_sel" (6) "csr_addr_sel 1,CsrKmacStatus ,-,-,0,-,-,-,-,-" -ANNOTATION: "[UNR]: Predecode else conditions not reachable when static OtbnPQCEn is 1" +ANNOTATION: "[UNR]: Predecode else conditions not reachable when static AccPQCEn is 1" Branch 1 "2606768895" "csr_addr_sel" (4) "csr_addr_sel 1,CsrKmacPartialW ,-,0,-,-,-,-,-,-" CHECKSUM: "3569791575 3453920680" INSTANCE: tb.dut diff --git a/hw/ip/otbn/dv/uvm/cov/otbn_standard_cov_excl.el b/hw/ip/acc/dv/uvm/cov/acc_standard_cov_excl.el similarity index 57% rename from hw/ip/otbn/dv/uvm/cov/otbn_standard_cov_excl.el rename to hw/ip/acc/dv/uvm/cov/acc_standard_cov_excl.el index a1494c3b599..748f7c4c69b 100644 --- a/hw/ip/otbn/dv/uvm/cov/otbn_standard_cov_excl.el +++ b/hw/ip/acc/dv/uvm/cov/acc_standard_cov_excl.el @@ -11,25 +11,25 @@ //================================================== CHECKSUM: "3569791575 3453920680" INSTANCE: tb.dut -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_o.valid "logic kmac_data_o.valid" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_i.digest_share0 "logic kmac_data_i.digest_share0[383:0]" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_i.digest_share1 "logic kmac_data_i.digest_share1[383:0]" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_i.done "logic kmac_data_i.done" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_i.error "logic kmac_data_i.error" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_i.ready "logic kmac_data_i.ready" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_o.data "logic kmac_data_o.data[63:0]" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_o.hold "logic kmac_data_o.hold" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_o.next "logic kmac_data_o.next" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_o.last "logic kmac_data_o.last" -ANNOTATION: "[UNSUPPORTED]: standard OTBN does not use kmac interface" +ANNOTATION: "[UNSUPPORTED]: standard ACC does not use kmac interface" Toggle kmac_data_o.strb "logic kmac_data_o.strb[7:0]" diff --git a/hw/ip/otbn/dv/uvm/env/otbn_alu_bignum_if.sv b/hw/ip/acc/dv/uvm/env/acc_alu_bignum_if.sv similarity index 72% rename from hw/ip/otbn/dv/uvm/env/otbn_alu_bignum_if.sv rename to hw/ip/acc/dv/uvm/env/acc_alu_bignum_if.sv index dc566836873..862ee42bea0 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_alu_bignum_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_alu_bignum_if.sv @@ -2,32 +2,32 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Bound into the otbn_alu_bignum and used to help collect ISPR information for coverage. +// Bound into the acc_alu_bignum and used to help collect ISPR information for coverage. -interface otbn_alu_bignum_if ( +interface acc_alu_bignum_if ( input clk_i, input rst_ni, - input [otbn_pkg::ExtWLEN-1:0] mod_intg_q, + input [acc_pkg::ExtWLEN-1:0] mod_intg_q, input mod_used ); // Force the `mod_intg_q` register to `should_val`. This function needs to be static because its // argument must live as least as long as the `force` statement is in effect. - function static void force_mod_intg_q(input logic [otbn_pkg::ExtWLEN-1:0] should_val); - force u_otbn_alu_bignum.mod_intg_q = should_val; + function static void force_mod_intg_q(input logic [acc_pkg::ExtWLEN-1:0] should_val); + force u_acc_alu_bignum.mod_intg_q = should_val; endfunction // Release the forcing of the `mod_intg_q` register. function automatic void release_mod_intg_q(); - release u_otbn_alu_bignum.mod_intg_q; + release u_acc_alu_bignum.mod_intg_q; endfunction // Wait for the `mod_used` signal to be high (outside a reset) or until `max_cycles` clock cycles // have passed. When this task returns, the `used_words` output indicates which words are being // used. task automatic wait_for_mod_used(input int unsigned max_cycles, - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words); + output bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words); int unsigned cycle_cnt = 0; while (1) begin @(negedge clk_i); diff --git a/hw/ip/otbn/dv/uvm/env/otbn_controller_if.sv b/hw/ip/acc/dv/uvm/env/acc_controller_if.sv similarity index 82% rename from hw/ip/otbn/dv/uvm/env/otbn_controller_if.sv rename to hw/ip/acc/dv/uvm/env/acc_controller_if.sv index 6858bddb2ab..f84440502c0 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_controller_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_controller_if.sv @@ -2,15 +2,15 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Bound into the otbn_controller and used to help collect ISPR information for coverage. +// Bound into the acc_controller and used to help collect ISPR information for coverage. -interface otbn_controller_if - import otbn_pkg::*; +interface acc_controller_if + import acc_pkg::*; ( input clk_i, input rst_ni, - // Signal names from the otbn_controller module (where we are bound) + // Signal names from the acc_controller module (where we are bound) input logic [ExtWLEN-1:0] ispr_rdata_intg_i, input logic [BaseWordsPerWLEN-1:0] ispr_read_mask, input logic non_prefetch_insn_running @@ -19,12 +19,12 @@ interface otbn_controller_if // Force the `ispr_rdata_intg_i` signal to `should_val`. This function needs to be static because // its argument must live as least as long as the `force` statement is in effect. function static void force_ispr_rdata_intg_i(input logic [ExtWLEN-1:0] should_val); - force u_otbn_controller.ispr_rdata_intg_i = should_val; + force u_acc_controller.ispr_rdata_intg_i = should_val; endfunction // Release the forcing of the `ispr_rdata_intg_i` signal. function automatic void release_ispr_rdata_intg_i(); - release u_otbn_controller.ispr_rdata_intg_i; + release u_acc_controller.ispr_rdata_intg_i; endfunction // Wait until some ISPR data is being used (outside a reset) or until `max_cycles` clock cycles diff --git a/hw/ip/acc/dv/uvm/env/acc_env.core b/hw/ip/acc/dv/uvm/env/acc_env.core new file mode 100644 index 00000000000..d94fd4f4046 --- /dev/null +++ b/hw/ip/acc/dv/uvm/env/acc_env.core @@ -0,0 +1,86 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:acc_env:0.1" +description: "ACC DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:acc_pqc_env_pkg + - lowrisc:ip:acc + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:dv:dv_lib + - lowrisc:dv:sram_ctrl_bkdr_util + - lowrisc:dv:acc_app_agent:0.1 + - lowrisc:dv:tl_agent + - lowrisc:dv:alert_esc_agent + - lowrisc:dv:acc_model_agent + - lowrisc:dv:key_sideload_agent + files: + - acc_env_pkg.sv + - acc_loop_if.sv + - acc_alu_bignum_if.sv + - acc_controller_if.sv + - acc_mac_bignum_if.sv + - acc_rf_base_if.sv + - acc_insn_cnt_if.sv + - acc_rnd_if.sv + - acc_escalate_if.sv + - acc_ssctrl_if.sv + - acc_trace_item.sv: {is_include_file: true} + - acc_trace_monitor.sv: {is_include_file: true} + - acc_env_cfg.sv: {is_include_file: true} + - acc_env_cov.sv: {is_include_file: true} + - acc_virtual_sequencer.sv: {is_include_file: true} + - acc_scoreboard.sv: {is_include_file: true} + - acc_env.sv: {is_include_file: true} + - acc_test_helpers.cc: {file_type: cppSource} + - seq_lib/acc_vseq_list.sv: {is_include_file: true} + - seq_lib/acc_base_vseq.sv: {is_include_file: true} + - seq_lib/acc_common_vseq.sv: {is_include_file: true} + - seq_lib/acc_multi_vseq.sv: {is_include_file: true} + - seq_lib/acc_reset_vseq.sv: {is_include_file: true} + - seq_lib/acc_sequential_vseq.sv: {is_include_file: true} + - seq_lib/acc_imem_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_dmem_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_single_vseq.sv: {is_include_file: true} + - seq_lib/acc_smoke_vseq.sv: {is_include_file: true} + - seq_lib/acc_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/acc_escalate_vseq.sv: {is_include_file: true} + - seq_lib/acc_zero_state_err_urnd_vseq.sv: {is_include_file: true} + - seq_lib/acc_illegal_mem_acc_vseq.sv: {is_include_file: true} + - seq_lib/acc_rnd_sec_cm_vseq.sv: {is_include_file: true} + - seq_lib/acc_sw_errs_fatal_chk_vseq.sv: {is_include_file: true} + - seq_lib/acc_intg_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_alu_bignum_mod_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_controller_ispr_rdata_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_mac_bignum_acc_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_rf_base_intg_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_rf_bignum_intg_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_pc_ctrl_flow_redun_vseq.sv: {is_include_file: true} + - seq_lib/acc_ctrl_redun_vseq.sv: {is_include_file: true} + - seq_lib/acc_sec_wipe_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_urnd_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_sw_no_acc_vseq.sv: {is_include_file: true} + - seq_lib/acc_mem_gnt_acc_err_vseq.sv: {is_include_file: true} + - seq_lib/acc_stack_addr_integ_chk_vseq.sv: {is_include_file: true} + - seq_lib/acc_partial_wipe_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: acc + ip_hjson: ../../../data/acc.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env.sv b/hw/ip/acc/dv/uvm/env/acc_env.sv similarity index 55% rename from hw/ip/otbn/dv/uvm/env/otbn_env.sv rename to hw/ip/acc/dv/uvm/env/acc_env.sv index 1c0682b97d2..82e1d200b87 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_env.sv +++ b/hw/ip/acc/dv/uvm/env/acc_env.sv @@ -3,18 +3,18 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_env extends cip_base_env #( - .CFG_T (otbn_env_cfg), - .COV_T (otbn_env_cov), - .VIRTUAL_SEQUENCER_T(otbn_virtual_sequencer), - .SCOREBOARD_T (otbn_scoreboard) +class acc_env extends cip_base_env #( + .CFG_T (acc_env_cfg), + .COV_T (acc_env_cov), + .VIRTUAL_SEQUENCER_T(acc_virtual_sequencer), + .SCOREBOARD_T (acc_scoreboard) ); - `uvm_component_utils(otbn_env) + `uvm_component_utils(acc_env) - otbn_model_agent model_agent; - otbn_trace_monitor trace_monitor; - otbn_sideload_agent keymgr_sideload_agent; - otbn_app_agent m_otbn_app_agent; + acc_model_agent model_agent; + acc_trace_monitor trace_monitor; + acc_sideload_agent keymgr_sideload_agent; + acc_app_agent m_acc_app_agent; otp_key_agent key_agent; `uvm_component_new @@ -22,14 +22,14 @@ class otbn_env extends cip_base_env #( function void build_phase(uvm_phase phase); super.build_phase(phase); - cfg.mem_util = OtbnMemUtilMake(cfg.dut_instance_hier); + cfg.mem_util = AccMemUtilMake(cfg.dut_instance_hier); `DV_CHECK_FATAL(cfg.mem_util != null); - m_otbn_app_agent = otbn_app_agent::type_id::create("m_otbn_app_agent", this); - uvm_config_db#(otbn_app_agent_cfg)::set(this, "m_otbn_app_agent", "cfg", cfg.m_otbn_app_agent_cfg); + m_acc_app_agent = acc_app_agent::type_id::create("m_acc_app_agent", this); + uvm_config_db#(acc_app_agent_cfg)::set(this, "m_acc_app_agent", "cfg", cfg.m_acc_app_agent_cfg); - model_agent = otbn_model_agent::type_id::create("model_agent", this); - uvm_config_db#(otbn_model_agent_cfg)::set(this, "model_agent*", "cfg", cfg.model_agent_cfg); + model_agent = acc_model_agent::type_id::create("model_agent", this); + uvm_config_db#(acc_model_agent_cfg)::set(this, "model_agent*", "cfg", cfg.model_agent_cfg); cfg.model_agent_cfg.en_cov = cfg.en_cov; // Get the OTP clk/rst interface @@ -39,55 +39,55 @@ class otbn_env extends cip_base_env #( end cfg.otp_clk_rst_vif.set_freq_mhz(cfg.otp_freq_mhz); - keymgr_sideload_agent = otbn_sideload_agent::type_id::create("keymgr_sideload_agent", this); - uvm_config_db#(otbn_sideload_agent_cfg)::set( + keymgr_sideload_agent = acc_sideload_agent::type_id::create("keymgr_sideload_agent", this); + uvm_config_db#(acc_sideload_agent_cfg)::set( this, "keymgr_sideload_agent*", "cfg", cfg.keymgr_sideload_agent_cfg); key_agent = otp_key_agent::type_id::create("key_agent", this); uvm_config_db#(otp_key_agent_cfg)::set(this, "key_agent", "cfg", cfg.key_cfg); cfg.key_cfg.agent_type = push_pull_agent_pkg::PullAgent; cfg.key_cfg.if_mode = dv_utils_pkg::Device; - // CDC synchronization between OTP and OTBN clock domains requires that the scrambling seed data - // should be held for at least a few cycles before it can be safely latched by the OTBN domain. + // CDC synchronization between OTP and ACC clock domains requires that the scrambling seed data + // should be held for at least a few cycles before it can be safely latched by the ACC domain. // Easy way to do this is just to force the push_pull_agent to hold the data until the next key // request is sent out. cfg.key_cfg.hold_d_data_until_next_req = 1'b1; cfg.key_cfg.zero_delays = 1'b1; cfg.key_cfg.en_cov = cfg.en_cov; - if (!uvm_config_db#(virtual otbn_trace_if)::get(this, "", "trace_vif", cfg.trace_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_trace_if handle from uvm_config_db") + if (!uvm_config_db#(virtual acc_trace_if)::get(this, "", "trace_vif", cfg.trace_vif)) begin + `uvm_fatal(`gfn, "failed to get acc_trace_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_loop_if)::get(this, "", "loop_vif", cfg.loop_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_loop_if handle from uvm_config_db") + if (!uvm_config_db#(virtual acc_loop_if)::get(this, "", "loop_vif", cfg.loop_vif)) begin + `uvm_fatal(`gfn, "failed to get acc_loop_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_alu_bignum_if)::get(this, "", "alu_bignum_vif", + if (!uvm_config_db#(virtual acc_alu_bignum_if)::get(this, "", "alu_bignum_vif", cfg.alu_bignum_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_alu_bignum_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_alu_bignum_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_controller_if)::get(this, "", "controller_vif", + if (!uvm_config_db#(virtual acc_controller_if)::get(this, "", "controller_vif", cfg.controller_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_controller_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_controller_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_mac_bignum_if)::get(this, "", "mac_bignum_vif", + if (!uvm_config_db#(virtual acc_mac_bignum_if)::get(this, "", "mac_bignum_vif", cfg.mac_bignum_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_mac_bignum_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_mac_bignum_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_rf_base_if)::get(this, "", "rf_base_vif", + if (!uvm_config_db#(virtual acc_rf_base_if)::get(this, "", "rf_base_vif", cfg.rf_base_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_rf_base_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_rf_base_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_escalate_if)::get(this, "", "escalate_vif", + if (!uvm_config_db#(virtual acc_escalate_if)::get(this, "", "escalate_vif", cfg.escalate_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_escalate_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_escalate_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_rnd_if)::get(this, "", "rnd_vif", + if (!uvm_config_db#(virtual acc_rnd_if)::get(this, "", "rnd_vif", cfg.rnd_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_rnd_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_rnd_if handle from uvm_config_db") end - if (!uvm_config_db#(virtual otbn_ssctrl_if)::get(this, "", "ssctrl_vif", + if (!uvm_config_db#(virtual acc_ssctrl_if)::get(this, "", "ssctrl_vif", cfg.ssctrl_vif)) begin - `uvm_fatal(`gfn, "failed to get otbn_ssctrl_if handle from uvm_config_db") + `uvm_fatal(`gfn, "failed to get acc_ssctrl_if handle from uvm_config_db") end if (!uvm_config_db#(sram_ctrl_bkdr_util)::get(this, "", "imem_util", cfg.imem_util)) begin `uvm_fatal(`gfn, "failed to get imem_util from uvm_config_db") @@ -96,7 +96,7 @@ class otbn_env extends cip_base_env #( `uvm_fatal(`gfn, "failed to get dmem_util from uvm_config_db") end - trace_monitor = otbn_trace_monitor::type_id::create("trace_monitor", this); + trace_monitor = acc_trace_monitor::type_id::create("trace_monitor", this); trace_monitor.cfg = cfg; trace_monitor.cov = cov; endfunction @@ -107,7 +107,7 @@ class otbn_env extends cip_base_env #( trace_monitor.analysis_port.connect(scoreboard.trace_fifo.analysis_export); cfg.scoreboard = scoreboard; virtual_sequencer.key_sideload_sequencer_h = keymgr_sideload_agent.sequencer; - virtual_sequencer.otbn_app_sequencer_h = m_otbn_app_agent.sequencer; + virtual_sequencer.acc_app_sequencer_h = m_acc_app_agent.sequencer; // Configure the key sideload sequencer to use UVM_SEQ_ARB_STRICT_FIFO arbitration. This makes // sure that we can inject our own sequence if we need to override the default for a bit. @@ -118,7 +118,7 @@ class otbn_env extends cip_base_env #( super.final_phase(phase); `DV_CHECK_FATAL(cfg.mem_util != null); - OtbnMemUtilFree(cfg.mem_util); + AccMemUtilFree(cfg.mem_util); cfg.mem_util = null; endfunction diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv b/hw/ip/acc/dv/uvm/env/acc_env_cfg.sv similarity index 86% rename from hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv rename to hw/ip/acc/dv/uvm/env/acc_env_cfg.sv index 1dd755c1709..2dbcdd5ee3b 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv +++ b/hw/ip/acc/dv/uvm/env/acc_env_cfg.sv @@ -3,45 +3,45 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); +class acc_env_cfg extends cip_base_env_cfg #(.RAL_T(acc_reg_block)); // ext component cfgs - rand otbn_model_agent_cfg model_agent_cfg; + rand acc_model_agent_cfg model_agent_cfg; - rand otbn_sideload_agent_cfg keymgr_sideload_agent_cfg; + rand acc_sideload_agent_cfg keymgr_sideload_agent_cfg; rand otp_key_agent_cfg key_cfg; - rand otbn_app_agent_cfg m_otbn_app_agent_cfg; + rand acc_app_agent_cfg m_acc_app_agent_cfg; virtual clk_rst_if otp_clk_rst_vif; - `uvm_object_utils_begin(otbn_env_cfg) + `uvm_object_utils_begin(acc_env_cfg) `uvm_object_utils_end `uvm_object_new - virtual otbn_trace_if trace_vif; - virtual otbn_loop_if loop_vif; - virtual otbn_alu_bignum_if alu_bignum_vif; - virtual otbn_controller_if controller_vif; - virtual otbn_mac_bignum_if mac_bignum_vif; - virtual otbn_rf_base_if rf_base_vif; - virtual otbn_escalate_if escalate_vif; - virtual otbn_rnd_if rnd_vif; - virtual otbn_ssctrl_if ssctrl_vif; + virtual acc_trace_if trace_vif; + virtual acc_loop_if loop_vif; + virtual acc_alu_bignum_if alu_bignum_vif; + virtual acc_controller_if controller_vif; + virtual acc_mac_bignum_if mac_bignum_vif; + virtual acc_rf_base_if rf_base_vif; + virtual acc_escalate_if escalate_vif; + virtual acc_rnd_if rnd_vif; + virtual acc_ssctrl_if ssctrl_vif; sram_ctrl_bkdr_util imem_util; sram_ctrl_bkdr_util dmem_util; // A handle to the scoreboard, used to flag expected errors. - otbn_scoreboard scoreboard; + acc_scoreboard scoreboard; // The directory in which to look for ELF files (set by the test in build_phase; controlled by the - // +otbn_elf_dir plusarg). - string otbn_elf_dir; + // +acc_elf_dir plusarg). + string acc_elf_dir; - // An OtbnMemUtil handle for loading ELF files (set by the test in build_phase) + // An AccMemUtil handle for loading ELF files (set by the test in build_phase) chandle mem_util; // What fraction of the time should sequences use a back-door method to load up the ELF, rather @@ -63,12 +63,12 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); int unsigned allow_no_sideload_key_pct = 50; // By default, FIPS field is always high when we request RND EDN word. This is because if it is - // low, OTBN generates a recoverable error. We want to control this knob whenever we want to see + // low, ACC generates a recoverable error. We want to control this knob whenever we want to see // that behaviour but not anytime else. int unsigned rnd_fips_pct = 100; // The hierarchical scope of the DUT instance in the testbench. This is used when constructing the - // DPI wrapper (in otbn_env::build_phase) to tell it where to find the DUT for backdoor loading + // DPI wrapper (in acc_env::build_phase) to tell it where to find the DUT for backdoor loading // memories. The default value matches the block-level testbench, but it can be overridden in a // test class for e.g. system level tests. string dut_instance_hier = "tb.dut"; @@ -87,7 +87,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); // Set the list of alerts, needed by the CIP base code. This needs to match the names assigned // in tb.sv (where we bind in the alert interfaces and register each with the UVM DB). - list_of_alerts = otbn_env_pkg::LIST_OF_ALERTS; + list_of_alerts = acc_env_pkg::LIST_OF_ALERTS; // Tell the CIP base code how many interrupts we have (defaults to zero) num_interrupts = 1; @@ -96,9 +96,9 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); tl_intg_alert_name = "fatal"; sec_cm_alert_name = "fatal"; - model_agent_cfg = otbn_model_agent_cfg ::type_id::create("model_agent_cfg"); - m_otbn_app_agent_cfg = otbn_app_agent_cfg::type_id::create("m_otbn_app_agent_cfg"); - keymgr_sideload_agent_cfg = otbn_sideload_agent_cfg::type_id::create( + model_agent_cfg = acc_model_agent_cfg ::type_id::create("model_agent_cfg"); + m_acc_app_agent_cfg = acc_app_agent_cfg::type_id::create("m_acc_app_agent_cfg"); + keymgr_sideload_agent_cfg = acc_sideload_agent_cfg::type_id::create( "keymgr_sideload_agent_cfg"); @@ -113,7 +113,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); // Tell the CIP base code the fields that it should expect to see, together with their expected // values, in case of a TL fault. tl_intg_alert_fields[ral.fatal_alert_cause.bus_intg_violation] = 1; - tl_intg_alert_fields[ral.status.status] = otbn_pkg::StatusLocked; + tl_intg_alert_fields[ral.status.status] = acc_pkg::StatusLocked; // Configure the URND EDN connection to be quick. Unlike RND, there's nothing much that can be // going on while we're waiting for a URND seed, so there's no real benefit to modelling the @@ -123,7 +123,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); endfunction // Constrain the randomness of FIPS for RND. This is needed because otherwise FIPS would have - // a fifty percent chance of being low. That would result with OTBN getting a recoverable error + // a fifty percent chance of being low. That would result with ACC getting a recoverable error // half the time. function void gen_rnd_edn_rsp(); bit fips; @@ -137,7 +137,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); function logic poll_rnd_edn_req(); logic rnd_req; - string rnd_req_hier = $sformatf("%s.u_otbn_core.u_otbn_rnd.edn_rnd_req_o", dut_instance_hier); + string rnd_req_hier = $sformatf("%s.u_acc_core.u_acc_rnd.edn_rnd_req_o", dut_instance_hier); `DV_CHECK_FATAL(uvm_hdl_read(rnd_req_hier, rnd_req), "Failed to read RND EDN request from DUT") return rnd_req; endfunction @@ -173,7 +173,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); // Read a word from IMEM, descrambling but including integrity bits. function logic [38:0] read_imem_word(bit [ImemIndexWidth-1:0] idx, logic [127:0] key, - otbn_pkg::otbn_imem_nonce_t nonce); + acc_pkg::acc_imem_nonce_t nonce); logic [ImemIndexWidth-1:0] phys_idx; logic [38:0] scr_data, clr_data; @@ -204,7 +204,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); // Read a word from DMEM, descrambling but including integrity bits. function logic [311:0] read_dmem_word(bit [DmemIndexWidth-1:0] idx, logic [127:0] key, - otbn_pkg::otbn_dmem_nonce_t nonce); + acc_pkg::acc_dmem_nonce_t nonce); logic [DmemIndexWidth-1:0] phys_idx; logic [311:0] scr_data, clr_data; @@ -235,7 +235,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); function void write_imem_word(bit [ImemIndexWidth-1:0] idx, logic [38:0] clr_data, logic [127:0] key, - otbn_pkg::otbn_imem_nonce_t nonce, + acc_pkg::acc_imem_nonce_t nonce, bit [38:0] flip_bits = 0); logic [ImemIndexWidth-1:0] phys_idx; @@ -270,7 +270,7 @@ class otbn_env_cfg extends cip_base_env_cfg #(.RAL_T(otbn_reg_block)); function void write_dmem_word(bit [DmemIndexWidth-1:0] idx, logic [311:0] clr_data, logic [127:0] key, - otbn_pkg::otbn_dmem_nonce_t nonce, + acc_pkg::acc_dmem_nonce_t nonce, bit [311:0] flip_bits = 0); logic [DmemIndexWidth-1:0] phys_idx; diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv b/hw/ip/acc/dv/uvm/env/acc_env_cov.sv similarity index 98% rename from hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv rename to hw/ip/acc/dv/uvm/env/acc_env_cov.sv index 45aef2a40d8..273c427b468 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_env_cov.sv +++ b/hw/ip/acc/dv/uvm/env/acc_env_cov.sv @@ -8,9 +8,9 @@ * Covergroups may also be wrapped inside helper classes if needed. */ -class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); - `uvm_component_utils(otbn_env_cov) - import otbn_pqc_env_pkg::*; +class acc_env_cov extends cip_base_env_cov #(.CFG_T(acc_env_cfg)); + `uvm_component_utils(acc_env_cov) + import acc_pqc_env_pkg::*; // A field for each known mnemonic, cast to a mnem_str_t. We have to do this because VCS (at // least) complains if you put an uncast string literal in a position where it expects an integral @@ -331,7 +331,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); bins rnd = {15}; \ bins urnd = {16}; \ bins invalid = {-1}; \ - ignore_bins no_pqc = {12, 13, 14} iff (!OtbnPQCEn); \ + ignore_bins no_pqc = {12, 13, 14} iff (!AccPQCEn); \ illegal_bins bad = default; \ } @@ -369,7 +369,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); bins kmac_digest = {10}; \ bins acch = {11}; \ bins invalid = {-1}; \ - ignore_bins no_pqc = {8, 9, 10, 11} iff (!OtbnPQCEn); \ + ignore_bins no_pqc = {8, 9, 10, 11} iff (!AccPQCEn); \ illegal_bins bad = default; \ } @@ -437,18 +437,18 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); // CMD external CSR covergroup ext_csr_cmd_cg - with function sample(otbn_pkg::cmd_e value, + with function sample(acc_pkg::cmd_e value, access_e access_type, operational_state_e state); // Expect to see each genuine command, plus at least one bogus value cmd_cp: coverpoint {value} { - bins CmdExecute = {otbn_pkg::CmdExecute}; - bins CmdSecWipeDmem = {otbn_pkg::CmdSecWipeDmem}; - bins CmdSecWipeImem = {otbn_pkg::CmdSecWipeImem}; - bins BogusCmd = {[0:$]} with (!(item inside {otbn_pkg::CmdExecute, - otbn_pkg::CmdSecWipeDmem, - otbn_pkg::CmdSecWipeImem})); + bins CmdExecute = {acc_pkg::CmdExecute}; + bins CmdSecWipeDmem = {acc_pkg::CmdSecWipeDmem}; + bins CmdSecWipeImem = {acc_pkg::CmdSecWipeImem}; + bins BogusCmd = {[0:$]} with (!(item inside {acc_pkg::CmdExecute, + acc_pkg::CmdSecWipeDmem, + acc_pkg::CmdSecWipeImem})); } access_type_cp: coverpoint access_type; @@ -472,7 +472,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); // STATUS external CSR covergroup ext_csr_status_cg - with function sample(otbn_pkg::status_e value, + with function sample(acc_pkg::status_e value, access_e access_type); // Read each possible status value status_cp: coverpoint value iff (access_type == AccessSoftwareRead); @@ -483,7 +483,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); // ERR_BITS external CSR covergroup ext_csr_err_bits_cg - with function sample(otbn_pkg::err_bits_t value, + with function sample(acc_pkg::err_bits_t value, logic [31:0] old_value, access_e access_type, operational_state_e state); @@ -619,8 +619,8 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); covergroup scratchpad_writes_cg with function sample(uvm_reg_addr_t addr); // See attempted writes to the bottom and top address in the scratchpad memory addr_cp: coverpoint addr { - bins low = {OTBN_DMEM_OFFSET + OTBN_DMEM_SIZE}; - bins high = {OTBN_DMEM_OFFSET + DmemSizeByte - 4}; + bins low = {ACC_DMEM_OFFSET + ACC_DMEM_SIZE}; + bins high = {ACC_DMEM_OFFSET + DmemSizeByte - 4}; } endgroup @@ -680,10 +680,10 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); with function sample(logic urnd_all_zero, logic insn_addr_err, logic scramble_state_err, - otbn_pkg::predec_err_t predec_err, - otbn_pkg::missed_gnt_t missed_gnt, - otbn_pkg::controller_bad_int_t controller_bad_int, - otbn_pkg::start_stop_bad_int_t start_stop_bad_int, + acc_pkg::predec_err_t predec_err, + acc_pkg::missed_gnt_t missed_gnt, + acc_pkg::controller_bad_int_t controller_bad_int, + acc_pkg::start_stop_bad_int_t start_stop_bad_int, logic rf_base_spurious_we_err, logic rf_bignum_spurious_we_err); @@ -721,7 +721,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); endgroup // This covergroup tracks each possible "Internal Integrity Errors" with probes from RTL. - covergroup internal_intg_err_cg with function sample(otbn_pkg::internal_intg_err_t intg_err); + covergroup internal_intg_err_cg with function sample(acc_pkg::internal_intg_err_t intg_err); `DEF_SEEN_CP(rf_base_intg_err_cp, intg_err.rf_base_intg_err) `DEF_SEEN_CP(rf_bignum_intg_err_cp, intg_err.rf_bignum_intg_err) @@ -1072,7 +1072,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); mode_cp: coverpoint insn_data[25]; // Specifies lane mode or pairwise // Valid types are defined by the encoding scheme of bn.mulv - // hw/ip/otbn/data/bignum-insns.yml + // hw/ip/acc/data/bignum-insns.yml type_cp: coverpoint insn_data[31:26] { bins legal_enc[] = { [0:11], @@ -1108,7 +1108,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); mode_cp: coverpoint insn_data[25]; // Specifies lane mode or pairwise // Valid types are defined by the encoding scheme of bn.mulv.l - // hw/ip/otbn/data/bignum-insns.yml + // hw/ip/acc/data/bignum-insns.yml type_cp: coverpoint insn_data[31:26] { bins legal_enc[] = { [0:11], @@ -1125,7 +1125,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); } // If the lane index is greater than or equal to 8 then the encoding type can not - // be any .8 variant from hw/ip/otbn/data/bignum-insns.yml + // be any .8 variant from hw/ip/acc/data/bignum-insns.yml type_index_cross: cross type_cp, ln_idx_cp { illegal_bins bad_type_idx = binsof(ln_idx_cp) intersect {[8:15]} && @@ -2364,7 +2364,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); enc_wcsr_cg = new; enc_u_cg = new; - if (OtbnPQCEn) begin + if (AccPQCEn) begin pairwise_insn_pqc_cg = new; enc_bnam_pqc_cg = new; enc_bnmulv_cg = new; @@ -2456,7 +2456,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); insn_encodings[mnem_bn_wsrr] = "wcsr"; insn_encodings[mnem_bn_wsrw] = "wcsr"; - if (OtbnPQCEn) begin + if (AccPQCEn) begin insn_encodings[mnem_bn_addv] = "bnam"; insn_encodings[mnem_bn_subv] = "bnam"; insn_encodings[mnem_bn_mulv] = "bnmulv"; @@ -2508,7 +2508,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); // // This runs just before calling predict to update the RAL model, so the old value of the CSR can // be read with csr.get_mirrored_value(). - function void on_ext_csr_access(uvm_reg csr, otbn_env_pkg::access_e access_type, + function void on_ext_csr_access(uvm_reg csr, acc_env_pkg::access_e access_type, logic [31:0] data, operational_state_e state); csr_str_t csr_name = csr_str_t'(csr.get_name()); @@ -2516,18 +2516,18 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); case (csr_name) "cmd": begin - ext_csr_cmd_cg.sample(otbn_pkg::cmd_e'(data), access_type, state); + ext_csr_cmd_cg.sample(acc_pkg::cmd_e'(data), access_type, state); end "ctrl": begin track_write_then_read = 1'b1; ext_csr_ctrl_cg.sample(data[0], access_type, state); end "status": begin - ext_csr_status_cg.sample(otbn_pkg::status_e'(data), access_type); + ext_csr_status_cg.sample(acc_pkg::status_e'(data), access_type); end "err_bits": begin last_err_bits = data; - ext_csr_err_bits_cg.sample(otbn_pkg::err_bits_t'(data), + ext_csr_err_bits_cg.sample(acc_pkg::err_bits_t'(data), csr.get_mirrored_value(), access_type, state); end "fatal_alert_cause": begin @@ -2614,7 +2614,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); // iss_item is to extract the instruction mnemonic (to avoid needing it, we'd have to implement a // decoder in the coverage code, which doesn't seem like the right thing to do). // - function void on_insn(otbn_model_item iss_item, otbn_trace_item rtl_item); + function void on_insn(acc_model_item iss_item, acc_trace_item rtl_item); string encoding; mnem_str_t mnem; @@ -2667,7 +2667,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); // Track pairwise instructions. last_mnem is zero if this is the first instruction since // starting an operation. if (last_mnem != '0) begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin pairwise_insn_pqc_cg.sample(last_mnem, mnem); end else begin pairwise_insn_cg.sample(last_mnem, mnem); @@ -2692,7 +2692,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); rtl_item.wdr_operand_a, rtl_item.flags_write_data); "bnam": begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin enc_bnam_pqc_cg.sample(mnem, insn_data, rtl_item.wdr_operand_a, rtl_item.wdr_operand_b); end else begin enc_bnam_cg.sample(mnem, insn_data, rtl_item.wdr_operand_a, rtl_item.wdr_operand_b); @@ -2714,7 +2714,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); rtl_item.wdr_operand_a, rtl_item.wdr_operand_b, rtl_item.flags_write_data); "bnav": begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin enc_bnav_cg.sample(mnem, insn_data, rtl_item.wdr_operand_a); end else begin `dv_fatal($sformatf("Unknown encoding (%0s) for instruction `%0s'", encoding, mnem), @@ -2730,7 +2730,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); "bnmovr": enc_bnmovr_cg.sample(mnem, insn_data, rtl_item.gpr_operand_a, rtl_item.gpr_operand_b); "bnmulv": begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin enc_bnmulv_cg.sample(mnem, insn_data, rtl_item.wdr_operand_a, rtl_item.wdr_operand_b); end else begin `dv_fatal($sformatf("Unknown encoding (%0s) for instruction `%0s'", encoding, mnem), @@ -2738,7 +2738,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); end end "bnmulvl": begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin enc_bnmulvl_cg.sample(mnem, insn_data, rtl_item.wdr_operand_a); end else begin `dv_fatal($sformatf("Unknown encoding (%0s) for instruction `%0s'", encoding, mnem), @@ -2752,7 +2752,7 @@ class otbn_env_cov extends cip_base_env_cov #(.CFG_T(otbn_env_cfg)); rtl_item.wdr_operand_a, rtl_item.wdr_operand_b, rtl_item.flags_read_data); "bntrn": begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin enc_bntrn_cg.sample(mnem, insn_data, rtl_item.wdr_operand_a, rtl_item.wdr_operand_b); end else begin `dv_fatal($sformatf("Unknown encoding (%0s) for instruction `%0s'", encoding, mnem), diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv b/hw/ip/acc/dv/uvm/env/acc_env_pkg.sv similarity index 59% rename from hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv rename to hw/ip/acc/dv/uvm/env/acc_env_pkg.sv index 866b04a1601..103f8804a11 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_env_pkg.sv +++ b/hw/ip/acc/dv/uvm/env/acc_env_pkg.sv @@ -3,7 +3,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -package otbn_env_pkg; +package acc_env_pkg; // dep packages import uvm_pkg::*; import top_pkg::*; @@ -14,23 +14,23 @@ package otbn_env_pkg; import tl_agent_pkg::*; import cip_base_pkg::*; import push_pull_agent_pkg::*; - import otbn_model_agent_pkg::*; - import otbn_memutil_pkg::*; + import acc_model_agent_pkg::*; + import acc_memutil_pkg::*; import sram_ctrl_bkdr_util_pkg::sram_ctrl_bkdr_util; import prim_util_pkg::vbits; import prim_mubi_pkg::*; import key_sideload_agent_pkg::*; - import otbn_app_agent_pkg::*; + import acc_app_agent_pkg::*; import sec_cm_pkg::*; // autogenerated RAL model - import otbn_reg_pkg::*; - import otbn_ral_pkg::*; + import acc_reg_pkg::*; + import acc_ral_pkg::*; - import otbn_pkg::WLEN, otbn_pkg::ExtWLEN, otbn_pkg::BaseIntgWidth, otbn_pkg::BaseWordsPerWLEN; - import otbn_pkg::flags_t; + import acc_pkg::WLEN, acc_pkg::ExtWLEN, acc_pkg::BaseIntgWidth, acc_pkg::BaseWordsPerWLEN; + import acc_pkg::flags_t; - import otbn_pkg::status_e; + import acc_pkg::status_e; import bus_params_pkg::BUS_AW, bus_params_pkg::BUS_DW, bus_params_pkg::BUS_DBW; import top_pkg::TL_AIW; @@ -39,40 +39,40 @@ package otbn_env_pkg; `include "uvm_macros.svh" `include "dv_macros.svh" - // Imports for the functions defined in otbn_test_helpers.cc. There are documentation comments + // Imports for the functions defined in acc_test_helpers.cc. There are documentation comments // explaining what the functions do there. - import "DPI-C" function chandle OtbnTestHelperMake(string path); - import "DPI-C" function void OtbnTestHelperFree(chandle helper); - import "DPI-C" function int OtbnTestHelperCountFilesInDir(chandle helper); - import "DPI-C" function string OtbnTestHelperGetFilePath(chandle helper, int index); + import "DPI-C" function chandle AccTestHelperMake(string path); + import "DPI-C" function void AccTestHelperFree(chandle helper); + import "DPI-C" function int AccTestHelperCountFilesInDir(chandle helper); + import "DPI-C" function string AccTestHelperGetFilePath(chandle helper, int index); // parameters - parameter uint NUM_ALERTS = otbn_reg_pkg::NumAlerts; + parameter uint NUM_ALERTS = acc_reg_pkg::NumAlerts; parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"fatal", "recov"}; parameter uint NUM_EDN = 2; - // Number of bits in the otp_ctrl_pkg::otbn_otp_key_rsp_t struct: - parameter int KEY_RSP_DATA_SIZE = $bits(otp_ctrl_pkg::otbn_otp_key_rsp_t); + // Number of bits in the otp_ctrl_pkg::acc_otp_key_rsp_t struct: + parameter int KEY_RSP_DATA_SIZE = $bits(otp_ctrl_pkg::acc_otp_key_rsp_t); // typedefs - typedef virtual otbn_ssctrl_if ssctrl_vif; - typedef virtual otbn_escalate_if escalate_vif; + typedef virtual acc_ssctrl_if ssctrl_vif; + typedef virtual acc_escalate_if escalate_vif; typedef logic [TL_AIW-1:0] tl_source_t; - typedef key_sideload_agent#(keymgr_pkg::otbn_key_req_t) otbn_sideload_agent; - typedef key_sideload_agent_cfg#(keymgr_pkg::otbn_key_req_t) otbn_sideload_agent_cfg; + typedef key_sideload_agent#(keymgr_pkg::acc_key_req_t) acc_sideload_agent; + typedef key_sideload_agent_cfg#(keymgr_pkg::acc_key_req_t) acc_sideload_agent_cfg; typedef push_pull_agent#(.DeviceDataWidth(KEY_RSP_DATA_SIZE)) otp_key_agent; typedef push_pull_agent_cfg#(.DeviceDataWidth(KEY_RSP_DATA_SIZE)) otp_key_agent_cfg; typedef virtual push_pull_if#(.DeviceDataWidth(KEY_RSP_DATA_SIZE)) otp_key_vif; - // Expected data for a pending read (see exp_read_values in otbn_scoreboard.sv) + // Expected data for a pending read (see exp_read_values in acc_scoreboard.sv) typedef struct packed { bit upd; logic chk; logic [BUS_DW-1:0] val; - } otbn_exp_read_data_t; + } acc_exp_read_data_t; - // Used for coverage in otbn_env_cov.sv (where we need to convert strings giving mnemonics and CSR + // Used for coverage in acc_env_cov.sv (where we need to convert strings giving mnemonics and CSR // names to a packed integral type) parameter int unsigned MNEM_STR_LEN = 16; typedef bit [MNEM_STR_LEN*8-1:0] mnem_str_t; @@ -81,7 +81,7 @@ package otbn_env_pkg; typedef bit [CSR_STR_LEN*8-1:0] csr_str_t; // A very simple wrapper around a word that has been loaded from the input binary and needs - // storing to OTBN's IMEM or DMEM. + // storing to ACC's IMEM or DMEM. typedef struct packed { // Is this destined for IMEM? bit for_imem; @@ -90,7 +90,7 @@ package otbn_env_pkg; // The data to be loaded bit [31:0] data; - } otbn_loaded_word; + } acc_loaded_word; // The mapping from EDN agent indices to RND / URND connections typedef enum { @@ -118,16 +118,16 @@ package otbn_env_pkg; function automatic operational_state_e get_operational_state(status_e status); unique case (status) - otbn_pkg::StatusBusyExecute, - otbn_pkg::StatusBusySecWipeDmem, - otbn_pkg::StatusBusySecWipeImem, - otbn_pkg::StatusBusySecWipeInt: + acc_pkg::StatusBusyExecute, + acc_pkg::StatusBusySecWipeDmem, + acc_pkg::StatusBusySecWipeImem, + acc_pkg::StatusBusySecWipeInt: return OperationalStateBusy; - otbn_pkg::StatusLocked: + acc_pkg::StatusLocked: return OperationalStateLocked; - otbn_pkg::StatusIdle: + acc_pkg::StatusIdle: return OperationalStateIdle; default: ; endcase @@ -139,24 +139,24 @@ package otbn_env_pkg; } access_e; // Forward declaration to allow the config to hold a scoreboard handle. - typedef class otbn_scoreboard; + typedef class acc_scoreboard; - localparam int unsigned ImemSizeByte = int'(otbn_reg_pkg::OTBN_IMEM_SIZE); + localparam int unsigned ImemSizeByte = int'(acc_reg_pkg::ACC_IMEM_SIZE); localparam int unsigned DmemSizeByte = - int'(otbn_reg_pkg::OTBN_DMEM_SIZE) + otbn_pkg::DmemScratchSizeByte; + int'(acc_reg_pkg::ACC_DMEM_SIZE) + acc_pkg::DmemScratchSizeByte; parameter int unsigned ImemIndexWidth = vbits(ImemSizeByte / 4); parameter int unsigned DmemIndexWidth = vbits(DmemSizeByte / 32); // package sources - `include "otbn_env_cfg.sv" - `include "otbn_trace_item.sv" - `include "otbn_env_cov.sv" - `include "otbn_trace_monitor.sv" - `include "otbn_virtual_sequencer.sv" - `include "otbn_scoreboard.sv" - `include "otbn_env.sv" - - `include "otbn_vseq_list.sv" + `include "acc_env_cfg.sv" + `include "acc_trace_item.sv" + `include "acc_env_cov.sv" + `include "acc_trace_monitor.sv" + `include "acc_virtual_sequencer.sv" + `include "acc_scoreboard.sv" + `include "acc_env.sv" + + `include "acc_vseq_list.sv" endpackage diff --git a/hw/ip/otbn/dv/uvm/env/otbn_escalate_if.sv b/hw/ip/acc/dv/uvm/env/acc_escalate_if.sv similarity index 93% rename from hw/ip/otbn/dv/uvm/env/otbn_escalate_if.sv rename to hw/ip/acc/dv/uvm/env/acc_escalate_if.sv index 5e4e7d8bff0..8700d14bf06 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_escalate_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_escalate_if.sv @@ -4,7 +4,7 @@ // // An interface for lifecycle controller related ports -interface otbn_escalate_if ( +interface acc_escalate_if ( input logic clk_i, input logic rst_ni ); @@ -27,7 +27,7 @@ interface otbn_escalate_if ( .f_weight(f_weight), .other_weight(other_weight)); end, @(negedge rst_ni);, "Not setting req signal because we've gone into reset", - "otbn_escalate_if") + "acc_escalate_if") endtask task automatic randomize_enable_after_n_clocks(int unsigned n, int t_weight = 2, int f_weight = 2, @@ -38,7 +38,7 @@ interface otbn_escalate_if ( .f_weight(f_weight), .other_weight(other_weight)); end, @(negedge rst_ni);, "Not setting enable signal because we've gone into reset", - "otbn_escalate_if") + "acc_escalate_if") endtask diff --git a/hw/ip/otbn/dv/uvm/env/otbn_insn_cnt_if.sv b/hw/ip/acc/dv/uvm/env/acc_insn_cnt_if.sv similarity index 94% rename from hw/ip/otbn/dv/uvm/env/otbn_insn_cnt_if.sv rename to hw/ip/acc/dv/uvm/env/acc_insn_cnt_if.sv index f5cd915ff8f..fe8459bc7fa 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_insn_cnt_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_insn_cnt_if.sv @@ -6,7 +6,7 @@ `include "prim_assert.sv" -interface otbn_insn_cnt_if ( +interface acc_insn_cnt_if ( input clk_i, input rst_ni, @@ -17,7 +17,7 @@ interface otbn_insn_cnt_if ( input bit [31:0] model_insn_cnt_i ); - // Check that the model and OTBN have matching instruction counters + // Check that the model and ACC have matching instruction counters `ASSERT(InsnCntMatches_A, model_insn_cnt_i == insn_cnt_i) // As well as exposing the count itself, we've also exposed the "increment me" signal diff --git a/hw/ip/otbn/dv/uvm/env/otbn_loop_if.sv b/hw/ip/acc/dv/uvm/env/acc_loop_if.sv similarity index 91% rename from hw/ip/otbn/dv/uvm/env/otbn_loop_if.sv rename to hw/ip/acc/dv/uvm/env/acc_loop_if.sv index fb737e89462..8db490fb33f 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_loop_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_loop_if.sv @@ -2,17 +2,17 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Bound into the otbn_loop_controller and used to help collect loop information for coverage. +// Bound into the acc_loop_controller and used to help collect loop information for coverage. `include "prim_assert.sv" -interface otbn_loop_if #( - localparam int LoopStackIdxWidth = prim_util_pkg::vbits(otbn_pkg::LoopStackDepth) +interface acc_loop_if #( + localparam int LoopStackIdxWidth = prim_util_pkg::vbits(acc_pkg::LoopStackDepth) ) ( input clk_i, input rst_ni, - // Signal names from the otbn_loop_controller module (where we are bound) + // Signal names from the acc_loop_controller module (where we are bound) input logic [31:0] insn_addr_i, input logic at_current_loop_end_insn, input logic current_loop_valid, @@ -22,7 +22,7 @@ interface otbn_loop_if #( input logic loop_start_req_i, input logic loop_start_commit_i, input logic [31:0] loop_iterations_i, - input logic otbn_stall_i, + input logic acc_stall_i, input logic [31:0] current_loop_start, input logic [31:0] current_loop_end, @@ -37,14 +37,14 @@ interface otbn_loop_if #( input logic loop_stack_pop ); - function automatic otbn_env_pkg::stack_fullness_e get_fullness(); + function automatic acc_env_pkg::stack_fullness_e get_fullness(); if (loop_stack_full) begin - return otbn_env_pkg::StackFull; + return acc_env_pkg::StackFull; end if (current_loop_valid) begin - return otbn_env_pkg::StackPartial; + return acc_env_pkg::StackPartial; end - return otbn_env_pkg::StackEmpty; + return acc_env_pkg::StackEmpty; endfunction // Are assertions in the loop counters currently enabled? @@ -58,9 +58,9 @@ interface otbn_loop_if #( return; end if (enable) begin - $asserton(0, tb.dut.u_otbn_core.u_otbn_controller.u_otbn_loop_controller); + $asserton(0, tb.dut.u_acc_core.u_acc_controller.u_acc_loop_controller); end else begin - $assertoff(0, tb.dut.u_otbn_core.u_otbn_controller.u_otbn_loop_controller); + $assertoff(0, tb.dut.u_acc_core.u_acc_controller.u_acc_loop_controller); end loop_counter_assertions_enabled = enable; endfunction @@ -109,7 +109,7 @@ interface otbn_loop_if #( current_loop_valid && next_loop_valid && (insn_addr_i != current_loop_end) && (insn_addr_i == next_loop_end) && - !otbn_stall_i) + !acc_stall_i) // Jump into a loop body from outside. We don't bother checking that this is a jump: since the // code sequence is fixed, we know we can't get here through a straight line instruction because diff --git a/hw/ip/otbn/dv/uvm/env/otbn_mac_bignum_if.sv b/hw/ip/acc/dv/uvm/env/acc_mac_bignum_if.sv similarity index 71% rename from hw/ip/otbn/dv/uvm/env/otbn_mac_bignum_if.sv rename to hw/ip/acc/dv/uvm/env/acc_mac_bignum_if.sv index 6bba141ac45..4984814db81 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_mac_bignum_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_mac_bignum_if.sv @@ -3,20 +3,20 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Bound into the otbn_mac_bignum and used to help collect ISPR information for coverage. +// Bound into the acc_mac_bignum and used to help collect ISPR information for coverage. -interface otbn_mac_bignum_if #( +interface acc_mac_bignum_if #( // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = otbn_pqc_env_pkg::OtbnPQCEn, - localparam int WLEN = OtbnPQCEn ? 512 : 256 + parameter bit AccPQCEn = acc_pqc_env_pkg::AccPQCEn, + localparam int WLEN = AccPQCEn ? 512 : 256 ) ( input clk_i, input rst_ni, - // Signal names from the otbn_mac_bignum module (where we are bound) + // Signal names from the acc_mac_bignum module (where we are bound) input logic [WLEN-1:0] adder_op_a, input logic [WLEN-1:0] adder_op_b, - input logic [otbn_pkg::ExtWLEN-1:0] acc_intg_q, + input logic [acc_pkg::ExtWLEN-1:0] acc_intg_q, input logic acc_used ); @@ -27,20 +27,20 @@ interface otbn_mac_bignum_if #( // Force the `acc_intg_q` register to `should_val`. This function needs to be static because its // argument must live as least as long as the `force` statement is in effect. - function static void force_acc_intg_q(input logic [otbn_pkg::ExtWLEN-1:0] should_val); - force u_otbn_mac_bignum.acc_intg_q = should_val; + function static void force_acc_intg_q(input logic [acc_pkg::ExtWLEN-1:0] should_val); + force u_acc_mac_bignum.acc_intg_q = should_val; endfunction // Release the forcing of the `acc_intg_q` register. function automatic void release_acc_intg_q(); - release u_otbn_mac_bignum.acc_intg_q; + release u_acc_mac_bignum.acc_intg_q; endfunction // Wait for the `acc_used` signal to be high (outside a reset) or until `max_cycles` clock cycles // have passed. When this task returns, the `used_words` output indicates which words are being // used. task automatic wait_for_acc_used(input int unsigned max_cycles, - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words); + output bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words); int unsigned cycle_cnt = 0; while (1) begin @(negedge clk_i); diff --git a/hw/ip/otbn/dv/uvm/env/otbn_rf_base_if.sv b/hw/ip/acc/dv/uvm/env/acc_rf_base_if.sv similarity index 64% rename from hw/ip/otbn/dv/uvm/env/otbn_rf_base_if.sv rename to hw/ip/acc/dv/uvm/env/acc_rf_base_if.sv index 3dae95b1113..c2b8ec2b454 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_rf_base_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_rf_base_if.sv @@ -2,13 +2,13 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Bound into the otbn_rf_base and used to help collect call stack information for coverage. +// Bound into the acc_rf_base and used to help collect call stack information for coverage. -interface otbn_rf_base_if ( +interface acc_rf_base_if ( input clk_i, input rst_ni, - // Signal names from the otbn_rf_base module (where we are bound) + // Signal names from the acc_rf_base module (where we are bound) input logic pop_stack_a, input logic pop_stack_b, input logic push_stack_reqd, @@ -16,7 +16,7 @@ interface otbn_rf_base_if ( input logic stack_data_valid ); - function automatic otbn_env_pkg::call_stack_flags_t get_call_stack_flags(); + function automatic acc_env_pkg::call_stack_flags_t get_call_stack_flags(); return '{ pop_a: pop_stack_a, pop_b: pop_stack_b, @@ -24,40 +24,40 @@ interface otbn_rf_base_if ( }; endfunction - function automatic otbn_env_pkg::stack_fullness_e get_call_stack_fullness(); + function automatic acc_env_pkg::stack_fullness_e get_call_stack_fullness(); if (stack_full) begin - return otbn_env_pkg::StackFull; + return acc_env_pkg::StackFull; end if (stack_data_valid) begin - return otbn_env_pkg::StackPartial; + return acc_env_pkg::StackPartial; end - return otbn_env_pkg::StackEmpty; + return acc_env_pkg::StackEmpty; endfunction // Force the `rd_data_a_intg_o` signal to `should_val`. This function needs to be static because // its argument must live as least as long as the `force` statement is in effect. function static void force_rf_base_rd_data_a_intg( - input logic [otbn_pkg::BaseIntgWidth-1:0] should_val + input logic [acc_pkg::BaseIntgWidth-1:0] should_val ); - force u_otbn_rf_base.rd_data_a_intg_o = should_val; + force u_acc_rf_base.rd_data_a_intg_o = should_val; endfunction // Force the `rd_data_b_intg_o` signal to `should_val`. This function needs to be static because // its argument must live as least as long as the `force` statement is in effect. function static void force_rf_base_rd_data_b_intg( - input logic [otbn_pkg::BaseIntgWidth-1:0] should_val + input logic [acc_pkg::BaseIntgWidth-1:0] should_val ); - force u_otbn_rf_base.rd_data_b_intg_o = should_val; + force u_acc_rf_base.rd_data_b_intg_o = should_val; endfunction // Release the forcing of the `rd_data_a_intg_o` signal. function automatic void release_rf_base_rd_data_a_intg(); - release u_otbn_rf_base.rd_data_a_intg_o; + release u_acc_rf_base.rd_data_a_intg_o; endfunction // Release the forcing of the `rd_data_b_intg_o` signal. function automatic void release_rf_base_rd_data_b_intg(); - release u_otbn_rf_base.rd_data_b_intg_o; + release u_acc_rf_base.rd_data_b_intg_o; endfunction endinterface diff --git a/hw/ip/otbn/dv/uvm/env/otbn_rnd_if.sv b/hw/ip/acc/dv/uvm/env/acc_rnd_if.sv similarity index 96% rename from hw/ip/otbn/dv/uvm/env/otbn_rnd_if.sv rename to hw/ip/acc/dv/uvm/env/acc_rnd_if.sv index dd3d0bbbd5a..c3362f8ca5c 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_rnd_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_rnd_if.sv @@ -2,15 +2,15 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Bound into otbn_rnd_module and used to help collect events for coverage +// Bound into acc_rnd_module and used to help collect events for coverage `include "prim_assert.sv" -interface otbn_rnd_if ( +interface acc_rnd_if ( input logic clk_i, input logic rst_ni, - // The signals below are all bound in with .* so the names match those in otbn_rnd.sv + // The signals below are all bound in with .* so the names match those in acc_rnd.sv input logic rnd_req_i, input logic rnd_prefetch_req_i, input logic edn_rnd_ack_i, @@ -52,8 +52,8 @@ interface otbn_rnd_if ( // [EDN DATA TAKEN]: Random data arrives from the EDN that we take // [EDN DATA IGNORED]: Random data arrives from the EDN that we ignore // - // The easiest way to spot these events is to look at the ports of the otbn_rnd module. [RD RND] - // happens when we see the rnd_req_i signal of the otbn_rnd module go high. [WR RND_PREFETCH] + // The easiest way to spot these events is to look at the ports of the acc_rnd module. [RD RND] + // happens when we see the rnd_req_i signal of the acc_rnd module go high. [WR RND_PREFETCH] // happens if rnd_prefetch_req_i goes high. [EDN DATA TAKEN] happens when edn_rnd_ack_i goes high // and edn_rnd_data_ignore_q is false. [EDN DATA IGNORED] happens if edn_rnd_ack_i goes high and // edn_rnd_data_ignore_q is true. diff --git a/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv b/hw/ip/acc/dv/uvm/env/acc_scoreboard.sv similarity index 91% rename from hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv rename to hw/ip/acc/dv/uvm/env/acc_scoreboard.sv index 3ef52b5295d..ac3928c5336 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv +++ b/hw/ip/acc/dv/uvm/env/acc_scoreboard.sv @@ -2,22 +2,22 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_scoreboard extends cip_base_scoreboard #( - .CFG_T(otbn_env_cfg), - .RAL_T(otbn_reg_block), - .COV_T(otbn_env_cov) +class acc_scoreboard extends cip_base_scoreboard #( + .CFG_T(acc_env_cfg), + .RAL_T(acc_reg_block), + .COV_T(acc_env_cov) ); - `uvm_component_utils(otbn_scoreboard) + `uvm_component_utils(acc_scoreboard) - uvm_tlm_analysis_fifo #(otbn_model_item) model_fifo; - uvm_tlm_analysis_fifo #(otbn_trace_item) trace_fifo; + uvm_tlm_analysis_fifo #(acc_model_item) model_fifo; + uvm_tlm_analysis_fifo #(acc_trace_item) trace_fifo; // Queues of trace items copied from the model_fifo and trace_fifo, respectively. These get paired // up in pop_trace_queues(). process_model_fifo and process_trace_fifo copy items from the // (blocking) FIFOs to the queues and then call pop_trace_queues(), which avoids having to poll // the (non-blocking) queues directly. - otbn_model_item iss_trace_queue[$]; - otbn_trace_item rtl_trace_queue[$]; + acc_model_item iss_trace_queue[$]; + acc_trace_item rtl_trace_queue[$]; // Each time we see a read on the A side, we set an entry in the exp_read_values associative // array. There are three situations that we need to deal with: @@ -31,7 +31,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( // (3) A read from a register that can be updated by HW and where we have no idea what the value // should be. // - // To handle these three possibilities, we store a 34-bit otbn_exp_read_data_t value with fields + // To handle these three possibilities, we store a 34-bit acc_exp_read_data_t value with fields // upd, chk and val. Here upd and chk are 1 bit each and val is 32 bits. // // If upd is false, we ignore the other fields and do not update the RAL's mirrored value. @@ -40,10 +40,10 @@ class otbn_scoreboard extends cip_base_scoreboard #( // // To connect up the A-side request with a subsequent D-side response, we use an associative // array, mapping the transaction source ID (a_source in the TL transaction) to an expected value. - otbn_exp_read_data_t exp_read_values [tl_source_t]; + acc_exp_read_data_t exp_read_values [tl_source_t]; // A flag that tracks the fact that we've seen a TL write to the CMD register that we expect to - // start OTBN. We track this because we derive the "start" signal in the model from an internal + // start ACC. We track this because we derive the "start" signal in the model from an internal // DUT signal, so need to make sure it stays in sync with the TL side. // // If false, there are no transactions pending. This gets set in process_tl_addr when we see a @@ -57,8 +57,8 @@ class otbn_scoreboard extends cip_base_scoreboard #( // The mirrored STATUS register from the ISS. bit [7:0] model_status; - // The "locked" field is used to track whether OTBN is "locked". For most operational state - // tracking, we go through the ISS, but OTBN can become locked without actually starting an + // The "locked" field is used to track whether ACC is "locked". For most operational state + // tracking, we go through the ISS, but ACC can become locked without actually starting an // operation (for example, there might be a malformed TL transaction). We spot that sort of thing // here, updating the "locked" flag if either the ISS says to do so OR if we see something 'out of // band'. @@ -140,7 +140,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( uvm_reg csr; uvm_reg_addr_t masked_addr, aligned_addr; operational_state_e state; - otbn_exp_read_data_t exp_read_data = '{upd: 1'b0, chk: 'x, val: 'x}; + acc_exp_read_data_t exp_read_data = '{upd: 1'b0, chk: 'x, val: 'x}; state = get_operational_state(status_e'(model_status)); @@ -170,7 +170,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( if (item.is_write()) begin // Track coverage for write accesses to external CSRs over TL-UL. if (cfg.en_cov) begin - cov.on_ext_csr_access(csr, otbn_env_pkg::AccessSoftwareWrite, item.a_data, state); + cov.on_ext_csr_access(csr, acc_env_pkg::AccessSoftwareWrite, item.a_data, state); end // If this is a write, update the RAL model @@ -182,10 +182,10 @@ class otbn_scoreboard extends cip_base_scoreboard #( // We start any operation when we see a write of the related command and we are currently // in the IDLE operational state. See the comment above pending_start_tl_trans to see how // this tracking works. - bit cmd_operation = item.a_data[7:0] inside {otbn_pkg::CmdSecWipeImem, - otbn_pkg::CmdSecWipeDmem, - otbn_pkg::CmdExecute}; - if (cmd_operation && (model_status == otbn_pkg::StatusIdle)) begin + bit cmd_operation = item.a_data[7:0] inside {acc_pkg::CmdSecWipeImem, + acc_pkg::CmdSecWipeDmem, + acc_pkg::CmdExecute}; + if (cmd_operation && (model_status == acc_pkg::StatusIdle)) begin // Set a flag: we're expecting the model to start on the next posedge. Also, spawn off a // checking thread that will make sure the flag has been cleared again by the following // posedge (or the one after that in the case of memory secure wipe operations). @@ -212,7 +212,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( // Let model know that CTRL register has changed. This is not ideal since scoreboard // ideally supposed be a passive component. Although we are still not affecting DUT in // any way while doing this and an alternative way would include catching this register - // write in testbench level and sending a signal to otbn_core_model, which is not ideal + // write in testbench level and sending a signal to acc_core_model, which is not ideal // as well. if (item.is_write) begin cfg.model_agent_cfg.vif.set_software_errs_fatal(item.a_data[0]); @@ -225,7 +225,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( return; end - // Otherwise, this is a read transaction. Fill in an otbn_exp_read_data_t struct appropriately. + // Otherwise, this is a read transaction. Fill in an acc_exp_read_data_t struct appropriately. case (csr.get_name()) "intr_state": begin // Interrupt state register. @@ -284,7 +284,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( task process_tl_data(tl_seq_item item); uvm_reg csr; uvm_reg_addr_t csr_addr; - otbn_exp_read_data_t exp_read_data; + acc_exp_read_data_t exp_read_data; // The data-channel response to a write is just an ack, which isn't particularly interesting. // Check for integrity errors (which should lock the block), but otherwise there's nothing to @@ -304,7 +304,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( // Track coverage for read accesses through the bus to external CSRs. if (cfg.en_cov) begin - cov.on_ext_csr_access(csr, otbn_env_pkg::AccessSoftwareRead, item.d_data, + cov.on_ext_csr_access(csr, acc_env_pkg::AccessSoftwareRead, item.d_data, get_operational_state(status_e'(model_status))); end @@ -378,17 +378,17 @@ class otbn_scoreboard extends cip_base_scoreboard #( endfunction task process_model_fifo(); - otbn_model_item item; + acc_model_item item; forever begin model_fifo.get(item); `uvm_info(`gfn, $sformatf("received model transaction:\n%0s", item.sprint()), UVM_HIGH) case (item.item_type) - OtbnModelStatus: begin - bit was_executing = model_status inside {otbn_pkg::StatusBusyExecute, - otbn_pkg::StatusBusySecWipeInt}; - bit is_busy = otbn_pkg::is_busy_status(status_e'(item.status)); + AccModelStatus: begin + bit was_executing = model_status inside {acc_pkg::StatusBusyExecute, + acc_pkg::StatusBusySecWipeInt}; + bit is_busy = acc_pkg::is_busy_status(status_e'(item.status)); // Did the status change happen due to a reset? If so, reset the model status as well. if (item.rst_n !== 1'b1) model_status = item.status; @@ -397,7 +397,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( // command register on the previous posedge or there should be an RMA request. See comment // above pending_start_tl_trans for the details of how we track writes to the command // register. - if (model_status == otbn_pkg::StatusIdle && is_busy) begin + if (model_status == acc_pkg::StatusIdle && is_busy) begin `DV_CHECK_FATAL(pending_start_tl_trans || cfg.escalate_vif.req == lc_ctrl_pkg::On, "Saw start transaction without corresponding write to CMD") pending_start_tl_trans = 1'b0; @@ -411,7 +411,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( // We should also clear the pending_start_tl_trans flag if it is set. This would mean that // we've seen a start request, but it's being ignored because the model locks instead of // starting an execution. - if ((item.status == otbn_pkg::StatusLocked) && + if ((item.status == acc_pkg::StatusLocked) && (cfg.escalate_vif.req != lc_ctrl_pkg::On)) begin expect_alert("fatal"); pending_start_tl_trans = 1'b0; @@ -419,7 +419,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( // Has the status changed from executing to idle with a nonzero err_bits? // If so, we should see a recoverable alert. Note that we are not expecting to catch // recoverable alert when we do SecWipe of any kind. - if (was_executing && item.status == otbn_pkg::StatusIdle && item.err_bits != 0) begin + if (was_executing && item.status == acc_pkg::StatusIdle && item.err_bits != 0) begin expect_alert("recov"); end @@ -430,8 +430,8 @@ class otbn_scoreboard extends cip_base_scoreboard #( end end - OtbnModelInsn: begin - // The model agent's monitor should be configured to only emit OtbnModelInsn items if + AccModelInsn: begin + // The model agent's monitor should be configured to only emit AccModelInsn items if // coverage is enabled. `DV_CHECK_FATAL(cfg.en_cov) // We don't expect any instructions unless we're currently running something. @@ -448,7 +448,7 @@ class otbn_scoreboard extends cip_base_scoreboard #( endtask task process_trace_fifo(); - otbn_trace_item item; + acc_trace_item item; forever begin trace_fifo.get(item); @@ -465,8 +465,8 @@ class otbn_scoreboard extends cip_base_scoreboard #( // Pop from iss_trace_queue and rtl_trace_queue while they both contain an entry function void pop_trace_queues(); while ((iss_trace_queue.size() > 0) && (rtl_trace_queue.size() > 0)) begin - otbn_model_item iss_item = iss_trace_queue.pop_front(); - otbn_trace_item rtl_item = rtl_trace_queue.pop_front(); + acc_model_item iss_item = iss_trace_queue.pop_front(); + acc_trace_item rtl_item = rtl_trace_queue.pop_front(); cov.on_insn(iss_item, rtl_item); end endfunction @@ -645,20 +645,20 @@ class otbn_scoreboard extends cip_base_scoreboard #( endfunction virtual function void mem_compare(string ral_name, uvm_reg_addr_t addr, tl_seq_item item); - // We can only compare the contents inside memories when the OTBN is not busy executing + // We can only compare the contents inside memories when the ACC is not busy executing // or wiping the memories - if (model_status inside {otbn_pkg::StatusIdle, otbn_pkg::StatusBusySecWipeInt}) begin + if (model_status inside {acc_pkg::StatusIdle, acc_pkg::StatusBusySecWipeInt}) begin super.mem_compare(ral_name, addr, item); // Otherwise the contents will read out as zeros so compare expected memory with zero. end else begin - `DV_CHECK_EQ(item.d_data, '0, "Memory read out nonzero value while OTBN is not IDLE") + `DV_CHECK_EQ(item.d_data, '0, "Memory read out nonzero value while ACC is not IDLE") end endfunction virtual task process_mem_read(tl_seq_item item, string ral_name); super.process_mem_read(item, ral_name); if (model_status == 'b1 && item.d_data != 0) begin - `uvm_error(`gfn, "read data is non zero when memory is accessed while otbn is busy") + `uvm_error(`gfn, "read data is non zero when memory is accessed while acc is busy") end endtask diff --git a/hw/ip/otbn/dv/uvm/env/otbn_ssctrl_if.sv b/hw/ip/acc/dv/uvm/env/acc_ssctrl_if.sv similarity index 90% rename from hw/ip/otbn/dv/uvm/env/otbn_ssctrl_if.sv rename to hw/ip/acc/dv/uvm/env/acc_ssctrl_if.sv index 9c956562a9e..a1559f1887c 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_ssctrl_if.sv +++ b/hw/ip/acc/dv/uvm/env/acc_ssctrl_if.sv @@ -6,10 +6,10 @@ // This interface uses hierarchical references to control some assertions inside the design. // This can then be used by virtual sequences (which can't use hierarchical references directly) -`define SSCTRL_HPATH tb.dut.u_otbn_core.u_otbn_start_stop_control +`define SSCTRL_HPATH tb.dut.u_acc_core.u_acc_start_stop_control `define SSCTRL_PATH `"`SSCTRL_HPATH`" -interface otbn_ssctrl_if; +interface acc_ssctrl_if; function automatic string resolve_path(string signal); return {`SSCTRL_PATH, ".", signal}; diff --git a/hw/ip/otbn/dv/uvm/env/otbn_test_helpers.cc b/hw/ip/acc/dv/uvm/env/acc_test_helpers.cc similarity index 83% rename from hw/ip/otbn/dv/uvm/env/otbn_test_helpers.cc rename to hw/ip/acc/dv/uvm/env/acc_test_helpers.cc index 63e0cee7b69..e7a341234a0 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_test_helpers.cc +++ b/hw/ip/acc/dv/uvm/env/acc_test_helpers.cc @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 // Helper code for the UVM testbench. The corresponding SV declarations are in -// otbn_env_pkg.sv. +// acc_env_pkg.sv. #include #include @@ -32,12 +32,12 @@ static bool IsElfFileName(const char *name) { return (len >= 5) && (memcmp(name + len - 4, ".elf", 4) == 0); } -class OtbnTestHelper { +class AccTestHelper { public: std::string dir_path_; std::string file_path_; - OtbnTestHelper(const std::string dir_path) : dir_path_(dir_path) {} + AccTestHelper(const std::string dir_path) : dir_path_(dir_path) {} int CountFilesInDir() const { dir_ptr dir(opendir(dir_path_.c_str())); @@ -99,14 +99,14 @@ class OtbnTestHelper { }; } // namespace -// Make an OTBN test helper -extern "C" OtbnTestHelper *OtbnTestHelperMake(const char *path) { +// Make an ACC test helper +extern "C" AccTestHelper *AccTestHelperMake(const char *path) { assert(path != nullptr); - return new OtbnTestHelper(path); + return new AccTestHelper(path); } -// Free an OTBN test helper -extern "C" void OtbnTestHelperFree(OtbnTestHelper *helper) { +// Free an ACC test helper +extern "C" void AccTestHelperFree(AccTestHelper *helper) { assert(helper != nullptr); delete helper; } @@ -114,7 +114,7 @@ extern "C" void OtbnTestHelperFree(OtbnTestHelper *helper) { // Count the number of regular files in the directory at path. If path does not // name a directory (or names a directory that cannot be opened for some // reason), return zero. -extern "C" int OtbnTestHelperCountFilesInDir(OtbnTestHelper *helper) { +extern "C" int AccTestHelperCountFilesInDir(AccTestHelper *helper) { assert(helper != nullptr); return helper->CountFilesInDir(); } @@ -122,8 +122,8 @@ extern "C" int OtbnTestHelperCountFilesInDir(OtbnTestHelper *helper) { // Get a file in the given directory. The file is that at position index when // stepping through the directory with readdir(). On success, returns the path. // On failure, returns an empty string. -extern "C" const char *OtbnTestHelperGetFilePath(OtbnTestHelper *helper, - int index) { +extern "C" const char *AccTestHelperGetFilePath(AccTestHelper *helper, + int index) { assert(helper != nullptr); assert(index >= 0); diff --git a/hw/ip/otbn/dv/uvm/env/otbn_trace_item.sv b/hw/ip/acc/dv/uvm/env/acc_trace_item.sv similarity index 93% rename from hw/ip/otbn/dv/uvm/env/otbn_trace_item.sv rename to hw/ip/acc/dv/uvm/env/acc_trace_item.sv index b3ada643613..a9b42f8ed91 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_trace_item.sv +++ b/hw/ip/acc/dv/uvm/env/acc_trace_item.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_trace_item extends uvm_sequence_item; +class acc_trace_item extends uvm_sequence_item; logic [31:0] insn_addr; logic [31:0] insn_data; @@ -16,9 +16,9 @@ class otbn_trace_item extends uvm_sequence_item; logic [255:0] wdr_operand_b; // Flag read/write data - otbn_pkg::flags_t flags_read_data [2]; + acc_pkg::flags_t flags_read_data [2]; logic [1:0] flags_write_valid; - otbn_pkg::flags_t flags_write_data [2]; + acc_pkg::flags_t flags_write_data [2]; // GPR and WDR write data logic [31:0] gpr_write_data; @@ -48,7 +48,7 @@ class otbn_trace_item extends uvm_sequence_item; // Intermediate value for MULQACC instructions logic [256:0] new_acc_extended; - `uvm_object_utils_begin(otbn_trace_item) + `uvm_object_utils_begin(acc_trace_item) `uvm_field_int (insn_addr, UVM_DEFAULT | UVM_HEX) `uvm_field_int (insn_data, UVM_DEFAULT | UVM_HEX) `uvm_field_int (gpr_operand_a, UVM_DEFAULT | UVM_HEX) diff --git a/hw/ip/otbn/dv/uvm/env/otbn_trace_monitor.sv b/hw/ip/acc/dv/uvm/env/acc_trace_monitor.sv similarity index 92% rename from hw/ip/otbn/dv/uvm/env/otbn_trace_monitor.sv rename to hw/ip/acc/dv/uvm/env/acc_trace_monitor.sv index 306166eb883..8994256d864 100644 --- a/hw/ip/otbn/dv/uvm/env/otbn_trace_monitor.sv +++ b/hw/ip/acc/dv/uvm/env/acc_trace_monitor.sv @@ -2,17 +2,17 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_trace_monitor extends dv_base_monitor #( - .ITEM_T (otbn_trace_item), - .CFG_T (otbn_env_cfg), - .COV_T (otbn_env_cov) +class acc_trace_monitor extends dv_base_monitor #( + .ITEM_T (acc_trace_item), + .CFG_T (acc_env_cfg), + .COV_T (acc_env_cov) ); - `uvm_component_utils(otbn_trace_monitor) + `uvm_component_utils(acc_trace_monitor) `uvm_component_new protected task collect_trans(); - otbn_trace_item item; + acc_trace_item item; bit item_valid = 1'b0; // The trace monitor is only used for coverage collection; disable it if coverage is not @@ -37,7 +37,7 @@ class otbn_trace_monitor extends dv_base_monitor #( // about the same instruction. `DV_CHECK_EQ_FATAL(cfg.trace_vif.insn_addr, cfg.loop_vif.insn_addr_i) - item = otbn_trace_item::type_id::create("item"); + item = acc_trace_item::type_id::create("item"); item.insn_addr = cfg.trace_vif.insn_addr; item.insn_data = cfg.trace_vif.insn_data; item.gpr_operand_a = cfg.trace_vif.rf_base_rd_data_a; diff --git a/hw/ip/acc/dv/uvm/env/acc_virtual_sequencer.sv b/hw/ip/acc/dv/uvm/env/acc_virtual_sequencer.sv new file mode 100644 index 00000000000..985f3227170 --- /dev/null +++ b/hw/ip/acc/dv/uvm/env/acc_virtual_sequencer.sv @@ -0,0 +1,16 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class acc_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(acc_env_cfg), + .COV_T(acc_env_cov) + ); + `uvm_component_utils(acc_virtual_sequencer) + `uvm_component_new + + key_sideload_sequencer#(keymgr_pkg::acc_key_req_t) key_sideload_sequencer_h; + acc_app_sequencer acc_app_sequencer_h; + +endclass diff --git a/hw/ip/otbn/dv/uvm/env/pqc_on_env_pkg/otbn_pqc_env_pkg.core b/hw/ip/acc/dv/uvm/env/pqc_off_env_pkg/acc_pqc_env_pkg.core similarity index 62% rename from hw/ip/otbn/dv/uvm/env/pqc_on_env_pkg/otbn_pqc_env_pkg.core rename to hw/ip/acc/dv/uvm/env/pqc_off_env_pkg/acc_pqc_env_pkg.core index 7a1fa8c4eec..01bf6c74679 100644 --- a/hw/ip/otbn/dv/uvm/env/pqc_on_env_pkg/otbn_pqc_env_pkg.core +++ b/hw/ip/acc/dv/uvm/env/pqc_off_env_pkg/acc_pqc_env_pkg.core @@ -3,15 +3,15 @@ CAPI=2: # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_pqc_on_env_pkg" -description: "Environment parameters for PQC mode enabled on OTBN" +name: "lowrisc:dv:acc_pqc_off_env_pkg" +description: "Environment parameters for PQC mode disabled on ACC" virtual: - - lowrisc:dv:otbn_pqc_env_pkg + - lowrisc:dv:acc_pqc_env_pkg filesets: files_rtl: files: - - otbn_pqc_env_pkg.sv + - acc_pqc_env_pkg.sv file_type: systemVerilogSource targets: diff --git a/hw/ip/otbn/dv/uvm/env/pqc_off_env_pkg/otbn_pqc_env_pkg.sv b/hw/ip/acc/dv/uvm/env/pqc_off_env_pkg/acc_pqc_env_pkg.sv similarity index 77% rename from hw/ip/otbn/dv/uvm/env/pqc_off_env_pkg/otbn_pqc_env_pkg.sv rename to hw/ip/acc/dv/uvm/env/pqc_off_env_pkg/acc_pqc_env_pkg.sv index dc9e6cd81be..40376f3b6b2 100644 --- a/hw/ip/otbn/dv/uvm/env/pqc_off_env_pkg/otbn_pqc_env_pkg.sv +++ b/hw/ip/acc/dv/uvm/env/pqc_off_env_pkg/acc_pqc_env_pkg.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -package otbn_pqc_env_pkg; +package acc_pqc_env_pkg; // Disable PQC mode for the TB and DUT - parameter bit OtbnPQCEn = 0; + parameter bit AccPQCEn = 0; endpackage diff --git a/hw/ip/otbn/dv/uvm/env/pqc_off_env_pkg/otbn_pqc_env_pkg.core b/hw/ip/acc/dv/uvm/env/pqc_on_env_pkg/acc_pqc_env_pkg.core similarity index 62% rename from hw/ip/otbn/dv/uvm/env/pqc_off_env_pkg/otbn_pqc_env_pkg.core rename to hw/ip/acc/dv/uvm/env/pqc_on_env_pkg/acc_pqc_env_pkg.core index 1bc20333a8c..b53ac8ce11f 100644 --- a/hw/ip/otbn/dv/uvm/env/pqc_off_env_pkg/otbn_pqc_env_pkg.core +++ b/hw/ip/acc/dv/uvm/env/pqc_on_env_pkg/acc_pqc_env_pkg.core @@ -3,15 +3,15 @@ CAPI=2: # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_pqc_off_env_pkg" -description: "Environment parameters for PQC mode disabled on OTBN" +name: "lowrisc:dv:acc_pqc_on_env_pkg" +description: "Environment parameters for PQC mode enabled on ACC" virtual: - - lowrisc:dv:otbn_pqc_env_pkg + - lowrisc:dv:acc_pqc_env_pkg filesets: files_rtl: files: - - otbn_pqc_env_pkg.sv + - acc_pqc_env_pkg.sv file_type: systemVerilogSource targets: diff --git a/hw/ip/otbn/dv/uvm/env/pqc_on_env_pkg/otbn_pqc_env_pkg.sv b/hw/ip/acc/dv/uvm/env/pqc_on_env_pkg/acc_pqc_env_pkg.sv similarity index 77% rename from hw/ip/otbn/dv/uvm/env/pqc_on_env_pkg/otbn_pqc_env_pkg.sv rename to hw/ip/acc/dv/uvm/env/pqc_on_env_pkg/acc_pqc_env_pkg.sv index df1ae0d68d6..b608ebdce22 100644 --- a/hw/ip/otbn/dv/uvm/env/pqc_on_env_pkg/otbn_pqc_env_pkg.sv +++ b/hw/ip/acc/dv/uvm/env/pqc_on_env_pkg/acc_pqc_env_pkg.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -package otbn_pqc_env_pkg; +package acc_pqc_env_pkg; // Enable PQC mode for the TB and DUT - parameter bit OtbnPQCEn = 1; + parameter bit AccPQCEn = 1; endpackage diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_alu_bignum_mod_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_alu_bignum_mod_err_vseq.sv similarity index 59% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_alu_bignum_mod_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_alu_bignum_mod_err_vseq.sv index 798b6af3fc4..b01a8c5c311 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_alu_bignum_mod_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_alu_bignum_mod_err_vseq.sv @@ -3,26 +3,26 @@ // SPDX-License-Identifier: Apache-2.0 // A sequence that runs a program multiple times and corrupts the `mod_intg_q` register of -// `otbn_alu_bignum` while OTBN is still running. +// `acc_alu_bignum` while ACC is still running. -class otbn_alu_bignum_mod_err_vseq extends otbn_intg_err_vseq; - `uvm_object_utils(otbn_alu_bignum_mod_err_vseq) +class acc_alu_bignum_mod_err_vseq extends acc_intg_err_vseq; + `uvm_object_utils(acc_alu_bignum_mod_err_vseq) `uvm_object_new - protected task await_use(output bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words); + protected task await_use(output bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words); used_words = '0; `uvm_info(`gfn, "Waiting for `mod_intg_q` to be used", UVM_LOW) cfg.alu_bignum_vif.wait_for_mod_used(200, used_words); endtask - protected task inject_errors(input bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words, - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] corrupted_words); - bit [otbn_pkg::ExtWLEN-1:0] new_data = corrupt_data(cfg.alu_bignum_vif.mod_intg_q, + protected task inject_errors(input bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words, + output bit [acc_pkg::BaseWordsPerWLEN-1:0] corrupted_words); + bit [acc_pkg::ExtWLEN-1:0] new_data = corrupt_data(cfg.alu_bignum_vif.mod_intg_q, '{default: 50}, corrupted_words); if (corrupted_words != '0) begin - `uvm_info(`gfn, "Injecting errors into `mod_intg_q` of `otbn_alu_bignum`", UVM_LOW) + `uvm_info(`gfn, "Injecting errors into `mod_intg_q` of `acc_alu_bignum`", UVM_LOW) cfg.alu_bignum_vif.force_mod_intg_q(new_data); end else begin `uvm_info(`gfn, "Randomization decided to not inject any errors.", UVM_LOW) diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_base_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_base_vseq.sv similarity index 79% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_base_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_base_vseq.sv index 14b9b2e883d..12ff30ab058 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_base_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_base_vseq.sv @@ -4,22 +4,22 @@ // SPDX-License-Identifier: Apache-2.0 // -// Base class for all OTBN test sequences +// Base class for all ACC test sequences // -class otbn_base_vseq extends cip_base_vseq #( - .CFG_T (otbn_env_cfg), - .RAL_T (otbn_reg_block), - .COV_T (otbn_env_cov), - .VIRTUAL_SEQUENCER_T(otbn_virtual_sequencer) +class acc_base_vseq extends cip_base_vseq #( + .CFG_T (acc_env_cfg), + .RAL_T (acc_reg_block), + .COV_T (acc_env_cov), + .VIRTUAL_SEQUENCER_T(acc_virtual_sequencer) ); - `uvm_object_utils(otbn_base_vseq) + `uvm_object_utils(acc_base_vseq) `uvm_object_new - // "Running" flag to detect concurrent executions of run_otbn() + // "Running" flag to detect concurrent executions of run_acc() protected bit running_ = 1'b0; - // The longest run seen in calls to start_running_otbn. This gets reset to zero by load_elf (since + // The longest run seen in calls to start_running_acc. This gets reset to zero by load_elf (since // we assume we've got a new program, which might take a different amount of time) protected int unsigned longest_run_ = 0; @@ -30,7 +30,7 @@ class otbn_base_vseq extends cip_base_vseq #( // should allow an absent key (in which case, we have to disable end-address checking). protected bit absent_key_allowed = 1'b0; - // This counter is set in run_otbn() if our operation has finished and we're trying to stop. It's + // This counter is set in run_acc() if our operation has finished and we're trying to stop. It's // used by the code in _run_sideload_sequence() to spot that we should stop sending sideload keys // and that it should exit. (Note that we can't just use something like 'disable fork' because the // sideload sequencer will get upset if we kill a process that's waiting for a grant from it). @@ -57,7 +57,7 @@ class otbn_base_vseq extends cip_base_vseq #( // Load the contents of an ELF file into the DUT's memories, either by a DPI backdoor (if backdoor // is true) or with TL transactions. Also, pass loop warp rules to the ISS through the model. protected task load_elf(string path, bit backdoor); - otbn_pkg::cmd_e wipe_cmd; + acc_pkg::cmd_e wipe_cmd; bit [1:0] num_wipes; bit bogus_write; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL( @@ -67,24 +67,24 @@ class otbn_base_vseq extends cip_base_vseq #( 1 :/ 9 };) `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(num_wipes, num_wipes inside {[0 : 2]};) - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(wipe_cmd, wipe_cmd != otbn_pkg::CmdExecute;) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(wipe_cmd, wipe_cmd != acc_pkg::CmdExecute;) if (bogus_write) begin // Write a bogus value while we are in IDLE state for coverage. _send_bogus_cmd(); end case (num_wipes) - 1: _run_otbn_cmd(wipe_cmd); // Run a random wipe command + 1: _run_acc_cmd(wipe_cmd); // Run a random wipe command 2: begin // First run a random wipe command - _run_otbn_cmd(wipe_cmd); + _run_acc_cmd(wipe_cmd); // We also would like to try writing to register while we are not in IDLE. // In order to do tht we need to insert a random delay between the operations. // That would result with us sometimes successfully running back to back operations. // And sometimes writing to CMD while still doing the first operation. repeat ($urandom_range(0, 20)) @(cfg.clk_rst_vif.cbn); // Check the name of the first command, run the other one after the delay. - if (wipe_cmd.name() == "CmdSecWipeDmem") _run_otbn_cmd(otbn_pkg::CmdSecWipeImem); - else _run_otbn_cmd(otbn_pkg::CmdSecWipeDmem); + if (wipe_cmd.name() == "CmdSecWipeDmem") _run_acc_cmd(acc_pkg::CmdSecWipeImem); + else _run_acc_cmd(acc_pkg::CmdSecWipeDmem); end default: ; // Do nothing endcase @@ -94,7 +94,7 @@ class otbn_base_vseq extends cip_base_vseq #( load_elf_over_bus(path); end - // Pass loop warp rules that we've just loaded into otbn_memutil into the model. + // Pass loop warp rules that we've just loaded into acc_memutil into the model. cfg.model_agent_cfg.vif.take_loop_warps(cfg.mem_util); if (cfg.model_agent_cfg.vif.has_loop_warps(cfg.mem_util)) begin @@ -112,7 +112,7 @@ class otbn_base_vseq extends cip_base_vseq #( // Load the contents of an ELF file into the DUT's memories by a DPI backdoor protected function void load_elf_backdoor(string path); - if (!OtbnMemUtilLoadElf(cfg.mem_util, path)) begin + if (!AccMemUtilLoadElf(cfg.mem_util, path)) begin `uvm_fatal(`gfn, $sformatf("Failed to load ELF at `%0s'", path)) end endfunction @@ -144,14 +144,14 @@ class otbn_base_vseq extends cip_base_vseq #( // Load the contents of an ELF file into the DUT's memories by TL transactions protected task load_elf_over_bus(string path); - otbn_loaded_word to_load [$]; + acc_loaded_word to_load [$]; bit [33:0] opns [$]; bit run_fast; semaphore tx_sem = new(0); - // First, tell OtbnMemUtil to stage the ELF. This reads the file and stashes away the segments + // First, tell AccMemUtil to stage the ELF. This reads the file and stashes away the segments // we need. If something goes wrong, it will print a message to stderr, so we can just fail. - if (!OtbnMemUtilStageElf(cfg.mem_util, path)) begin + if (!AccMemUtilStageElf(cfg.mem_util, path)) begin `uvm_fatal(`gfn, $sformatf("Failed to stage ELF at `%0s'", path)) end @@ -236,7 +236,7 @@ class otbn_base_vseq extends cip_base_vseq #( restore_tl_config(); endtask - protected task send_mem_operation(otbn_loaded_word to_load[$], bit [1:0] op, bit [31:0] value); + protected task send_mem_operation(acc_loaded_word to_load[$], bit [1:0] op, bit [31:0] value); case (op) 2'b00: csr_utils_pkg::mem_wr(to_load[value].for_imem ? ral.imem : ral.dmem, to_load[value].offset, @@ -251,29 +251,29 @@ class otbn_base_vseq extends cip_base_vseq #( endtask protected function automatic void get_queue_entries(bit for_imem, - ref otbn_loaded_word entries[$]); + ref acc_loaded_word entries[$]); // Get the bus-accessible size of this memory (to make sure the number of loaded words makes // sense) - int unsigned mem_size = for_imem ? OTBN_IMEM_SIZE : OTBN_DMEM_SIZE; + int unsigned mem_size = for_imem ? ACC_IMEM_SIZE : ACC_DMEM_SIZE; // Iterate over the segments for this memory - int seg_count = OtbnMemUtilGetSegCount(cfg.mem_util, for_imem); + int seg_count = AccMemUtilGetSegCount(cfg.mem_util, for_imem); for (int seg_idx = 0; seg_idx < seg_count; seg_idx++) begin // What offset and size (in 32 bit words) is this segment? bit [31:0] seg_off, seg_size; - if (!OtbnMemUtilGetSegInfo(cfg.mem_util, for_imem, seg_idx, seg_off, seg_size)) begin + if (!AccMemUtilGetSegInfo(cfg.mem_util, for_imem, seg_idx, seg_off, seg_size)) begin `uvm_fatal(`gfn, $sformatf("Failed to get segment info for segment %0d.", seg_idx)) end // Add each word. for (bit [31:0] i = 0; i < seg_size; i++) begin bit [31:0] word_off, data; - otbn_loaded_word entry; + acc_loaded_word entry; word_off = seg_off + i; - if (!OtbnMemUtilGetSegData(cfg.mem_util, for_imem, word_off, data)) begin + if (!AccMemUtilGetSegData(cfg.mem_util, for_imem, word_off, data)) begin `uvm_fatal(`gfn, $sformatf("Failed to get segment data at word offset %0d.", word_off)) end @@ -281,7 +281,7 @@ class otbn_base_vseq extends cip_base_vseq #( // address space, we know that the top two bits of the word address are zero. `DV_CHECK_FATAL(word_off[31:30] == 2'b00) - // OtbnMemUtil should have checked that this address was valid for the given memory, but it + // AccMemUtil should have checked that this address was valid for the given memory, but it // can't hurt to check again. `DV_CHECK_FATAL({word_off, 2'b00} < {2'b00, mem_size}) @@ -295,7 +295,7 @@ class otbn_base_vseq extends cip_base_vseq #( // Write a random CMD value, which may or may not be a valid command. // - // This is only used when OTBN is either known to be locked or running (so it will ignore the + // This is only used when ACC is either known to be locked or running (so it will ignore the // write) or is known to be ready to receive a command (For example, maybe we tried to send the // command when it was running, but were a little bit late. That would still be fine because we // know that we've got an ELF file loaded up) @@ -306,9 +306,9 @@ class otbn_base_vseq extends cip_base_vseq #( logic [31:0] val; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(val, val[7:0] dist { - otbn_pkg::CmdExecute :/ 2, - otbn_pkg::CmdSecWipeDmem :/ 2, - otbn_pkg::CmdSecWipeImem :/ 2, + acc_pkg::CmdExecute :/ 2, + acc_pkg::CmdSecWipeDmem :/ 2, + acc_pkg::CmdSecWipeImem :/ 2, [0 : $] :/ 1 };) `uvm_info(`gfn, $sformatf("\n\t ----| Writing a random value (0x%08h) to CMD register", val), @@ -320,25 +320,25 @@ class otbn_base_vseq extends cip_base_vseq #( protected task _send_bogus_cmd(); logic [31:0] val; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(val, - !(val[7:0] inside {otbn_pkg::CmdExecute, - otbn_pkg::CmdSecWipeDmem, - otbn_pkg::CmdSecWipeImem});) + !(val[7:0] inside {acc_pkg::CmdExecute, + acc_pkg::CmdSecWipeDmem, + acc_pkg::CmdSecWipeImem});) `uvm_info(`gfn, $sformatf("\n\t ----| Writing a bogus value (0x%08h) to CMD register", val), UVM_MEDIUM) csr_utils_pkg::csr_wr(ral.cmd, val); endtask - // Start OTBN and then wait until done + // Start ACC and then wait until done // // If the block gets reset, this task will exit early. - protected task run_otbn(input check_end_addr = 1); + protected task run_acc(input check_end_addr = 1); int exp_end_addr; int rd_pc; int wr_pc; // Check that we haven't been called re-entrantly. This could happen if there's a bug in the - // reset sequence, which relies on run_otbn() to exit properly when it sees a device reset. - // Explode here if that happens, which should be easier to debug than two concurrent run_otbn() + // reset sequence, which relies on run_acc() to exit properly when it sees a device reset. + // Explode here if that happens, which should be easier to debug than two concurrent run_acc() // processes fighting over the interface. `DV_CHECK_FATAL(!running_) `DV_CHECK_FATAL(stop_tokens == 0) @@ -348,7 +348,7 @@ class otbn_base_vseq extends cip_base_vseq #( // immediately, causing all sorts of confusion. It's a testbench bug if we are. `DV_CHECK_FATAL(!cfg.under_reset) - // Wait for OTBN to be idle. We expect getting there to take some time: OTBN has to get two URND + // Wait for ACC to be idle. We expect getting there to take some time: ACC has to get two URND // values from the EDN and then perform its initial secure wipe. To wait for this, wait until // the EDN comes out of reset and then allow some extra time for the actual data to be // transferred. Transferring each URND word will take 8 EDN words and each of those words will @@ -358,7 +358,7 @@ class otbn_base_vseq extends cip_base_vseq #( // // Stop waiting on a reset. fork : wait_for_idle_fork - wait(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle); + wait(cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle); begin // Wait for both clock/reset interfaces to be out of reset. wait(cfg.edn_clk_rst_vif.rst_n); @@ -373,26 +373,26 @@ class otbn_base_vseq extends cip_base_vseq #( join_any // Exit early if: - // - OTBN has been reset during the initial secure wipe; or - // - OTBN went from the initial secure wipe directly into the Locked state due to a fatal + // - ACC has been reset during the initial secure wipe; or + // - ACC went from the initial secure wipe directly into the Locked state due to a fatal // internal error (e.g., on URND). - if (cfg.under_reset || cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) begin + if (cfg.under_reset || cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) begin running_ = 1'b0; return; end - `DV_CHECK_FATAL(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle, - "Timed out waiting for OTBN to be idle before execution"); + `DV_CHECK_FATAL(cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle, + "Timed out waiting for ACC to be idle before execution"); fork : isolation_fork begin fork - // Only _run_otbn_cmd will complete - _run_otbn_cmd(otbn_pkg::CmdExecute); + // Only _run_acc_cmd will complete + _run_acc_cmd(acc_pkg::CmdExecute); _run_loop_warps(); _run_sideload_sequence(); _run_rnd_edn_rsp(); - _run_otbn_app_rsp(); + _run_acc_app_rsp(); join_any // Consumed by _run_sideload_sequence() @@ -402,14 +402,14 @@ class otbn_base_vseq extends cip_base_vseq #( // TODO: Remove the stop sequences call once the reset safe base libaries // have been implemented for the driver and sequencers. - p_sequencer.otbn_app_sequencer_h.stop_sequences(); + p_sequencer.acc_app_sequencer_h.stop_sequences(); // Kill any processes that didn't use the stop token mechanism disable fork; end join - // The wait for OTBN to finish short-circuits and exits immediately if the reset line goes low. + // The wait for ACC to finish short-circuits and exits immediately if the reset line goes low. // If that happens, we don't want to run any further checks (since the run didn't finish // properly). if (cfg.under_reset) begin @@ -425,13 +425,13 @@ class otbn_base_vseq extends cip_base_vseq #( // If there was an expected end address, compare it with the model. This isn't really a test of // the RTL, but it's handy to make sure that the RIG really is generating the control flow that // it expects. - exp_end_addr = OtbnMemUtilGetExpEndAddr(cfg.mem_util); + exp_end_addr = AccMemUtilGetExpEndAddr(cfg.mem_util); if (exp_end_addr >= 0) begin `DV_CHECK_EQ_FATAL(exp_end_addr, cfg.model_agent_cfg.vif.stop_pc) end end - // If OTBN stopped with an error then it should trigger a recoverable or fatal alert. The + // If ACC stopped with an error then it should trigger a recoverable or fatal alert. The // scoreboard is already checking that this goes out properly, but we don't want to follow up // with another execution before that happens. The problem is that the alert system sometimes // takes a while to actually send the alert and the second operation might also generate an @@ -448,7 +448,7 @@ class otbn_base_vseq extends cip_base_vseq #( end cfg.m_alert_agent_cfgs["recov"].vif.wait_ack_complete(); - if (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) begin + if (cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) begin bit cmd_wr; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL( cmd_wr, @@ -475,28 +475,28 @@ class otbn_base_vseq extends cip_base_vseq #( end // Note: This must be the last thing in the function before we return. We use this flag to - // synchronise with a "disable fork" in start_running_otbn(). + // synchronise with a "disable fork" in start_running_acc(). running_ = 1'b0; endtask - // Runs the transaction sequence for the OTBN AppIntf + // Runs the transaction sequence for the ACC AppIntf // Monitors the req to provide appropriate handshaking with DUT. Also // generates the rsp digest payload to send to DUT for comparison with the ISS model. // Sequence is inside forever loop so it will continue running after transaction completion. - // This is to allow for handshaking, and to prevent the task from terminating in run_otbn. - // Only the _run_otbn_cmd fork is allowed to terminate in run_otbn. - virtual task _run_otbn_app_rsp(); + // This is to allow for handshaking, and to prevent the task from terminating in run_acc. + // Only the _run_acc_cmd fork is allowed to terminate in run_acc. + virtual task _run_acc_app_rsp(); forever begin - otbn_app_base_seq otbn_app_seq; + acc_app_base_seq acc_app_seq; // Create and send sequence - `uvm_create_on(otbn_app_seq, p_sequencer.otbn_app_sequencer_h); - `DV_CHECK_RANDOMIZE_FATAL(otbn_app_seq) - `uvm_send(otbn_app_seq) + `uvm_create_on(acc_app_seq, p_sequencer.acc_app_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(acc_app_seq) + `uvm_send(acc_app_seq) end endtask - // Wait for OTBN to finish, either by polling or by waiting on the interrupt pins + // Wait for ACC to finish, either by polling or by waiting on the interrupt pins // // When polling, this waits up to 1ms before failing with a timeout. If polling, we pass the // backdoor flag to csr_rd, which is a way to avoid starting requests on the TL sequencer. @@ -506,21 +506,21 @@ class otbn_base_vseq extends cip_base_vseq #( fork begin `DV_WAIT_TIMEOUT(10_000_000, , - "Timed out waiting for OTBN run to complete") + "Timed out waiting for ACC run to complete") end begin if (_pick_use_interrupt()) begin - `uvm_info(`gfn, "\n\t ----| Waiting for OTBN to finish (interrupt)", verbosity) + `uvm_info(`gfn, "\n\t ----| Waiting for ACC to finish (interrupt)", verbosity) wait_for_interrupt(); end else begin uvm_reg_data_t run_status; - `uvm_info(`gfn, "\n\t ----| Waiting for OTBN to finish (polling)", verbosity) + `uvm_info(`gfn, "\n\t ----| Waiting for ACC to finish (polling)", verbosity) while (cfg.clk_rst_vif.rst_n) begin uvm_reg_data_t rdata; csr_rd(.ptr(ral.status), .value(rdata), .blocking(1), .backdoor(backdoor)); - if (rdata inside {otbn_pkg::StatusIdle, otbn_pkg::StatusLocked}) begin - `uvm_info(`gfn, $sformatf("Seen end of OTBN run (status is %0x)", rdata), UVM_HIGH) + if (rdata inside {acc_pkg::StatusIdle, acc_pkg::StatusLocked}) begin + `uvm_info(`gfn, $sformatf("Seen end of ACC run (status is %0x)", rdata), UVM_HIGH) break; end if (backdoor) cfg.clk_rst_vif.wait_clks(10); @@ -532,18 +532,18 @@ class otbn_base_vseq extends cip_base_vseq #( end join endtask - // The guts of the run_otbn task. Writes to the CMD register to start OTBN and polls the status + // The guts of the run_acc task. Writes to the CMD register to start ACC and polls the status // register until completion. On reset, this returns immediately. - protected task _run_otbn_cmd(logic [7:0] cmd_i); + protected task _run_acc_cmd(logic [7:0] cmd_i); case (cmd_i) - otbn_pkg::CmdSecWipeDmem: begin - `uvm_info(`gfn, "\n\t ----| Starting OTBN SecWipeDmem", UVM_MEDIUM) + acc_pkg::CmdSecWipeDmem: begin + `uvm_info(`gfn, "\n\t ----| Starting ACC SecWipeDmem", UVM_MEDIUM) end - otbn_pkg::CmdSecWipeImem: begin - `uvm_info(`gfn, "\n\t ----| Starting OTBN SecWipeImem", UVM_MEDIUM) + acc_pkg::CmdSecWipeImem: begin + `uvm_info(`gfn, "\n\t ----| Starting ACC SecWipeImem", UVM_MEDIUM) end - otbn_pkg::CmdExecute: begin - `uvm_info(`gfn, "\n\t ----| Starting OTBN Execution", UVM_MEDIUM) + acc_pkg::CmdExecute: begin + `uvm_info(`gfn, "\n\t ----| Starting ACC Execution", UVM_MEDIUM) end default: `uvm_fatal(`gfn, "Invalid operation") endcase @@ -553,15 +553,15 @@ class otbn_base_vseq extends cip_base_vseq #( wait_for_run_completion(UVM_MEDIUM); if (cfg.clk_rst_vif.rst_n) begin - `uvm_info(`gfn, "\n\t ----| OTBN finished", UVM_MEDIUM) + `uvm_info(`gfn, "\n\t ----| ACC finished", UVM_MEDIUM) end else begin - `uvm_info(`gfn, "\n\t ----| OTBN reset", UVM_MEDIUM) + `uvm_info(`gfn, "\n\t ----| ACC reset", UVM_MEDIUM) end endtask - // How should we wait until OTBN has finished? + // How should we wait until ACC has finished? // - // Use polling if OTBN is not idle, the interrupt is disabled or if the interrupt pin is already + // Use polling if ACC is not idle, the interrupt is disabled or if the interrupt pin is already // high. If enabled, wait on the interrupt pin except occasionally (poll_despite_interrupts_pct). // This exceptional case is to spot any weirdness in updating the STATUS register when interrupts // are enabled. @@ -569,9 +569,9 @@ class otbn_base_vseq extends cip_base_vseq #( uvm_status_e peek_status; uvm_reg_data_t peek_value; - // If OTBN is not in the IDLE state, starting an operation won't actually do anything, and we + // If ACC is not in the IDLE state, starting an operation won't actually do anything, and we // won't get a follow-up interrupt. So we shouldn't wait for an interrupt in this case! - if (cfg.model_agent_cfg.vif.status != otbn_pkg::StatusIdle) begin + if (cfg.model_agent_cfg.vif.status != acc_pkg::StatusIdle) begin return 1'b0; end @@ -601,7 +601,7 @@ class otbn_base_vseq extends cip_base_vseq #( endtask // Monitor the bound-in loop controller interface to take action on loop warp events. Runs - // forever, but is spawned by run_otbn(), which will kill it when the OTBN run completes or the + // forever, but is spawned by run_acc(), which will kill it when the ACC run completes or the // block is reset. protected task _run_loop_warps(); logic [31:0] addr, old_iters, old_count; @@ -624,9 +624,9 @@ class otbn_base_vseq extends cip_base_vseq #( // (counting up from zero). old_count = cfg.loop_vif.loop_iters_to_count(old_iters); - // Do a DPI call to otbn_memutil to look up whether there is a loop warp that we should be + // Do a DPI call to acc_memutil to look up whether there is a loop warp that we should be // taking. This returns 1'b1 and fills in new_count if there is a warp that does something. - if (!OtbnMemUtilGetLoopWarp(cfg.mem_util, addr, old_count, new_count)) continue; + if (!AccMemUtilGetLoopWarp(cfg.mem_util, addr, old_count, new_count)) continue; // Loop warping assumes we're not manipulating the loop stack (i.e. no new loop starting or // current loop finishing the same cycle we warp). @@ -647,7 +647,7 @@ class otbn_base_vseq extends cip_base_vseq #( string counter_path, index; string deposit_path_d, deposit_path_q; - counter_path = $sformatf("u_otbn_loop_controller.g_loop_counters[%0d].u_loop_count", + counter_path = $sformatf("u_acc_loop_controller.g_loop_counters[%0d].u_loop_count", cfg.loop_vif.loop_stack_rd_idx); // The prim_count primitive employs a "cross" counter, meaning that it contains a set of two @@ -672,9 +672,9 @@ class otbn_base_vseq extends cip_base_vseq #( for (int k = 0; k < 2; k++) begin index = $sformatf("[%0d]", k); deposit_path_d = - $sformatf({"tb.dut.u_otbn_core.u_otbn_controller.", counter_path, ".cnt_d", index}); + $sformatf({"tb.dut.u_acc_core.u_acc_controller.", counter_path, ".cnt_d", index}); deposit_path_q = - $sformatf({"tb.dut.u_otbn_core.u_otbn_controller.", counter_path, ".cnt_q", index}); + $sformatf({"tb.dut.u_acc_core.u_acc_controller.", counter_path, ".cnt_q", index}); `DV_CHECK_FATAL(uvm_hdl_deposit(deposit_path_d, new_cnt_d[k]) == 1, { "Failed to override cnt_d", index, " for loop warp."}) @@ -687,7 +687,7 @@ class otbn_base_vseq extends cip_base_vseq #( // Run the correct key sideload sequence protected task _run_sideload_sequence(); // First, pick a value for absent_key_allowed. This will be used here to configure the sideload - // sequence and then will be checked at the end of run_otbn(). + // sequence and then will be checked at the end of run_acc(). absent_key_allowed = $urandom_range(100) <= cfg.allow_no_sideload_key_pct; if (absent_key_allowed) begin @@ -697,7 +697,7 @@ class otbn_base_vseq extends cip_base_vseq #( end else begin // If absent keys are not allowed, we want to generate our own sequence that doesn't allow // keys to be invalid. We send it with a higher priority to override the default sequence. - key_sideload_set_seq #(keymgr_pkg::otbn_key_req_t) sideload_seq; + key_sideload_set_seq #(keymgr_pkg::acc_key_req_t) sideload_seq; `uvm_create_on(sideload_seq, p_sequencer.key_sideload_sequencer_h) while (stop_tokens == 0) begin `DV_CHECK_RANDOMIZE_WITH_FATAL(sideload_seq, sideload_key.valid == 1'b1;) @@ -714,25 +714,25 @@ class otbn_base_vseq extends cip_base_vseq #( int num_files; string elf_path; - // Check that cfg.otbn_elf_dir was set by the test - `DV_CHECK_FATAL(cfg.otbn_elf_dir.len() > 0); + // Check that cfg.acc_elf_dir was set by the test + `DV_CHECK_FATAL(cfg.acc_elf_dir.len() > 0); // Pick an ELF file to use in the test. We have to do this via DPI (because you can't list a // directory in pure SystemVerilog). To do so, we have to construct a helper object, which will // look after memory allocation for the string holding the path. - helper = OtbnTestHelperMake(cfg.otbn_elf_dir); + helper = AccTestHelperMake(cfg.acc_elf_dir); `DV_CHECK_FATAL(helper != null) // Ask the helper how many files there are. If it returns zero, the directory name is bogus or // the directory is empty. - num_files = OtbnTestHelperCountFilesInDir(helper); + num_files = AccTestHelperCountFilesInDir(helper); `DV_CHECK_FATAL(num_files > 0, $sformatf( - "No regular files found in directory `%0s'.", cfg.otbn_elf_dir)) + "No regular files found in directory `%0s'.", cfg.acc_elf_dir)) // Pick a file, any file... Note that we pick an index on the SV side so that we use the right // random seed. Then we convert back to a filename with another DPI call. If the result is the // empty string, something went wrong. - elf_path = OtbnTestHelperGetFilePath(helper, $urandom_range(num_files - 1)); + elf_path = AccTestHelperGetFilePath(helper, $urandom_range(num_files - 1)); `DV_CHECK_FATAL(elf_path.len() > 0, "Bad index for ELF file") // Use sformat in a trivial way to take a copy of the string, so we can safely free helper (and @@ -740,20 +740,20 @@ class otbn_base_vseq extends cip_base_vseq #( elf_path = $sformatf("%0s", elf_path); // Now that we've taken a copy of elf_path, we can safely free the test helper. - OtbnTestHelperFree(helper); + AccTestHelperFree(helper); return elf_path; endfunction - // Start running OTBN (forking off a run_otbn task) and return when it's still going. + // Start running ACC (forking off a run_acc task) and return when it's still going. // // This works by guessing the number of cycles to run and then returning after that time. Of - // course, the run_otbn task might actually finish in less time than that! If so, we run a second + // course, the run_acc task might actually finish in less time than that! If so, we run a second // time and guess a smaller value. // // This can be used to implement things like the reset test where we want to inject some sort of // error part-way into a run. - task start_running_otbn(bit check_end_addr); + task start_running_acc(bit check_end_addr); bit timed_out = 1'b0; for (int i = 0; i < 10; i++) begin @@ -769,9 +769,9 @@ class otbn_base_vseq extends cip_base_vseq #( fork : isolation_fork begin fork - run_otbn(.check_end_addr(check_end_addr)); + run_acc(.check_end_addr(check_end_addr)); begin - wait(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusBusyExecute); + wait(cfg.model_agent_cfg.vif.status == acc_pkg::StatusBusyExecute); repeat (wait_cycles) begin @(cfg.clk_rst_vif.cbn); cycle_counter++; @@ -779,24 +779,24 @@ class otbn_base_vseq extends cip_base_vseq #( end join_any - // When we get here, we know that either the OTBN sequence finished or we timed out and - // it's still going. We can see whether OTBN is still in the middle of a run by looking at + // When we get here, we know that either the ACC sequence finished or we timed out and + // it's still going. We can see whether ACC is still in the middle of a run by looking at // the status from the model (which is also in sync with the RTL). Because we wait on the // negedge when updating cycle_counter above, we know we've got the "new version" of the // status at this point. - if (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusBusyExecute) begin + if (cfg.model_agent_cfg.vif.status == acc_pkg::StatusBusyExecute) begin timed_out = 1'b1; end else begin timed_out = 1'b0; - // The OTBN sequence finished so update wait_cycles. cycle_counter should be at most equal - // to wait_cycles because we'll stop at that point. It can be equal if OTBN happens to + // The ACC sequence finished so update wait_cycles. cycle_counter should be at most equal + // to wait_cycles because we'll stop at that point. It can be equal if ACC happens to // complete its operation in wait_cycles cycles. `DV_CHECK_LE_FATAL(cycle_counter, wait_cycles); longest_run_ = cycle_counter; - // Wait for the run_otbn thread to finish. This will usually be instant, but might take + // Wait for the run_acc thread to finish. This will usually be instant, but might take // a couple of cycles if we happen to have timed out exactly at the end of the run (when - // the status has switched, but before run_otbn finishes) + // the status has switched, but before run_acc finishes) wait(!running_); // Kill the counter thread @@ -813,9 +813,9 @@ class otbn_base_vseq extends cip_base_vseq #( // happen! `DV_CHECK_FATAL(timed_out, "Failed to pick a working time-out") - // We have stopped the run_otbn process that was running. Update the "internal state to the + // We have stopped the run_acc process that was running. Update the "internal state to the // vseq" so that we can safely call this task another time. The running_ status is used to track - // the fact that run_otbn is going (not true because we just killed the process). Similarly, + // the fact that run_acc is going (not true because we just killed the process). Similarly, // stop_tokens is positive because _run_sideload_sequence was running when it was killed. Zero // that. running_ = 1'b0; @@ -832,8 +832,8 @@ class otbn_base_vseq extends cip_base_vseq #( // Overridden from cip_base_vseq // // This task in the base sequence checks whether any alerts fire. This doesn't really work for - // OTBN because it's not in sync with the logic that actually generates the alerts. We handle this - // properly in the scoreboard so want to disable this check except in otbn_common_vseq (which is + // ACC because it's not in sync with the logic that actually generates the alerts. We handle this + // properly in the scoreboard so want to disable this check except in acc_common_vseq (which is // used for the generic alert tests). task check_no_fatal_alerts(); if (enable_base_alert_checks) super.check_no_fatal_alerts(); @@ -889,16 +889,16 @@ class otbn_base_vseq extends cip_base_vseq #( end endtask - // Task to check if otbn is in locked state. If otbn is indeed locked, then ensure fatal error is + // Task to check if acc is in locked state. If acc is indeed locked, then ensure fatal error is // asserted and reset the dut. virtual task reset_if_locked(); uvm_reg_data_t act_val; - wait (!(cfg.model_agent_cfg.vif.status inside {otbn_pkg::StatusBusyExecute, - otbn_pkg::StatusBusySecWipeInt})); + wait (!(cfg.model_agent_cfg.vif.status inside {acc_pkg::StatusBusyExecute, + acc_pkg::StatusBusySecWipeInt})); // At this point, our status has changed. We're probably actually seeing the alert now, but make // sure that it has gone out in at most 100 cycles. - if (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) begin + if (cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) begin fork begin csr_utils_pkg::csr_rd(.ptr(ral.status), .value(act_val)); @@ -920,21 +920,21 @@ class otbn_base_vseq extends cip_base_vseq #( // wait until the end of this one. Otherwise, it will wait for the next one to start. protected task wait_edn_beat(edn_idx_e iface_idx, int max_wait_before); // Wait at least one cycle (EDN clock) to clear any finishing beat on the EDN interface. Then - // wait up to max_wait_before cycles (main clock) for OTBN to ask for some data. + // wait up to max_wait_before cycles (main clock) for ACC to ask for some data. @(cfg.m_edn_pull_agent_cfgs[iface_idx].vif.mon_cb); for (int i = 0; i < max_wait_before; ++i) begin if (!cfg.m_edn_pull_agent_cfgs[iface_idx].is_silent()) break; @(cfg.clk_rst_vif.cbn); end - // Now we know that OTBN is asking for *something*. Wait until the beat has completed. + // Now we know that ACC is asking for *something*. Wait until the beat has completed. cfg.m_edn_pull_agent_cfgs[iface_idx].wait_while_running(); endtask // Wait for a reseed on RND or URND // // This assumes that none of the 8 beats of data had been transferred so far, so it waits for each - // of them. The max_wait_before argument gives the number of cycles allowed before OTBN asks for + // of them. The max_wait_before argument gives the number of cycles allowed before ACC asks for // each beat of data. // // If we are called when some beats have already been transferred then we'll end up waiting some @@ -975,4 +975,4 @@ class otbn_base_vseq extends cip_base_vseq #( repeat (2) wait_secure_wipe_phase(); endtask -endclass : otbn_base_vseq +endclass : acc_base_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_common_vseq.sv similarity index 90% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_common_vseq.sv index 5b1d4d24871..be25f223e45 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_common_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_common_vseq.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_common_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_common_vseq) +class acc_common_vseq extends acc_base_vseq; + `uvm_object_utils(acc_common_vseq) bit sb_setting; constraint num_trans_c { num_trans inside {[1:2]}; @@ -43,9 +43,9 @@ class otbn_common_vseq extends otbn_base_vseq; // If we see a write which causes an integrity error AND we've disabled the scoreboard (which // has its own predictor), we update the predicted value of the STATUS register to be LOCKED. if (completed && saw_err && !cfg.en_scb && tl_intg_err_type != TlIntgErrNone) begin - `DV_WAIT(!(cfg.model_agent_cfg.vif.status inside {otbn_pkg::StatusBusyExecute, - otbn_pkg::StatusBusySecWipeInt})); - `DV_CHECK_FATAL(ral.status.status.predict(otbn_pkg::StatusLocked, .kind(UVM_PREDICT_READ)), + `DV_WAIT(!(cfg.model_agent_cfg.vif.status inside {acc_pkg::StatusBusyExecute, + acc_pkg::StatusBusySecWipeInt})); + `DV_CHECK_FATAL(ral.status.status.predict(acc_pkg::StatusLocked, .kind(UVM_PREDICT_READ)), "Failed to update STATUS register") end endtask @@ -55,9 +55,9 @@ class otbn_common_vseq extends otbn_base_vseq; // don't actually start the processor or model (or, indeed, tell the model about the error), this // assertion will be false. task run_tl_intg_err_vseq(int num_times = 1); - `DV_ASSERT_CTRL_REQ("otbn_status_assert_en", 1'b0) + `DV_ASSERT_CTRL_REQ("acc_status_assert_en", 1'b0) super.run_tl_intg_err_vseq(num_times); - `DV_ASSERT_CTRL_REQ("otbn_status_assert_en", 1'b1) + `DV_ASSERT_CTRL_REQ("acc_status_assert_en", 1'b1) endtask // Overridden from cip_base_vseq. Initialise Imem and Dmem and then call the super function. @@ -70,8 +70,8 @@ class otbn_common_vseq extends otbn_base_vseq; virtual function void inject_intg_fault_in_passthru_mem(dv_base_mem mem, bit [bus_params_pkg::BUS_AW-1:0] addr); - logic [otp_ctrl_pkg::OtbnKeyWidth-1:0] key; - logic [otp_ctrl_pkg::OtbnNonceWidth-1:0] nonce; + logic [otp_ctrl_pkg::AccKeyWidth-1:0] key; + logic [otp_ctrl_pkg::AccNonceWidth-1:0] nonce; bit [BaseIntgWidth-1:0] flip_bits; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL( @@ -123,8 +123,8 @@ class otbn_common_vseq extends otbn_base_vseq; // // The CSR read uses a back-door interface because then we will get a response, even if TL // access is frozen. - `DV_WAIT(!(cfg.model_agent_cfg.vif.status inside {otbn_pkg::StatusBusyExecute, - otbn_pkg::StatusBusySecWipeInt})); + `DV_WAIT(!(cfg.model_agent_cfg.vif.status inside {acc_pkg::StatusBusyExecute, + acc_pkg::StatusBusySecWipeInt})); cfg.clk_rst_vif.wait_clks(1); csr_utils_pkg::csr_rd_check(.ptr(ral.status), .compare_value('hFF), .backdoor(1)); @@ -190,15 +190,15 @@ class otbn_common_vseq extends otbn_base_vseq; virtual function void sec_cm_fi_ctrl_svas(sec_cm_base_if_proxy if_proxy, bit enable); if (enable) begin - $asserton(0, "tb.dut.u_otbn_core.u_otbn_controller.ControllerStateValid"); + $asserton(0, "tb.dut.u_acc_core.u_acc_controller.ControllerStateValid"); $asserton(0, "tb.MatchingStatus_A"); $asserton(0, "tb.MatchingReqURND_A"); - $asserton(0, "tb.dut.u_otbn_core.u_otbn_start_stop_control.StartStopStateValid_A"); + $asserton(0, "tb.dut.u_acc_core.u_acc_start_stop_control.StartStopStateValid_A"); end else begin - $assertoff(0, "tb.dut.u_otbn_core.u_otbn_controller.ControllerStateValid"); + $assertoff(0, "tb.dut.u_acc_core.u_acc_controller.ControllerStateValid"); $assertoff(0, "tb.MatchingStatus_A"); $assertoff(0, "tb.MatchingReqURND_A"); - $assertoff(0, "tb.dut.u_otbn_core.u_otbn_start_stop_control.StartStopStateValid_A"); + $assertoff(0, "tb.dut.u_acc_core.u_acc_start_stop_control.StartStopStateValid_A"); end if (if_proxy.sec_cm_type == SecCmPrimCount) begin @@ -251,7 +251,7 @@ class otbn_common_vseq extends otbn_base_vseq; begin bit [31:0] err_val = 32'd1 << 20; `uvm_info(`gfn, "injecting fsm error into ISS", UVM_HIGH) - if (!uvm_re_match("*u_otbn_start_stop_control*", if_proxy.path)) begin + if (!uvm_re_match("*u_acc_start_stop_control*", if_proxy.path)) begin cfg.model_agent_cfg.vif.lock_immediately(err_val); end else begin cfg.model_agent_cfg.vif.send_err_escalation(err_val); diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_controller_ispr_rdata_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_controller_ispr_rdata_err_vseq.sv similarity index 65% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_controller_ispr_rdata_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_controller_ispr_rdata_err_vseq.sv index 7e63d45a3fa..45d77cf3807 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_controller_ispr_rdata_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_controller_ispr_rdata_err_vseq.sv @@ -3,25 +3,25 @@ // SPDX-License-Identifier: Apache-2.0 // A sequence that runs a program multiple times and corrupts the `ispr_rdata_intg_i` signal of -// `otbn_controller` while OTBN is still running. +// `acc_controller` while ACC is still running. -class otbn_controller_ispr_rdata_err_vseq extends otbn_intg_err_vseq; - `uvm_object_utils(otbn_controller_ispr_rdata_err_vseq) +class acc_controller_ispr_rdata_err_vseq extends acc_intg_err_vseq; + `uvm_object_utils(acc_controller_ispr_rdata_err_vseq) `uvm_object_new - protected task await_use(output bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words); + protected task await_use(output bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words); used_words = '0; `uvm_info(`gfn, "Waiting for `ispr_rdata_intg` to be used", UVM_LOW) cfg.controller_vif.wait_for_ispr_rdata_used(200, used_words); endtask - protected task inject_errors(input bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words, - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] corrupted_words); - int unsigned corrupt_word_pct[otbn_pkg::BaseWordsPerWLEN]; - bit [otbn_pkg::ExtWLEN-1:0] new_data; + protected task inject_errors(input bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words, + output bit [acc_pkg::BaseWordsPerWLEN-1:0] corrupted_words); + int unsigned corrupt_word_pct[acc_pkg::BaseWordsPerWLEN]; + bit [acc_pkg::ExtWLEN-1:0] new_data; - for (int i_word = 0; i_word < otbn_pkg::BaseWordsPerWLEN; i_word++) begin + for (int i_word = 0; i_word < acc_pkg::BaseWordsPerWLEN; i_word++) begin if (used_words[i_word]) begin // Corrupt used words with a fairly high chance. corrupt_word_pct[i_word] = 75; @@ -36,7 +36,7 @@ class otbn_controller_ispr_rdata_err_vseq extends otbn_intg_err_vseq; corrupted_words); if (corrupted_words != '0) begin - `uvm_info(`gfn, "Injecting errors into `ispr_rdata_intg_i` of `otbn_controller`", UVM_LOW) + `uvm_info(`gfn, "Injecting errors into `ispr_rdata_intg_i` of `acc_controller`", UVM_LOW) cfg.controller_vif.force_ispr_rdata_intg_i(new_data); end else begin `uvm_info(`gfn, "Randomization decided to not inject any errors.", UVM_LOW) diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_ctrl_redun_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_ctrl_redun_vseq.sv similarity index 78% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_ctrl_redun_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_ctrl_redun_vseq.sv index 95429899e34..2a356bf9ae7 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_ctrl_redun_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_ctrl_redun_vseq.sv @@ -4,8 +4,8 @@ // A sequence to verify the countermeasure(s) PC.CTRL_FLOW.REDUN. -class otbn_ctrl_redun_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_ctrl_redun_vseq) +class acc_ctrl_redun_vseq extends acc_single_vseq; + `uvm_object_utils(acc_ctrl_redun_vseq) `uvm_object_new bit have_injected_error; @@ -13,7 +13,7 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; task body(); do_end_addr_check = 0; - // Try to run an OTBN application to completion, injecting an error in the middle. We might be + // Try to run an ACC application to completion, injecting an error in the middle. We might be // unlucky and fail to find a good time to inject an error. In that case, try_once will tidy up // and we can try again. repeat (4) begin @@ -26,12 +26,12 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; endtask: body - // Run the otbn_single_vseq body, which runs a single OTBN application to completion. At the + // Run the acc_single_vseq body, which runs a single ACC application to completion. At the // same time, try to inject an error and check that the RTL (and model) both spot the error. task try_once(); fork begin : isolation_fork fork - // Run the otbn_single_vseq body + // Run the acc_single_vseq body super.body(); // Try to inject an error inject_redun_err(); @@ -40,7 +40,7 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; // If have_injected_error is false then super.body() has run to completion and we should kill // the inject_redun_err process (since it isn't going to find a time now). If it is true then // we managed to inject an error. In that case, wait until super.body() has run to completion, - // which lets the run_otbn task tidy up properly. + // which lets the run_acc task tidy up properly. if (!have_injected_error) disable fork; else wait fork; end join @@ -88,8 +88,8 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; case(err_type) 0: begin report_err_type("error on ispr_addr during a write"); - err_path = "tb.dut.u_otbn_core.u_otbn_alu_bignum.ispr_addr_i"; - wait_for_flag("tb.dut.u_otbn_core.u_otbn_alu_bignum.ispr_wr_en", 1); + err_path = "tb.dut.u_acc_core.u_acc_alu_bignum.ispr_addr_i"; + wait_for_flag("tb.dut.u_acc_core.u_acc_alu_bignum.ispr_wr_en", 1); `DV_CHECK_FATAL(uvm_hdl_read(err_path, good_addr)); // Mask to corrupt 1 to 2 bits of the ispr addr `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask, $countones(mask) inside {[1:2]};) @@ -98,8 +98,8 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; end 1: begin report_err_type("error on ispr_addr during a read"); - err_path = "tb.dut.u_otbn_core.u_otbn_alu_bignum.ispr_addr_i"; - wait_for_flag("tb.dut.u_otbn_core.u_otbn_alu_bignum.ispr_rd_en_i", 1); + err_path = "tb.dut.u_acc_core.u_acc_alu_bignum.ispr_addr_i"; + wait_for_flag("tb.dut.u_acc_core.u_acc_alu_bignum.ispr_rd_en_i", 1); `DV_CHECK_FATAL(uvm_hdl_read(err_path, good_addr)); // Mask to corrupt 1 to 2 bits of the ispr addr `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask, $countones(mask) inside {[1:2]};) @@ -113,13 +113,13 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; bit avoid_addv = 1'b0; bit op_valid = 1'b0; - string alu_path = "tb.dut.u_otbn_core.u_otbn_alu_bignum"; + string alu_path = "tb.dut.u_acc_core.u_acc_alu_bignum"; string op_path = {alu_path, ".operation_i.op"}; string op_valid_path = {alu_path, ".operation_valid_i"}; string carry_path = {alu_path, ".selected_flags.C"}; report_err_type("error in opcode on the bignum side"); - err_path = "tb.dut.u_otbn_core.u_otbn_alu_bignum.operation_i.op"; + err_path = "tb.dut.u_acc_core.u_acc_alu_bignum.operation_i.op"; // We want to inject an error when the bignum ALU is performing an operation, so its // operation_valid_i flag should be high, and this should be the opcode for a genuine @@ -128,7 +128,7 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; wait_for_flag(op_valid_path, 1); uvm_hdl_read(op_valid_path, op_valid); `DV_CHECK_FATAL(uvm_hdl_read(err_path, good_op)) - if (good_op <= otbn_pkg::AluOpBignumNot) + if (good_op <= acc_pkg::AluOpBignumNot) break; // If the opcode doesn't specify a known operation, we'll need to wait a bit longer. Go // around again. @@ -155,35 +155,35 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; // additions or subtractions. This will avoid e.g. converting between add and subb. `DV_CHECK_FATAL(uvm_hdl_read(carry_path, selected_flags_C)) if (!selected_flags_C) begin - if (good_op inside {otbn_pkg::AluOpBignumAdd, otbn_pkg::AluOpBignumAddc, - otbn_pkg::AluOpBignumSub, otbn_pkg::AluOpBignumSubb}) begin + if (good_op inside {acc_pkg::AluOpBignumAdd, acc_pkg::AluOpBignumAddc, + acc_pkg::AluOpBignumSub, acc_pkg::AluOpBignumSubb}) begin avoid_addc = 1'b1; end - if (good_op inside {otbn_pkg::AluOpBignumAddm, otbn_pkg::AluOpBignumAddv, - otbn_pkg::AluOpBignumSubm, otbn_pkg::AluOpBignumSubv, - otbn_pkg::AluOpBignumAddvm, otbn_pkg::AluOpBignumSubvm}) begin + if (good_op inside {acc_pkg::AluOpBignumAddm, acc_pkg::AluOpBignumAddv, + acc_pkg::AluOpBignumSubm, acc_pkg::AluOpBignumSubv, + acc_pkg::AluOpBignumAddvm, acc_pkg::AluOpBignumSubvm}) begin avoid_addv = 1'b1; end end `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_op, bad_op != good_op; - bad_op != otbn_pkg::AluOpBignumNone; - avoid_addc -> (bad_op != otbn_pkg::AluOpBignumAdd && - bad_op != otbn_pkg::AluOpBignumAddc && - bad_op != otbn_pkg::AluOpBignumSub && - bad_op != otbn_pkg::AluOpBignumSubb); + bad_op != acc_pkg::AluOpBignumNone; + avoid_addc -> (bad_op != acc_pkg::AluOpBignumAdd && + bad_op != acc_pkg::AluOpBignumAddc && + bad_op != acc_pkg::AluOpBignumSub && + bad_op != acc_pkg::AluOpBignumSubb); bad_op != good_op + 3; good_op != bad_op + 3;) `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_op, bad_op != good_op; - bad_op != otbn_pkg::AluOpBignumNone; - avoid_addv -> (bad_op != otbn_pkg::AluOpBignumAddm && - bad_op != otbn_pkg::AluOpBignumAddv && - bad_op != otbn_pkg::AluOpBignumSubm && - bad_op != otbn_pkg::AluOpBignumSubv && - bad_op != otbn_pkg::AluOpBignumAddvm && - bad_op != otbn_pkg::AluOpBignumSubvm); + bad_op != acc_pkg::AluOpBignumNone; + avoid_addv -> (bad_op != acc_pkg::AluOpBignumAddm && + bad_op != acc_pkg::AluOpBignumAddv && + bad_op != acc_pkg::AluOpBignumSubm && + bad_op != acc_pkg::AluOpBignumSubv && + bad_op != acc_pkg::AluOpBignumAddvm && + bad_op != acc_pkg::AluOpBignumSubvm); bad_op != good_op + 5; good_op != bad_op + 5;) `uvm_info(`gfn, @@ -193,13 +193,13 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; end 3: begin bit choose_err; - otbn_pkg::insn_dec_shared_t insn_dec_shared_i; + acc_pkg::insn_dec_shared_t insn_dec_shared_i; `DV_CHECK_STD_RANDOMIZE_FATAL(choose_err) report_err_type($sformatf("error on lsu_addr_en (choose_err = %0d)", choose_err)); - err_path = "tb.dut.u_otbn_core.u_otbn_controller.insn_dec_shared_i"; - wait_for_flag("tb.dut.u_otbn_core.u_otbn_controller.insn_valid_i", 1); + err_path = "tb.dut.u_acc_core.u_acc_controller.insn_dec_shared_i"; + wait_for_flag("tb.dut.u_acc_core.u_acc_controller.insn_valid_i", 1); `DV_CHECK_FATAL(uvm_hdl_read(err_path, insn_dec_shared_i)); case(choose_err) 0: begin @@ -222,12 +222,12 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; report_err_type($sformatf("core error (choose_err = %0d, after %0d clocks)", choose_err, num_clks)); cfg.clk_rst_vif.wait_clks(num_clks); - wait_for_flag("tb.dut.u_otbn_core.insn_valid", 1); + wait_for_flag("tb.dut.u_acc_core.insn_valid", 1); case(choose_err) 0: begin bit [31:0] bad_rf_ren_a; bit [31:0] good_rf_ren_a; - err_path = "tb.dut.u_otbn_core.rf_predec_bignum.rf_ren_a"; + err_path = "tb.dut.u_acc_core.rf_predec_bignum.rf_ren_a"; `DV_CHECK_FATAL(uvm_hdl_read(err_path, good_rf_ren_a)); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_rf_ren_a, $countones(bad_rf_ren_a) == 1; bad_rf_ren_a != good_rf_ren_a;) @@ -236,7 +236,7 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; 1: begin bit [31:0] bad_rf_ren_b; bit [31:0] good_rf_ren_b; - err_path = "tb.dut.u_otbn_core.rf_predec_bignum.rf_ren_b"; + err_path = "tb.dut.u_acc_core.rf_predec_bignum.rf_ren_b"; `DV_CHECK_FATAL(uvm_hdl_read(err_path, good_rf_ren_b)); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_rf_ren_b, $countones(bad_rf_ren_b) == 1; bad_rf_ren_b != good_rf_ren_b;) @@ -245,7 +245,7 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; 2: begin bit [8:0] bad_ispr_rd_en; bit [8:0] good_ispr_rd_en; - err_path = "tb.dut.u_otbn_core.ispr_predec_bignum.ispr_rd_en"; + err_path = "tb.dut.u_acc_core.ispr_predec_bignum.ispr_rd_en"; `DV_CHECK_FATAL(uvm_hdl_read(err_path, good_ispr_rd_en)); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_ispr_rd_en, $countones(bad_ispr_rd_en) == 1; bad_ispr_rd_en != good_ispr_rd_en;) @@ -262,24 +262,24 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; int unsigned num_clks = $urandom_range(10, 100); `DV_CHECK_STD_RANDOMIZE_FATAL(choose_err) - report_err_type($sformatf("error in otbn_mac_bignum (choose_err=%0d, after %0d clocks)", + report_err_type($sformatf("error in acc_mac_bignum (choose_err=%0d, after %0d clocks)", choose_err, num_clks)); - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusBusyExecute) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusBusyExecute) cfg.clk_rst_vif.wait_clks(num_clks); - // Wait for valid instruction, because `otbn_core` only propagates bignum MAC predec errors + // Wait for valid instruction, because `acc_core` only propagates bignum MAC predec errors // for valid instructions. - wait_for_flag("tb.dut.u_otbn_core.insn_valid", 1); + wait_for_flag("tb.dut.u_acc_core.insn_valid", 1); case(choose_err) 0: begin - err_path = "tb.dut.u_otbn_core.u_otbn_mac_bignum.mac_en_i"; + err_path = "tb.dut.u_acc_core.u_acc_mac_bignum.mac_en_i"; `DV_CHECK_FATAL(uvm_hdl_read(err_path, mac_en)); `DV_CHECK_FATAL(uvm_hdl_force(err_path, !mac_en) == 1); end 1: begin bit zero_acc; - err_path = "tb.dut.u_otbn_core.u_otbn_mac_bignum.operation_i.zero_acc"; - wait_for_flag("tb.dut.u_otbn_core.u_otbn_mac_bignum.mac_en_i", 1); + err_path = "tb.dut.u_acc_core.u_acc_mac_bignum.operation_i.zero_acc"; + wait_for_flag("tb.dut.u_acc_core.u_acc_mac_bignum.mac_en_i", 1); `DV_CHECK_FATAL(uvm_hdl_read(err_path, zero_acc)); `DV_CHECK_FATAL(uvm_hdl_force(err_path, !zero_acc) == 1); end @@ -294,11 +294,11 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; bit [4:0] mask; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(choose_err, choose_err inside {[0:2]};) - report_err_type($sformatf("error in otbn_rf_bignum (choose_err=%0d)", choose_err)); + report_err_type($sformatf("error in acc_rf_bignum (choose_err=%0d)", choose_err)); case(choose_err) 0: begin - err_path = "tb.dut.u_otbn_core.u_otbn_rf_bignum.wr_addr_i[4:0]"; - wait_for_flag("tb.dut.u_otbn_core.u_otbn_rf_bignum.wr_en_i[1:0]", 2); + err_path = "tb.dut.u_acc_core.u_acc_rf_bignum.wr_addr_i[4:0]"; + wait_for_flag("tb.dut.u_acc_core.u_acc_rf_bignum.wr_en_i[1:0]", 2); `DV_CHECK_FATAL(uvm_hdl_read(err_path, addr)); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask, $countones(mask) inside {[1:2]};) addr = addr ^ mask; @@ -311,16 +311,16 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; cfg.clk_rst_vif.wait_clks(1); end 1: begin - err_path = "tb.dut.u_otbn_core.u_otbn_rf_bignum.rd_addr_a_i"; - wait_for_flag("tb.dut.u_otbn_core.u_otbn_rf_bignum.rd_en_a_i", 1); + err_path = "tb.dut.u_acc_core.u_acc_rf_bignum.rd_addr_a_i"; + wait_for_flag("tb.dut.u_acc_core.u_acc_rf_bignum.rd_en_a_i", 1); `DV_CHECK_FATAL(uvm_hdl_read(err_path, addr)); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask, $countones(mask) inside {[1:2]};) addr = addr ^ mask; `DV_CHECK_FATAL(uvm_hdl_force(err_path, addr) == 1); end 2: begin - err_path = "tb.dut.u_otbn_core.u_otbn_rf_bignum.rd_addr_b_i"; - wait_for_flag("tb.dut.u_otbn_core.u_otbn_rf_bignum.rd_en_b_i", 1); + err_path = "tb.dut.u_acc_core.u_acc_rf_bignum.rd_addr_b_i"; + wait_for_flag("tb.dut.u_acc_core.u_acc_rf_bignum.rd_en_b_i", 1); `DV_CHECK_FATAL(uvm_hdl_read(err_path, addr)); `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask, $countones(mask) inside {[1:2]};) addr = addr ^ mask; @@ -338,7 +338,7 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; `uvm_info(`gfn, "injecting bad internal state error into ISS", UVM_HIGH) have_injected_error = 1'b1; cfg.model_agent_cfg.vif.send_err_escalation(err_val); - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) `DV_CHECK_FATAL(uvm_hdl_release(err_path) == 1); reset_if_locked(); @@ -347,4 +347,4 @@ class otbn_ctrl_redun_vseq extends otbn_single_vseq; $asserton(0, "tb.dut.g_secure_wipe_assertions"); endtask -endclass : otbn_ctrl_redun_vseq +endclass : acc_ctrl_redun_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_dmem_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_dmem_err_vseq.sv similarity index 72% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_dmem_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_dmem_err_vseq.sv index 5b07ac51eac..0cb12798bc4 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_dmem_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_dmem_err_vseq.sv @@ -3,10 +3,10 @@ // SPDX-License-Identifier: Apache-2.0 // A sequence that runs a program multiple times and corrupts the -// dmem registers while the otbn is still running. +// dmem registers while the acc is still running. -class otbn_dmem_err_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_dmem_err_vseq) +class acc_dmem_err_vseq extends acc_base_vseq; + `uvm_object_utils(acc_dmem_err_vseq) `uvm_object_new @@ -19,11 +19,11 @@ class otbn_dmem_err_vseq extends otbn_base_vseq; logic [63:0] nonce; elf_path = pick_elf_path(); - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) load_elf(elf_path, 1'b1); - // Start OTBN running. When this task returns, we'll be in the middle of a run. - start_running_otbn(.check_end_addr(1'b0)); + // Start ACC running. When this task returns, we'll be in the middle of a run. + start_running_acc(.check_end_addr(1'b0)); key = cfg.get_dmem_key(); nonce = cfg.get_dmem_nonce(); @@ -43,8 +43,8 @@ class otbn_dmem_err_vseq extends otbn_base_vseq; cfg.model_agent_cfg.vif.invalidate_dmem(); - wait (!(cfg.model_agent_cfg.vif.status inside {otbn_pkg::StatusBusyExecute, - otbn_pkg::StatusBusySecWipeInt})); + wait (!(cfg.model_agent_cfg.vif.status inside {acc_pkg::StatusBusyExecute, + acc_pkg::StatusBusySecWipeInt})); // At this point, our status has changed. We're probably actually seeing the alert now, but make // sure that it has gone out in at most 100 cycles. diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_escalate_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_escalate_vseq.sv similarity index 78% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_escalate_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_escalate_vseq.sv index 3e27b732335..d1f06cc4259 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_escalate_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_escalate_vseq.sv @@ -5,8 +5,8 @@ // A sequence that runs a program, asserting the lc_escalate_en_i or lc_rma_req_i at some point // during the run. Occasionally, it will assert just before or just after. -class otbn_escalate_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_escalate_vseq) +class acc_escalate_vseq extends acc_base_vseq; + `uvm_object_utils(acc_escalate_vseq) `uvm_object_new @@ -22,20 +22,20 @@ class otbn_escalate_vseq extends otbn_base_vseq; string elf_path; bit select_rma_req; escalate_timing_e escalate_timing; - otbn_pkg::otbn_start_stop_state_e start_stop_state_for_escalate; + acc_pkg::acc_start_stop_state_e start_stop_state_for_escalate; elf_path = pick_elf_path(); - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) - // Pick whether we're going to send RMA request or escalation to OTBN. + // Pick whether we're going to send RMA request or escalation to ACC. select_rma_req = $urandom_range(1); // Choose when we send the lc_ctrl stimulus - // Immediate - Within 5 cycles of simulation start and before we run the OTBN program - // Before - Within 100 cycles of simulation start and before we run the OTBN program - // During - During the OTBN run + // Immediate - Within 5 cycles of simulation start and before we run the ACC program + // Before - Within 100 cycles of simulation start and before we run the ACC program + // During - During the ACC run // Sec Wipe State - When we observe a particular state of the secure wipe process - // After - After the OTBN run is complete + // After - After the ACC run is complete `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(escalate_timing, escalate_timing dist { GO_IMMEDIATELY := 15, @@ -68,9 +68,9 @@ class otbn_escalate_vseq extends otbn_base_vseq; end if (escalate_timing == GO_AFTER) begin - // We want to send the escalation/RMA signal after OTBN is finished. Run an operation, send + // We want to send the escalation/RMA signal after ACC is finished. Run an operation, send // the signal, then wait for the fatal alert. - run_otbn(); + run_acc(); send_lc_ctrl_stimulus(10, select_rma_req); wait_alert_and_reset(); return; @@ -80,28 +80,28 @@ class otbn_escalate_vseq extends otbn_base_vseq; `uvm_info(`gfn, "Going during", UVM_LOW) if (escalate_timing == GO_DURING) begin - // Start OTBN running. When this task returns, we'll be in the middle of a run. - start_running_otbn(.check_end_addr(1'b0)); + // Start ACC running. When this task returns, we'll be in the middle of a run. + start_running_acc(.check_end_addr(1'b0)); end else begin // GO_SEC_WIPE_STATE // Randomly choose a state of secure wipe to send the stimulus in `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(start_stop_state_for_escalate, start_stop_state_for_escalate inside { - otbn_pkg::OtbnStartStopSecureWipeWdrUrnd, - otbn_pkg::OtbnStartStopSecureWipeAccModBaseUrnd, - otbn_pkg::OtbnStartStopSecureWipeAllZero, - otbn_pkg::OtbnStartStopSecureWipeComplete + acc_pkg::AccStartStopSecureWipeWdrUrnd, + acc_pkg::AccStartStopSecureWipeAccModBaseUrnd, + acc_pkg::AccStartStopSecureWipeAllZero, + acc_pkg::AccStartStopSecureWipeComplete }; ) - // Start running OTBN and wait for the state to reach the chosen one in parallel. Fork exits + // Start running ACC and wait for the state to reach the chosen one in parallel. Fork exits // only once we've hit the chosen state fork - start_running_otbn(.check_end_addr(1'b0)); - wait (cfg.trace_vif.otbn_start_stop_state == start_stop_state_for_escalate); + start_running_acc(.check_end_addr(1'b0)); + wait (cfg.trace_vif.acc_start_stop_state == start_stop_state_for_escalate); join end // Send an escalation/RMA signal immediately (the randomisation about where we should strike - // has already been done inside start_running_otbn() for GO_DURING) + // has already been done inside start_running_acc() for GO_DURING) send_lc_ctrl_stimulus(1, select_rma_req); // Wait for an alert to come out before returning @@ -131,7 +131,7 @@ class otbn_escalate_vseq extends otbn_base_vseq; `DV_SPINWAIT_EXIT( wait(cfg.escalate_vif.ack == lc_ctrl_pkg::On);, cfg.clk_rst_vif.wait_clks(500);, - "Not getting rma_ack from OTBN for 500 cycles!") + "Not getting rma_ack from ACC for 500 cycles!") endtask // Wait for a fatal alert to come out and retrigger at least once. Then reset the DUT. This is diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_illegal_mem_acc_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_illegal_mem_acc_vseq.sv similarity index 91% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_illegal_mem_acc_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_illegal_mem_acc_vseq.sv index 73172daff78..1a333a4355c 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_illegal_mem_acc_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_illegal_mem_acc_vseq.sv @@ -2,10 +2,10 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// A sequence to do illegal read and write accesses to the imem when the otbn is busy +// A sequence to do illegal read and write accesses to the imem when the acc is busy -class otbn_illegal_mem_acc_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_illegal_mem_acc_vseq) +class acc_illegal_mem_acc_vseq extends acc_single_vseq; + `uvm_object_utils(acc_illegal_mem_acc_vseq) `uvm_object_new task body(); @@ -36,7 +36,7 @@ class otbn_illegal_mem_acc_vseq extends otbn_single_vseq; // Pick on which memory we will be working on mem = is_imem ? ral.imem : ral.dmem; - wait (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusBusyExecute); + wait (cfg.model_agent_cfg.vif.status == acc_pkg::StatusBusyExecute); offset = $urandom_range(0, mem.get_n_bytes() - 1); cfg.en_scb_tl_err_chk = 0; fork @@ -79,4 +79,4 @@ class otbn_illegal_mem_acc_vseq extends otbn_single_vseq; cfg.en_scb_tl_err_chk = 1; endtask -endclass : otbn_illegal_mem_acc_vseq +endclass : acc_illegal_mem_acc_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_imem_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_imem_err_vseq.sv similarity index 75% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_imem_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_imem_err_vseq.sv index c8ea5f58f01..78feabfba87 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_imem_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_imem_err_vseq.sv @@ -3,10 +3,10 @@ // SPDX-License-Identifier: Apache-2.0 // A sequence that runs a program multiple times and corrupts the -// imem registers while the otbn is still running. +// imem registers while the acc is still running. -class otbn_imem_err_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_imem_err_vseq) +class acc_imem_err_vseq extends acc_base_vseq; + `uvm_object_utils(acc_imem_err_vseq) `uvm_object_new @@ -19,11 +19,11 @@ class otbn_imem_err_vseq extends otbn_base_vseq; logic [63:0] nonce; elf_path = pick_elf_path(); - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) load_elf(elf_path, 1'b1); - // Start OTBN running. When this task returns, we'll be in the middle of a run. - start_running_otbn(.check_end_addr(1'b0)); + // Start ACC running. When this task returns, we'll be in the middle of a run. + start_running_acc(.check_end_addr(1'b0)); key = cfg.get_imem_key(); nonce = cfg.get_imem_nonce(); @@ -44,13 +44,13 @@ class otbn_imem_err_vseq extends otbn_base_vseq; cfg.model_agent_cfg.vif.invalidate_imem(); - // If we were unlucky, we might have injected the errors while OTBN was executing an instruction + // If we were unlucky, we might have injected the errors while ACC was executing an instruction // that was already causing it to stop. To allow for this specific case, we wait 100 cycles to // let that instruction flush through and secure wiping to finish. repeat (100) @(cfg.clk_rst_vif.cbn); - // If OTBN is now idle, we hit this exact window and the test didn't do anything useful. Ho + // If ACC is now idle, we hit this exact window and the test didn't do anything useful. Ho // hum... Note that we don't need to apply a reset in this case. - if (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) begin + if (cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle) begin `uvm_info(`gfn, "Skipping test: we happened to inject the IMEM error at a bad time", UVM_LOW) return; end diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_intg_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_intg_err_vseq.sv similarity index 75% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_intg_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_intg_err_vseq.sv index 49d3f2a48f1..27387c025ce 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_intg_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_intg_err_vseq.sv @@ -2,31 +2,31 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// A sequence that runs a program multiple times and corrupts an integrity-checked signal while OTBN +// A sequence that runs a program multiple times and corrupts an integrity-checked signal while ACC // is still running. -class otbn_intg_err_vseq extends otbn_base_vseq; +class acc_intg_err_vseq extends acc_base_vseq; - `uvm_object_utils(otbn_intg_err_vseq) + `uvm_object_utils(acc_intg_err_vseq) `uvm_object_new // Wait until the integrity-checked signal is used (otherwise an injected error would not have any // consequences) or an internal timeout expires. The `used_words` output indicates which words // were used during the call of this task. - protected virtual task await_use(output bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words); + protected virtual task await_use(output bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words); endtask // Probabilistically corrupt 1 to 2 bits of each word of `orig_data`, with a probability of // `corrupt_word_pct` (in percent) per word. The `corrupted_words` output indicates which words // were corrupted. - protected function bit [otbn_pkg::ExtWLEN-1:0] corrupt_data( - input bit [otbn_pkg::ExtWLEN-1:0] orig_data, - input int unsigned corrupt_word_pct[otbn_pkg::BaseWordsPerWLEN], - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] corrupted_words + protected function bit [acc_pkg::ExtWLEN-1:0] corrupt_data( + input bit [acc_pkg::ExtWLEN-1:0] orig_data, + input int unsigned corrupt_word_pct[acc_pkg::BaseWordsPerWLEN], + output bit [acc_pkg::BaseWordsPerWLEN-1:0] corrupted_words ); - bit [otbn_pkg::ExtWLEN-1:0] new_data; - for (int i_word = 0; i_word < otbn_pkg::BaseWordsPerWLEN; i_word++) begin + bit [acc_pkg::ExtWLEN-1:0] new_data; + for (int i_word = 0; i_word < acc_pkg::BaseWordsPerWLEN; i_word++) begin bit [BaseIntgWidth-1:0] orig_word = orig_data[i_word*39+:39]; bit corrupt_word = $urandom_range(100) < corrupt_word_pct[i_word]; if (corrupt_word) begin @@ -44,8 +44,8 @@ class otbn_intg_err_vseq extends otbn_base_vseq; endfunction // Inject errors into the integrity-checked signal by `force`ing it. - protected virtual task inject_errors(input bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words, - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] corrupted_words); + protected virtual task inject_errors(input bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words, + output bit [acc_pkg::BaseWordsPerWLEN-1:0] corrupted_words); endtask // Release the `force`ing of the integrity-checked signal. @@ -60,11 +60,11 @@ class otbn_intg_err_vseq extends otbn_base_vseq; bit [ExtWLEN-1:0] new_data; elf_path = pick_elf_path(); - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) load_elf(elf_path, 1'b1); - // Start running OTBN. When this task returns, we'll be in the middle of a run. - start_running_otbn(.check_end_addr(1'b0)); + // Start running ACC. When this task returns, we'll be in the middle of a run. + start_running_acc(.check_end_addr(1'b0)); // Wait until the register containing the integrity-checked value is being used. await_use(used_words); @@ -83,7 +83,7 @@ class otbn_intg_err_vseq extends otbn_base_vseq; // Notify the model about the integrity violation error. if (|(corrupted_words & used_words)) begin - otbn_pkg::err_bits_t err_bits; + acc_pkg::err_bits_t err_bits; err_bits = '{reg_intg_violation: 1'b1, default: 1'b0}; cfg.model_agent_cfg.vif.send_err_escalation(err_bits); end @@ -92,13 +92,13 @@ class otbn_intg_err_vseq extends otbn_base_vseq; release_force(); if (|(corrupted_words & used_words)) begin - // OTBN should now do a secure wipe. Give it up to 4000 cycles to do so (because it needs to + // ACC should now do a secure wipe. Give it up to 4000 cycles to do so (because it needs to // go twice over all registers and reseed URND in between, the time of which depends on the // delay configured in the EDN model). cfg.clk_rst_vif.wait_n_clks(4000); // We should now be in a locked state after the secure wipe. - `DV_CHECK_FATAL(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked); + `DV_CHECK_FATAL(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked); // The scoreboard will have seen the transition to locked state and inferred that it should // see a fatal alert. However, it doesn't really have a way to ensure that we keep generating diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_mac_bignum_acc_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_mac_bignum_acc_err_vseq.sv similarity index 59% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_mac_bignum_acc_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_mac_bignum_acc_err_vseq.sv index 4ee01bab543..35d57ef4682 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_mac_bignum_acc_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_mac_bignum_acc_err_vseq.sv @@ -3,26 +3,26 @@ // SPDX-License-Identifier: Apache-2.0 // A sequence that runs a program multiple times and corrupts the `acc_intg_q` register of -// `otbn_mac_bignum` while OTBN is still running. +// `acc_mac_bignum` while ACC is still running. -class otbn_mac_bignum_acc_err_vseq extends otbn_intg_err_vseq; - `uvm_object_utils(otbn_mac_bignum_acc_err_vseq) +class acc_mac_bignum_acc_err_vseq extends acc_intg_err_vseq; + `uvm_object_utils(acc_mac_bignum_acc_err_vseq) `uvm_object_new - protected task await_use(output bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words); + protected task await_use(output bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words); used_words = '0; `uvm_info(`gfn, "Waiting for `acc_intg_q` to be used", UVM_LOW) cfg.mac_bignum_vif.wait_for_acc_used(200, used_words); endtask - protected task inject_errors(input bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words, - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] corrupted_words); - bit [otbn_pkg::ExtWLEN-1:0] new_data = corrupt_data(cfg.mac_bignum_vif.acc_intg_q, + protected task inject_errors(input bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words, + output bit [acc_pkg::BaseWordsPerWLEN-1:0] corrupted_words); + bit [acc_pkg::ExtWLEN-1:0] new_data = corrupt_data(cfg.mac_bignum_vif.acc_intg_q, '{default: 50}, corrupted_words); if (corrupted_words != '0) begin - `uvm_info(`gfn, "Injecting errors into `acc_intg_q` of `otbn_mac_bignum`", UVM_LOW) + `uvm_info(`gfn, "Injecting errors into `acc_intg_q` of `acc_mac_bignum`", UVM_LOW) cfg.mac_bignum_vif.force_acc_intg_q(new_data); end else begin `uvm_info(`gfn, "Randomization decided to not inject any errors.", UVM_LOW) diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_mem_gnt_acc_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_mem_gnt_acc_err_vseq.sv similarity index 89% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_mem_gnt_acc_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_mem_gnt_acc_err_vseq.sv index cbf969563bd..86825095982 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_mem_gnt_acc_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_mem_gnt_acc_err_vseq.sv @@ -4,8 +4,8 @@ // A sequence to verify the countermeasure(s) PC.CTRL_FLOW.REDUN. -class otbn_mem_gnt_acc_err_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_mem_gnt_acc_err_vseq) +class acc_mem_gnt_acc_err_vseq extends acc_single_vseq; + `uvm_object_utils(acc_mem_gnt_acc_err_vseq) `uvm_object_new task body(); @@ -59,9 +59,9 @@ class otbn_mem_gnt_acc_err_vseq extends otbn_single_vseq; `uvm_info(`gfn, "injecting bad internal state error into ISS", UVM_HIGH) @(cfg.clk_rst_vif.cb); cfg.model_agent_cfg.vif.send_err_escalation(err_val); - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) `DV_CHECK_FATAL(uvm_hdl_release(gnt_path) == 1); reset_if_locked(); `DV_ASSERT_CTRL_REQ("DMemAsserts", 1) endtask: inject_gnt_err -endclass : otbn_mem_gnt_acc_err_vseq +endclass : acc_mem_gnt_acc_err_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_multi_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_multi_vseq.sv similarity index 85% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_multi_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_multi_vseq.sv index 9cb49963cb5..71b040c037e 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_multi_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_multi_vseq.sv @@ -4,8 +4,8 @@ // A sequence that runs multiple programs (or maybe the same program multiple times) -class otbn_multi_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_multi_vseq) +class acc_multi_vseq extends acc_base_vseq; + `uvm_object_utils(acc_multi_vseq) // If we've already loaded a binary, we might decide to re-run it (this is going to be "more // back-to-back" because then we don't wait for the front-door load between runs). Make this @@ -41,16 +41,16 @@ class otbn_multi_vseq extends otbn_base_vseq; end begin if (rerun) begin - `uvm_info(`gfn, $sformatf("Re-using OTBN binary at `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Re-using ACC binary at `%0s'", elf_path), UVM_LOW) end else begin elf_path = pick_elf_path(); - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) load_elf(elf_path, 1'b0); end end join - run_otbn(do_end_addr_check); + run_acc(do_end_addr_check); end endtask diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_partial_wipe_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_partial_wipe_vseq.sv similarity index 75% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_partial_wipe_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_partial_wipe_vseq.sv index 0d08e4c9ac8..37d4a81f39a 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_partial_wipe_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_partial_wipe_vseq.sv @@ -5,20 +5,20 @@ // A sequence that injects faults to try to trigger bits of a secure wipe, but when they wouldn't // otherwise be expected. We should expect a fatal error whenever this happens. -class otbn_partial_wipe_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_partial_wipe_vseq) +class acc_partial_wipe_vseq extends acc_single_vseq; + `uvm_object_utils(acc_partial_wipe_vseq) `uvm_object_new // Wait a random time and then force a signal inside the design, which would mean a request for // part of a secure wipe, but not in the middle of a real secure wipe. task inject_partial_wipe(); - string hdl_path = "tb.dut.u_otbn_core"; + string hdl_path = "tb.dut.u_acc_core"; int ticks_until_err = 1; randcase - 1: hdl_path = {hdl_path, ".u_otbn_alu_bignum.sec_wipe_mod_urnd_i"}; - 1: hdl_path = {hdl_path, ".u_otbn_controller.sec_wipe_zero_i"}; + 1: hdl_path = {hdl_path, ".u_acc_alu_bignum.sec_wipe_mod_urnd_i"}; + 1: hdl_path = {hdl_path, ".u_acc_controller.sec_wipe_zero_i"}; 1: hdl_path = {hdl_path, ".sec_wipe_base"}; - 1: hdl_path = {hdl_path, ".u_otbn_rf_base.sec_wipe_stack_reset_i"}; + 1: hdl_path = {hdl_path, ".u_acc_rf_base.sec_wipe_stack_reset_i"}; 1: begin hdl_path = {hdl_path, ".sec_wipe_wdr_q"}; ticks_until_err = 0; @@ -27,7 +27,7 @@ class otbn_partial_wipe_vseq extends otbn_single_vseq; // Wait until we are not doing a secure wipe, and sync up with a negative clock edge (to make // the timing more obvious in any trace file) - `DV_WAIT(cfg.model_agent_cfg.vif.status != otbn_pkg::StatusBusySecWipeInt) + `DV_WAIT(cfg.model_agent_cfg.vif.status != acc_pkg::StatusBusySecWipeInt) cfg.clk_rst_vif.wait_n_clks(1); fork @@ -49,7 +49,7 @@ class otbn_partial_wipe_vseq extends otbn_single_vseq; task dut_init(string reset_kind = "HARD"); super.dut_init(reset_kind); - // Override the do_end_addr_check flag. It is set in otbn_single_vseq, but we might cause a stop + // Override the do_end_addr_check flag. It is set in acc_single_vseq, but we might cause a stop // at an unexpected address. do_end_addr_check = 1'b0; endtask @@ -61,7 +61,7 @@ class otbn_partial_wipe_vseq extends otbn_single_vseq; join // Now wait for the processor to finish: we expect it to lock. - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) reset_if_locked(); endtask diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_pc_ctrl_flow_redun_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_pc_ctrl_flow_redun_vseq.sv similarity index 72% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_pc_ctrl_flow_redun_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_pc_ctrl_flow_redun_vseq.sv index d839d8d784b..b68a593153c 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_pc_ctrl_flow_redun_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_pc_ctrl_flow_redun_vseq.sv @@ -4,8 +4,8 @@ // A sequence to verify the countermeasure(s) PC.CTRL_FLOW.REDUN. -class otbn_pc_ctrl_flow_redun_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_pc_ctrl_flow_redun_vseq) +class acc_pc_ctrl_flow_redun_vseq extends acc_single_vseq; + `uvm_object_utils(acc_pc_ctrl_flow_redun_vseq) `uvm_object_new task body(); @@ -28,16 +28,16 @@ class otbn_pc_ctrl_flow_redun_vseq extends otbn_single_vseq; bit [11:0] bad_addr; bit [11:0] mask; bit [31:0] err_val = 32'd1 << 20; - string addr_path = "tb.dut.u_otbn_core.u_otbn_instruction_fetch.insn_prefetch_addr"; + string addr_path = "tb.dut.u_acc_core.u_acc_instruction_fetch.insn_prefetch_addr"; do begin @(cfg.clk_rst_vif.cb); - if (!uvm_hdl_read("tb.dut.u_otbn_core.u_otbn_instruction_fetch.imem_rvalid_i", imem_rvalid)) + if (!uvm_hdl_read("tb.dut.u_acc_core.u_acc_instruction_fetch.imem_rvalid_i", imem_rvalid)) `uvm_fatal(`gfn, "failed to read imem_rvalid_i"); - if (!uvm_hdl_read("tb.dut.u_otbn_core.u_otbn_instruction_fetch.insn_fetch_req_valid_raw_i", + if (!uvm_hdl_read("tb.dut.u_acc_core.u_acc_instruction_fetch.insn_fetch_req_valid_raw_i", insn_fetch_req_valid)) `uvm_fatal(`gfn, "failed to read insn_fetch_req_valid_raw_i"); - if (!uvm_hdl_read("tb.dut.u_otbn_core.u_otbn_instruction_fetch.prefetch_ignore_errs_i", + if (!uvm_hdl_read("tb.dut.u_acc_core.u_acc_instruction_fetch.prefetch_ignore_errs_i", prefetch_ignore_err)) `uvm_fatal(`gfn, "failed to read prefetch_ignore_errs_i"); end while(!(imem_rvalid & insn_fetch_req_valid & !prefetch_ignore_err)); @@ -48,9 +48,9 @@ class otbn_pc_ctrl_flow_redun_vseq extends otbn_single_vseq; `DV_CHECK_FATAL(uvm_hdl_force(addr_path, bad_addr) == 1); `uvm_info(`gfn, "injecting bad internal state error into ISS", UVM_HIGH) cfg.model_agent_cfg.vif.send_err_escalation(err_val); - wait(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked); + wait(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked); `DV_CHECK_FATAL(uvm_hdl_release(addr_path) == 1); reset_if_locked(); endtask -endclass : otbn_pc_ctrl_flow_redun_vseq +endclass : acc_pc_ctrl_flow_redun_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_reset_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_reset_vseq.sv similarity index 74% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_reset_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_reset_vseq.sv index f5410a453c2..24f2ad51ab3 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_reset_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_reset_vseq.sv @@ -4,8 +4,8 @@ // A sequence that runs a program multiple times, resetting in the middle of runs -class otbn_reset_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_reset_vseq) +class acc_reset_vseq extends acc_base_vseq; + `uvm_object_utils(acc_reset_vseq) int unsigned num_iters = 10; @@ -20,12 +20,12 @@ class otbn_reset_vseq extends otbn_base_vseq; // Load up the binary. Since we always load the same binary, we take a copy of longest_run_, // which would otherwise be splatted by load_elf. longest_run_mirror = longest_run_; - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) load_elf(elf_path, 1'b1); longest_run_ = longest_run_mirror; - // Start OTBN. When the task returns, we'll be part-way through a run. - start_running_otbn(.check_end_addr(1'b1)); + // Start ACC. When the task returns, we'll be part-way through a run. + start_running_acc(.check_end_addr(1'b1)); // If this isn't the last iteration, reset the DUT if (i + 1 < num_iters) begin diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rf_base_intg_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_rf_base_intg_err_vseq.sv similarity index 80% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rf_base_intg_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_rf_base_intg_err_vseq.sv index 55b32fe129d..49afd9e490b 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rf_base_intg_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_rf_base_intg_err_vseq.sv @@ -5,8 +5,8 @@ // A sequence to insert 1 or 2 bit flips to base register file read outputs. // Time it so that only when a registers gets used, data corruption happen. -class otbn_rf_base_intg_err_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_rf_base_intg_err_vseq) +class acc_rf_base_intg_err_vseq extends acc_base_vseq; + `uvm_object_utils(acc_rf_base_intg_err_vseq) `uvm_object_new rand bit insert_intg_err_to_a; @@ -29,14 +29,14 @@ class otbn_rf_base_intg_err_vseq extends otbn_base_vseq; end while(!rd_en); // Wait until the program stops running. If it has stopped, there definitely won't be a read // in the future. - wait (cfg.model_agent_cfg.vif.status != otbn_pkg::StatusBusyExecute); + wait (cfg.model_agent_cfg.vif.status != acc_pkg::StatusBusyExecute); join_any disable fork; end join seen_use = rd_en; endtask - // Start running a program through OTBN and finish the task on a cycle when the selected register + // Start running a program through ACC and finish the task on a cycle when the selected register // file is being used. task run_until_use(); int num_tries = 4; @@ -44,8 +44,8 @@ class otbn_rf_base_intg_err_vseq extends otbn_base_vseq; repeat (num_tries) begin bit seen_use; - // Start running OTBN. When this task returns, we'll be in the middle of a run. - start_running_otbn(.check_end_addr(1'b0)); + // Start running ACC. When this task returns, we'll be in the middle of a run. + start_running_acc(.check_end_addr(1'b0)); // Now wait until the register file is being used await_use(seen_use); @@ -53,32 +53,32 @@ class otbn_rf_base_intg_err_vseq extends otbn_base_vseq; // We expect that to have worked (so seen_use is true). In that case, we can return. if (seen_use) return; - // The program run has completed. Before we try again, we need to allow OTBN to finish its + // The program run has completed. Before we try again, we need to allow ACC to finish its // current operation (to allow it to do the secure wipe after the run). Wait until we get to // Idle. In theory, we might get to Locked, but that shouldn't happen when running a standard // binary without outside interference! - wait (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle); + wait (cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle); end // The test run completed several times while we were waiting to see a read on the expected - // side. This shouldn't really happen, because it means that start_running_otbn() picked a time + // side. This shouldn't really happen, because it means that start_running_acc() picked a time // that was "almost at the end" of the program several times in a row. `uvm_fatal(`gfn, $sformatf("Program completed %d times before using register file %0s.", num_tries, insert_intg_err_to_a ? "A" : "B")) endtask - function bit [otbn_pkg::BaseIntgWidth-1:0] corrupt_data( - input bit [otbn_pkg::BaseIntgWidth-1:0] orig_data + function bit [acc_pkg::BaseIntgWidth-1:0] corrupt_data( + input bit [acc_pkg::BaseIntgWidth-1:0] orig_data ); - bit [otbn_pkg::BaseIntgWidth-1:0] mask; + bit [acc_pkg::BaseIntgWidth-1:0] mask; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask, $countones(mask) inside {[1:2]};) return cfg.fix_integrity_32(orig_data) ^ mask; endfunction task inject_errors(); - logic [otbn_pkg::BaseIntgWidth-1:0] orig_data; - bit [otbn_pkg::BaseIntgWidth-1:0] new_data; + logic [acc_pkg::BaseIntgWidth-1:0] orig_data; + bit [acc_pkg::BaseIntgWidth-1:0] new_data; orig_data = insert_intg_err_to_a ? cfg.trace_vif.rf_base_rd_data_a : cfg.trace_vif.rf_base_rd_data_b; new_data = corrupt_data(orig_data); @@ -103,13 +103,13 @@ class otbn_rf_base_intg_err_vseq extends otbn_base_vseq; string elf_path; bit [BaseWordsPerWLEN-1:0] corrupted_words; bit [ExtWLEN-1:0] new_data; - otbn_pkg::err_bits_t err_bits; + acc_pkg::err_bits_t err_bits; elf_path = pick_elf_path(); - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) load_elf(elf_path, 1'b1); - // Start running OTBN. When this task returns, we'll be in the middle of a run and executing an + // Start running ACC. When this task returns, we'll be in the middle of a run and executing an // instruction that reads from the selected register file. run_until_use(); @@ -122,11 +122,11 @@ class otbn_rf_base_intg_err_vseq extends otbn_base_vseq; @(cfg.clk_rst_vif.cbn); release_force(); - // OTBN should now do a secure wipe + // ACC should now do a secure wipe wait_secure_wipe(); // We should now be in a locked state after the secure wipe. - `DV_CHECK_FATAL(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked); + `DV_CHECK_FATAL(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked); // The scoreboard will have seen the transition to locked state and inferred that it should // see a fatal alert. However, it doesn't really have a way to ensure that we keep generating // them. Wait for 3 fatal alerts and also read STATUS, ERR_BITS and FATAL_ALERT_CAUSE in diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rf_bignum_intg_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_rf_bignum_intg_err_vseq.sv similarity index 74% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rf_bignum_intg_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_rf_bignum_intg_err_vseq.sv index 46e01bacf91..89583008c09 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rf_bignum_intg_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_rf_bignum_intg_err_vseq.sv @@ -3,15 +3,15 @@ // SPDX-License-Identifier: Apache-2.0 // A sequence to insert 1 or 2 bit flips per word to bignum register file while -// OTBN is trying to read from it. +// ACC is trying to read from it. -class otbn_rf_bignum_intg_err_vseq extends otbn_intg_err_vseq; - `uvm_object_utils(otbn_rf_bignum_intg_err_vseq) +class acc_rf_bignum_intg_err_vseq extends acc_intg_err_vseq; + `uvm_object_utils(acc_rf_bignum_intg_err_vseq) `uvm_object_new rand bit insert_intg_err_to_a; - protected task await_use(output bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words); + protected task await_use(output bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words); logic rd_en; used_words = '0; `uvm_info(`gfn, "Waiting for selected RF to be used", UVM_LOW) @@ -22,14 +22,14 @@ class otbn_rf_bignum_intg_err_vseq extends otbn_intg_err_vseq; cfg.trace_vif.rf_bignum_rd_en_b; end while(!rd_en); used_words = '1;, cfg.clk_rst_vif.wait_clks(2000);, - "Not getting selected rd_en from OTBN for 2000 cycles!" + "Not getting selected rd_en from ACC for 2000 cycles!" ) endtask - protected task inject_errors(input bit [otbn_pkg::BaseWordsPerWLEN-1:0] used_words, - output bit [otbn_pkg::BaseWordsPerWLEN-1:0] corrupted_words); - logic [otbn_pkg::ExtWLEN-1:0] orig_data; - bit [otbn_pkg::ExtWLEN-1:0] new_data; + protected task inject_errors(input bit [acc_pkg::BaseWordsPerWLEN-1:0] used_words, + output bit [acc_pkg::BaseWordsPerWLEN-1:0] corrupted_words); + logic [acc_pkg::ExtWLEN-1:0] orig_data; + bit [acc_pkg::ExtWLEN-1:0] new_data; orig_data = insert_intg_err_to_a ? cfg.trace_vif.rf_bignum_rd_data_a_intg : cfg.trace_vif.rf_bignum_rd_data_b_intg; diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rnd_sec_cm_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_rnd_sec_cm_vseq.sv similarity index 89% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rnd_sec_cm_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_rnd_sec_cm_vseq.sv index e642cef7427..819ca1143dd 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_rnd_sec_cm_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_rnd_sec_cm_vseq.sv @@ -3,15 +3,15 @@ // SPDX-License-Identifier: Apache-2.0 // Test sequence to check both RND.RNG.DIGEST and RND.BUS.CONSISTENCY security countermeasures. -// The main skeleton is otbn_multi test in which we run multiple programs. It is better suited -// to see RND behaviour between different OTBN operations. +// The main skeleton is acc_multi test in which we run multiple programs. It is better suited +// to see RND behaviour between different ACC operations. // Behaviour of the test changes with accordance to the randomized number of repeated EDN words // as an answer to the RND request. If number of repeated EDN words is zero, only error will be // about FIPS non-compliant cases. In the case of repeats being greater or equal than eight // -the number of total EDN words for RND, only repetition errors will be seen. -class otbn_rnd_sec_cm_vseq extends otbn_multi_vseq; - `uvm_object_utils(otbn_rnd_sec_cm_vseq) +class acc_rnd_sec_cm_vseq extends acc_multi_vseq; + `uvm_object_utils(acc_rnd_sec_cm_vseq) `uvm_object_new task body(); @@ -42,7 +42,7 @@ class otbn_rnd_sec_cm_vseq extends otbn_multi_vseq; // In this case, we want to fill the remaining 7 EDN words with "FIPS qualified" // randomness each time. Because creating a FIPS error is not important in this // case. - repeat (otbn_pkg::EdnDataWidth/cip_base_pkg::EDN_BUS_WIDTH - 1) + repeat (acc_pkg::EdnDataWidth/cip_base_pkg::EDN_BUS_WIDTH - 1) cfg.m_edn_pull_agent_cfgs[RndEdnIdx].add_d_user_data({1'b1, $urandom}); else repeat (num_repeated_edn) @@ -57,4 +57,4 @@ class otbn_rnd_sec_cm_vseq extends otbn_multi_vseq; end endtask -endclass : otbn_rnd_sec_cm_vseq +endclass : acc_rnd_sec_cm_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sec_wipe_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sec_wipe_err_vseq.sv similarity index 63% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sec_wipe_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_sec_wipe_err_vseq.sv index 6aca3e8ad81..2f0c6877cc1 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sec_wipe_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sec_wipe_err_vseq.sv @@ -6,8 +6,8 @@ // between the controller and the start-stop controller. -class otbn_sec_wipe_err_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_sec_wipe_err_vseq) +class acc_sec_wipe_err_vseq extends acc_base_vseq; + `uvm_object_utils(acc_sec_wipe_err_vseq) `uvm_object_new @@ -15,13 +15,13 @@ class otbn_sec_wipe_err_vseq extends otbn_base_vseq; task send_spurious_req(); string err_path = cfg.ssctrl_vif.resolve_path("secure_wipe_req_i"); - // Secure wipe requests are not allowed when OTBN is idle; so wait for OTBN to become idle. - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) + // Secure wipe requests are not allowed when ACC is idle; so wait for ACC to become idle. + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle) @(cfg.clk_rst_vif.cbn); // Disable assertion that would abort simulation when the fault is injected. cfg.ssctrl_vif.control_secwipe_running_assertion(1'b0); - `uvm_info(`gfn, "Requesting secure wipe while OTBN is idle, which is not allowed.", UVM_LOW) + `uvm_info(`gfn, "Requesting secure wipe while ACC is idle, which is not allowed.", UVM_LOW) // Inject error. `uvm_info(`gfn, "Injecting error by force.", UVM_LOW) @@ -34,8 +34,8 @@ class otbn_sec_wipe_err_vseq extends otbn_base_vseq; `uvm_info(`gfn, "Releasing force.", UVM_LOW) `DV_CHECK_FATAL(uvm_hdl_release(err_path) == 1) - `uvm_info(`gfn, "Waiting for OTBN to lock up.", UVM_LOW) - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `uvm_info(`gfn, "Waiting for ACC to lock up.", UVM_LOW) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) cfg.ssctrl_vif.control_secwipe_running_assertion(1'b1); endtask @@ -45,20 +45,20 @@ class otbn_sec_wipe_err_vseq extends otbn_base_vseq; string err_path = cfg.ssctrl_vif.resolve_path("secure_wipe_req_i"); bit skip_err_injection = 0; - // The OTBN controller requests a secure wipe from the start-stop controller at the end of + // The ACC controller requests a secure wipe from the start-stop controller at the end of // execution. To reach that point, we must first execute a binary. string elf_path = pick_elf_path(); load_elf(elf_path, 1'b1); - `uvm_info(`gfn, $sformatf("Executing OTBN binary `%0s'.", elf_path), UVM_LOW) - start_running_otbn(.check_end_addr(1'b0)); - - // Wait until binary has completed execution and OTBN does the internal secure wipe. - `uvm_info(`gfn, "Waiting for OTBN to complete execution.", UVM_LOW) - `DV_WAIT(cfg.model_agent_cfg.vif.status != otbn_pkg::StatusBusyExecute) - if (cfg.model_agent_cfg.vif.status != otbn_pkg::StatusBusySecWipeInt) begin - // If OTBN is no longer executing but also not performing the internal secure wipe, we have - // missed the opportunity (the `start_running_otbn()` function does not guarantee that it - // returns while OTBN is still running). So we cannot inject the error anymore. + `uvm_info(`gfn, $sformatf("Executing ACC binary `%0s'.", elf_path), UVM_LOW) + start_running_acc(.check_end_addr(1'b0)); + + // Wait until binary has completed execution and ACC does the internal secure wipe. + `uvm_info(`gfn, "Waiting for ACC to complete execution.", UVM_LOW) + `DV_WAIT(cfg.model_agent_cfg.vif.status != acc_pkg::StatusBusyExecute) + if (cfg.model_agent_cfg.vif.status != acc_pkg::StatusBusySecWipeInt) begin + // If ACC is no longer executing but also not performing the internal secure wipe, we have + // missed the opportunity (the `start_running_acc()` function does not guarantee that it + // returns while ACC is still running). So we cannot inject the error anymore. skip_err_injection = 1; end @(cfg.clk_rst_vif.cbn); @@ -82,8 +82,8 @@ class otbn_sec_wipe_err_vseq extends otbn_base_vseq; @(cfg.clk_rst_vif.cbn); cfg.model_agent_cfg.vif.send_err_escalation(32'd1 << 20); - `uvm_info(`gfn, "Waiting for OTBN to lock up.", UVM_LOW) - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `uvm_info(`gfn, "Waiting for ACC to lock up.", UVM_LOW) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) cfg.ssctrl_vif.control_secwipe_running_assertion(1'b1); end @@ -98,23 +98,23 @@ class otbn_sec_wipe_err_vseq extends otbn_base_vseq; `DV_CHECK_STD_RANDOMIZE_FATAL(while_executing) if (while_executing) begin - // Secure wipe acknowledges are not allowed when OTBN is executing; so load and execute a + // Secure wipe acknowledges are not allowed when ACC is executing; so load and execute a // binary. string elf_path = pick_elf_path(); load_elf(elf_path, 1'b1); - `uvm_info(`gfn, $sformatf("Executing OTBN binary `%0s'.", elf_path), UVM_LOW) - start_running_otbn(.check_end_addr(1'b0)); + `uvm_info(`gfn, $sformatf("Executing ACC binary `%0s'.", elf_path), UVM_LOW) + start_running_acc(.check_end_addr(1'b0)); @(cfg.clk_rst_vif.cbn); - // If we are unlucky, OTBN is now already securely wiping due to a different error. In + // If we are unlucky, ACC is now already securely wiping due to a different error. In // that case, we skip error injection. - if (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusBusySecWipeInt) begin + if (cfg.model_agent_cfg.vif.status == acc_pkg::StatusBusySecWipeInt) begin skip_err_injection = 1; end end else begin - // Secure wipe acknowledges are not allowed when OTBN is idle; so wait for OTBN to become + // Secure wipe acknowledges are not allowed when ACC is idle; so wait for ACC to become // idle. - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle) @(cfg.clk_rst_vif.cbn); end @@ -133,8 +133,8 @@ class otbn_sec_wipe_err_vseq extends otbn_base_vseq; `uvm_info(`gfn, "Releasing force.", UVM_LOW) `DV_CHECK_FATAL(uvm_hdl_release(err_path) == 1) - `uvm_info(`gfn, "Waiting for OTBN to lock up.", UVM_LOW) - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `uvm_info(`gfn, "Waiting for ACC to lock up.", UVM_LOW) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) end endtask diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sequential_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sequential_vseq.sv similarity index 66% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sequential_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_sequential_vseq.sv index 26aad11e0d3..b8e721f165e 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sequential_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sequential_vseq.sv @@ -3,10 +3,10 @@ // SPDX-License-Identifier: Apache-2.0 // A specialized sequence that runs each of the available binaries exactly once. This is used for -// directed tests when each causes an OTBN error, so you need to start a new operation for each. +// directed tests when each causes an ACC error, so you need to start a new operation for each. -class otbn_sequential_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_sequential_vseq) +class acc_sequential_vseq extends acc_base_vseq; + `uvm_object_utils(acc_sequential_vseq) `uvm_object_new @@ -20,34 +20,34 @@ class otbn_sequential_vseq extends otbn_base_vseq; string buffer; string paths[$]; - // Check that cfg.otbn_elf_dir was set by the test - `DV_CHECK_FATAL(cfg.otbn_elf_dir.len() > 0); + // Check that cfg.acc_elf_dir was set by the test + `DV_CHECK_FATAL(cfg.acc_elf_dir.len() > 0); // Use a C++ helper over DPI (because you can't list a directory in pure SystemVerilog). To do // so, we have to construct a helper object, which will look after memory allocation for the // string holding the path. - helper = OtbnTestHelperMake(cfg.otbn_elf_dir); + helper = AccTestHelperMake(cfg.acc_elf_dir); `DV_CHECK_FATAL(helper != null) // Ask the helper how many files there are. If it returns zero, the directory name is bogus or // the directory is empty. - num_files = OtbnTestHelperCountFilesInDir(helper); + num_files = AccTestHelperCountFilesInDir(helper); `DV_CHECK_FATAL(num_files > 0, - $sformatf("No regular files found in directory `%0s'.", cfg.otbn_elf_dir)) + $sformatf("No regular files found in directory `%0s'.", cfg.acc_elf_dir)) - // Get each path from the C++ code. OtbnTestHelperGetFilePath returns the empty string on error. + // Get each path from the C++ code. AccTestHelperGetFilePath returns the empty string on error. for (int idx = 0; idx < num_files; idx++) begin - buffer = OtbnTestHelperGetFilePath(helper, idx); + buffer = AccTestHelperGetFilePath(helper, idx); `DV_CHECK_FATAL(buffer.len() > 0, "Bad index for ELF file") - // Take a copy of the string so that we can safely call OtbnTestHelperGetFilePath on the next + // Take a copy of the string so that we can safely call AccTestHelperGetFilePath on the next // iteration (or free helper) without trashing the string we just got. buffer = $sformatf("%0s", buffer); paths.push_back(buffer); end - OtbnTestHelperFree(helper); + AccTestHelperFree(helper); // Finally, shuffle paths before returning them paths.shuffle(); @@ -57,9 +57,9 @@ class otbn_sequential_vseq extends otbn_base_vseq; task body(); string paths[$] = list_elf_paths(); foreach (paths[i]) begin - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", paths[i]), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", paths[i]), UVM_LOW) load_elf(paths[i], 1'b0); - run_otbn(); + run_acc(); end endtask diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_single_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_single_vseq.sv similarity index 85% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_single_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_single_vseq.sv index 7cbbd3d9fc7..af476881deb 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_single_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_single_vseq.sv @@ -4,8 +4,8 @@ // A basic sequence that loads up an ELF file, lets it run to completion, and then finishes. -class otbn_single_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_single_vseq) +class acc_single_vseq extends acc_base_vseq; + `uvm_object_utils(acc_single_vseq) `uvm_object_new // Should the ELF file be loaded with a backdoor DPI method, or should we actually generate the @@ -26,7 +26,7 @@ class otbn_single_vseq extends otbn_base_vseq; bit enable_interrupts = $urandom_range(100) < cfg.enable_interrupts_pct; // Load the binary and (if required) enable interrupts. These run in parallel - `uvm_info(`gfn, $sformatf("Loading OTBN binary from `%0s'", elf_path), UVM_LOW) + `uvm_info(`gfn, $sformatf("Loading ACC binary from `%0s'", elf_path), UVM_LOW) fork load_elf(elf_path, do_backdoor_load); cfg_interrupts(enable_interrupts); @@ -37,7 +37,7 @@ class otbn_single_vseq extends otbn_base_vseq; return; end // We've loaded the binary. Run the processor to see what happens! - run_otbn(do_end_addr_check); + run_acc(do_end_addr_check); endtask : body -endclass : otbn_single_vseq +endclass : acc_single_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_smoke_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_smoke_vseq.sv similarity index 66% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_smoke_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_smoke_vseq.sv index d1f18bd3265..2b2e241698a 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_smoke_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_smoke_vseq.sv @@ -5,18 +5,18 @@ // A smoke test sequence. This loads up the fixed "smoke.elf" binary and forces everything to be in // "simple" mode. -class otbn_smoke_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_smoke_vseq) +class acc_smoke_vseq extends acc_single_vseq; + `uvm_object_utils(acc_smoke_vseq) `uvm_object_new constraint do_backdoor_load_c { do_backdoor_load == 1'b0; } // Override pick_elf_path to always choose "smoke.elf" protected function string pick_elf_path(); - // Check that cfg.otbn_elf_dir was set by the test - `DV_CHECK_FATAL(cfg.otbn_elf_dir.len() > 0); + // Check that cfg.acc_elf_dir was set by the test + `DV_CHECK_FATAL(cfg.acc_elf_dir.len() > 0); - return $sformatf("%0s/smoke_test.elf", cfg.otbn_elf_dir); + return $sformatf("%0s/smoke_test.elf", cfg.acc_elf_dir); endfunction endclass diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_stack_addr_integ_chk_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_stack_addr_integ_chk_vseq.sv similarity index 90% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_stack_addr_integ_chk_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_stack_addr_integ_chk_vseq.sv index 95cd5fb64d1..dfa88a9ad25 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_stack_addr_integ_chk_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_stack_addr_integ_chk_vseq.sv @@ -2,10 +2,10 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// A sequence to verify the countermeasure(s) OTBN.*_STACK.ADDR.INTEGRITY. +// A sequence to verify the countermeasure(s) ACC.*_STACK.ADDR.INTEGRITY. -class otbn_stack_addr_integ_chk_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_stack_addr_integ_chk_vseq) +class acc_stack_addr_integ_chk_vseq extends acc_single_vseq; + `uvm_object_utils(acc_stack_addr_integ_chk_vseq) `uvm_object_new bit end_test; @@ -18,7 +18,7 @@ class otbn_stack_addr_integ_chk_vseq extends otbn_single_vseq; join endtask: body - // Wait until the value at path is nonzero or until OTBN finishes execution. + // Wait until the value at path is nonzero or until ACC finishes execution. // // This process is safe to kill at any time, because it doesn't start any TL transactions. task wait_for_flag(string path); @@ -33,7 +33,7 @@ class otbn_stack_addr_integ_chk_vseq extends otbn_single_vseq; `DV_CHECK_FATAL(uvm_hdl_read(path, value)); end while (!value);) end - // This process waits until OTBN completes execution or until reset. Passing backdoor=1 + // This process waits until ACC completes execution or until reset. Passing backdoor=1 // ensures that we won't start any TL reads of the status register. wait_for_run_completion(.verbosity(UVM_HIGH), .backdoor(1'b1)); @@ -80,12 +80,12 @@ class otbn_stack_addr_integ_chk_vseq extends otbn_single_vseq; if (err_type) begin // We want to inject an error into the call stack (the data backing x1) - base_path = "tb.dut.u_otbn_core.u_otbn_rf_base"; + base_path = "tb.dut.u_acc_core.u_acc_rf_base"; stack_path = {base_path, ".u_call_stack"}; msb = 38; end else begin // We want to inject an error into the loop stack - base_path = "tb.dut.u_otbn_core.u_otbn_controller.u_otbn_loop_controller"; + base_path = "tb.dut.u_acc_core.u_acc_controller.u_acc_loop_controller"; stack_path = {base_path, ".loop_info_stack"}; msb = 34; end @@ -130,7 +130,7 @@ class otbn_stack_addr_integ_chk_vseq extends otbn_single_vseq; disable fork; end: isolation_fork join - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) foreach (forced_paths[i]) begin `DV_CHECK_FATAL(uvm_hdl_release(forced_paths[i]) == 1); end @@ -194,7 +194,7 @@ class otbn_stack_addr_integ_chk_vseq extends otbn_single_vseq; if (immediately_escalate) begin // When immediately_escalate is true, we assume that the corruption we have just introduced - // will be visible through the top_data_o port from otbn_stack. This is almost immediate, but + // will be visible through the top_data_o port from acc_stack. This is almost immediate, but // the index of the element to be exposed is computed from stack_rd_idx which might be a cycle // behind the "correct" value that we have calculated from stack_wr_idx. // @@ -208,8 +208,8 @@ class otbn_stack_addr_integ_chk_vseq extends otbn_single_vseq; end send_escalation_to_model(); - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) end_test = 1; end endtask: corrupt_stack -endclass : otbn_stack_addr_integ_chk_vseq +endclass : acc_stack_addr_integ_chk_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_stress_all_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_stress_all_vseq.sv similarity index 61% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_stress_all_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_stress_all_vseq.sv index b5ae98cc775..2d2118a85b0 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_stress_all_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_stress_all_vseq.sv @@ -3,29 +3,29 @@ // SPDX-License-Identifier: Apache-2.0 // A sequence that runs other sequences one after the other. This *always* re-loads binaries, which -// is different from otbn_multi_vseq where we are cleverer about reloading things. +// is different from acc_multi_vseq where we are cleverer about reloading things. -class otbn_stress_all_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_stress_all_vseq) +class acc_stress_all_vseq extends acc_base_vseq; + `uvm_object_utils(acc_stress_all_vseq) `uvm_object_new // The sequences that we'll run back-to-back string vseq_names[$] = { - "otbn_dmem_err_vseq", - "otbn_imem_err_vseq", - "otbn_single_vseq" + "acc_dmem_err_vseq", + "acc_imem_err_vseq", + "acc_single_vseq" }; task body(); `uvm_info(`gfn, $sformatf("Running %0d sub-sequences", num_trans), UVM_LOW) for (int i = 0; i < num_trans; i++) begin uvm_sequence seq; - otbn_base_vseq otbn_vseq; + acc_base_vseq acc_vseq; uint seq_idx = $urandom_range(0, vseq_names.size() - 1); string cur_vseq_name = vseq_names[seq_idx]; - // If we're running as a subsequence of otbn_stress_all_with_rand_reset and i > 0, the + // If we're running as a subsequence of acc_stress_all_with_rand_reset and i > 0, the // previous sequence might have exited early when the controlling sequence applied a reset. In // this case, wait until we come back out of reset before running the next one. if (cfg.under_reset) begin @@ -33,13 +33,13 @@ class otbn_stress_all_vseq extends otbn_base_vseq; end seq = create_seq_by_name(cur_vseq_name); - `downcast(otbn_vseq, seq) + `downcast(acc_vseq, seq) - // Only force a reset at the start of the sequence if OTBN is currently locked (in which case, + // Only force a reset at the start of the sequence if ACC is currently locked (in which case, // we wouldn't be able to do anything) - otbn_vseq.do_apply_reset = (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked); - otbn_vseq.set_sequencer(p_sequencer); - otbn_vseq.start(p_sequencer); + acc_vseq.do_apply_reset = (cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked); + acc_vseq.set_sequencer(p_sequencer); + acc_vseq.start(p_sequencer); end endtask diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sw_errs_fatal_chk_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sw_errs_fatal_chk_vseq.sv similarity index 56% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sw_errs_fatal_chk_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_sw_errs_fatal_chk_vseq.sv index 9203a9700b4..a3479192340 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sw_errs_fatal_chk_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sw_errs_fatal_chk_vseq.sv @@ -2,19 +2,19 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_sw_errs_fatal_chk_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_sw_errs_fatal_chk_vseq) +class acc_sw_errs_fatal_chk_vseq extends acc_single_vseq; + `uvm_object_utils(acc_sw_errs_fatal_chk_vseq) `uvm_object_new task body(); - // Wait for OTBN to complete its secure wipe after reset and become Idle. Otherwise, OTBN will + // Wait for ACC to complete its secure wipe after reset and become Idle. Otherwise, ACC will // ignore writes of `CTRL.software_errs_fatal`. - wait(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle); + wait(cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle); // Set ctrl.software_errs_fatal. This change also will be passed to our model through - // otbn_scoreboard. + // acc_scoreboard. csr_utils_pkg::csr_wr(ral.ctrl, 'b1); super.body(); reset_if_locked(); endtask : body -endclass : otbn_sw_errs_fatal_chk_vseq +endclass : acc_sw_errs_fatal_chk_vseq diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sw_no_acc_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sw_no_acc_vseq.sv similarity index 67% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sw_no_acc_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_sw_no_acc_vseq.sv index 5487951542d..e2c577e4375 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_sw_no_acc_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_sw_no_acc_vseq.sv @@ -4,8 +4,8 @@ // A sequence that writes to 1st Kib of address in DMEM which is inaccessible on TLUL. -class otbn_sw_no_acc_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_sw_no_acc_vseq) +class acc_sw_no_acc_vseq extends acc_single_vseq; + `uvm_object_utils(acc_sw_no_acc_vseq) `uvm_object_new @@ -19,8 +19,8 @@ class otbn_sw_no_acc_vseq extends otbn_single_vseq; bit [31:0] err_val = 32'd1 << 21; bit [14:0] offset; - localparam int unsigned OTBN_TOTAL_DMEM = otbn_reg_pkg::OTBN_DMEM_SIZE - + otbn_pkg::DmemScratchSizeByte; + localparam int unsigned ACC_TOTAL_DMEM = acc_reg_pkg::ACC_DMEM_SIZE + + acc_pkg::DmemScratchSizeByte; key = cfg.get_dmem_key(); nonce = cfg.get_dmem_nonce(); @@ -28,14 +28,14 @@ class otbn_sw_no_acc_vseq extends otbn_single_vseq; `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(data, $countones(data) != BUS_DW;) `DV_CHECK_STD_RANDOMIZE_FATAL(write) - `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(offset, offset dist {otbn_reg_pkg::OTBN_DMEM_SIZE :/ 5, - [otbn_reg_pkg::OTBN_DMEM_SIZE:OTBN_TOTAL_DMEM] :/ 1, - OTBN_TOTAL_DMEM :/ 5};) - addr = cfg.ral.get_addr_from_offset(otbn_reg_pkg::OTBN_DMEM_OFFSET + offset); + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(offset, offset dist {acc_reg_pkg::ACC_DMEM_SIZE :/ 5, + [acc_reg_pkg::ACC_DMEM_SIZE:ACC_TOTAL_DMEM] :/ 1, + ACC_TOTAL_DMEM :/ 5};) + addr = cfg.ral.get_addr_from_offset(acc_reg_pkg::ACC_DMEM_OFFSET + offset); `uvm_info(`gfn, $sformatf("addr = %h", addr), UVM_LOW) super.body(); - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle) if (write) begin tl_access(.addr(addr), .write(1), .data(data), .exp_err_rsp(1)); `uvm_info(`gfn, diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_urnd_err_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_urnd_err_vseq.sv similarity index 71% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_urnd_err_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_urnd_err_vseq.sv index 7969ee3b817..1074bbbb51b 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_urnd_err_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_urnd_err_vseq.sv @@ -4,8 +4,8 @@ // A sequence that injects a spurious acknowledge to URND requests. -class otbn_urnd_err_vseq extends otbn_base_vseq; - `uvm_object_utils(otbn_urnd_err_vseq) +class acc_urnd_err_vseq extends acc_base_vseq; + `uvm_object_utils(acc_urnd_err_vseq) `uvm_object_new @@ -22,23 +22,23 @@ class otbn_urnd_err_vseq extends otbn_base_vseq; `DV_CHECK_STD_RANDOMIZE_FATAL(while_executing) if (while_executing) begin - // Inject spurious URND acknowledge while OTBN is executing. + // Inject spurious URND acknowledge while ACC is executing. - // The OTBN controller requests a secure wipe from the start-stop controller at the end of + // The ACC controller requests a secure wipe from the start-stop controller at the end of // execution. To reach that point, we must first execute a binary. string elf_path = pick_elf_path(); load_elf(elf_path, 1'b1); - `uvm_info(`gfn, $sformatf("Executing OTBN binary `%0s'.", elf_path), UVM_LOW) - start_running_otbn(.check_end_addr(1'b0)); + `uvm_info(`gfn, $sformatf("Executing ACC binary `%0s'.", elf_path), UVM_LOW) + start_running_acc(.check_end_addr(1'b0)); - if (!(cfg.model_agent_cfg.vif.status inside {otbn_pkg::StatusBusyExecute, - otbn_pkg::StatusBusySecWipeInt})) begin - // If OTBN is no longer executing, we have missed the opportunity (the - // `start_running_otbn()` function does not guarantee that it returns while OTBN is still + if (!(cfg.model_agent_cfg.vif.status inside {acc_pkg::StatusBusyExecute, + acc_pkg::StatusBusySecWipeInt})) begin + // If ACC is no longer executing, we have missed the opportunity (the + // `start_running_acc()` function does not guarantee that it returns while ACC is still // running). So we cannot inject the error anymore. skip_err_injection = 1'b1; end else begin - // OTBN does an URND request when it starts executing as well as between secure wipes. We + // ACC does an URND request when it starts executing as well as between secure wipes. We // must wait for that request to complete before we can inject a spurious acknowledge. logic urnd_req; string path = "tb.dut.edn_urnd_req"; @@ -65,8 +65,8 @@ class otbn_urnd_err_vseq extends otbn_base_vseq; end end else begin - // Inject spurious URND acknowledge while OTBN is idle. - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) + // Inject spurious URND acknowledge while ACC is idle. + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusIdle) @(cfg.clk_rst_vif.cbn); if (skip_err_injection) begin @@ -88,8 +88,8 @@ class otbn_urnd_err_vseq extends otbn_base_vseq; `uvm_info(`gfn, "Releasing force.", UVM_LOW) `DV_CHECK_FATAL(uvm_hdl_release(err_path) == 1) - `uvm_info(`gfn, "Waiting for OTBN to lock up.", UVM_LOW) - `DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked) + `uvm_info(`gfn, "Waiting for ACC to lock up.", UVM_LOW) + `DV_WAIT(cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked) end reset_if_locked(); diff --git a/hw/ip/acc/dv/uvm/env/seq_lib/acc_vseq_list.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_vseq_list.sv new file mode 100644 index 00000000000..e4aa313c441 --- /dev/null +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_vseq_list.sv @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "acc_base_vseq.sv" +`include "acc_common_vseq.sv" +`include "acc_multi_vseq.sv" +`include "acc_reset_vseq.sv" +`include "acc_sequential_vseq.sv" +`include "acc_single_vseq.sv" +`include "acc_smoke_vseq.sv" +`include "acc_imem_err_vseq.sv" +`include "acc_dmem_err_vseq.sv" +`include "acc_stress_all_vseq.sv" +`include "acc_escalate_vseq.sv" +`include "acc_zero_state_err_urnd_vseq.sv" +`include "acc_illegal_mem_acc_vseq.sv" +`include "acc_sw_errs_fatal_chk_vseq.sv" +`include "acc_intg_err_vseq.sv" +`include "acc_alu_bignum_mod_err_vseq.sv" +`include "acc_controller_ispr_rdata_err_vseq.sv" +`include "acc_mac_bignum_acc_err_vseq.sv" +`include "acc_rf_base_intg_err_vseq.sv" +`include "acc_rf_bignum_intg_err_vseq.sv" +`include "acc_pc_ctrl_flow_redun_vseq.sv" +`include "acc_rnd_sec_cm_vseq.sv" +`include "acc_ctrl_redun_vseq.sv" +`include "acc_sec_wipe_err_vseq.sv" +`include "acc_urnd_err_vseq.sv" +`include "acc_sw_no_acc_vseq.sv" +`include "acc_mem_gnt_acc_err_vseq.sv" +`include "acc_stack_addr_integ_chk_vseq.sv" +`include "acc_partial_wipe_vseq.sv" diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_zero_state_err_urnd_vseq.sv b/hw/ip/acc/dv/uvm/env/seq_lib/acc_zero_state_err_urnd_vseq.sv similarity index 77% rename from hw/ip/otbn/dv/uvm/env/seq_lib/otbn_zero_state_err_urnd_vseq.sv rename to hw/ip/acc/dv/uvm/env/seq_lib/acc_zero_state_err_urnd_vseq.sv index ae60458e7b0..be4451d571d 100644 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_zero_state_err_urnd_vseq.sv +++ b/hw/ip/acc/dv/uvm/env/seq_lib/acc_zero_state_err_urnd_vseq.sv @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_zero_state_err_urnd_vseq extends otbn_single_vseq; - `uvm_object_utils(otbn_zero_state_err_urnd_vseq) +class acc_zero_state_err_urnd_vseq extends acc_single_vseq; + `uvm_object_utils(acc_zero_state_err_urnd_vseq) `uvm_object_new task body(); @@ -22,21 +22,21 @@ class otbn_zero_state_err_urnd_vseq extends otbn_single_vseq; end begin bit [31:0] err_val = 32'd1 << 20; - string prng_path = "tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q"; + string prng_path = "tb.dut.u_acc_core.u_acc_rnd.u_xoshiro256pp.xoshiro_q"; cfg.clk_rst_vif.wait_clks($urandom_range(10, 1000)); `DV_CHECK_FATAL(uvm_hdl_force(prng_path, 'b0) == 1); `uvm_info(`gfn,"injecting zero state error into ISS", UVM_HIGH) cfg.model_agent_cfg.vif.send_err_escalation(err_val); cfg.clk_rst_vif.wait_clks(1); - cfg.model_agent_cfg.vif.otbn_set_no_sec_wipe_chk(); + cfg.model_agent_cfg.vif.acc_set_no_sec_wipe_chk(); `DV_CHECK_FATAL(uvm_hdl_release(prng_path) == 1); `uvm_info(`gfn,"string released", UVM_HIGH) - wait (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked); + wait (cfg.model_agent_cfg.vif.status == acc_pkg::StatusLocked); reset_if_locked(); end join endtask : body -endclass : otbn_zero_state_err_urnd_vseq +endclass : acc_zero_state_err_urnd_vseq diff --git a/hw/ip/otbn/dv/uvm/gen-binaries.py b/hw/ip/acc/dv/uvm/gen-binaries.py similarity index 82% rename from hw/ip/otbn/dv/uvm/gen-binaries.py rename to hw/ip/acc/dv/uvm/gen-binaries.py index 14945a853b0..93b9beeab84 100755 --- a/hw/ip/otbn/dv/uvm/gen-binaries.py +++ b/hw/ip/acc/dv/uvm/gen-binaries.py @@ -3,7 +3,7 @@ # Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''A helper script to generate a default set of binaries for OTBN testing +'''A helper script to generate a default set of binaries for ACC testing This is intended for use with dvsim, which should call this script as part of the test build phase. @@ -46,8 +46,8 @@ def is_exe(path: str) -> bool: class Toolchain: def __init__(self, env_data: Dict[str, str]) -> None: - self.otbn_as = self.get_tool(env_data, 'OTBN_AS') - self.otbn_ld = self.get_tool(env_data, 'OTBN_LD') + self.acc_as = self.get_tool(env_data, 'ACC_AS') + self.acc_ld = self.get_tool(env_data, 'ACC_LD') self.rv32_tool_as = self.get_tool(env_data, 'RV32_TOOL_AS') self.rv32_tool_ld = self.get_tool(env_data, 'RV32_TOOL_LD') @@ -66,13 +66,13 @@ def run(self, cmd: List[str]) -> None: subprocess.run(cmd, env=env) -def get_toolchain(otbn_dir: str) -> Toolchain: +def get_toolchain(acc_dir: str) -> Toolchain: '''Reads environment variables to get toolchain info.''' env_dict = {} # type: Dict[str, str] - # OTBN assembler and linker - env_dict['OTBN_AS'] = f"{otbn_dir}/util/otbn_as.py" - env_dict['OTBN_LD'] = f"{otbn_dir}/util/otbn_ld.py" + # ACC assembler and linker + env_dict['ACC_AS'] = f"{acc_dir}/util/acc_as.py" + env_dict['ACC_LD'] = f"{acc_dir}/util/acc_ld.py" # RV32 assembler and linker env_dict['RV32_TOOL_AS'] = os.getenv('RV32_TOOL_AS') @@ -140,10 +140,10 @@ def main() -> int: 'both supplied.') script_dir = os.path.dirname(__file__) - otbn_dir = os.path.normpath(os.path.join(script_dir, '../' * 2)) + acc_dir = os.path.normpath(os.path.join(script_dir, '../' * 2)) try: - toolchain = get_toolchain(otbn_dir) + toolchain = get_toolchain(acc_dir) except RuntimeError as err: print(err, file=sys.stderr) return 1 @@ -156,10 +156,10 @@ def main() -> int: with open(os.path.join(args.destdir, ninja_fname), 'w') as ninja_handle: if args.src_dir is None: - write_ninja_rnd(ninja_handle, toolchain, otbn_dir, args.count, + write_ninja_rnd(ninja_handle, toolchain, acc_dir, args.count, args.seed, args.size, args.config, args.pqc) else: - write_ninja_fixed(ninja_handle, toolchain, otbn_dir, args.src_dir) + write_ninja_fixed(ninja_handle, toolchain, acc_dir, args.src_dir) if args.gen_only: return 0 @@ -181,39 +181,39 @@ def main() -> int: return subprocess.run(cmd, cwd=args.destdir, check=False).returncode -def write_ninja_rnd(handle: TextIO, toolchain: Toolchain, otbn_dir: str, +def write_ninja_rnd(handle: TextIO, toolchain: Toolchain, acc_dir: str, count: int, start_seed: int, size: int, config: str, pqc: int) -> None: '''Write a build.ninja to build random binaries. The rules build everything in the same directory as the build.ninja file. - OTBN tooling is found through the toolchain argument. + ACC tooling is found through the toolchain argument. ''' assert count > 0 assert start_seed >= 0 assert size > 0 - otbn_rig = os.path.join(otbn_dir, 'dv/rig/otbn-rig') + acc_rig = os.path.join(acc_dir, 'dv/rig/acc-rig') handle.write( 'rule rig-gen\n' ' command = {rig} gen --size {size} --config {config} --pqc {pqc} ' - '--seed $seed -o $out\n\n'.format(rig=otbn_rig, size=size, config=config, pqc=pqc)) + '--seed $seed -o $out\n\n'.format(rig=acc_rig, size=size, config=config, pqc=pqc)) handle.write('rule rig-asm\n' - ' command = {rig} asm -o $seed $in\n\n'.format(rig=otbn_rig)) + ' command = {rig} asm -o $seed $in\n\n'.format(rig=acc_rig)) handle.write( 'rule as\n' - ' command = RV32_TOOL_AS={rv32_as} {otbn_as} -o $out $in\n\n'.format( - rv32_as=toolchain.rv32_tool_as, otbn_as=toolchain.otbn_as)) + ' command = RV32_TOOL_AS={rv32_as} {acc_as} -o $out $in\n\n'.format( + rv32_as=toolchain.rv32_tool_as, acc_as=toolchain.acc_as)) handle.write('rule ld\n' ' command = RV32_TOOL_LD={rv32_ld} ' - '{otbn_ld} -o $out -T $ldscript $in\n'.format( + '{acc_ld} -o $out -T $ldscript $in\n'.format( rv32_ld=toolchain.rv32_tool_ld, - otbn_ld=toolchain.otbn_ld)) + acc_ld=toolchain.acc_ld)) for seed in range(start_seed, start_seed + count): # Generate the .s and .ld files. @@ -231,24 +231,24 @@ def write_ninja_rnd(handle: TextIO, toolchain: Toolchain, otbn_dir: str, ' ldscript = {seed}.ld\n\n'.format(seed=seed)) -def write_ninja_fixed(handle: TextIO, toolchain: Toolchain, otbn_dir: str, +def write_ninja_fixed(handle: TextIO, toolchain: Toolchain, acc_dir: str, src_dir: str) -> None: '''Write a build.ninja to build a fixed set of binaries The rules build everything in the same directory as the build.ninja file. - OTBN tooling is found through the toolchain argument. + ACC tooling is found through the toolchain argument. ''' handle.write( 'rule as\n' - ' command = RV32_TOOL_AS={rv32_as} {otbn_as} -o $out $in\n\n'.format( - rv32_as=toolchain.rv32_tool_as, otbn_as=toolchain.otbn_as)) + ' command = RV32_TOOL_AS={rv32_as} {acc_as} -o $out $in\n\n'.format( + rv32_as=toolchain.rv32_tool_as, acc_as=toolchain.acc_as)) handle.write( 'rule ld\n' - ' command = RV32_TOOL_LD={rv32_ld} {otbn_ld} -o $out $in\n\n'.format( - rv32_ld=toolchain.rv32_tool_ld, otbn_ld=toolchain.otbn_ld)) + ' command = RV32_TOOL_LD={rv32_ld} {acc_ld} -o $out $in\n\n'.format( + rv32_ld=toolchain.rv32_tool_ld, acc_ld=toolchain.acc_ld)) count = 0 for fname in os.listdir(src_dir): diff --git a/hw/ip/otbn/dv/uvm/get-toolchain-paths.sh b/hw/ip/acc/dv/uvm/get-toolchain-paths.sh similarity index 100% rename from hw/ip/otbn/dv/uvm/get-toolchain-paths.sh rename to hw/ip/acc/dv/uvm/get-toolchain-paths.sh diff --git a/hw/ip/otbn/dv/uvm/sva/otbn_bind.sv b/hw/ip/acc/dv/uvm/sva/acc_bind.sv similarity index 70% rename from hw/ip/otbn/dv/uvm/sva/otbn_bind.sv rename to hw/ip/acc/dv/uvm/sva/acc_bind.sv index 6b7732bd3a6..422fe855155 100644 --- a/hw/ip/otbn/dv/uvm/sva/otbn_bind.sv +++ b/hw/ip/acc/dv/uvm/sva/acc_bind.sv @@ -2,9 +2,9 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module otbn_bind; +module acc_bind; - bind otbn tlul_assert #( + bind acc tlul_assert #( .EndpointType("Device") ) tlul_checker ( .clk_i (clk_i), @@ -13,14 +13,14 @@ module otbn_bind; .d2h (tl_o) ); - bind otbn otbn_csr_assert_fpv csr_checker ( + bind acc acc_csr_assert_fpv csr_checker ( .clk_i (clk_i), .rst_ni (rst_ni), .h2d (tl_i), .d2h (tl_o) ); - bind otbn otbn_idle_checker idle_checker ( + bind acc acc_idle_checker idle_checker ( .clk_i (clk_i), .rst_ni (rst_ni), .reg2hw (reg2hw), @@ -28,8 +28,8 @@ module otbn_bind; .done_i (done), .idle_o_i (idle_o), - .otbn_dmem_scramble_key_req_busy_i(otbn_dmem_scramble_key_req_busy), - .otbn_imem_scramble_key_req_busy_i(otbn_imem_scramble_key_req_busy), + .acc_dmem_scramble_key_req_busy_i(acc_dmem_scramble_key_req_busy), + .acc_imem_scramble_key_req_busy_i(acc_imem_scramble_key_req_busy), .status_q_i(status_q), .busy_secure_wipe, diff --git a/hw/ip/otbn/dv/uvm/sva/otbn_idle_checker.sv b/hw/ip/acc/dv/uvm/sva/acc_idle_checker.sv similarity index 77% rename from hw/ip/otbn/dv/uvm/sva/otbn_idle_checker.sv rename to hw/ip/acc/dv/uvm/sva/acc_idle_checker.sv index ea693baddc0..80ce791958d 100644 --- a/hw/ip/otbn/dv/uvm/sva/otbn_idle_checker.sv +++ b/hw/ip/acc/dv/uvm/sva/acc_idle_checker.sv @@ -4,21 +4,21 @@ `include "prim_assert.sv" -module otbn_idle_checker - import otbn_reg_pkg::*; - import otbn_pkg::*; +module acc_idle_checker + import acc_reg_pkg::*; + import acc_pkg::*; ( input logic clk_i, input logic rst_ni, - input otbn_reg2hw_t reg2hw, - input otbn_hw2reg_t hw2reg, + input acc_reg2hw_t reg2hw, + input acc_hw2reg_t hw2reg, input logic done_i, input prim_mubi_pkg::mubi4_t idle_o_i, - input logic otbn_dmem_scramble_key_req_busy_i, - input logic otbn_imem_scramble_key_req_busy_i, + input logic acc_dmem_scramble_key_req_busy_i, + input logic acc_imem_scramble_key_req_busy_i, input logic [7:0] status_q_i, input logic busy_secure_wipe, @@ -26,7 +26,7 @@ module otbn_idle_checker input logic [ExtWLEN-1:0] dmem_rdata_bus ); - // Several of the internal signals that we snoop from the otbn module run "a cycle early". This + // Several of the internal signals that we snoop from the acc module run "a cycle early". This // lets the design flop some outputs, but we need to do some converting here to get everything to // line up. logic rotating_keys, done; @@ -35,7 +35,7 @@ module otbn_idle_checker rotating_keys <= 1'b0; done <= 1'b0; end else begin - rotating_keys <= otbn_dmem_scramble_key_req_busy_i | otbn_imem_scramble_key_req_busy_i; + rotating_keys <= acc_dmem_scramble_key_req_busy_i | acc_imem_scramble_key_req_busy_i; done <= done_i; end end @@ -43,15 +43,15 @@ module otbn_idle_checker // Detect writes to CMD. They only take effect if we are in state IDLE logic cmd_operation, start_req, do_start; - assign cmd_operation = reg2hw.cmd.q inside {otbn_pkg::CmdSecWipeImem, - otbn_pkg::CmdSecWipeDmem, - otbn_pkg::CmdExecute}; + assign cmd_operation = reg2hw.cmd.q inside {acc_pkg::CmdSecWipeImem, + acc_pkg::CmdSecWipeDmem, + acc_pkg::CmdExecute}; assign start_req = reg2hw.cmd.qe && cmd_operation; - assign do_start = start_req && (hw2reg.status.d == otbn_pkg::StatusIdle); + assign do_start = start_req && (hw2reg.status.d == acc_pkg::StatusIdle); - // Track whether OTBN has completed its initial secure wipe. + // Track whether ACC has completed its initial secure wipe. logic init_sec_wipe_done; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin @@ -63,7 +63,7 @@ module otbn_idle_checker end end - // Our model of whether OTBN is running or not. We start on `do_start` once the initial secure + // Our model of whether ACC is running or not. We start on `do_start` once the initial secure // wipe is done, and we stop on `done`. logic running_qq, running_q, running_d; always_ff @(posedge clk_i or negedge rst_ni) begin @@ -81,7 +81,7 @@ module otbn_idle_checker running_q; // keep // We should never see done when we're not already running. The converse assertion, that we never - // see cmd_start when we are running, need not be true: the host can do that if it likes and OTBN + // see cmd_start when we are running, need not be true: the host can do that if it likes and ACC // will ignore it. But we should never see do_start when we think we're running. `ASSERT(RunningIfDone_A, done |-> running_q) `ASSERT(IdleIfStart_A, do_start |-> !running_q) @@ -122,7 +122,7 @@ module otbn_idle_checker // - We should only have a key request in flight if we are either running (as tracked by // start/done) or LOCKED (OnlyKeyRotationWhenRunningOrLocked_A) // - // - If STATUS has value LOCKED and no secure wipe is running, we should not think OTBN is + // - If STATUS has value LOCKED and no secure wipe is running, we should not think ACC is // running (NotRunningWhenLocked_A). `ASSERT(NotIdleIfRunning_A, @@ -137,7 +137,7 @@ module otbn_idle_checker logic missing_idle_d, missing_idle_q; assign running_or_locked = running_qq || busy_secure_wipe || - status_q_i == otbn_pkg::StatusLocked; + status_q_i == acc_pkg::StatusLocked; assign missing_idle_d = !running_or_locked && (idle_o_i != prim_mubi_pkg::MuBi4True); always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin @@ -150,33 +150,33 @@ module otbn_idle_checker `ASSERT(IdleIfNotRunningOrLocked_A, !(missing_idle_d && missing_idle_q)) `ASSERT(NotIdleIfLockedAndRotatingKeys_A, - ((status_q_i == otbn_pkg::StatusLocked) && keys_busy) |-> + ((status_q_i == acc_pkg::StatusLocked) && keys_busy) |-> (idle_o_i == prim_mubi_pkg::MuBi4False)) `ASSERT(IdleIfLockedAndNotRotatingKeys_A, // `keys_busy` runs a cycle late compared to `busy_secure_wipe`. Thus, depending on which // component causes the condition to become true, it can take one or two cycles for `idle` // to become true. - ((status_q_i == otbn_pkg::StatusLocked) && !keys_busy && !busy_secure_wipe) |-> ##[1:2] + ((status_q_i == acc_pkg::StatusLocked) && !keys_busy && !busy_secure_wipe) |-> ##[1:2] (idle_o_i == prim_mubi_pkg::MuBi4True)) `ASSERT(NoStartKeyRotationWhenLocked_A, - (status_q_i == otbn_pkg::StatusLocked) |=> !$rose(keys_busy)) + (status_q_i == acc_pkg::StatusLocked) |=> !$rose(keys_busy)) `ASSERT(OnlyKeyRotationWhenRunningOrLocked_A, - keys_busy |-> (running_q || (status_q_i == otbn_pkg::StatusLocked))) + keys_busy |-> (running_q || (status_q_i == acc_pkg::StatusLocked))) `ASSERT(NotRunningWhenLocked_A, - (status_q_i == otbn_pkg::StatusLocked && !busy_secure_wipe) |-> + (status_q_i == acc_pkg::StatusLocked && !busy_secure_wipe) |-> !running_d) - // When OTBN locks bus read data integrity is forced to the correct value for 0 data (so reads to - // a locked OTBN don't cause an integrity error). There is a small window where running_q is set + // When ACC locks bus read data integrity is forced to the correct value for 0 data (so reads to + // a locked ACC don't cause an integrity error). There is a small window where running_q is set // with status_q reporting 'StatusLocked'. So expected bus read data depends upon locked status // when running. `ASSERT(NoMemRdataWhenBusy_A, - running_q && !(status_q_i == otbn_pkg::StatusBusySecWipeInt) |-> - ((status_q_i == otbn_pkg::StatusLocked) ? + running_q && !(status_q_i == acc_pkg::StatusBusySecWipeInt) |-> + ((status_q_i == acc_pkg::StatusLocked) ? imem_rdata_bus == EccZeroWord && dmem_rdata_bus == EccWideZeroWord : imem_rdata_bus == 'b0 && dmem_rdata_bus == 'b0)) diff --git a/hw/ip/otbn/dv/uvm/sva/otbn_sva.core b/hw/ip/acc/dv/uvm/sva/acc_sva.core similarity index 72% rename from hw/ip/otbn/dv/uvm/sva/otbn_sva.core rename to hw/ip/acc/dv/uvm/sva/acc_sva.core index 36781a7fb2c..a1498c9a167 100644 --- a/hw/ip/otbn/dv/uvm/sva/otbn_sva.core +++ b/hw/ip/acc/dv/uvm/sva/acc_sva.core @@ -2,29 +2,29 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_sva:0.1" -description: "OTBN assertion modules and bind file." +name: "lowrisc:dv:acc_sva:0.1" +description: "ACC assertion modules and bind file." filesets: files_dv: depend: - lowrisc:fpv:csr_assert_gen - - lowrisc:ip:otbn + - lowrisc:ip:acc - lowrisc:prim:assert - lowrisc:tlul:headers files: - - otbn_bind.sv - - otbn_idle_checker.sv + - acc_bind.sv + - acc_idle_checker.sv file_type: systemVerilogSource files_formal: depend: - - lowrisc:ip:otbn + - lowrisc:ip:acc generate: csr_assert_gen: generator: csr_assert_gen parameters: - spec: ../../../data/otbn.hjson + spec: ../../../data/acc.hjson targets: default: &default_target @@ -38,4 +38,4 @@ targets: filesets: - files_formal - files_dv - toplevel: otbn + toplevel: acc diff --git a/hw/ip/otbn/dv/uvm/tb.sv b/hw/ip/acc/dv/uvm/tb.sv similarity index 72% rename from hw/ip/otbn/dv/uvm/tb.sv rename to hw/ip/acc/dv/uvm/tb.sv index 641e40789d1..ef245b478e6 100644 --- a/hw/ip/otbn/dv/uvm/tb.sv +++ b/hw/ip/acc/dv/uvm/tb.sv @@ -8,13 +8,13 @@ module tb; import uvm_pkg::*; import dv_utils_pkg::*; import sram_ctrl_bkdr_util_pkg::sram_ctrl_bkdr_util; - import otbn_pqc_env_pkg::*; - import otbn_env_pkg::*; - import otbn_test_pkg::*; - import otbn_pkg::NGpr, otbn_pkg::NWdr; + import acc_pqc_env_pkg::*; + import acc_env_pkg::*; + import acc_test_pkg::*; + import acc_pkg::NGpr, acc_pkg::NWdr; // dep packages (rtl) - import otbn_reg_pkg::*; + import acc_reg_pkg::*; import edn_pkg::*; import otp_ctrl_pkg::*; import keymgr_pkg::*; @@ -33,20 +33,20 @@ module tb; // interfaces clk_rst_if clk_rst_if (.clk(clk), .rst_n(rst_n)); - otbn_app_intf otbn_app_intf (.clk(clk), .rst_n(rst_n)); + acc_app_intf acc_app_intf (.clk(clk), .rst_n(rst_n)); tl_if tl_if (.clk(clk), .rst_n(rst_n)); - otbn_escalate_if escalate_if (.clk_i (clk), .rst_ni (rst_n)); + acc_escalate_if escalate_if (.clk_i (clk), .rst_ni (rst_n)); pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); assign interrupts[0] = {intr_done}; - otbn_key_req_t sideload_key; - key_sideload_if#(keymgr_pkg::otbn_key_req_t) keymgr_if ( + acc_key_req_t sideload_key; + key_sideload_if#(keymgr_pkg::acc_key_req_t) keymgr_if ( .clk_i (clk), .rst_ni (rst_n), .sideload_key (sideload_key) ); - otbn_model_if #( + acc_model_if #( .ImemSizeByte (ImemSizeByte) ) model_if ( .clk_i (clk), @@ -58,11 +58,11 @@ module tb; localparam logic [127:0] TestScrambleKey = 128'h48ecf6c738f0f108a5b08620695ffd4d; localparam logic [63:0] TestScrambleNonce = 64'hf88c2578fa4cd123; - otbn_otp_key_req_t otp_key_req; - otbn_otp_key_rsp_t otp_key_rsp; + acc_otp_key_req_t otp_key_req; + acc_otp_key_rsp_t otp_key_rsp; - otp_ctrl_pkg::otbn_key_t key; - otp_ctrl_pkg::otbn_nonce_t nonce; + otp_ctrl_pkg::acc_key_t key; + otp_ctrl_pkg::acc_nonce_t nonce; wire seed_valid; wire otp_rst_n = rst_n; @@ -70,7 +70,7 @@ module tb; clk_rst_if otp_clk_rst_if(.clk(otp_clk), .rst_n(otp_rst_n)); - // Initiate push pull interface for the OTP<->OTBN connections + // Initiate push pull interface for the OTP<->ACC connections push_pull_if #( .DeviceDataWidth(KEY_RSP_DATA_SIZE) ) otp_key_if ( @@ -93,10 +93,10 @@ module tb; `DV_ALERT_IF_CONNECT() // dut - otbn # ( - .RndCnstOtbnKey(TestScrambleKey), - .RndCnstOtbnNonce(TestScrambleNonce), - .OtbnPQCEn(OtbnPQCEn) + acc # ( + .RndCnstAccKey(TestScrambleKey), + .RndCnstAccNonce(TestScrambleNonce), + .AccPQCEn(AccPQCEn) ) dut ( .clk_i (clk), .rst_ni(rst_n), @@ -104,7 +104,7 @@ module tb; .tl_i(tl_if.h2d), .tl_o(tl_if.d2h), - // Correct behaviour of the idle output is ensured by the bound-in otbn_idle_checker instance. + // Correct behaviour of the idle output is ensured by the bound-in acc_idle_checker instance. .idle_o(), .intr_done_o(intr_done), @@ -132,8 +132,8 @@ module tb; .clk_otp_i (otp_clk), .rst_otp_ni (otp_rst_n), - .otbn_otp_key_o(otp_key_req), - .otbn_otp_key_i(otp_key_rsp), + .acc_otp_key_o(otp_key_req), + .acc_otp_key_i(otp_key_rsp), .keymgr_key_i(sideload_key), .kmac_data_o(app_req), @@ -141,25 +141,25 @@ module tb; ); // Assert that the DUT and Package have the same PQC parameter - `ASSERT(MatchingPQC_A, otbn_pqc_env_pkg::OtbnPQCEn == dut.OtbnPQCEn, clk, !rst_n) + `ASSERT(MatchingPQC_A, acc_pqc_env_pkg::AccPQCEn == dut.AccPQCEn, clk, !rst_n) - bind dut.u_otbn_core otbn_trace_if #( + bind dut.u_acc_core acc_trace_if #( .ImemAddrWidth (ImemAddrWidth), .DmemAddrWidth (DmemAddrWidth) - ) i_otbn_trace_if (.*); + ) i_acc_trace_if (.*); - assign dut.u_otbn_core.i_otbn_trace_if.scramble_state_err_i = dut.otbn_scramble_state_error; - assign dut.u_otbn_core.i_otbn_trace_if.missed_gnt_i.imem_gnt_missed_err = dut.imem_missed_gnt; - assign dut.u_otbn_core.i_otbn_trace_if.missed_gnt_i.dmem_gnt_missed_err = dut.dmem_missed_gnt; + assign dut.u_acc_core.i_acc_trace_if.scramble_state_err_i = dut.acc_scramble_state_error; + assign dut.u_acc_core.i_acc_trace_if.missed_gnt_i.imem_gnt_missed_err = dut.imem_missed_gnt; + assign dut.u_acc_core.i_acc_trace_if.missed_gnt_i.dmem_gnt_missed_err = dut.dmem_missed_gnt; // Connect AppIntf between DUT and UVM vif - assign otbn_app_intf.kmac_data_req = app_req; - assign app_rsp = otbn_app_intf.kmac_data_rsp; + assign acc_app_intf.kmac_data_req = app_req; + assign app_rsp = acc_app_intf.kmac_data_rsp; - bind dut.u_otbn_core otbn_tracer u_otbn_tracer(.*, .otbn_trace(i_otbn_trace_if)); + bind dut.u_acc_core acc_tracer u_acc_tracer(.*, .acc_trace(i_acc_trace_if)); - bind dut.u_otbn_core.u_otbn_controller.u_otbn_loop_controller - otbn_loop_if i_otbn_loop_if ( + bind dut.u_acc_core.u_acc_controller.u_acc_loop_controller + acc_loop_if i_acc_loop_if ( .clk_i, .rst_ni, // The insn_addr_i signal in the loop controller is of width ImemAddrWidth. We expand it to a @@ -173,7 +173,7 @@ module tb; .loop_start_req_i, .loop_start_commit_i, .loop_iterations_i, - .otbn_stall_i, + .acc_stall_i, // These addresses are start/end addresses for entries in the loop stack. As with insn_addr_i, // we expand them to 32 bits. Also the loop stack entries have a type that's not exposed @@ -191,14 +191,14 @@ module tb; .loop_stack_pop ); - bind dut.u_otbn_core.u_otbn_alu_bignum otbn_alu_bignum_if i_otbn_alu_bignum_if (.*); - bind dut.u_otbn_core.u_otbn_controller otbn_controller_if i_otbn_controller_if (.*); - bind dut.u_otbn_core.u_otbn_mac_bignum otbn_mac_bignum_if i_otbn_mac_bignum_if (.*); - bind dut.u_otbn_core.u_otbn_rf_base otbn_rf_base_if i_otbn_rf_base_if (.*); + bind dut.u_acc_core.u_acc_alu_bignum acc_alu_bignum_if i_acc_alu_bignum_if (.*); + bind dut.u_acc_core.u_acc_controller acc_controller_if i_acc_controller_if (.*); + bind dut.u_acc_core.u_acc_mac_bignum acc_mac_bignum_if i_acc_mac_bignum_if (.*); + bind dut.u_acc_core.u_acc_rf_base acc_rf_base_if i_acc_rf_base_if (.*); - bind dut.u_otbn_core.u_otbn_rnd otbn_rnd_if i_otbn_rnd_if (.*); + bind dut.u_acc_core.u_acc_rnd acc_rnd_if i_acc_rnd_if (.*); - // OTBN model, wrapping an ISS. + // ACC model, wrapping an ISS. // // Note that we pull the "start" signal out of the DUT. This is because it's much more difficult // to grab the decoded signal from TL transactions on the cycle it happens. We have an explicit @@ -215,13 +215,13 @@ module tb; assign edn_rnd_cdc_done = dut.edn_rnd_req & dut.edn_rnd_ack; assign edn_urnd_cdc_done = dut.edn_urnd_req & dut.edn_urnd_ack; - assign otp_key_cdc_done = dut.u_otbn_scramble_ctrl.otp_key_ack; + assign otp_key_cdc_done = dut.u_acc_scramble_ctrl.otp_key_ack; bit [31:0] model_insn_cnt; - otbn_core_model #( + acc_core_model #( .MemScope ("..dut"), - .DesignScope ("..dut.u_otbn_core") + .DesignScope ("..dut.u_acc_core") ) u_model ( .clk_i (model_if.clk_i), .clk_edn_i (edn_clk), @@ -244,7 +244,7 @@ module tb; .edn_urnd_o (edn_urnd_req_model), .edn_urnd_cdc_done_i(edn_urnd_cdc_done), - .init_sec_wipe_done_i(dut.u_otbn_core.i_otbn_trace_if.initial_secure_wipe_done), + .init_sec_wipe_done_i(dut.u_acc_core.i_acc_trace_if.initial_secure_wipe_done), .otp_key_cdc_done_i(otp_key_cdc_done), @@ -258,7 +258,7 @@ module tb; .keymgr_key_i(model_if.keymgr_key_i) ); - // Pull the final PC and the OtbnModel handle out of the SV model wrapper. + // Pull the final PC and the AccModel handle out of the SV model wrapper. assign model_if.stop_pc = u_model.stop_pc_q; // The always_ff is because the spec doesn't allow continuous assignments for chandles. The value // is populated in an init block and we'll only read this when the start signal is asserted, which @@ -267,18 +267,18 @@ module tb; model_if.handle <= u_model.model_handle; end - otbn_insn_cnt_if insn_cnt_if ( + acc_insn_cnt_if insn_cnt_if ( .clk_i (clk), .rst_ni (rst_n), .insn_cnt_i (dut.insn_cnt), - .insn_executing_i (dut.u_otbn_core.u_otbn_controller.insn_executing), - .stall_i (dut.u_otbn_core.u_otbn_controller.stall), + .insn_executing_i (dut.u_acc_core.u_acc_controller.insn_executing), + .stall_i (dut.u_acc_core.u_acc_controller.stall), .model_insn_cnt_i (model_insn_cnt) ); - otbn_ssctrl_if ssctrl_if(); + acc_ssctrl_if ssctrl_if(); ////////////////////////////////////////////////////////////////////////////// // Model/RTL consistency checks @@ -309,12 +309,12 @@ module tb; `ASSERT(MatchingStatus_A, {status_mismatch_d, status_mismatch_q} != 2'b11, clk, !rst_n) // Check that if the modelled EDN requests are matching with the requests from DUT - `ASSERT(MatchingReqRND_A, dut.u_otbn_core.edn_rnd_req_o == edn_rnd_req_model, clk, !rst_n) + `ASSERT(MatchingReqRND_A, dut.u_acc_core.edn_rnd_req_o == edn_rnd_req_model, clk, !rst_n) // Disable checking URND in the case of Locked status since it's modelling is not exactly accurate // for that state. // TODO (#15710): Fix modelling of URND in the locked state. - `ASSERT(MatchingReqURND_A, dut.u_otbn_core.edn_urnd_req_o == edn_urnd_req_model, - clk, !rst_n || model_if.status == otbn_pkg::StatusLocked) + `ASSERT(MatchingReqURND_A, dut.u_acc_core.edn_urnd_req_o == edn_urnd_req_model, + clk, !rst_n || model_if.status == acc_pkg::StatusLocked) initial begin sram_ctrl_bkdr_util imem_util, dmem_util; @@ -325,39 +325,39 @@ module tb; uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "otp_clk_rst_vif", otp_clk_rst_if); uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); - uvm_config_db#(virtual otbn_app_intf)::set(null, "*env.m_otbn_app_agent", "vif", otbn_app_intf); + uvm_config_db#(virtual acc_app_intf)::set(null, "*env.m_acc_app_agent", "vif", acc_app_intf); uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); uvm_config_db#(ssctrl_vif)::set(null, "*.env", "ssctrl_vif", ssctrl_if); uvm_config_db#(escalate_vif)::set(null, "*.env", "escalate_vif", escalate_if); uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); - uvm_config_db#(virtual otbn_model_if#(.ImemSizeByte(ImemSizeByte)))::set( + uvm_config_db#(virtual acc_model_if#(.ImemSizeByte(ImemSizeByte)))::set( null, "*.env.model_agent", "vif", model_if); - uvm_config_db#(virtual key_sideload_if#(keymgr_pkg::otbn_key_req_t))::set( + uvm_config_db#(virtual key_sideload_if#(keymgr_pkg::acc_key_req_t))::set( null, "*.env.keymgr_sideload_agent", "vif", keymgr_if); uvm_config_db#(otp_key_vif)::set( null, "*.env.key_agent*", "vif", otp_key_if); - uvm_config_db#(virtual otbn_trace_if)::set(null, "*.env", "trace_vif", - dut.u_otbn_core.i_otbn_trace_if); - uvm_config_db#(virtual otbn_loop_if)::set( + uvm_config_db#(virtual acc_trace_if)::set(null, "*.env", "trace_vif", + dut.u_acc_core.i_acc_trace_if); + uvm_config_db#(virtual acc_loop_if)::set( null, "*.env", "loop_vif", - dut.u_otbn_core.u_otbn_controller.u_otbn_loop_controller.i_otbn_loop_if); - uvm_config_db#(virtual otbn_alu_bignum_if)::set( + dut.u_acc_core.u_acc_controller.u_acc_loop_controller.i_acc_loop_if); + uvm_config_db#(virtual acc_alu_bignum_if)::set( null, "*.env", "alu_bignum_vif", - dut.u_otbn_core.u_otbn_alu_bignum.i_otbn_alu_bignum_if); - uvm_config_db#(virtual otbn_controller_if)::set( + dut.u_acc_core.u_acc_alu_bignum.i_acc_alu_bignum_if); + uvm_config_db#(virtual acc_controller_if)::set( null, "*.env", "controller_vif", - dut.u_otbn_core.u_otbn_controller.i_otbn_controller_if); - uvm_config_db#(virtual otbn_mac_bignum_if)::set( + dut.u_acc_core.u_acc_controller.i_acc_controller_if); + uvm_config_db#(virtual acc_mac_bignum_if)::set( null, "*.env", "mac_bignum_vif", - dut.u_otbn_core.u_otbn_mac_bignum.i_otbn_mac_bignum_if); - uvm_config_db#(virtual otbn_rf_base_if)::set( + dut.u_acc_core.u_acc_mac_bignum.i_acc_mac_bignum_if); + uvm_config_db#(virtual acc_rf_base_if)::set( null, "*.env", "rf_base_vif", - dut.u_otbn_core.u_otbn_rf_base.i_otbn_rf_base_if); - uvm_config_db#(virtual otbn_rnd_if)::set( + dut.u_acc_core.u_acc_rf_base.i_acc_rf_base_if); + uvm_config_db#(virtual acc_rnd_if)::set( null, "*.env", "rnd_vif", - dut.u_otbn_core.u_otbn_rnd.i_otbn_rnd_if); + dut.u_acc_core.u_acc_rnd.i_acc_rnd_if); // Instantiate mem_bkdr_util objects to allow access to IMEM and DMEM // @@ -387,12 +387,12 @@ module tb; // Assertion controls for turning them on/off easily // A hook to allow sequences to enable or disable the MatchingStatus_A assertion below. This is - // needed for sequences that trigger alerts (locking OTBN) without telling the model. - `DV_ASSERT_CTRL("otbn_status_assert_en", tb.MatchingStatus_A) + // needed for sequences that trigger alerts (locking ACC) without telling the model. + `DV_ASSERT_CTRL("acc_status_assert_en", tb.MatchingStatus_A) // We need to turn off DMEM related assertions in the tests where we force internals of DMEM to generate errors - `DV_ASSERT_CTRL("DMemAsserts", tb.dut.u_otbn_core.u_otbn_lsu.DMemRValidAfterReq) - `DV_ASSERT_CTRL("DMemAsserts", tb.dut.u_otbn_core.OnlyWriteLoadDataBaseWhenDMemValid_A) - `DV_ASSERT_CTRL("DMemAsserts", tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A) + `DV_ASSERT_CTRL("DMemAsserts", tb.dut.u_acc_core.u_acc_lsu.DMemRValidAfterReq) + `DV_ASSERT_CTRL("DMemAsserts", tb.dut.u_acc_core.OnlyWriteLoadDataBaseWhenDMemValid_A) + `DV_ASSERT_CTRL("DMemAsserts", tb.dut.u_acc_core.OnlyWriteLoadDataBignumWhenDMemValid_A) endmodule diff --git a/hw/ip/otbn/dv/uvm/tests/otbn_base_test.sv b/hw/ip/acc/dv/uvm/tests/acc_base_test.sv similarity index 51% rename from hw/ip/otbn/dv/uvm/tests/otbn_base_test.sv rename to hw/ip/acc/dv/uvm/tests/acc_base_test.sv index 27f0360df04..e00a3af20ab 100644 --- a/hw/ip/otbn/dv/uvm/tests/otbn_base_test.sv +++ b/hw/ip/acc/dv/uvm/tests/acc_base_test.sv @@ -2,23 +2,23 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -class otbn_base_test extends cip_base_test #( - .CFG_T(otbn_env_cfg), - .ENV_T(otbn_env) +class acc_base_test extends cip_base_test #( + .CFG_T(acc_env_cfg), + .ENV_T(acc_env) ); - `uvm_component_utils(otbn_base_test) + `uvm_component_utils(acc_base_test) `uvm_component_new // the base class dv_base_test creates the following instances: - // otbn_env_cfg: cfg - // otbn_env: env + // acc_env_cfg: cfg + // acc_env: env function void build_phase(uvm_phase phase); super.build_phase(phase); - if (!$value$plusargs("otbn_elf_dir=%0s", cfg.otbn_elf_dir)) begin - `uvm_fatal(`gfn, "Missing required plusarg: otbn_elf_dir.") + if (!$value$plusargs("acc_elf_dir=%0s", cfg.acc_elf_dir)) begin + `uvm_fatal(`gfn, "Missing required plusarg: acc_elf_dir.") end endfunction -endclass : otbn_base_test +endclass : acc_base_test diff --git a/hw/ip/otbn/dv/uvm/tests/otbn_test.core b/hw/ip/acc/dv/uvm/tests/acc_test.core similarity index 60% rename from hw/ip/otbn/dv/uvm/tests/otbn_test.core rename to hw/ip/acc/dv/uvm/tests/acc_test.core index 01b09ac1b32..5053102dda6 100644 --- a/hw/ip/otbn/dv/uvm/tests/otbn_test.core +++ b/hw/ip/acc/dv/uvm/tests/acc_test.core @@ -2,16 +2,16 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_test:0.1" -description: "OTBN DV UVM test" +name: "lowrisc:dv:acc_test:0.1" +description: "ACC DV UVM test" filesets: files_dv: depend: - - lowrisc:dv:otbn_env - - lowrisc:dv:otbn_memutil + - lowrisc:dv:acc_env + - lowrisc:dv:acc_memutil files: - - otbn_test_pkg.sv - - otbn_base_test.sv: {is_include_file: true} + - acc_test_pkg.sv + - acc_base_test.sv: {is_include_file: true} file_type: systemVerilogSource targets: diff --git a/hw/ip/otbn/dv/uvm/tests/otbn_test_pkg.sv b/hw/ip/acc/dv/uvm/tests/acc_test_pkg.sv similarity index 77% rename from hw/ip/otbn/dv/uvm/tests/otbn_test_pkg.sv rename to hw/ip/acc/dv/uvm/tests/acc_test_pkg.sv index 2f038553d75..c1a8e11b5d7 100644 --- a/hw/ip/otbn/dv/uvm/tests/otbn_test_pkg.sv +++ b/hw/ip/acc/dv/uvm/tests/acc_test_pkg.sv @@ -2,12 +2,12 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -package otbn_test_pkg; +package acc_test_pkg; // dep packages import uvm_pkg::*; import cip_base_pkg::*; - import otbn_env_pkg::*; - import otbn_memutil_pkg::*; + import acc_env_pkg::*; + import acc_memutil_pkg::*; // macro includes `include "uvm_macros.svh" @@ -18,6 +18,6 @@ package otbn_test_pkg; // functions // package sources - `include "otbn_base_test.sv" + `include "acc_base_test.sv" endpackage diff --git a/hw/ip/otbn/dv/verilator/otbn_mock_edn.sv b/hw/ip/acc/dv/verilator/acc_mock_edn.sv similarity index 97% rename from hw/ip/otbn/dv/verilator/otbn_mock_edn.sv rename to hw/ip/acc/dv/verilator/acc_mock_edn.sv index 9a2bdbcb3ee..03f47e20fcf 100644 --- a/hw/ip/otbn/dv/verilator/otbn_mock_edn.sv +++ b/hw/ip/acc/dv/verilator/acc_mock_edn.sv @@ -4,9 +4,9 @@ /** * Mock EDN end point that returns a fixed value after a fixed delay used for - * OTBN simulation purposes. + * ACC simulation purposes. */ -module otbn_mock_edn +module acc_mock_edn import edn_pkg::*; #( parameter int Width = 256, diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.cc b/hw/ip/acc/dv/verilator/acc_top_sim.cc similarity index 74% rename from hw/ip/otbn/dv/verilator/otbn_top_sim.cc rename to hw/ip/acc/dv/verilator/acc_top_sim.cc index d48d35efc20..8ee8e6ab0e8 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim.cc +++ b/hw/ip/acc/dv/verilator/acc_top_sim.cc @@ -10,39 +10,39 @@ #include #include -#include "Votbn_top_sim__Syms.h" +#include "Vacc_top_sim__Syms.h" +#include "acc_memutil.h" +#include "acc_model.h" +#include "acc_trace_checker.h" +#include "acc_trace_source.h" #include "log_trace_listener.h" -#include "otbn_memutil.h" -#include "otbn_model.h" -#include "otbn_trace_checker.h" -#include "otbn_trace_source.h" #include "sv_scoped.h" #include "verilated_toplevel.h" #include "verilator_memutil.h" #include "verilator_sim_ctrl.h" extern "C" { -extern unsigned int otbn_base_call_stack_get_size(); -extern unsigned int otbn_base_call_stack_get_element(int index); -extern unsigned int otbn_base_reg_get(int index); -extern unsigned int otbn_bignum_reg_get(int index, int quarter); -extern svBit otbn_err_get(); -extern int otbn_core_get_stop_pc(); +extern unsigned int acc_base_call_stack_get_size(); +extern unsigned int acc_base_call_stack_get_element(int index); +extern unsigned int acc_base_reg_get(int index); +extern unsigned int acc_bignum_reg_get(int index, int quarter); +extern svBit acc_err_get(); +extern int acc_core_get_stop_pc(); } /** - * SimCtrlExtension that adds a '--otbn-trace-file' command line option. If set + * SimCtrlExtension that adds a '--acc-trace-file' command line option. If set * it sets up a LogTraceListener that will dump out the trace to the given log * file */ -class OtbnTraceUtil : public SimCtrlExtension { +class AccTraceUtil : public SimCtrlExtension { private: std::unique_ptr log_trace_listener_; bool SetupTraceLog(const std::string &log_filename) { try { log_trace_listener_.reset(new LogTraceListener(log_filename)); - OtbnTraceSource::get().AddListener(log_trace_listener_.get()); + AccTraceSource::get().AddListener(log_trace_listener_.get()); return true; } catch (const std::runtime_error &err) { std::cerr << "ERROR: Failed to set up trace log: " << err.what() @@ -55,14 +55,14 @@ class OtbnTraceUtil : public SimCtrlExtension { void PrintHelp() { std::cout << "Trace log utilities:\n\n" - "--otbn-trace-file=FILE\n" - " Write OTBN trace log to FILE\n\n"; + "--acc-trace-file=FILE\n" + " Write ACC trace log to FILE\n\n"; } public: virtual bool ParseCLIArguments(int argc, char **argv, bool &exit_app) { const struct option long_options[] = { - {"otbn-trace-file", required_argument, nullptr, 'l'}, + {"acc-trace-file", required_argument, nullptr, 'l'}, {"help", no_argument, nullptr, 'h'}, {nullptr, no_argument, nullptr, 0}}; @@ -90,21 +90,21 @@ class OtbnTraceUtil : public SimCtrlExtension { return true; } - ~OtbnTraceUtil() { + ~AccTraceUtil() { if (log_trace_listener_) - OtbnTraceSource::get().RemoveListener(log_trace_listener_.get()); + AccTraceSource::get().RemoveListener(log_trace_listener_.get()); } }; -static otbn_top_sim *verilator_top; -static OtbnMemUtil otbn_memutil("TOP.otbn_top_sim"); +static acc_top_sim *verilator_top; +static AccMemUtil acc_memutil("TOP.acc_top_sim"); int main(int argc, char **argv) { - VerilatorMemUtil memutil(&otbn_memutil); - OtbnTraceUtil traceutil; + VerilatorMemUtil memutil(&acc_memutil); + AccTraceUtil traceutil; - otbn_top_sim top; - // Make the otbn_top_sim object visible to OtbnTopApplyLoopWarp. + acc_top_sim top; + // Make the acc_top_sim object visible to AccTopApplyLoopWarp. // This will leave a dangling pointer when we exit main, but that // doesn't really matter because we don't have anything that uses it // running in atexit hooks. @@ -116,7 +116,7 @@ int main(int argc, char **argv) { simctrl.RegisterExtension(&memutil); simctrl.RegisterExtension(&traceutil); - std::cout << "Simulation of OTBN" << std::endl + std::cout << "Simulation of ACC" << std::endl << "==================" << std::endl << std::endl; @@ -128,17 +128,17 @@ int main(int argc, char **argv) { return ret_code; } - svSetScope(svGetScopeFromName("TOP.otbn_top_sim")); + svSetScope(svGetScopeFromName("TOP.acc_top_sim")); - svBit model_err = otbn_err_get(); + svBit model_err = acc_err_get(); if (model_err) { return 1; } - int exp_stop_pc = otbn_memutil.GetExpEndAddr(); + int exp_stop_pc = acc_memutil.GetExpEndAddr(); if (exp_stop_pc >= 0) { - SVScoped core_scope("TOP.otbn_top_sim.u_otbn_core_model"); - int act_stop_pc = otbn_core_get_stop_pc(); + SVScoped core_scope("TOP.acc_top_sim.u_acc_core_model"); + int act_stop_pc = acc_core_get_stop_pc(); if (exp_stop_pc != act_stop_pc) { std::cerr << "ERROR: Expected stop PC from ELF file was 0x" << std::hex << exp_stop_pc << ", but simulation actually stopped at 0x" @@ -153,24 +153,24 @@ int main(int argc, char **argv) { // This is executed over DPI on the first posedge of the clock after each // reset. It's in charge of telling the model about any loop warp symbols in // the ELF file. -extern "C" int OtbnTopInstallLoopWarps() { - // Cast to the right base class of otbn_top_sim. Otherwise, you can't access - // the "otbn_top_sim" member because you get the derived class's constructor +extern "C" int AccTopInstallLoopWarps() { + // Cast to the right base class of acc_top_sim. Otherwise, you can't access + // the "acc_top_sim" member because you get the derived class's constructor // by accident. - Votbn_top_sim &top = *verilator_top; + Vacc_top_sim &top = *verilator_top; - // Grab the model handle from the otbn_core_model module. This should have + // Grab the model handle from the acc_core_model module. This should have // been initialised by now because it gets set up in an initial block and // this code doesn't run until the first clock edge. - auto sv_model_handle = top.otbn_top_sim->u_otbn_core_model->model_handle; + auto sv_model_handle = top.acc_top_sim->u_acc_core_model->model_handle; // sv_model_handle will be some integer type. Check it's nonzero and, if so, - // convert it to an OtbnModel*. + // convert it to an AccModel*. assert(sv_model_handle != 0); - OtbnModel *model_handle = (OtbnModel *)sv_model_handle; + AccModel *model_handle = (AccModel *)sv_model_handle; - if (model_handle->take_loop_warps(otbn_memutil) != 0) { + if (model_handle->take_loop_warps(acc_memutil) != 0) { // Something went wrong when trying to update the model. We've already // written to something to stderr, so should just pass the non-zero return // value up the stack. @@ -230,14 +230,14 @@ auto get_loop_counter(LoopControllerT *loop_controller, uint32_t counter_idx) // This is executed over DPI on every negedge of the clock and is in charge of // updating the top of the loop stack if necessary to match loop warp symbols // in the ELF file. -extern "C" void OtbnTopApplyLoopWarp() { +extern "C" void AccTopApplyLoopWarp() { static std::vector loop_count_stack; - // See not in OtbnTopInstallLoopWarps for why this upcast is needed. - Votbn_top_sim &top = *verilator_top; + // See not in AccTopInstallLoopWarps for why this upcast is needed. + Vacc_top_sim &top = *verilator_top; auto loop_controller = - top.otbn_top_sim->u_otbn_core->u_otbn_controller->u_otbn_loop_controller; + top.acc_top_sim->u_acc_core->u_acc_controller->u_acc_loop_controller; // Track loop stack state. if (loop_controller->current_loop_finish) { @@ -275,7 +275,7 @@ extern "C" void OtbnTopApplyLoopWarp() { uint32_t old_cnt = total - old_iters; uint32_t insn_addr = loop_controller->insn_addr_i; - uint32_t new_cnt = otbn_memutil.GetLoopWarp(insn_addr, old_cnt); + uint32_t new_cnt = acc_memutil.GetLoopWarp(insn_addr, old_cnt); if (old_cnt != new_cnt) { // Convert from new_cnt back to the "iters" format by subtracting from // the total, but bottom out at 1 (the last iteration). @@ -292,13 +292,13 @@ extern "C" void OtbnTopApplyLoopWarp() { // This is executed over DPI when the model says that execution has just // finished. We use it to dump out the current RTL state before secure wipe // zeroes everything out. -extern "C" void OtbnTopDumpState() { +extern "C" void AccTopDumpState() { std::cout << "Call Stack:" << std::endl; std::cout << "-----------" << std::endl; - for (int i = 0; i < otbn_base_call_stack_get_size(); ++i) { + for (int i = 0; i < acc_base_call_stack_get_size(); ++i) { std::cout << std::setfill(' ') << "0x" << std::hex << std::setw(8) << std::setfill('0') << std::right - << otbn_base_call_stack_get_element(i) << std::endl; + << acc_base_call_stack_get_element(i) << std::endl; } std::cout << std::endl; @@ -309,7 +309,7 @@ extern "C" void OtbnTopDumpState() { for (int i = 2; i < 32; ++i) { std::cout << "x" << std::left << std::dec << std::setw(2) << std::setfill(' ') << i << " | 0x" << std::hex << std::setw(8) - << std::setfill('0') << std::right << otbn_base_reg_get(i) + << std::setfill('0') << std::right << acc_base_reg_get(i) << std::endl; } @@ -326,27 +326,27 @@ extern "C" void OtbnTopDumpState() { << std::setfill(' ') << i << " | 0x" << std::hex; std::cout << std::setw(8) << std::setfill('0') << std::right - << otbn_bignum_reg_get(i, 7) << "_"; + << acc_bignum_reg_get(i, 7) << "_"; - std::cout << std::setw(8) << std::setfill('0') << otbn_bignum_reg_get(i, 6) + std::cout << std::setw(8) << std::setfill('0') << acc_bignum_reg_get(i, 6) << "_"; - std::cout << std::setw(8) << std::setfill('0') << otbn_bignum_reg_get(i, 5) + std::cout << std::setw(8) << std::setfill('0') << acc_bignum_reg_get(i, 5) << "_"; - std::cout << std::setw(8) << std::setfill('0') << otbn_bignum_reg_get(i, 4) + std::cout << std::setw(8) << std::setfill('0') << acc_bignum_reg_get(i, 4) << "_"; - std::cout << std::setw(8) << std::setfill('0') << otbn_bignum_reg_get(i, 3) + std::cout << std::setw(8) << std::setfill('0') << acc_bignum_reg_get(i, 3) << "_"; - std::cout << std::setw(8) << std::setfill('0') << otbn_bignum_reg_get(i, 2) + std::cout << std::setw(8) << std::setfill('0') << acc_bignum_reg_get(i, 2) << "_"; - std::cout << std::setw(8) << std::setfill('0') << otbn_bignum_reg_get(i, 1) + std::cout << std::setw(8) << std::setfill('0') << acc_bignum_reg_get(i, 1) << "_"; - std::cout << std::setw(8) << std::setfill('0') << otbn_bignum_reg_get(i, 0) + std::cout << std::setw(8) << std::setfill('0') << acc_bignum_reg_get(i, 0) << std::endl; } } diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.core b/hw/ip/acc/dv/verilator/acc_top_sim.core similarity index 76% rename from hw/ip/otbn/dv/verilator/otbn_top_sim.core rename to hw/ip/acc/dv/verilator/acc_top_sim.core index 0a834d4e6c0..22eccaded8e 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim.core +++ b/hw/ip/acc/dv/verilator/acc_top_sim.core @@ -3,38 +3,38 @@ CAPI=2: # Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:ip:otbn_top_sim:0.1" -description: "Standalone OpenTitan Big Number Accelerator (OTBN) simulation" +name: "lowrisc:ip:acc_top_sim:0.1" +description: "Standalone OpenTitan Big Number Accelerator (ACC) simulation" filesets: - files_otbn: + files_acc: depend: - - lowrisc:ip:otbn - - lowrisc:dv:otbn_pqc_off_env_pkg - - lowrisc:dv:otbn_model - - lowrisc:ip:otbn_tracer + - lowrisc:ip:acc + - lowrisc:dv:acc_pqc_off_env_pkg + - lowrisc:dv:acc_model + - lowrisc:ip:acc_tracer - lowrisc:ip:keymgr_pkg files_verilator: depend: - - lowrisc:dv:otbn_memutil + - lowrisc:dv:acc_memutil - lowrisc:dv_verilator:memutil_verilator - lowrisc:dv_verilator:simutil_verilator files: - - otbn_top_sim.cc: { file_type: cppSource } - - otbn_top_sim.sv: { file_type: systemVerilogSource } - - otbn_mock_edn.sv: { file_type: systemVerilogSource } + - acc_top_sim.cc: { file_type: cppSource } + - acc_top_sim.sv: { file_type: systemVerilogSource } + - acc_mock_edn.sv: { file_type: systemVerilogSource } files_verilator_waiver: files: - - otbn_top_sim_waivers.vlt + - acc_top_sim_waivers.vlt file_type: vlt targets: default: &default_target filesets: - files_verilator_waiver - - files_otbn + - files_acc - files_verilator - toplevel: otbn_top_sim + toplevel: acc_top_sim lint: <<: *default_target @@ -66,7 +66,7 @@ targets: - '--trace-structs' - '--trace-params' - '--trace-max-array 1024' - - '-CFLAGS "-std=c++17 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=otbn_top_sim"' + - '-CFLAGS "-std=c++17 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=acc_top_sim"' - '-LDFLAGS "-pthread -lutil -lelf"' - "-Wall" # RAM primitives wider than 64bit (required for ECC) fail to build in diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.sv b/hw/ip/acc/dv/verilator/acc_top_sim.sv similarity index 73% rename from hw/ip/otbn/dv/verilator/otbn_top_sim.sv rename to hw/ip/acc/dv/verilator/acc_top_sim.sv index 725d77c3c9e..bb493ec53fb 100644 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim.sv +++ b/hw/ip/acc/dv/verilator/acc_top_sim.sv @@ -3,19 +3,19 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module otbn_top_sim ( +module acc_top_sim ( input IO_CLK, input IO_RST_N ); - import otbn_pkg::*; - import otbn_pqc_env_pkg::*; + import acc_pkg::*; + import acc_pqc_env_pkg::*; import edn_pkg::*; - import keymgr_pkg::otbn_key_req_t; + import keymgr_pkg::acc_key_req_t; // Size of the instruction memory, in bytes - parameter int ImemSizeByte = otbn_reg_pkg::OTBN_IMEM_SIZE; + parameter int ImemSizeByte = acc_reg_pkg::ACC_IMEM_SIZE; // Size of the data memory, in bytes - parameter int DmemSizeByte = otbn_reg_pkg::OTBN_DMEM_SIZE + otbn_pkg::DmemScratchSizeByte; + parameter int DmemSizeByte = acc_reg_pkg::ACC_DMEM_SIZE + acc_pkg::DmemScratchSizeByte; localparam int ImemAddrWidth = prim_util_pkg::vbits(ImemSizeByte); localparam int DmemAddrWidth = prim_util_pkg::vbits(DmemSizeByte); @@ -24,14 +24,14 @@ module otbn_top_sim ( localparam logic [127:0] TestScrambleKey = 128'h48ecf6c738f0f108a5b08620695ffd4d; localparam logic [63:0] TestScrambleNonce = 64'hf88c2578fa4cd123; - logic otbn_done, otbn_done_r, otbn_done_rr; + logic acc_done, acc_done_r, acc_done_rr; core_err_bits_t core_err_bits; - err_bits_t otbn_err_bits, otbn_err_bits_r, otbn_err_bits_rr; - logic otbn_start, otbn_start_r; + err_bits_t acc_err_bits, acc_err_bits_r, acc_err_bits_rr; + logic acc_start, acc_start_r; - // Initialise otbn_start_done to 1 so that we only signal otbn_start after we have seen a reset. If - // you don't do this, we start OTBN before the reset, which can generate confusing trace messages. - logic otbn_start_done = 1'b1; + // Initialise acc_start_done to 1 so that we only signal acc_start after we have seen a reset. If + // you don't do this, we start ACC before the reset, which can generate confusing trace messages. + logic acc_start_done = 1'b1; // Instruction memory (IMEM) signals logic imem_req; @@ -56,30 +56,30 @@ module otbn_top_sim ( logic edn_rnd_data_valid; logic edn_urnd_data_valid; - // Instruction counter (feeds into otbn.INSN_CNT in full block) + // Instruction counter (feeds into acc.INSN_CNT in full block) logic [31:0] insn_cnt; logic [1:0][SideloadKeyWidth-1:0] sideload_key_shares; assign sideload_key_shares[0] = {12{32'hDEADBEEF}}; assign sideload_key_shares[1] = {12{32'hBAADF00D}}; - otbn_key_req_t keymgr_key; + acc_key_req_t keymgr_key; assign keymgr_key.key[0] = sideload_key_shares[0]; assign keymgr_key.key[1] = sideload_key_shares[1]; assign keymgr_key.valid = 1'b1; logic secure_wipe_running; - otbn_core #( + acc_core #( .ImemSizeByte ( ImemSizeByte ), .DmemSizeByte ( DmemSizeByte ), .SecMuteUrnd ( 1'b0 ), .SecSkipUrndReseedAtStart ( 1'b0 ), - .OtbnPQCEn ( OtbnPQCEn ) - ) u_otbn_core ( + .AccPQCEn ( AccPQCEn ) + ) u_acc_core ( .clk_i ( IO_CLK ), .rst_ni ( IO_RST_N ), - .start_i ( otbn_start_r ), - .done_o ( otbn_done ), + .start_i ( acc_start_r ), + .done_o ( acc_done ), .locking_o ( ), .secure_wipe_running_o ( secure_wipe_running ), @@ -141,7 +141,7 @@ module otbn_top_sim ( assign rnd_req.edn_req = edn_rnd_req; - otbn_mock_edn #( + acc_mock_edn #( .Width ( WLEN ), .FixedEdnVals ( FixedEdnVals ) ) u_mock_rnd_edn( @@ -162,7 +162,7 @@ module otbn_top_sim ( assign urnd_req.edn_req = edn_urnd_req; - otbn_mock_edn #( + acc_mock_edn #( .Width ( WLEN ), .FixedEdnVals ( FixedEdnVals ) ) u_mock_urnd_edn( @@ -178,14 +178,14 @@ module otbn_top_sim ( assign edn_urnd_data_valid = edn_urnd_req & edn_urnd_ack; - bind otbn_core otbn_trace_if #(.ImemAddrWidth, .DmemAddrWidth) i_otbn_trace_if (.*); - bind otbn_core otbn_tracer u_otbn_tracer(.*, .otbn_trace(i_otbn_trace_if)); + bind acc_core acc_trace_if #(.ImemAddrWidth, .DmemAddrWidth) i_acc_trace_if (.*); + bind acc_core acc_tracer u_acc_tracer(.*, .acc_trace(i_acc_trace_if)); - assign u_otbn_core.i_otbn_trace_if.scramble_state_err_i = '0; - assign u_otbn_core.i_otbn_trace_if.missed_gnt_i = '0; + assign u_acc_core.i_acc_trace_if.scramble_state_err_i = '0; + assign u_acc_core.i_acc_trace_if.missed_gnt_i = '0; // Convert from core_err_bits_t to err_bits_t - assign otbn_err_bits = '{ + assign acc_err_bits = '{ fatal_software: core_err_bits.fatal_software, lifecycle_escalation: 0, illegal_bus_access: 0, @@ -204,10 +204,10 @@ module otbn_top_sim ( bad_data_addr: core_err_bits.bad_data_addr }; - // Track when OTBN is done with its initial secure wipe of the internal state. We use this to - // wait for the OTBN core to complete the initial secure wipe before we send it the start signal. + // Track when ACC is done with its initial secure wipe of the internal state. We use this to + // wait for the ACC core to complete the initial secure wipe before we send it the start signal. // Also keep a delayed copy of the done signal. This is necessary to align with the status of - // OTBN and the model, which lags one cycle behind the completion of the OTBN core. + // ACC and the model, which lags one cycle behind the completion of the ACC core. logic init_sec_wipe_done_q, init_sec_wipe_done_qq; always_ff @(posedge IO_CLK, negedge IO_RST_N) begin if (!IO_RST_N) begin @@ -219,30 +219,30 @@ module otbn_top_sim ( end end - // Pulse otbn_start for 1 cycle after the initial secure wipe is done. - // Flop `done_o` from otbn_core to match up with model done signal. + // Pulse acc_start for 1 cycle after the initial secure wipe is done. + // Flop `done_o` from acc_core to match up with model done signal. always @(posedge IO_CLK or negedge IO_RST_N) begin if (!IO_RST_N) begin - otbn_start <= 1'b0; - otbn_start_r <= 1'b0; - otbn_start_done <= 1'b0; - otbn_done_r <= 1'b0; - otbn_done_rr <= 1'b0; - otbn_err_bits_r <= '0; - otbn_err_bits_rr <= '0; + acc_start <= 1'b0; + acc_start_r <= 1'b0; + acc_start_done <= 1'b0; + acc_done_r <= 1'b0; + acc_done_rr <= 1'b0; + acc_err_bits_r <= '0; + acc_err_bits_rr <= '0; end else begin - if (!otbn_start_done && init_sec_wipe_done_q) begin - otbn_start <= 1'b1; - otbn_start_done <= 1'b1; - end else if (otbn_start) begin - otbn_start <= 1'b0; + if (!acc_start_done && init_sec_wipe_done_q) begin + acc_start <= 1'b1; + acc_start_done <= 1'b1; + end else if (acc_start) begin + acc_start <= 1'b0; end - otbn_start_r <= otbn_start; - otbn_done_r <= otbn_done; - otbn_done_rr <= otbn_done_r; - otbn_err_bits_r <= otbn_err_bits; - otbn_err_bits_rr <= otbn_err_bits_r; + acc_start_r <= acc_start; + acc_done_r <= acc_done; + acc_done_rr <= acc_done_r; + acc_err_bits_r <= acc_err_bits; + acc_err_bits_rr <= acc_err_bits_r; end end @@ -338,14 +338,14 @@ module otbn_top_sim ( .alert_o ( ) ); - // When OTBN is done let a few more cycles run then finish simulation + // When ACC is done let a few more cycles run then finish simulation logic [1:0] finish_counter; always @(posedge IO_CLK or negedge IO_RST_N) begin if (!IO_RST_N) begin finish_counter <= 2'd0; end else begin - if (otbn_done_r) begin + if (acc_done_r) begin finish_counter <= 2'd1; end @@ -363,29 +363,29 @@ module otbn_top_sim ( // // This runs in parallel with the real core above, with consistency checks between the two. - localparam string DesignScope = "..u_otbn_core"; + localparam string DesignScope = "..u_acc_core"; - err_bits_t otbn_model_err_bits; - bit [31:0] otbn_model_insn_cnt; - bit otbn_model_done_rr; - bit otbn_model_err; + err_bits_t acc_model_err_bits; + bit [31:0] acc_model_insn_cnt; + bit acc_model_done_rr; + bit acc_model_err; - otbn_core_model #( + acc_core_model #( .MemScope ( ".." ), .DesignScope ( DesignScope ) - ) u_otbn_core_model ( + ) u_acc_core_model ( .clk_i ( IO_CLK ), .clk_edn_i ( IO_CLK ), .rst_ni ( IO_RST_N ), .rst_edn_ni ( IO_RST_N ), - .cmd_i ( otbn_pkg::CmdExecute ), - .cmd_en_i ( otbn_start ), + .cmd_i ( acc_pkg::CmdExecute ), + .cmd_en_i ( acc_start ), .lc_escalate_en_i ( lc_ctrl_pkg::Off ), .lc_rma_req_i ( lc_ctrl_pkg::Off ), - .err_bits_o ( otbn_model_err_bits ), + .err_bits_o ( acc_model_err_bits ), .edn_rnd_i ( rnd_rsp ), .edn_rnd_o ( ), @@ -400,13 +400,13 @@ module otbn_top_sim ( .otp_key_cdc_done_i ( 1'b0 ), .status_o ( ), - .insn_cnt_o ( otbn_model_insn_cnt ), + .insn_cnt_o ( acc_model_insn_cnt ), .keymgr_key_i ( keymgr_key), - .done_rr_o ( otbn_model_done_rr ), + .done_rr_o ( acc_model_done_rr ), - .err_o ( otbn_model_err ) + .err_o ( acc_model_err ) ); bit done_mismatch_latched, err_bits_mismatch_latched, cnt_mismatch_latched; @@ -421,29 +421,29 @@ module otbn_top_sim ( end else begin // Check that the 'done_o' output from the RTL matches the 'done_rr_o' output from the model // (with two cycles' delay). - if (otbn_done_rr && !otbn_model_done_rr) begin + if (acc_done_rr && !acc_model_done_rr) begin $display("ERROR: At time %0t, RTL done on previous cycle, but model still busy.", $time); done_mismatch_latched <= 1'b1; end - if (otbn_model_done_rr && !otbn_done_rr) begin + if (acc_model_done_rr && !acc_done_rr) begin $display("ERROR: At time %0t, model finished, but RTL not done in time.", $time); done_mismatch_latched <= 1'b1; end - if (otbn_model_done_rr && otbn_done_rr) begin - if (otbn_err_bits_rr != otbn_model_err_bits) begin - $display("ERROR: At time %0t, otbn_err_bits != otbn_model_err_bits (0x%0x != 0x%0x).", - $time, otbn_err_bits_rr, otbn_model_err_bits); + if (acc_model_done_rr && acc_done_rr) begin + if (acc_err_bits_rr != acc_model_err_bits) begin + $display("ERROR: At time %0t, acc_err_bits != acc_model_err_bits (0x%0x != 0x%0x).", + $time, acc_err_bits_rr, acc_model_err_bits); err_bits_mismatch_latched <= 1'b1; end end - if (insn_cnt != otbn_model_insn_cnt) begin + if (insn_cnt != acc_model_insn_cnt) begin if (!cnt_mismatch_latched) begin - $display("ERROR: At time %0t, insn_cnt != otbn_model_insn_cnt (0x%0x != 0x%0x).", - $time, insn_cnt, otbn_model_insn_cnt); + $display("ERROR: At time %0t, insn_cnt != acc_model_insn_cnt (0x%0x != 0x%0x).", + $time, insn_cnt, acc_model_insn_cnt); end cnt_mismatch_latched <= 1'b1; end - model_err_latched <= model_err_latched | otbn_model_err | loop_warp_model_err; + model_err_latched <= model_err_latched | acc_model_err | loop_warp_model_err; end end @@ -465,10 +465,10 @@ module otbn_top_sim ( end end - // Defined in otbn_top_sim.cc - import "DPI-C" context function int OtbnTopInstallLoopWarps(); - import "DPI-C" context function void OtbnTopApplyLoopWarp(); - import "DPI-C" context function void OtbnTopDumpState(); + // Defined in acc_top_sim.cc + import "DPI-C" context function int AccTopInstallLoopWarps(); + import "DPI-C" context function void AccTopApplyLoopWarp(); + import "DPI-C" context function void AccTopDumpState(); bit warps_installed; always_ff @(negedge IO_CLK or negedge IO_RST_N) begin @@ -476,8 +476,8 @@ module otbn_top_sim ( warps_installed <= 1'b0; end else begin if (!warps_installed) begin - if (OtbnTopInstallLoopWarps() != 0) begin - $display("ERROR: At time %0t, OtbnTopInstallLoopWarps() failed.", $time); + if (AccTopInstallLoopWarps() != 0) begin + $display("ERROR: At time %0t, AccTopInstallLoopWarps() failed.", $time); loop_warp_model_err <= 1'b1; end end @@ -486,49 +486,49 @@ module otbn_top_sim ( end always_ff @(posedge IO_CLK or negedge IO_RST_N) begin if (IO_RST_N) begin - OtbnTopApplyLoopWarp(); + AccTopApplyLoopWarp(); end end always_ff @(negedge IO_CLK or negedge IO_RST_N) begin - if (IO_RST_N && u_otbn_core.u_otbn_controller.start_secure_wipe) begin - // When OTBN starts a secure wipe this indicates the program has either terminated (executed + if (IO_RST_N && u_acc_core.u_acc_controller.start_secure_wipe) begin + // When ACC starts a secure wipe this indicates the program has either terminated (executed // 'ecall') or hit an error, either way the execution is done. The state must be dumped as the // secure wipe is started so we can dump the final execution state not the all zeros state // that will be present once a secure wipe is finished. - OtbnTopDumpState(); + AccTopDumpState(); end end - export "DPI-C" function otbn_base_call_stack_get_size; + export "DPI-C" function acc_base_call_stack_get_size; - function automatic int unsigned otbn_base_call_stack_get_size(); + function automatic int unsigned acc_base_call_stack_get_size(); // Explicit zero extension required because Verilator (tested with v4.216) otherwise raises // a `WIDTH` warning (which is promoted to an error). - return {{(32-$bits(u_otbn_core.u_otbn_rf_base.u_call_stack.stack_wr_ptr)){1'b0}}, - u_otbn_core.u_otbn_rf_base.u_call_stack.stack_wr_ptr}; + return {{(32-$bits(u_acc_core.u_acc_rf_base.u_call_stack.stack_wr_ptr)){1'b0}}, + u_acc_core.u_acc_rf_base.u_call_stack.stack_wr_ptr}; endfunction - export "DPI-C" function otbn_base_call_stack_get_element; + export "DPI-C" function acc_base_call_stack_get_element; - function automatic int unsigned otbn_base_call_stack_get_element(int index); - return u_otbn_core.u_otbn_rf_base.u_call_stack.stack_storage[index][31:0]; + function automatic int unsigned acc_base_call_stack_get_element(int index); + return u_acc_core.u_acc_rf_base.u_call_stack.stack_storage[index][31:0]; endfunction - export "DPI-C" function otbn_base_reg_get; + export "DPI-C" function acc_base_reg_get; - function automatic int unsigned otbn_base_reg_get(int index); - return u_otbn_core.u_otbn_rf_base.gen_rf_base_ff.u_otbn_rf_base_inner.rf_reg[index][31:0]; + function automatic int unsigned acc_base_reg_get(int index); + return u_acc_core.u_acc_rf_base.gen_rf_base_ff.u_acc_rf_base_inner.rf_reg[index][31:0]; endfunction - export "DPI-C" function otbn_bignum_reg_get; + export "DPI-C" function acc_bignum_reg_get; - function automatic int unsigned otbn_bignum_reg_get(int index, int word); - return u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf[index][word*39+:32]; + function automatic int unsigned acc_bignum_reg_get(int index, int word); + return u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf[index][word*39+:32]; endfunction - export "DPI-C" function otbn_err_get; + export "DPI-C" function acc_err_get; - function automatic bit otbn_err_get(); + function automatic bit acc_err_get(); return err_latched; endfunction diff --git a/hw/ip/acc/dv/verilator/acc_top_sim_waivers.vlt b/hw/ip/acc/dv/verilator/acc_top_sim_waivers.vlt new file mode 100644 index 00000000000..8527776d56c --- /dev/null +++ b/hw/ip/acc/dv/verilator/acc_top_sim_waivers.vlt @@ -0,0 +1,28 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +lint_off -rule WIDTH -file "*/acc_top_sim.sv" -match "*'ImemStartAddr' generates 32 bits*" +lint_off -rule WIDTH -file "*/acc_top_sim.sv" -match "*'stack_wr_ptr_q' generates 4 bits*" + +// Mark some signals in the loop controller as public. These are used +// by the AccTopApplyLoopWarp() function in acc_top_sim.cc +public -module "acc_loop_controller" -var "insn_addr_i" +public -module "acc_loop_controller" -var "loop_start_req_i" +public -module "acc_loop_controller" -var "loop_start_commit_i" +public -module "acc_loop_controller" -var "loop_iterations_i" +public -module "acc_loop_controller" -var "current_loop_valid" +public -module "acc_loop_controller" -var "current_loop" +public -module "acc_loop_controller" -var "current_loop_finish" +public -module "acc_loop_controller" -var "loop_stack_rd_idx" +public -module "acc_loop_controller" -var "prefetch_loop_iterations_o" +public -module "prim_count" -var "max_val" +public -module "prim_count" -var "down_cnt" +public -module "prim_flop" -var "d_i" + +// Mark the "model_handle" variable in the core model as public. We +// use this to pass the information from the ELF file to the ISS on +// the first call to AccTopApplyLoopWarp() in acc_top_sim.cc. +public -module "acc_core_model" -var "model_handle" diff --git a/hw/ip/otbn/dv/verilator/run-some.py b/hw/ip/acc/dv/verilator/run-some.py similarity index 93% rename from hw/ip/otbn/dv/verilator/run-some.py rename to hw/ip/acc/dv/verilator/run-some.py index e5aa69cb1fe..90fbe81756b 100755 --- a/hw/ip/otbn/dv/verilator/run-some.py +++ b/hw/ip/acc/dv/verilator/run-some.py @@ -9,9 +9,9 @@ run-some.py --size=1500 --count=10 XXX -which will generate 10 OTBN binaries, each with up to 1500 instructions in -their respective traces. It will also build a Verilated model of OTBN (using -otbn_top_sim) and run the model on each binary. +which will generate 10 ACC binaries, each with up to 1500 instructions in +their respective traces. It will also build a Verilated model of ACC (using +acc_top_sim) and run the model on each binary. ''' @@ -90,10 +90,10 @@ def write_ninja(handle: TextIO, handle.write('rule fusesoc\n' f' command = fusesoc --cores-root={projdir_from_destdir} ' 'run --target=sim --setup --build ' - '--mapping=lowrisc:prim_generic:all:0.1 lowrisc:ip:otbn_top_sim ' + '--mapping=lowrisc:prim_generic:all:0.1 lowrisc:ip:acc_top_sim ' '>fusesoc.log 2>&1\n\n') - handle.write('tb = build/lowrisc_ip_otbn_top_sim_0.1/' - 'sim-verilator/Votbn_top_sim\n\n') + handle.write('tb = build/lowrisc_ip_acc_top_sim_0.1/' + 'sim-verilator/Vacc_top_sim\n\n') handle.write('build $tb: fusesoc\n\n') # Collect up all the generated files diff --git a/hw/ip/otbn/lint/otbn.vlt b/hw/ip/acc/lint/acc.vlt similarity index 71% rename from hw/ip/otbn/lint/otbn.vlt rename to hw/ip/acc/lint/acc.vlt index 5890fcd56f9..77b0316cb31 100644 --- a/hw/ip/otbn/lint/otbn.vlt +++ b/hw/ip/acc/lint/acc.vlt @@ -6,14 +6,14 @@ // Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 3 // bits. -lint_off -rule WIDTH -file "*/rtl/otbn_lsu.sv" -match "*'addr' generates 3 bits*" +lint_off -rule WIDTH -file "*/rtl/acc_lsu.sv" -match "*'addr' generates 3 bits*" -lint_off -rule UNUSED -file "*/rtl/otbn_decoder.sv" -match "Bits of signal are not used: 'insn_alu'[24:15,11:7]" +lint_off -rule UNUSED -file "*/rtl/acc_decoder.sv" -match "Bits of signal are not used: 'insn_alu'[24:15,11:7]" // imem_wmask_bus is only used in an assertion (which Verilator doesn't see). -lint_off -rule UNUSED -file "*/rtl/otbn.sv" -match "Signal is not used: 'imem_wmask_bus'" +lint_off -rule UNUSED -file "*/rtl/acc.sv" -match "Signal is not used: 'imem_wmask_bus'" -split_var -module "otbn_controller" -var "err_bits" +split_var -module "acc_controller" -var "err_bits" // Without some hints, Verilator's conservative combo-loop detection check flags a combinational // loop caused by the fact that a requested secure wipe appears as the "stop" signal in the module. @@ -23,9 +23,9 @@ split_var -module "otbn_controller" -var "err_bits" // // Break the apparent loop by telling Verilator to factor the writes to sec_wipe_base_o into their // own always_comb block, which will not depend on the stop signal. -isolate_assignments -module "otbn_start_stop_control" -var "sec_wipe_base_o" +isolate_assignments -module "acc_start_stop_control" -var "sec_wipe_base_o" // This is an analogous problem, where a secure wipe request feeds into the always_comb block that // can write to state_error_d (when state_q is invalid), which then (correctly) feeds into an error // condition that can start a secure wipe. -isolate_assignments -module "otbn_start_stop_control" -var "state_error_d" +isolate_assignments -module "acc_start_stop_control" -var "state_error_d" diff --git a/hw/ip/otbn/lint/otbn.waiver b/hw/ip/acc/lint/acc.waiver similarity index 52% rename from hw/ip/otbn/lint/otbn.waiver rename to hw/ip/acc/lint/acc.waiver index d9f7b88f767..f8f7ad4d319 100644 --- a/hw/ip/otbn/lint/otbn.waiver +++ b/hw/ip/acc/lint/acc.waiver @@ -2,43 +2,43 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for otbn +# waiver file for acc -waive -rules {IFDEF_CODE} -location {otbn.sv} \ - -regexp {'otbn_core' instance 'u_otbn_core' contained within `else block} \ +waive -rules {IFDEF_CODE} -location {acc.sv} \ + -regexp {'acc_core' instance 'u_acc_core' contained within `else block} \ -comment {It's true, and expected.} -waive -rules {CLOCK_USE RESET_USE} -location {otbn_core.sv} \ - -regexp {'(clk_i|rst_ni)' is connected to 'otbn_decoder'} \ +waive -rules {CLOCK_USE RESET_USE} -location {acc_core.sv} \ + -regexp {'(clk_i|rst_ni)' is connected to 'acc_decoder'} \ -comment {The module is fully combinatorial, clk/rst are only used for assertions.} -waive -rules {CLOCK_USE RESET_USE} -location {otbn_core.sv} \ - -regexp {'(clk_i|rst_ni)' is connected to 'otbn_lsu'} \ +waive -rules {CLOCK_USE RESET_USE} -location {acc_core.sv} \ + -regexp {'(clk_i|rst_ni)' is connected to 'acc_lsu'} \ -comment {The module is fully combinatorial, clk/rst are only used for assertions.} -waive -rules {CLOCK_USE RESET_USE} -location {otbn_core.sv} \ - -regexp {'(clk_i|rst_ni)' is connected to 'otbn_alu_base'} \ +waive -rules {CLOCK_USE RESET_USE} -location {acc_core.sv} \ + -regexp {'(clk_i|rst_ni)' is connected to 'acc_alu_base'} \ -comment {The module is fully combinatorial, clk/rst are only used for assertions.} -waive -rules {RESET_USE} -location {otbn_core.sv} \ - -regexp {'rst_ni' is connected to 'otbn_instruction_fetch'} \ +waive -rules {RESET_USE} -location {acc_core.sv} \ + -regexp {'rst_ni' is connected to 'acc_instruction_fetch'} \ -comment {The only flop in this module is not reset.} -waive -rules {ONE_BRANCH} -location {otbn_decoder.sv} \ +waive -rules {ONE_BRANCH} -location {acc_decoder.sv} \ -comment {For consistency in the decoder some case statements have only one branch.} -waive -rules {HIER_NET_NOT_READ NOT_READ} -location {otbn.sv} \ +waive -rules {HIER_NET_NOT_READ NOT_READ} -location {acc.sv} \ -regexp {(Net|Signal) 'imem_wmask_bus' is not read from} \ -comment {Signal is used in an assertion.} -waive -rules {CLOCK_USE RESET_USE} -location {otbn_alu_bignum.sv otbn_rf_bignum_ff.sv otbn_core.sv} \ - -regexp {'(clk_i|rst_ni)' is connected to '(prim_onehot_mux|otbn_mac_bignum)' port} \ +waive -rules {CLOCK_USE RESET_USE} -location {acc_alu_bignum.sv acc_rf_bignum_ff.sv acc_core.sv} \ + -regexp {'(clk_i|rst_ni)' is connected to '(prim_onehot_mux|acc_mac_bignum)' port} \ -comment {The module is fully combinatorial, clk/rst are only used for assertions.} -waive -rules {CLOCK_USE RESET_USE} -location {otbn_instruction_fetch.sv} \ - -regexp {'(clk_i|rst_ni)' is connected to 'otbn_predecode' port} \ +waive -rules {CLOCK_USE RESET_USE} -location {acc_instruction_fetch.sv} \ + -regexp {'(clk_i|rst_ni)' is connected to 'acc_predecode' port} \ -comment {The module is fully combinatorial, clk/rst are only used for assertions.} -waive -rules {ONE_BIT_MEM_WIDTH} -location {otbn_alu_bignum.sv} \ +waive -rules {ONE_BIT_MEM_WIDTH} -location {acc_alu_bignum.sv} \ -msg {Memory 'flag_mux_in' has word width which is single bit wide} \ -comment {The in_i input of prim_onehot_mux has an unpacked and a packed dimension where in this particular case the latter is 1.} diff --git a/hw/ip/otbn/pre_sca/alma/README.md b/hw/ip/acc/pre_sca/alma/README.md similarity index 76% rename from hw/ip/otbn/pre_sca/alma/README.md rename to hw/ip/acc/pre_sca/alma/README.md index 82c84c33488..ebda4ee75f5 100644 --- a/hw/ip/otbn/pre_sca/alma/README.md +++ b/hw/ip/acc/pre_sca/alma/README.md @@ -1,6 +1,6 @@ -# OTBN Formal Masking Verification Using Alma +# ACC Formal Masking Verification Using Alma -This directory contains support files to formally verify the OTBN core using the +This directory contains support files to formally verify the ACC core using the tool [Alma: Execution-aware Masking Verification](https://github.com/IAIK/coco-alma). @@ -12,9 +12,9 @@ Verilator 4.106 (2020-12-02 rev v4.106). Other tool versions might not be compatible. 1. Download the Alma tool from this specific repo and check out to the - `coco-otbn-latest` branch of the tool + `coco-acc-latest` branch of the tool ```sh - git clone git@github.com:abdullahvarici/coco-alma.git -b coco-otbn-latest + git clone git@github.com:abdullahvarici/coco-alma.git -b coco-acc-latest ``` Enter the directory using ```sh @@ -29,7 +29,7 @@ compatible. ```sh pip3 install -r requirements.txt ``` - Update `examples/otbn/config.json` to point correct locations for `asm`, + Update `examples/acc/config.json` to point correct locations for `asm`, `objdump` and `rv_objdump`. 1. Generate a Verilog netlist @@ -37,7 +37,7 @@ compatible. A netlist of the DUT can be generated using the Yosys synthesis flow from the OpenTitan repository. From the OpenTitan top level, run ```sh - cd hw/ip/otbn/pre_syn + cd hw/ip/acc/pre_syn ``` Set up the synthesis flow as described in the corresponding README. Then run the synthesis @@ -45,9 +45,9 @@ compatible. ./syn_yosys.sh ``` -## Formally verifying the masking of the OTBN core +## Formally verifying the masking of the ACC core -After downloading the Alma tool, installing dependencies and synthesizing OTBN, +After downloading the Alma tool, installing dependencies and synthesizing ACC, the masking can finally be formally verified. 1. Enter the directory where you have downloaded Alma and load the virtual @@ -66,11 +66,11 @@ the masking can finally be formally verified. the netlist. For simplicity, a single script is provided to launch all the required steps with a single command. Simply run: ```sh - ${REPO_TOP}/hw/ip/otbn/pre_sca/alma/verify_otbn.sh + ${REPO_TOP}/hw/ip/acc/pre_sca/alma/verify_acc.sh ``` This should produce output similar to the one below: ```sh - Verifying OTBN using Alma + Verifying ACC using Alma Starting yosys synthesis... | CircuitGraph | Total: 234238 | Linear: 22351 | Non-linear: 107502 | Registers: 21338 | Mux: 41352 | parse.py successful (755.32s) @@ -84,11 +84,11 @@ the masking can finally be formally verified. 2: Compiling verilated netlist library 3: Compiling provided verilator testbench 4: Simulating circuit and generating VCD - Line 0: WDR label found - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf [7800] = secret 0 - Line 1: WDR label found - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf [7488] = secret 0 - Line 2: WDR label found - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf [7176] = secret 1 - Line 3: WDR label found - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf [6864] = secret 1 - Line 4: WDR label found - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf [6552] = static_random + Line 0: WDR label found - u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf [7800] = secret 0 + Line 1: WDR label found - u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf [7488] = secret 0 + Line 2: WDR label found - u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf [7176] = secret 1 + Line 3: WDR label found - u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf [6864] = secret 1 + Line 4: WDR label found - u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf [6552] = static_random | CircuitGraph | Total: 234238 | Linear: 22351 | Non-linear: 107502 | Registers: 21338 | Mux: 41352 | 0 nodes are ignored. tmp/circuit.vcd:57091: [WARNING] Entry for name clk_sys already exists in namemap (clk_sys -> #33) @@ -130,12 +130,12 @@ the masking can finally be formally verified. The execution is not secure, here are some leaks: leak 0: (cycle: 3, cell: mux _10580_[0], id: 223382) 3 stable mux _10580_[0] vars : ['s0:0', 's0:1'] - 3 stable mux _10580_[0] signals: u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf[7800] ^ u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf[7488] + 3 stable mux _10580_[0] signals: u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf[7800] ^ u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf[7488] ``` ## Individual steps in detail -Below we outline the individual steps performed by the `verify_otbn.sh` script. +Below we outline the individual steps performed by the `verify_acc.sh` script. This is useful if you, e.g., want to verify the masking of your own module. For more details, please refer to the [Alma @@ -149,17 +149,17 @@ tutorial](https://github.com/IAIK/coco-alma/tree/hw-verif#usage) 1. The first step involves the parsing of the synthesized netlist. ```sh - python3 parse.py --keep --top-module otbn_top_coco --log-yosys \ - --source ${REPO_TOP}/hw/ip/otbn/pre_sca/alma/rtl/ram_1p.v \ - ${REPO_TOP}/hw/ip/otbn/pre_syn/syn_out/latest/generated/otbn_core.alma.v \ - ${REPO_TOP}/hw/ip/otbn/pre_sca/alma/rtl/otbn_top_coco.v + python3 parse.py --keep --top-module acc_top_coco --log-yosys \ + --source ${REPO_TOP}/hw/ip/acc/pre_sca/alma/rtl/ram_1p.v \ + ${REPO_TOP}/hw/ip/acc/pre_syn/syn_out/latest/generated/acc_core.alma.v \ + ${REPO_TOP}/hw/ip/acc/pre_sca/alma/rtl/acc_top_coco.v ``` 1. Next, run the `assemble.py` script to generate memory initialization file for - OTBN. + ACC. ```sh program=isw_and - cd examples/otbn + cd examples/acc python3 assemble.py --program programs/${program}.S \ --netlist ../../tmp/circuit.v cd ../../ @@ -182,15 +182,15 @@ tutorial](https://github.com/IAIK/coco-alma/tree/hw-verif#usage) It is pretty tedious to compute the actual indices for bignum register file labels. Generate it with the following command: ```sh - examples/otbn/labels/generate_bignum_rf_labels.py \ - -i examples/otbn/labels/${program}_labels.txt \ + examples/acc/labels/generate_bignum_rf_labels.py \ + -i examples/acc/labels/${program}_labels.txt \ -o tmp/labels_updated.txt -w 1 -s 0 ``` 1. Finally the verification of the masking implementation can be started. ```sh python3 verify.py --json tmp/circuit.json \ - --top-module otbn_top_coco \ + --top-module acc_top_coco \ --label tmp/labels_updated.txt \ --vcd tmp/circuit.vcd \ --checking-mode per-location \ @@ -198,8 +198,8 @@ tutorial](https://github.com/IAIK/coco-alma/tree/hw-verif#usage) --rst-phase 0 \ --rst-cycles 2 \ --init-delay 139 \ - --excluded-signals u_otbn_core.u_otbn_controller.rf_bignum_intg_err_i[0] \ - --dbg-signals otbn_cycle_cnt_o \ + --excluded-signals u_acc_core.u_acc_controller.rf_bignum_intg_err_i[0] \ + --dbg-signals acc_cycle_cnt_o \ --cycles 25 \ --mode stable ``` diff --git a/hw/ip/otbn/pre_sca/alma/rtl/otbn_top_coco.v b/hw/ip/acc/pre_sca/alma/rtl/acc_top_coco.v similarity index 80% rename from hw/ip/otbn/pre_sca/alma/rtl/otbn_top_coco.v rename to hw/ip/acc/pre_sca/alma/rtl/acc_top_coco.v index f9fda5d211b..9391231a37c 100644 --- a/hw/ip/otbn/pre_sca/alma/rtl/otbn_top_coco.v +++ b/hw/ip/acc/pre_sca/alma/rtl/acc_top_coco.v @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module otbn_top_coco #( +module acc_top_coco #( // Instruction data width parameter ImemDataWidth = 39, // Data path width for BN (wide) instructions, in bits. @@ -19,7 +19,7 @@ module otbn_top_coco #( input [WLEN-1:0] edn_urnd_data_i, input [SideloadKeyWidth-1:0] sideload_key_share_0_i, input [SideloadKeyWidth-1:0] sideload_key_share_1_i, - output [31:0] otbn_cycle_cnt_o + output [31:0] acc_cycle_cnt_o ); // Size of the instruction memory, in bytes localparam ImemSizeByte = 128*4; //32'h1000; @@ -56,10 +56,10 @@ module otbn_top_coco #( // Data memory adress width localparam DmemAddrWidth = vbits(DmemSizeByte); - reg otbn_start; - // Intialise otbn_start_done to 1 so that we only signal otbn_start after we have seen a reset. If - // you don't do this, we start OTBN before the reset, which can generate confusing trace messages. - reg otbn_start_done = 1'b1; + reg acc_start; + // Intialise acc_start_done to 1 so that we only signal acc_start after we have seen a reset. If + // you don't do this, we start ACC before the reset, which can generate confusing trace messages. + reg acc_start_done = 1'b1; wire secure_wipe_running; // Instruction memory (IMEM) signals @@ -90,11 +90,11 @@ module otbn_top_coco #( localparam [3:0] MuBi4False = 4'h9; - otbn_core u_otbn_core ( + acc_core u_acc_core ( .clk_i (clk_sys), .rst_ni(rst_sys_n), - .start_i (otbn_start), + .start_i (acc_start), .done_o (), .locking_o (), .secure_wipe_running_o(secure_wipe_running), @@ -145,10 +145,10 @@ module otbn_top_coco #( .sideload_key_shares_valid_i(2'b11) ); - // Track when OTBN is done with its initial secure wipe of the internal state. We use this to - // wait for the OTBN core to complete the initial secure wipe before we send it the start signal. + // Track when ACC is done with its initial secure wipe of the internal state. We use this to + // wait for the ACC core to complete the initial secure wipe before we send it the start signal. // Also keep a delayed copy of the done signal. This is necessary to align with the status of - // OTBN and the model, which lags one cycle behind the completion of the OTBN core. + // ACC and the model, which lags one cycle behind the completion of the ACC core. reg init_sec_wipe_done_q; always @(posedge clk_sys, negedge rst_sys_n) begin if (!rst_sys_n) begin @@ -160,37 +160,37 @@ module otbn_top_coco #( end end - // Pulse otbn_start for 1 cycle after the initial secure wipe is done. - // Flop `done_o` from otbn_core to match up with model done signal. + // Pulse acc_start for 1 cycle after the initial secure wipe is done. + // Flop `done_o` from acc_core to match up with model done signal. always @(posedge clk_sys or negedge rst_sys_n) begin if (!rst_sys_n) begin - otbn_start <= 1'b0; - otbn_start_done <= 1'b0; + acc_start <= 1'b0; + acc_start_done <= 1'b0; end else begin - if (!otbn_start_done && init_sec_wipe_done_q) begin - otbn_start <= 1'b1; - otbn_start_done <= 1'b1; - end else if (otbn_start) begin - otbn_start <= 1'b0; + if (!acc_start_done && init_sec_wipe_done_q) begin + acc_start <= 1'b1; + acc_start_done <= 1'b1; + end else if (acc_start) begin + acc_start <= 1'b0; end end end - // OTBN cycle counter to easily inspect waves and associate those waves with COCO-ALMA tool + // ACC cycle counter to easily inspect waves and associate those waves with COCO-ALMA tool // output. The counter is reset with the start pulse being sent. - reg [31:0] otbn_cycle_cnt_q; + reg [31:0] acc_cycle_cnt_q; always @(posedge clk_sys or negedge rst_sys_n) begin if (!rst_sys_n) begin - otbn_cycle_cnt_q <= 32'b0; + acc_cycle_cnt_q <= 32'b0; end else begin - if (otbn_start) begin - otbn_cycle_cnt_q <= 32'b0; - end else if (otbn_start_done) begin - otbn_cycle_cnt_q <= otbn_cycle_cnt_q + 1; + if (acc_start) begin + acc_cycle_cnt_q <= 32'b0; + end else if (acc_start_done) begin + acc_cycle_cnt_q <= acc_cycle_cnt_q + 1; end end end - assign otbn_cycle_cnt_o = otbn_cycle_cnt_q; + assign acc_cycle_cnt_o = acc_cycle_cnt_q; localparam DmemSizeWords = DmemSizeByte / (WLEN / 8); localparam DmemIndexWidth = vbits(DmemSizeWords); diff --git a/hw/ip/otbn/pre_sca/alma/rtl/ram_1p.v b/hw/ip/acc/pre_sca/alma/rtl/ram_1p.v similarity index 100% rename from hw/ip/otbn/pre_sca/alma/rtl/ram_1p.v rename to hw/ip/acc/pre_sca/alma/rtl/ram_1p.v diff --git a/hw/ip/otbn/pre_sca/alma/verify_otbn.sh b/hw/ip/acc/pre_sca/alma/verify_acc.sh similarity index 55% rename from hw/ip/otbn/pre_sca/alma/verify_otbn.sh rename to hw/ip/acc/pre_sca/alma/verify_acc.sh index 55ea4178013..5390fa5c5eb 100755 --- a/hw/ip/otbn/pre_sca/alma/verify_otbn.sh +++ b/hw/ip/acc/pre_sca/alma/verify_acc.sh @@ -3,19 +3,19 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# Script to formally verify the masking of the OTBN using Alma. +# Script to formally verify the masking of the ACC using Alma. -echo "Verifying OTBN using Alma" +echo "Verifying ACC using Alma" # Parse -python3 parse.py --keep --top-module otbn_top_coco --log-yosys \ - --source ${REPO_TOP}/hw/ip/otbn/pre_sca/alma/rtl/ram_1p.v \ - ${REPO_TOP}/hw/ip/otbn/pre_syn/syn_out/latest/generated/otbn_core.alma.v \ - ${REPO_TOP}/hw/ip/otbn/pre_sca/alma/rtl/otbn_top_coco.v +python3 parse.py --keep --top-module acc_top_coco --log-yosys \ + --source ${REPO_TOP}/hw/ip/acc/pre_sca/alma/rtl/ram_1p.v \ + ${REPO_TOP}/hw/ip/acc/pre_syn/syn_out/latest/generated/acc_core.alma.v \ + ${REPO_TOP}/hw/ip/acc/pre_sca/alma/rtl/acc_top_coco.v # Assemble the program program=isw_and -cd examples/otbn || exit +cd examples/acc || exit python3 assemble.py --program programs/${program}.S \ --netlist ../../tmp/circuit.v cd ../../ || exit @@ -27,13 +27,13 @@ python3 trace.py --testbench tmp/verilator_tb.c \ --make-jobs 16 # Generate bignum register file labels -examples/otbn/labels/generate_bignum_rf_labels.py \ - -i examples/otbn/labels/${program}_labels.txt \ +examples/acc/labels/generate_bignum_rf_labels.py \ + -i examples/acc/labels/${program}_labels.txt \ -o tmp/labels_updated.txt -w 1 -s 0 # Verify python3 verify.py --json tmp/circuit.json \ - --top-module otbn_top_coco \ + --top-module acc_top_coco \ --label tmp/labels_updated.txt \ --vcd tmp/circuit.vcd \ --checking-mode per-location \ @@ -41,7 +41,7 @@ python3 verify.py --json tmp/circuit.json \ --rst-phase 0 \ --rst-cycles 2 \ --init-delay 139 \ - --excluded-signals u_otbn_core.u_otbn_controller.rf_bignum_intg_err_i[0] \ - --dbg-signals otbn_cycle_cnt_o \ + --excluded-signals u_acc_core.u_acc_controller.rf_bignum_intg_err_i[0] \ + --dbg-signals acc_cycle_cnt_o \ --cycles 25 \ --mode stable diff --git a/hw/ip/otbn/pre_syn/.gitignore b/hw/ip/acc/pre_syn/.gitignore similarity index 100% rename from hw/ip/otbn/pre_syn/.gitignore rename to hw/ip/acc/pre_syn/.gitignore diff --git a/hw/ip/otbn/pre_syn/README.md b/hw/ip/acc/pre_syn/README.md similarity index 100% rename from hw/ip/otbn/pre_syn/README.md rename to hw/ip/acc/pre_syn/README.md diff --git a/hw/ip/otbn/pre_syn/otbn.nangate.sdc b/hw/ip/acc/pre_syn/acc.nangate.sdc similarity index 100% rename from hw/ip/otbn/pre_syn/otbn.nangate.sdc rename to hw/ip/acc/pre_syn/acc.nangate.sdc diff --git a/hw/ip/otbn/pre_syn/otbn_abc.nangate.sdc b/hw/ip/acc/pre_syn/acc_abc.nangate.sdc similarity index 100% rename from hw/ip/otbn/pre_syn/otbn_abc.nangate.sdc rename to hw/ip/acc/pre_syn/acc_abc.nangate.sdc diff --git a/hw/ip/otbn/pre_syn/otbn_lr_synth_conf.tcl b/hw/ip/acc/pre_syn/acc_lr_synth_conf.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/otbn_lr_synth_conf.tcl rename to hw/ip/acc/pre_syn/acc_lr_synth_conf.tcl diff --git a/hw/ip/otbn/pre_syn/python b/hw/ip/acc/pre_syn/python similarity index 100% rename from hw/ip/otbn/pre_syn/python rename to hw/ip/acc/pre_syn/python diff --git a/hw/ip/otbn/pre_syn/syn_setup.example.sh b/hw/ip/acc/pre_syn/syn_setup.example.sh similarity index 93% rename from hw/ip/otbn/pre_syn/syn_setup.example.sh rename to hw/ip/acc/pre_syn/syn_setup.example.sh index e13107c0a9c..5e3c2ccf628 100644 --- a/hw/ip/otbn/pre_syn/syn_setup.example.sh +++ b/hw/ip/acc/pre_syn/syn_setup.example.sh @@ -7,9 +7,9 @@ # Setup IP name and top module. # When changing the top module, some parameters might not exist and # tcl/yosys_run_synth.tcl might need to be adjusted accordingly. -# Known working top modules are: otbn_core, otbn -export LR_SYNTH_IP_NAME=otbn -export LR_SYNTH_TOP_MODULE=otbn_core +# Known working top modules are: acc_core, acc +export LR_SYNTH_IP_NAME=acc +export LR_SYNTH_TOP_MODULE=acc_core # Setup module parameters. export LR_SYNTH_IMEM_SIZE_BYTE=4096 diff --git a/hw/ip/otbn/pre_syn/syn_yosys.sh b/hw/ip/acc/pre_syn/syn_yosys.sh similarity index 98% rename from hw/ip/otbn/pre_syn/syn_yosys.sh rename to hw/ip/acc/pre_syn/syn_yosys.sh index 07e4d865d9c..f7ec2abe5f9 100755 --- a/hw/ip/otbn/pre_syn/syn_yosys.sh +++ b/hw/ip/acc/pre_syn/syn_yosys.sh @@ -166,7 +166,7 @@ for file in "$LR_SYNTH_SRC_DIR"/rtl/*.sv; do # Remove the StateEnumT parameter from prim_sparse_fsm_flop instances. Yosys doesn't seem to # support this. sed -i '/\.StateEnumT(logic \[.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v - sed -i '/\.StateEnumT_otbn_pkg.*Width.*(.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v + sed -i '/\.StateEnumT_acc_pkg.*Width.*(.*/d' $LR_SYNTH_OUT_DIR/generated/${module}.v done #------------------------------------------------------------------------- diff --git a/hw/ip/otbn/pre_syn/tcl/flow_utils.tcl b/hw/ip/acc/pre_syn/tcl/flow_utils.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/flow_utils.tcl rename to hw/ip/acc/pre_syn/tcl/flow_utils.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/lr_synth_flow_var_setup.tcl b/hw/ip/acc/pre_syn/tcl/lr_synth_flow_var_setup.tcl similarity index 96% rename from hw/ip/otbn/pre_syn/tcl/lr_synth_flow_var_setup.tcl rename to hw/ip/acc/pre_syn/tcl/lr_synth_flow_var_setup.tcl index 660c133ade8..ceccb8ee4ef 100644 --- a/hw/ip/otbn/pre_syn/tcl/lr_synth_flow_var_setup.tcl +++ b/hw/ip/acc/pre_syn/tcl/lr_synth_flow_var_setup.tcl @@ -8,8 +8,8 @@ puts "=================== Flow Vars ===================" # function (see flow_utils.tcl) - variable name - default value set_flow_var cell_library_path "cmos_cells.lib" "Path to cell library" -set_flow_var ip_name "otbn" "IP name" -set_flow_var top_module "otbn_core" "top module" +set_flow_var ip_name "acc" "IP name" +set_flow_var top_module "acc_core" "top module" set_flow_var out_dir "syn_out" "Output directory for synthesis" set_flow_var pre_map_out "./${lr_synth_out_dir}/generated/${lr_synth_top_module}.pre_map.v" "Pre-mapping netlist out" set_flow_var alma_out "./${lr_synth_out_dir}/generated/${lr_synth_top_module}.alma.v" "Alma netlist out for pre-silicon SCA verification" diff --git a/hw/ip/otbn/pre_syn/tcl/sta_common.tcl b/hw/ip/acc/pre_syn/tcl/sta_common.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/sta_common.tcl rename to hw/ip/acc/pre_syn/tcl/sta_common.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/sta_open_design.tcl b/hw/ip/acc/pre_syn/tcl/sta_open_design.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/sta_open_design.tcl rename to hw/ip/acc/pre_syn/tcl/sta_open_design.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/sta_run_reports.tcl b/hw/ip/acc/pre_syn/tcl/sta_run_reports.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/sta_run_reports.tcl rename to hw/ip/acc/pre_syn/tcl/sta_run_reports.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/sta_utils.tcl b/hw/ip/acc/pre_syn/tcl/sta_utils.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/sta_utils.tcl rename to hw/ip/acc/pre_syn/tcl/sta_utils.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/yosys_common.tcl b/hw/ip/acc/pre_syn/tcl/yosys_common.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/yosys_common.tcl rename to hw/ip/acc/pre_syn/tcl/yosys_common.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/yosys_post_synth.tcl b/hw/ip/acc/pre_syn/tcl/yosys_post_synth.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/yosys_post_synth.tcl rename to hw/ip/acc/pre_syn/tcl/yosys_post_synth.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/yosys_pre_map.tcl b/hw/ip/acc/pre_syn/tcl/yosys_pre_map.tcl similarity index 100% rename from hw/ip/otbn/pre_syn/tcl/yosys_pre_map.tcl rename to hw/ip/acc/pre_syn/tcl/yosys_pre_map.tcl diff --git a/hw/ip/otbn/pre_syn/tcl/yosys_run_synth.tcl b/hw/ip/acc/pre_syn/tcl/yosys_run_synth.tcl similarity index 98% rename from hw/ip/otbn/pre_syn/tcl/yosys_run_synth.tcl rename to hw/ip/acc/pre_syn/tcl/yosys_run_synth.tcl index ea79e7be352..e6011570814 100644 --- a/hw/ip/otbn/pre_syn/tcl/yosys_run_synth.tcl +++ b/hw/ip/acc/pre_syn/tcl/yosys_run_synth.tcl @@ -17,7 +17,7 @@ if { $lr_synth_timing_run } { yosys "read_verilog -sv $lr_synth_out_dir/generated/*.v" # Set top-module parameters. -if { $lr_synth_top_module == "otbn_core" } { +if { $lr_synth_top_module == "acc_core" } { yosys "chparam -set ImemSizeByte $lr_synth_imem_size_byte $lr_synth_top_module" yosys "chparam -set DmemSizeByte $lr_synth_dmem_size_byte $lr_synth_top_module" } diff --git a/hw/ip/otbn/pre_syn/translate_timing_rpts.sh b/hw/ip/acc/pre_syn/translate_timing_rpts.sh similarity index 100% rename from hw/ip/otbn/pre_syn/translate_timing_rpts.sh rename to hw/ip/acc/pre_syn/translate_timing_rpts.sh diff --git a/hw/ip/otbn/rtl/otbn.sv b/hw/ip/acc/rtl/acc.sv similarity index 82% rename from hw/ip/otbn/rtl/otbn.sv rename to hw/ip/acc/rtl/acc.sv index 98d0a604a02..577cc1b5b71 100644 --- a/hw/ip/otbn/rtl/otbn.sv +++ b/hw/ip/acc/rtl/acc.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -13,19 +13,19 @@ `include "prim_fifo_assert.svh" /** - * OpenTitan Big Number Accelerator (OTBN) + * OpenTitan Big Number Accelerator (ACC) */ -module otbn +module acc import prim_alert_pkg::*; - import otbn_pkg::*; - import otbn_reg_pkg::*; + import acc_pkg::*; + import acc_reg_pkg::*; #( parameter bit Stub = 1'b0, parameter regfile_e RegFile = RegFileFF, parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b0, + parameter bit AccPQCEn = 1'b0, // Number of cycles a differential skew is tolerated on the alert signal parameter int unsigned AlertSkewCycles = 1, @@ -39,8 +39,8 @@ module otbn parameter bit SecSkipUrndReseedAtStart = 1'b0, // Default seed and nonce for scrambling - parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnKey = RndCnstOtbnKeyDefault, - parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnNonce = RndCnstOtbnNonceDefault + parameter otp_ctrl_pkg::acc_key_t RndCnstAccKey = RndCnstAccKeyDefault, + parameter otp_ctrl_pkg::acc_nonce_t RndCnstAccNonce = RndCnstAccNonceDefault ) ( input clk_i, input rst_ni, @@ -82,9 +82,9 @@ module otbn // Key request to OTP (running on clk_fixed) input clk_otp_i, input rst_otp_ni, - output otp_ctrl_pkg::otbn_otp_key_req_t otbn_otp_key_o, - input otp_ctrl_pkg::otbn_otp_key_rsp_t otbn_otp_key_i, - input keymgr_pkg::otbn_key_req_t keymgr_key_i, + output otp_ctrl_pkg::acc_otp_key_req_t acc_otp_key_o, + input otp_ctrl_pkg::acc_otp_key_rsp_t acc_otp_key_i, + input keymgr_pkg::acc_key_req_t keymgr_key_i, // KMAC interface output kmac_pkg::app_req_t kmac_data_o, @@ -97,19 +97,19 @@ module otbn logic rst_n; // hold module in reset permanently when stubbing - if (Stub) begin : gen_stub_otbn + if (Stub) begin : gen_stub_acc assign rst_n = 1'b0; - end else begin : gen_real_otbn + end else begin : gen_real_acc assign rst_n = rst_ni; end - // The OTBN_*_SIZE parameters are auto-generated by regtool and come from the bus window sizes; + // The ACC_*_SIZE parameters are auto-generated by regtool and come from the bus window sizes; // they are given in bytes and must be powers of two. // - // DMEM is actually a bit bigger than OTBN_DMEM_SIZE: there are an extra DmemScratchSizeByte bytes + // DMEM is actually a bit bigger than ACC_DMEM_SIZE: there are an extra DmemScratchSizeByte bytes // that aren't accessible over the bus. - localparam int ImemSizeByte = int'(otbn_reg_pkg::OTBN_IMEM_SIZE); - localparam int DmemSizeByte = int'(otbn_reg_pkg::OTBN_DMEM_SIZE + DmemScratchSizeByte); + localparam int ImemSizeByte = int'(acc_reg_pkg::ACC_IMEM_SIZE); + localparam int DmemSizeByte = int'(acc_reg_pkg::ACC_DMEM_SIZE + DmemScratchSizeByte); localparam int ImemAddrWidth = vbits(ImemSizeByte); localparam int DmemAddrWidth = vbits(DmemSizeByte); @@ -139,16 +139,16 @@ module otbn logic err_bits_en; // ERR_BITS register should be cleared due to a write request from the host processor - // when OTBN is not running. + // when ACC is not running. logic err_bits_clear; logic software_errs_fatal_q, software_errs_fatal_d; - otbn_reg2hw_t reg2hw; - otbn_hw2reg_t hw2reg; + acc_reg2hw_t reg2hw; + acc_hw2reg_t hw2reg; status_e status_d, status_q; - // Bus device windows, as specified in otbn.hjson + // Bus device windows, as specified in acc.hjson typedef enum logic { TlWinImem = 1'b0, TlWinDmem = 1'b1 @@ -161,7 +161,7 @@ module otbn kmac_pkg::app_rsp_t kmac_rsp; generate - if (OtbnPQCEn) begin : gen_active_app_intf + if (AccPQCEn) begin : gen_active_app_intf assign kmac_data_o = kmac_req; assign kmac_rsp = kmac_data_i; end else begin : gen_inactive_app_intf @@ -170,20 +170,20 @@ module otbn end endgenerate - // The clock can be gated and some registers can be updated as long as OTBN isn't currently - // running. Other registers can only be updated when OTBN is in the Idle state (which also implies + // The clock can be gated and some registers can be updated as long as ACC isn't currently + // running. Other registers can only be updated when ACC is in the Idle state (which also implies // we are not locked). logic is_not_running_d, is_not_running_q; - logic otbn_dmem_scramble_key_req_busy, otbn_imem_scramble_key_req_busy; + logic acc_dmem_scramble_key_req_busy, acc_imem_scramble_key_req_busy; assign is_not_running_d = ~|{busy_execute_d, - otbn_dmem_scramble_key_req_busy, - otbn_imem_scramble_key_req_busy, + acc_dmem_scramble_key_req_busy, + acc_imem_scramble_key_req_busy, busy_secure_wipe}; always_ff @(posedge clk_i or negedge rst_ni) begin if(!rst_ni) begin - // OTBN starts busy, performing the initial secure wipe. + // ACC starts busy, performing the initial secure wipe. is_not_running_q <= 1'b0; end else begin is_not_running_q <= is_not_running_d; @@ -226,7 +226,7 @@ module otbn .lc_en_o({lc_rma_req}) ); - // Internally, OTBN uses MUBI types. + // Internally, ACC uses MUBI types. mubi4_t mubi_rma_req, mubi_rma_ack; assign mubi_rma_req = lc_ctrl_pkg::lc_to_mubi4(lc_rma_req); @@ -314,52 +314,52 @@ module otbn logic [1:0] unused_imem_addr_core_wordbits; assign unused_imem_addr_core_wordbits = imem_addr_core[1:0]; - otp_ctrl_pkg::otbn_key_t otbn_imem_scramble_key; - otbn_imem_nonce_t otbn_imem_scramble_nonce; - logic otbn_imem_scramble_valid; - logic unused_otbn_imem_scramble_key_seed_valid; + otp_ctrl_pkg::acc_key_t acc_imem_scramble_key; + acc_imem_nonce_t acc_imem_scramble_nonce; + logic acc_imem_scramble_valid; + logic unused_acc_imem_scramble_key_seed_valid; - otp_ctrl_pkg::otbn_key_t otbn_dmem_scramble_key; - otbn_dmem_nonce_t otbn_dmem_scramble_nonce; - logic otbn_dmem_scramble_valid; - logic unused_otbn_dmem_scramble_key_seed_valid; + otp_ctrl_pkg::acc_key_t acc_dmem_scramble_key; + acc_dmem_nonce_t acc_dmem_scramble_nonce; + logic acc_dmem_scramble_valid; + logic unused_acc_dmem_scramble_key_seed_valid; - logic otbn_scramble_state_error; + logic acc_scramble_state_error; // SEC_CM: SCRAMBLE.KEY.SIDELOAD - otbn_scramble_ctrl #( - .RndCnstOtbnKey (RndCnstOtbnKey), - .RndCnstOtbnNonce(RndCnstOtbnNonce) - ) u_otbn_scramble_ctrl ( + acc_scramble_ctrl #( + .RndCnstAccKey (RndCnstAccKey), + .RndCnstAccNonce(RndCnstAccNonce) + ) u_acc_scramble_ctrl ( .clk_i, .rst_ni, .clk_otp_i, .rst_otp_ni, - .otbn_otp_key_o, - .otbn_otp_key_i, + .acc_otp_key_o, + .acc_otp_key_i, - .otbn_dmem_scramble_key_o (otbn_dmem_scramble_key), - .otbn_dmem_scramble_nonce_o (otbn_dmem_scramble_nonce), - .otbn_dmem_scramble_valid_o (otbn_dmem_scramble_valid), - .otbn_dmem_scramble_key_seed_valid_o(unused_otbn_dmem_scramble_key_seed_valid), + .acc_dmem_scramble_key_o (acc_dmem_scramble_key), + .acc_dmem_scramble_nonce_o (acc_dmem_scramble_nonce), + .acc_dmem_scramble_valid_o (acc_dmem_scramble_valid), + .acc_dmem_scramble_key_seed_valid_o(unused_acc_dmem_scramble_key_seed_valid), - .otbn_imem_scramble_key_o (otbn_imem_scramble_key), - .otbn_imem_scramble_nonce_o (otbn_imem_scramble_nonce), - .otbn_imem_scramble_valid_o (otbn_imem_scramble_valid), - .otbn_imem_scramble_key_seed_valid_o(unused_otbn_imem_scramble_key_seed_valid), + .acc_imem_scramble_key_o (acc_imem_scramble_key), + .acc_imem_scramble_nonce_o (acc_imem_scramble_nonce), + .acc_imem_scramble_valid_o (acc_imem_scramble_valid), + .acc_imem_scramble_key_seed_valid_o(unused_acc_imem_scramble_key_seed_valid), - .otbn_dmem_scramble_sec_wipe_i (dmem_sec_wipe), - .otbn_dmem_scramble_sec_wipe_key_i(dmem_sec_wipe_urnd_key), - .otbn_imem_scramble_sec_wipe_i (imem_sec_wipe), - .otbn_imem_scramble_sec_wipe_key_i(imem_sec_wipe_urnd_key), + .acc_dmem_scramble_sec_wipe_i (dmem_sec_wipe), + .acc_dmem_scramble_sec_wipe_key_i(dmem_sec_wipe_urnd_key), + .acc_imem_scramble_sec_wipe_i (imem_sec_wipe), + .acc_imem_scramble_sec_wipe_key_i(imem_sec_wipe_urnd_key), - .otbn_dmem_scramble_key_req_busy_o(otbn_dmem_scramble_key_req_busy), - .otbn_imem_scramble_key_req_busy_o(otbn_imem_scramble_key_req_busy), + .acc_dmem_scramble_key_req_busy_o(acc_dmem_scramble_key_req_busy), + .acc_imem_scramble_key_req_busy_o(acc_imem_scramble_key_req_busy), - .state_error_o(otbn_scramble_state_error) + .state_error_o(acc_scramble_state_error) ); // SEC_CM: MEM.SCRAMBLE @@ -373,9 +373,9 @@ module otbn .clk_i, .rst_ni(rst_n), - .key_valid_i(otbn_imem_scramble_valid), - .key_i (otbn_imem_scramble_key), - .nonce_i (otbn_imem_scramble_nonce), + .key_valid_i(acc_imem_scramble_valid), + .key_i (acc_imem_scramble_key), + .nonce_i (acc_imem_scramble_nonce), .req_i (imem_req), .gnt_o (imem_gnt), @@ -403,7 +403,7 @@ module otbn // IMEM access from main TL-UL bus logic imem_gnt_bus; - // Always grant to bus accesses, when OTBN is running a dummy response is returned + // Always grant to bus accesses, when ACC is running a dummy response is returned assign imem_gnt_bus = imem_req_bus; tlul_adapter_sram #( @@ -472,8 +472,8 @@ module otbn // SEC_CM: DATA_REG_SW.SCA // Blank bus read data interface during core operation to avoid leaking the currently executed - // instruction from IMEM through the bus unintentionally. Also blank when OTBN is returning - // a dummy response (responding to an illegal bus access) and when OTBN is locked. + // instruction from IMEM through the bus unintentionally. Also blank when ACC is returning + // a dummy response (responding to an illegal bus access) and when ACC is locked. assign imem_rdata_bus_en_d = ~(busy_execute_d | start_d) & ~imem_dummy_response_d & ~locking; always_ff @(posedge clk_i or negedge rst_ni) begin @@ -490,8 +490,8 @@ module otbn .out_o(imem_rdata_bus_raw) ); - // When OTBN is locked all imem bus reads should return 0. The blanker produces the 0s, this adds - // the appropriate ECC. When OTBN is not locked the output of the blanker is passed straight + // When ACC is locked all imem bus reads should return 0. The blanker produces the 0s, this adds + // the appropriate ECC. When ACC is not locked the output of the blanker is passed straight // through. Data bits are always left un-modified. A registered version of `locking` is used for // timing reasons. When a read comes in when `locking` has just been asserted, `locking_q` will be // set the following cycle and the rdata will be forced to 0 with appropriate ECC. When `locking` @@ -524,7 +524,7 @@ module otbn localparam int DmemSizeWords = DmemSizeByte / (WLEN / 8); localparam int DmemIndexWidth = vbits(DmemSizeWords); - localparam int DmemBusSizeWords = int'(otbn_reg_pkg::OTBN_DMEM_SIZE) / (WLEN / 8); + localparam int DmemBusSizeWords = int'(acc_reg_pkg::ACC_DMEM_SIZE) / (WLEN / 8); localparam int DmemBusIndexWidth = vbits(DmemBusSizeWords); // Access select to DMEM: core (1), or bus (0) @@ -590,9 +590,9 @@ module otbn .clk_i, .rst_ni(rst_n), - .key_valid_i(otbn_dmem_scramble_valid), - .key_i (otbn_dmem_scramble_key), - .nonce_i (otbn_dmem_scramble_nonce), + .key_valid_i(acc_dmem_scramble_valid), + .key_i (acc_dmem_scramble_key), + .nonce_i (acc_dmem_scramble_nonce), .req_i (dmem_req), .gnt_o (dmem_gnt), @@ -643,8 +643,8 @@ module otbn ); // Only report an error where the word was actually accessed. Otherwise uninitialised memory - // that OTBN isn't using will cause false errors. dmem_rerror is only reported for reads from - // OTBN. For Ibex reads integrity checking on TL responses will serve the same purpose. + // that ACC isn't using will cause false errors. dmem_rerror is only reported for reads from + // ACC. For Ibex reads integrity checking on TL responses will serve the same purpose. assign dmem_rerror_vec[i_word*2 +: 2] = dmem_rerror_raw & {2{dmem_rmask_core_q[i_word] & dmem_rvalid & dmem_access_core}}; end @@ -656,7 +656,7 @@ module otbn // DMEM access from main TL-UL bus logic dmem_gnt_bus; - // Always grant to bus accesses, when OTBN is running a dummy response is returned + // Always grant to bus accesses, when ACC is running a dummy response is returned assign dmem_gnt_bus = dmem_req_bus; tlul_adapter_sram #( @@ -715,8 +715,8 @@ module otbn // SEC_CM: DATA_REG_SW.SCA // Blank bus read data interface during core operation to avoid leaking DMEM data through the bus - // unintentionally. Also blank when OTBN is returning a dummy response (responding to an illegal - // bus access) and when OTBN is locked. + // unintentionally. Also blank when ACC is returning a dummy response (responding to an illegal + // bus access) and when ACC is locked. assign dmem_rdata_bus_en_d = ~(busy_execute_d | start_d) & ~dmem_dummy_response_d & ~locking; always_ff @(posedge clk_i or negedge rst_ni) begin @@ -733,8 +733,8 @@ module otbn .out_o(dmem_rdata_bus_raw) ); - // When OTBN is locked all dmem bus reads should return 0. The blanker produces the 0s, this adds - // the appropriate ECC. When OTBN is not locked the output of the blanker is passed straight + // When ACC is locked all dmem bus reads should return 0. The blanker produces the 0s, this adds + // the appropriate ECC. When ACC is not locked the output of the blanker is passed straight // through. Data bits are always left un-modified. A registered version of `locking` is used for // timing reasons. When a read comes in when `locking` has just been asserted, `locking_q` will be // timing reasons. When a read comes in when `locking` has just been asserted, `locking_q` will be @@ -811,7 +811,7 @@ module otbn logic reg_bus_intg_violation; - otbn_reg_top u_reg ( + acc_reg_top u_reg ( .clk_i, .rst_ni (rst_n), .tl_i, @@ -833,7 +833,7 @@ module otbn // CMD register always_comb begin - // start is flopped to avoid long timing paths from the TL fabric into OTBN internals. + // start is flopped to avoid long timing paths from the TL fabric into ACC internals. start_d = 1'b0; dmem_sec_wipe = 1'b0; imem_sec_wipe = 1'b0; @@ -849,7 +849,7 @@ module otbn endcase end end else if (busy_execute_q) begin - // OTBN can command a secure wipe of IMEM and DMEM. This occurs when OTBN encounters a fatal + // ACC can command a secure wipe of IMEM and DMEM. This occurs when ACC encounters a fatal // error. if (mems_sec_wipe) begin dmem_sec_wipe = 1'b1; @@ -870,7 +870,7 @@ module otbn assign missed_gnt_error_d = dmem_missed_gnt | imem_missed_gnt; // Flop `illegal_bus_access_q` and `missed_gnt_error_q` to break timing paths from the TL - // interface into the OTBN core. + // interface into the ACC core. always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin start_q <= 1'b0; @@ -893,8 +893,8 @@ module otbn assign status_d = locking ? StatusLocked : busy_secure_wipe ? StatusBusySecWipeInt : busy_execute_d ? StatusBusyExecute : - otbn_dmem_scramble_key_req_busy ? StatusBusySecWipeDmem : - otbn_imem_scramble_key_req_busy ? StatusBusySecWipeImem : + acc_dmem_scramble_key_req_busy ? StatusBusySecWipeDmem : + acc_imem_scramble_key_req_busy ? StatusBusySecWipeImem : StatusIdle; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin @@ -908,15 +908,15 @@ module otbn assign hw2reg.status.de = 1'b1; // Only certain combinations of the state variable {locking, busy_execute_d, - // otbn_dmem_scramble_key_req_busy, otbn_imem_scramble_key_req_busy} are possible. + // acc_dmem_scramble_key_req_busy, acc_imem_scramble_key_req_busy} are possible. // // - Once locking is high, we guarantee never to see a new execution or the start of a key // rotation. (Assertion: NoStartWhenLocked_A) `ASSERT(NoStartWhenLocked_A, locking |=> !($rose(busy_execute_d) || - $rose(otbn_dmem_scramble_key_req_busy) || - $rose(otbn_imem_scramble_key_req_busy))) + $rose(acc_dmem_scramble_key_req_busy) || + $rose(acc_imem_scramble_key_req_busy))) // CTRL register assign software_errs_fatal_d = @@ -934,7 +934,7 @@ module otbn assign hw2reg.ctrl.d = software_errs_fatal_q; // ERR_BITS register - // The error bits for an OTBN operation get stored on the cycle that done is + // The error bits for an ACC operation get stored on the cycle that done is // asserted. Software is expected to read them out before starting the next operation. assign hw2reg.err_bits.bad_data_addr.d = err_bits_q.bad_data_addr; @@ -1111,7 +1111,7 @@ module otbn ); - // OTBN Core ================================================================= + // ACC Core ================================================================= always_ff @(posedge clk_i or negedge rst_n) begin if (!rst_n) begin @@ -1125,15 +1125,15 @@ module otbn assign busy_execute_d = (busy_execute_q | start_d) & ~done_core; assign init_sec_wipe_done_d = init_sec_wipe_done_q | ~busy_secure_wipe; - otbn_core #( + acc_core #( .RegFile(RegFile), .DmemSizeByte(DmemSizeByte), .ImemSizeByte(ImemSizeByte), - .OtbnPQCEn(OtbnPQCEn), + .AccPQCEn(AccPQCEn), .RndCnstUrndPrngSeed(RndCnstUrndPrngSeed), .SecMuteUrnd(SecMuteUrnd), .SecSkipUrndReseedAtStart(SecSkipUrndReseedAtStart) - ) u_otbn_core ( + ) u_acc_core ( .clk_i, .rst_ni (rst_n), @@ -1204,7 +1204,7 @@ module otbn assign non_core_err_bits = '{ lifecycle_escalation: lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]), illegal_bus_access: illegal_bus_access_q, - bad_internal_state: otbn_scramble_state_error | missed_gnt_error_q, + bad_internal_state: acc_scramble_state_error | missed_gnt_error_q, bus_intg_violation: bus_intg_violation }; @@ -1255,13 +1255,13 @@ module otbn for (genvar i = 0; i < LoopStackDepth; ++i) begin : gen_loop_stack_cntr_asserts `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( LoopStackCntAlertCheck_A, - u_otbn_core.u_otbn_controller.u_otbn_loop_controller.g_loop_counters[i].u_loop_count, + u_acc_core.u_acc_controller.u_acc_loop_controller.g_loop_counters[i].u_loop_count, alert_tx_o[AlertFatal] ) end // GPR assertions for secure wipe - // 1. urnd_reseed_err disables the assertion because secure wipe finishes with failure and OTBN + // 1. urnd_reseed_err disables the assertion because secure wipe finishes with failure and ACC // goes to LOCKED state immediately after this error which means that it's not guaranteed to have // secure wiping complete. // 2. mubi_err_d of start_stop_control disables the internal secure wipe related assertion @@ -1271,22 +1271,22 @@ module otbn // Initial secure wipe needs to initialise all registers to nonzero `ASSERT(InitSecWipeNonZeroBaseRegs_A, $fell(busy_secure_wipe) |-> - u_otbn_core.u_otbn_rf_base.gen_rf_base_ff.u_otbn_rf_base_inner.g_rf_flops[i].rf_reg_q != + u_acc_core.u_acc_rf_base.gen_rf_base_ff.u_acc_rf_base_inner.g_rf_flops[i].rf_reg_q != EccZeroWord, clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d) // After execution, it's expected to see a change resulting with a nonzero register value `ASSERT(SecWipeChangedBaseRegs_A, $rose(busy_secure_wipe) |-> ((##[0:$] - u_otbn_core.u_otbn_rf_base.gen_rf_base_ff.u_otbn_rf_base_inner.g_rf_flops[i].rf_reg_q != + u_acc_core.u_acc_rf_base.gen_rf_base_ff.u_acc_rf_base_inner.g_rf_flops[i].rf_reg_q != EccZeroWord && $changed( - u_otbn_core.u_otbn_rf_base.gen_rf_base_ff.u_otbn_rf_base_inner.g_rf_flops[i].rf_reg_q)) + u_acc_core.u_acc_rf_base.gen_rf_base_ff.u_acc_rf_base_inner.g_rf_flops[i].rf_reg_q)) within ($rose(busy_secure_wipe) ##[0:$] $fell(busy_secure_wipe))), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d) end // We have several assertions that check that secure wipe worked properly. However, we've also got @@ -1301,7 +1301,7 @@ module otbn // therefore expect its name to start with a "g_". if (1) begin : g_secure_wipe_assertions // WDR assertions for secure wipe - // 1. urnd_reseed_err disables the assertion because secure wipe finishes with failure and OTBN + // 1. urnd_reseed_err disables the assertion because secure wipe finishes with failure and ACC // goes to LOCKED state immediately after this error which means that it's not guaranteed to // have secure wiping complete. // 2. mubi_err_d of start_stop_control disables the internal secure wipe related assertion @@ -1311,99 +1311,99 @@ module otbn // Initial secure wipe needs to initialise all registers to nonzero `ASSERT(InitSecWipeNonZeroWideRegs_A, $fell(busy_secure_wipe) |-> - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf[i] != + u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf[i] != EccWideZeroWord, clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d) // After execution, it's expected to see a change resulting with a nonzero register value `ASSERT(SecWipeChangedWideRegs_A, $rose(busy_secure_wipe) |-> ((##[0:$] - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf[i] != + u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf[i] != EccWideZeroWord && $changed( - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.rf[i])) + u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.rf[i])) within ($rose(busy_secure_wipe) ##[0:$] $fell(busy_secure_wipe))), - clk_i, !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d) + clk_i, !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d) end end // Secure wipe needs to invalidate call and loop stack, initialize MOD, ACC to nonzero and set // FLAGS CSR to zero - // 1. urnd_reseed_err disables the assertion because secure wipe finishes with failure and OTBN + // 1. urnd_reseed_err disables the assertion because secure wipe finishes with failure and ACC // goes to LOCKED state immediately after this error which means that it's not guaranteed to have // secure wiping complete. // 2. mubi_err_d of start_stop_control disables the secure wipe related assertions because a // fatal error affecting internal secure wiping could cause an immediate locking behaviour // in which it's not guaranteed to see a successful secure wipe. `ASSERT(SecWipeInvalidCallStack_A, - $fell(busy_secure_wipe) |-> (!u_otbn_core.u_otbn_rf_base.u_call_stack.top_valid_o), + $fell(busy_secure_wipe) |-> (!u_acc_core.u_acc_rf_base.u_call_stack.top_valid_o), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d || + u_acc_core.u_acc_start_stop_control.state_error_d) `ASSERT(SecWipeInvalidLoopStack_A, $fell(busy_secure_wipe) |-> - (!u_otbn_core.u_otbn_controller.u_otbn_loop_controller.loop_info_stack.top_valid_o), + (!u_acc_core.u_acc_controller.u_acc_loop_controller.loop_info_stack.top_valid_o), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d || + u_acc_core.u_acc_start_stop_control.state_error_d) `ASSERT(SecWipeNonZeroMod_A, - $fell(busy_secure_wipe) |-> u_otbn_core.u_otbn_alu_bignum.mod_intg_q != EccWideZeroWord, + $fell(busy_secure_wipe) |-> u_acc_core.u_acc_alu_bignum.mod_intg_q != EccWideZeroWord, clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d || + u_acc_core.u_acc_start_stop_control.state_error_d) `ASSERT(SecWipeNonZeroACC_A, $fell(busy_secure_wipe) |-> - u_otbn_core.u_otbn_alu_bignum.ispr_acc_intg_i != EccWideZeroWord, + u_acc_core.u_acc_alu_bignum.ispr_acc_intg_i != EccWideZeroWord, clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d) `ASSERT(SecWipeNonZeroFlags_A, - $fell(busy_secure_wipe) |-> (!u_otbn_core.u_otbn_alu_bignum.flags_flattened), + $fell(busy_secure_wipe) |-> (!u_acc_core.u_acc_alu_bignum.flags_flattened), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d || - u_otbn_core.u_otbn_start_stop_control.state_error_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d || + u_acc_core.u_acc_start_stop_control.state_error_d || + u_acc_core.u_acc_start_stop_control.state_error_d) // Secure wipe of IMEM and DMEM first happens with a key change from URND (while valid is zero) `ASSERT(ImemSecWipeRequiresUrndKey_A, - $rose(imem_sec_wipe) |=> (otbn_imem_scramble_key == $past(imem_sec_wipe_urnd_key)), + $rose(imem_sec_wipe) |=> (acc_imem_scramble_key == $past(imem_sec_wipe_urnd_key)), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d) `ASSERT(DmemSecWipeRequiresUrndKey_A, - $rose(dmem_sec_wipe) |=> (otbn_dmem_scramble_key == $past(dmem_sec_wipe_urnd_key)), + $rose(dmem_sec_wipe) |=> (acc_dmem_scramble_key == $past(dmem_sec_wipe_urnd_key)), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d) // Then it is guaranteed to have a valid key from OTP interface which is different from URND key `ASSERT(ImemSecWipeRequiresOtpKey_A, - $rose(imem_sec_wipe) ##1 (otbn_imem_scramble_key == $past(imem_sec_wipe_urnd_key)) |=> - ##[0:$] otbn_imem_scramble_valid && $changed(otbn_imem_scramble_key), + $rose(imem_sec_wipe) ##1 (acc_imem_scramble_key == $past(imem_sec_wipe_urnd_key)) |=> + ##[0:$] acc_imem_scramble_valid && $changed(acc_imem_scramble_key), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d) `ASSERT(DmemSecWipeRequiresOtpKey_A, - $rose(dmem_sec_wipe) ##1 (otbn_dmem_scramble_key == $past(dmem_sec_wipe_urnd_key)) |=> - ##[0:$] otbn_dmem_scramble_valid && $changed(otbn_dmem_scramble_key), + $rose(dmem_sec_wipe) ##1 (acc_dmem_scramble_key == $past(dmem_sec_wipe_urnd_key)) |=> + ##[0:$] acc_dmem_scramble_valid && $changed(acc_dmem_scramble_key), clk_i, - !rst_ni || u_otbn_core.urnd_reseed_err || - u_otbn_core.u_otbn_start_stop_control.mubi_err_d) + !rst_ni || u_acc_core.urnd_reseed_err || + u_acc_core.u_acc_start_stop_control.mubi_err_d) // All outputs should be known value after reset `ASSERT_KNOWN(TlODValidKnown_A, tl_o.d_valid) @@ -1413,7 +1413,7 @@ module otbn `ASSERT_KNOWN(AlertTxOKnown_A, alert_tx_o) `ASSERT_KNOWN(EdnRndOKnown_A, edn_rnd_o, clk_edn_i, !rst_edn_ni) `ASSERT_KNOWN(EdnUrndOKnown_A, edn_urnd_o, clk_edn_i, !rst_edn_ni) - `ASSERT_KNOWN(OtbnOtpKeyO_A, otbn_otp_key_o, clk_otp_i, !rst_otp_ni) + `ASSERT_KNOWN(AccOtpKeyO_A, acc_otp_key_o, clk_otp_i, !rst_otp_ni) `ASSERT_KNOWN(ErrBitsKnown_A, err_bits) // Incoming key must be valid (other inputs go via prim modules that handle the X checks). @@ -1445,17 +1445,17 @@ module otbn // Constraint from package, check here as we cannot have `ASSERT_INIT in package `ASSERT_INIT(WsrESizeMatchesParameter_A, $bits(wsr_e) == WsrNumWidth) - `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(OtbnStartStopFsmCheck_A, - u_otbn_core.u_otbn_start_stop_control.u_state_regs, alert_tx_o[AlertFatal]) - `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(OtbnControllerFsmCheck_A, - u_otbn_core.u_otbn_controller.u_state_regs, alert_tx_o[AlertFatal]) - `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(OtbnScrambleCtrlFsmCheck_A, - u_otbn_scramble_ctrl.u_state_regs, alert_tx_o[AlertFatal]) - - `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(OtbnCallStackWrPtrAlertCheck_A, - u_otbn_core.u_otbn_rf_base.u_call_stack.u_stack_wr_ptr, alert_tx_o[AlertFatal]) - `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(OtbnLoopInfoStackWrPtrAlertCheck_A, - u_otbn_core.u_otbn_controller.u_otbn_loop_controller.loop_info_stack.u_stack_wr_ptr, + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(AccStartStopFsmCheck_A, + u_acc_core.u_acc_start_stop_control.u_state_regs, alert_tx_o[AlertFatal]) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(AccControllerFsmCheck_A, + u_acc_core.u_acc_controller.u_state_regs, alert_tx_o[AlertFatal]) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(AccScrambleCtrlFsmCheck_A, + u_acc_scramble_ctrl.u_state_regs, alert_tx_o[AlertFatal]) + + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(AccCallStackWrPtrAlertCheck_A, + u_acc_core.u_acc_rf_base.u_call_stack.u_stack_wr_ptr, alert_tx_o[AlertFatal]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(AccLoopInfoStackWrPtrAlertCheck_A, + u_acc_core.u_acc_controller.u_acc_loop_controller.loop_info_stack.u_stack_wr_ptr, alert_tx_o[AlertFatal]) // Alert assertions for reg_we onehot check @@ -1463,10 +1463,10 @@ module otbn u_reg, alert_tx_o[AlertFatal]) // other onehot checks `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RfBaseOnehotCheck_A, - u_otbn_core.u_otbn_rf_base.gen_rf_base_ff.u_otbn_rf_base_inner.u_prim_onehot_check, + u_acc_core.u_acc_rf_base.gen_rf_base_ff.u_acc_rf_base_inner.u_prim_onehot_check, alert_tx_o[AlertFatal]) `ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(RfBignumOnehotCheck_A, - u_otbn_core.u_otbn_rf_bignum.gen_rf_bignum_ff.u_otbn_rf_bignum_inner.u_prim_onehot_check, + u_acc_core.u_acc_rf_bignum.gen_rf_bignum_ff.u_acc_rf_bignum_inner.u_prim_onehot_check, alert_tx_o[AlertFatal]) `ASSERT_PRIM_FIFO_SYNC_ERROR_TRIGGERS_ALERT1(DmemRspFifo, diff --git a/hw/ip/otbn/rtl/otbn_alu_base.sv b/hw/ip/acc/rtl/acc_alu_base.sv similarity index 96% rename from hw/ip/otbn/rtl/otbn_alu_base.sv rename to hw/ip/acc/rtl/acc_alu_base.sv index 4176f0e2a21..5989df122b6 100644 --- a/hw/ip/otbn/rtl/otbn_alu_base.sv +++ b/hw/ip/acc/rtl/acc_alu_base.sv @@ -5,12 +5,12 @@ `include "prim_assert.sv" /** - * OTBN execute block for the base instruction subset + * ACC execute block for the base instruction subset * - * This ALU supports the execution of all of OTBN's base instruction subset. + * This ALU supports the execution of all of ACC's base instruction subset. */ -module otbn_alu_base - import otbn_pkg::*; +module acc_alu_base + import acc_pkg::*; ( // Block is combinatorial; clk/rst are for assertions only. input logic clk_i, diff --git a/hw/ip/otbn/rtl/otbn_alu_bignum.sv b/hw/ip/acc/rtl/acc_alu_bignum.sv similarity index 98% rename from hw/ip/otbn/rtl/otbn_alu_bignum.sv rename to hw/ip/acc/rtl/acc_alu_bignum.sv index e0bd8724b86..578cfc0d8fe 100644 --- a/hw/ip/otbn/rtl/otbn_alu_bignum.sv +++ b/hw/ip/acc/rtl/acc_alu_bignum.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -12,7 +12,7 @@ `include "prim_assert.sv" /** - * OTBN alu block for the bignum instruction subset + * ACC alu block for the bignum instruction subset * * This ALU supports all of the 'plain' arithmetic and logic bignum instructions, BN.MULQACC is * implemented in a separate block. @@ -75,11 +75,11 @@ */ -module otbn_alu_bignum - import otbn_pkg::*; +module acc_alu_bignum + import acc_pkg::*; #( // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1 + parameter bit AccPQCEn = 1'b1 ) ( input logic clk_i, input logic rst_ni, @@ -139,13 +139,13 @@ module otbn_alu_bignum input kmac_pkg::app_rsp_t kmac_app_rsp_i ); // Localparam net widths base on PQC enable - localparam int ADDY_LEN = (OtbnPQCEn) ? WLEN-1 : WLEN+1; - localparam int ADDER_MSB_IDX = (OtbnPQCEn) ? WLEN-1 : WLEN; - localparam int ADDER_LSB_IDX = (OtbnPQCEn) ? 0 : 1; + localparam int ADDY_LEN = (AccPQCEn) ? WLEN-1 : WLEN+1; + localparam int ADDER_MSB_IDX = (AccPQCEn) ? WLEN-1 : WLEN; + localparam int ADDER_LSB_IDX = (AccPQCEn) ? 0 : 1; // Tie unused ports to '0 generate - if (!OtbnPQCEn) begin : gen_unused_outputs + if (!AccPQCEn) begin : gen_unused_outputs // Tie off unused inputs logic unused_bits; assign unused_bits = ^{operation_i.trn_type, operation_i.vector_sel, operation_i.vector_type, @@ -169,7 +169,7 @@ module otbn_alu_bignum logic [ADDY_LEN:0] adder_y_res; generate - if (OtbnPQCEn) begin : gen_adder_y_res_pqc + if (AccPQCEn) begin : gen_adder_y_res_pqc logic [15:0] adder_y_carry_out; end endgenerate @@ -286,7 +286,7 @@ module otbn_alu_bignum // Adder operations update all flags. generate - if (OtbnPQCEn) begin : gen_adder_flags_pqc + if (AccPQCEn) begin : gen_adder_flags_pqc assign adder_carry = gen_adder_y_res_pqc.adder_y_carry_out[15]; end else begin : gen_adder_flags assign adder_carry = adder_y_res[WLEN+1]; @@ -472,7 +472,7 @@ module otbn_alu_bignum // KMAC // ////////// generate - if (OtbnPQCEn) begin : gen_pqc_wsr + if (AccPQCEn) begin : gen_pqc_wsr // CFG logic [BaseIntgWidth-1:0] kmac_cfg_intg_q; logic [31:0] kmac_cfg_no_intg_d; @@ -925,8 +925,8 @@ generate end // If there is an error we need to flush the remainder of the FIFO under the assumption - // that KMAC won't be asserting a ready signal to OTBN. Latch the error flag until a new - // config is written to OTBN and use this to empty the FIFO and prepare for the next transaction. + // that KMAC won't be asserting a ready signal to ACC. Latch the error flag until a new + // config is written to ACC and use this to empty the FIFO and prepare for the next transaction. always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin kmac_msg_err_clr_q <= 1'b0; @@ -1014,7 +1014,7 @@ generate end end - // Internal copy of otbn_controller stall signal to determine pending msg writes + // Internal copy of acc_controller stall signal to determine pending msg writes assign kmac_msg_wr_stall = (kmac_msg_write & (~kmac_msg_fifo_wready)); // When reading the return digest the message has already been sent and any remainder is cleared @@ -1039,7 +1039,7 @@ generate .mask_o (kmac_msg_fifo_rdata_mask), .ready_i (kmac_msg_fifo_rready), - // kmac_msg_err_clr is for internal OTBN error to empty the FIFO + // kmac_msg_err_clr is for internal ACC error to empty the FIFO // kmac_msg_fifo_flush reads a partial word at the end of the msg // kmac_msg_fifo_clr ensures the fifo is empty outside of an active msg .flush_i (kmac_msg_err_clr || kmac_msg_fifo_flush || kmac_msg_fifo_clr), @@ -1257,7 +1257,7 @@ endgenerate // ACCH // ////////// generate - if (OtbnPQCEn) begin : gen_acch_wsr + if (AccPQCEn) begin : gen_acch_wsr assign ispr_acch_wr_en_o = ((ispr_addr_i == IsprAccH) & ispr_bignum_wr_en_i & ispr_wr_commit_i) | ispr_init_i; @@ -1287,7 +1287,7 @@ endgenerate localparam int IsprModIntg = 0; localparam int IsprAccIntg = 1; generate - if (OtbnPQCEn) begin : gen_ispr_ids_pqc + if (AccPQCEn) begin : gen_ispr_ids_pqc localparam int IsprKmacMsgIntg = 2; localparam int IsprKmacDigestIntg = 3; localparam int IsprAccHIntg = 4; @@ -1295,9 +1295,9 @@ endgenerate endgenerate // ID representing all ISPRs with no integrity - localparam int IsprNoIntg = OtbnPQCEn ? 5 : 2; + localparam int IsprNoIntg = AccPQCEn ? 5 : 2; // Number of ISPRs that have integrity protection - localparam int NIntgIspr = OtbnPQCEn ? 5 : 2; + localparam int NIntgIspr = AccPQCEn ? 5 : 2; logic [NIntgIspr:0] ispr_rdata_intg_mux_sel; logic [ExtWLEN-1:0] ispr_rdata_intg_mux_in [NIntgIspr+1]; @@ -1308,7 +1308,7 @@ endgenerate assign ispr_rdata_no_intg_mux_in[IsprMod] = 0; assign ispr_rdata_no_intg_mux_in[IsprAcc] = 0; generate - if (OtbnPQCEn) begin : gen_ispr_no_intg_mux_pqc + if (AccPQCEn) begin : gen_ispr_no_intg_mux_pqc assign ispr_rdata_no_intg_mux_in[IsprKmacMsg] = 0; assign ispr_rdata_no_intg_mux_in[IsprKmacCfg] = @@ -1362,7 +1362,7 @@ endgenerate assign ispr_rdata_intg_mux_in[IsprNoIntg] = ispr_rdata_intg_calc; generate - if (OtbnPQCEn) begin : gen_ispr_intg_mux_pqc + if (AccPQCEn) begin : gen_ispr_intg_mux_pqc assign ispr_rdata_intg_mux_in[gen_ispr_ids_pqc.IsprKmacMsgIntg] = gen_pqc_wsr.kmac_msg_intg_q; assign ispr_rdata_intg_mux_in[gen_ispr_ids_pqc.IsprKmacDigestIntg] = @@ -1375,7 +1375,7 @@ endgenerate assign ispr_rdata_intg_mux_sel[IsprAccIntg] = ispr_predec_bignum_i.ispr_rd_en[IsprAcc]; generate - if (OtbnPQCEn) begin : gen_ispr_intg_mux_sel_pqc + if (AccPQCEn) begin : gen_ispr_intg_mux_sel_pqc assign ispr_rdata_intg_mux_sel[gen_ispr_ids_pqc.IsprKmacMsgIntg] = ispr_predec_bignum_i.ispr_rd_en[IsprKmacMsg]; assign ispr_rdata_intg_mux_sel[gen_ispr_ids_pqc.IsprKmacDigestIntg] = @@ -1386,7 +1386,7 @@ endgenerate endgenerate generate - if (OtbnPQCEn) begin : gen_ispr_intg_mux_sel_cat_pqc + if (AccPQCEn) begin : gen_ispr_intg_mux_sel_cat_pqc assign ispr_rdata_intg_mux_sel[IsprNoIntg] = |{ispr_predec_bignum_i.ispr_rd_en[IsprKeyS1H:IsprKeyS0L], ispr_predec_bignum_i.ispr_rd_en[IsprUrnd], @@ -1417,7 +1417,7 @@ endgenerate ispr_predec_bignum_i.ispr_rd_en[IsprAcc] |-> !ispr_rdata_intg_mux_sel[IsprNoIntg]) generate - if (OtbnPQCEn) begin : gen_acch_intg_assert + if (AccPQCEn) begin : gen_acch_intg_assert `ASSERT(IsprAccHMustTakeIntg_A, ispr_predec_bignum_i.ispr_rd_en[IsprAccH] |-> !ispr_rdata_intg_mux_sel[IsprNoIntg]) end @@ -1480,7 +1480,7 @@ endgenerate ); generate - if (OtbnPQCEn) begin : gen_shifter_pqc + if (AccPQCEn) begin : gen_shifter_pqc logic [WLEN-1:0] shifter_bignum_in_upper, shifter_bignum_in_lower; logic [WLEN-1:0] shifter_bignum_in_lower_reverse; logic [WLEN*2-1:0] shifter_bignum_in; @@ -1553,7 +1553,7 @@ generate end // SHIFTER RESULT - assign shifter_res = (operation_i.op == otbn_pkg::AluOpBignumShv) ? shifter_vec_res + assign shifter_res = (operation_i.op == acc_pkg::AluOpBignumShv) ? shifter_vec_res : shifter_bignum_res; // Only the lower WLEN bits of the shift result are returned. @@ -1597,7 +1597,7 @@ generate // Transpose // /////////////// generate - if (OtbnPQCEn) begin : gen_trn_pqc + if (AccPQCEn) begin : gen_trn_pqc logic [WLEN/16-1:0] trn_op0_16h [16]; logic [WLEN/8-1:0] trn_op0_8s [8]; logic [WLEN/4-1:0] trn_op0_4d [4]; @@ -1709,7 +1709,7 @@ generate logic [WLEN-1:0] x_res_operand_a_mux_out; generate - if (OtbnPQCEn) begin : gen_adder_pqc + if (AccPQCEn) begin : gen_adder_pqc // ADDER X logic logic [WLEN-1:0] adder_x_op_a_blanked, adder_x_op_b, adder_x_op_b_blanked; logic [WLEN-1:0] adder_x_res; @@ -1858,7 +1858,7 @@ generate logic [3:0] expected_logic_res_sel; generate - if (OtbnPQCEn) begin : gen_shift_add_ctrl_pqc + if (AccPQCEn) begin : gen_shift_add_ctrl_pqc alu_vector_type_t expected_vector_type; alu_trn_type_t expected_trn_type; logic expected_vector_sel; @@ -2224,7 +2224,7 @@ generate // SEC_CM: CTRL.REDUN generate - if (OtbnPQCEn) begin : gen_alu_predec_error_pqc + if (AccPQCEn) begin : gen_alu_predec_error_pqc assign alu_predec_error_o = |{expected_adder_x_en != alu_predec_bignum_i.adder_x_en, expected_x_res_operand_a_sel != alu_predec_bignum_i.x_res_operand_a_sel, @@ -2318,7 +2318,7 @@ generate logic adder_y_res_used; generate - if (OtbnPQCEn) begin : gen_output_mux_pqc + if (AccPQCEn) begin : gen_output_mux_pqc always_comb begin operation_result_o = adder_y_res; adder_y_res_used = 1'b1; @@ -2494,7 +2494,7 @@ generate // Tie off unused bits from pqc signals generate - if (OtbnPQCEn) begin : gen_tie_pqc_bits + if (AccPQCEn) begin : gen_tie_pqc_bits assign gen_unused_pqc_bits.unused_pqc_bits = ^{gen_pqc_wsr.ispr_kmac_cfg_bignum_wdata_intg_blanked[311:39], gen_pqc_wsr.ispr_kmac_pw_bignum_wdata_intg_blanked[311:39], @@ -2514,7 +2514,7 @@ generate `ASSERT_KNOWN(ModUsed_A, mod_used) generate - if (OtbnPQCEn) begin : gen_reg_intg_err_pqc + if (AccPQCEn) begin : gen_reg_intg_err_pqc logic kmac_used; assign kmac_used = operation_valid_i & (operation_i.op != AluOpBignumNone) & ( |(ispr_predec_bignum_i.ispr_rd_en[IsprKmacMsg]) | @@ -2548,12 +2548,12 @@ generate // Blanking Assertions // All blanking assertions are reset with predec_error or overall error in the whole system - // -indicated by operation_commit_i port- as OTBN does not guarantee blanking in the case + // -indicated by operation_commit_i port- as ACC does not guarantee blanking in the case // of an error. // adder_x_res related blanking generate - if (OtbnPQCEn) begin : gen_blanking_x_res_pqc + if (AccPQCEn) begin : gen_blanking_x_res_pqc `ASSERT(BlankingBignumAluXOp_A, !expected_adder_x_en |-> {gen_adder_pqc.adder_x_op_a_blanked, gen_adder_pqc.adder_x_op_b_blanked, @@ -2580,7 +2580,7 @@ generate // `a >= b` (thus the result of Adder X has the carry bit set), the result of Adder Y is not used // but it cannot be blanked solely based on the carry bit. generate - if (OtbnPQCEn) begin : gen_blanking_alu_y_res_pqc + if (AccPQCEn) begin : gen_blanking_alu_y_res_pqc `ASSERT(BlankingBignumAluYResUsed_A, !adder_y_res_used && !(operation_i.op == AluOpBignumSubm && gen_adder_pqc.adder_x_res[WLEN+1]) @@ -2628,7 +2628,7 @@ generate clk_i, !rst_ni || ispr_predec_error_o || alu_predec_error_o || !operation_commit_i) generate - if (OtbnPQCEn) begin : gen_kmac_ispr_blanking + if (AccPQCEn) begin : gen_kmac_ispr_blanking // KMAC CFG ISPR Blanking `ASSERT(BlankingIsprKmacCfg_A, !(|gen_pqc_wsr.kmac_cfg_wr_en) |-> diff --git a/hw/ip/otbn/rtl/otbn_controller.sv b/hw/ip/acc/rtl/acc_controller.sv similarity index 96% rename from hw/ip/otbn/rtl/otbn_controller.sv rename to hw/ip/acc/rtl/acc_controller.sv index 81eac51a16c..d54edaaa909 100644 --- a/hw/ip/otbn/rtl/otbn_controller.sv +++ b/hw/ip/acc/rtl/acc_controller.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -12,10 +12,10 @@ `include "prim_assert.sv" /** - * OTBN Controller + * ACC Controller */ -module otbn_controller - import otbn_pkg::*; +module acc_controller + import acc_pkg::*; #( // Size of the instruction memory, in bytes parameter int ImemSizeByte = 4096, @@ -23,7 +23,7 @@ module otbn_controller parameter int DmemSizeByte = 4096, // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1, + parameter bit AccPQCEn = 1'b1, localparam int ImemAddrWidth = prim_util_pkg::vbits(ImemSizeByte), localparam int DmemAddrWidth = prim_util_pkg::vbits(DmemSizeByte) @@ -190,7 +190,7 @@ module otbn_controller import prim_mubi_pkg::*; generate - if (!OtbnPQCEn) begin : gen_unused_ports + if (!AccPQCEn) begin : gen_unused_ports // Tie off unused inputs logic unused_bits; assign unused_bits = ^{kmac_msg_write_ready_i, kmac_msg_pending_write_i, @@ -198,7 +198,7 @@ module otbn_controller end endgenerate - otbn_state_e state_q, state_d; + acc_state_e state_q, state_d; controller_err_bits_t err_bits_q, err_bits_d; @@ -228,7 +228,7 @@ module otbn_controller logic ispr_stall; generate - if (OtbnPQCEn) begin : gen_kmac_nets + if (AccPQCEn) begin : gen_kmac_nets logic kmac_write_stall; logic kmac_digest_req_raw; logic kmac_msg_write_req_raw; @@ -402,7 +402,7 @@ module otbn_controller assign mem_stall = lsu_load_req_raw; assign rf_indirect_stall = insn_valid_i & - (state_q != OtbnStateStall) & + (state_q != AccStateStall) & (insn_dec_shared_i.subset == InsnSubsetBignum) & (insn_dec_bignum_i.rf_a_indirect | insn_dec_bignum_i.rf_b_indirect | @@ -412,7 +412,7 @@ module otbn_controller // Also, writes to the KMAC_MSG register are only // allowed if it can accept new data. generate - if (OtbnPQCEn) begin : gen_ispr_stall_pqc + if (AccPQCEn) begin : gen_ispr_stall_pqc assign ispr_stall = (rnd_req_raw & ~rnd_valid_i) | (gen_kmac_nets.kmac_digest_req_raw & ~kmac_digest_valid_i); @@ -427,14 +427,14 @@ module otbn_controller end endgenerate - // OTBN is done when it was executing something (in state OtbnStateRun or OtbnStateStall) + // ACC is done when it was executing something (in state AccStateRun or AccStateStall) // and either it executes an ecall or an error occurs. A pulse on the done signal raises the // 'done' interrupt and also tells the top-level to update its ERR_BITS status // register. The calculation that ecall triggered done is factored out as `done_complete` to // avoid logic loops in the error handling logic. assign done_complete = (insn_valid_i & insn_dec_shared_i.ecall_insn); - assign executing = (state_q == OtbnStateRun) || - (state_q == OtbnStateStall); + assign executing = (state_q == AccStateRun) || + (state_q == AccStateStall); // Set the *locking* output when the next state is the *locked* state and no secure wipe is // running or there is a URND reseed error. `locking_o` is thus set only after the secure wipe @@ -442,7 +442,7 @@ module otbn_controller // `secure_wipe_req_o` and `urnd_reseed_err_i` will remain high). The condition for secure wipe // running involves `secure_wipe_running_i`, which is high for the initial secure wipe, and // `secure_wipe_req_o`, which is high for post-execution secure wipes. - assign locking_o = (state_d == OtbnStateLocked) & (~(secure_wipe_running_i | secure_wipe_req_o) | + assign locking_o = (state_d == AccStateLocked) & (~(secure_wipe_running_i | secure_wipe_req_o) | urnd_reseed_err_i | mubi_err_d); assign start_secure_wipe = executing & (done_complete | err); @@ -481,30 +481,30 @@ module otbn_controller state_error = 1'b0; unique case (state_q) - OtbnStateHalt: begin + AccStateHalt: begin if (start_i) begin - state_d = OtbnStateRun; + state_d = AccStateRun; insn_fetch_req_addr_o = '0; insn_fetch_req_valid_raw = 1'b1; prefetch_en_o = 1'b1; end end - OtbnStateRun: begin + AccStateRun: begin insn_fetch_req_valid_raw = 1'b1; prefetch_en_o = 1'b1; if (!insn_valid_i) begin insn_fetch_req_addr_o = insn_fetch_req_addr_last; end else if (done_complete) begin - state_d = OtbnStateHalt; + state_d = AccStateHalt; insn_fetch_req_valid_raw = 1'b0; prefetch_en_o = 1'b0; end else begin if (stall) begin // When stalling don't request a new fetch and don't clear response either to keep // current instruction. - state_d = OtbnStateStall; + state_d = AccStateStall; insn_fetch_req_valid_raw = 1'b0; insn_fetch_resp_clear_o = 1'b0; end else begin @@ -518,11 +518,11 @@ module otbn_controller end end end - OtbnStateStall: begin + AccStateStall: begin prefetch_en_o = 1'b1; // When stalling refetch the same instruction to keep decode inputs constant if (stall) begin - state_d = OtbnStateStall; + state_d = AccStateStall; //insn_fetch_req_addr_o = insn_addr_i; insn_fetch_req_valid_raw = 1'b0; insn_fetch_resp_clear_o = 1'b0; @@ -535,37 +535,37 @@ module otbn_controller insn_fetch_req_addr_o = next_insn_addr; end - state_d = OtbnStateRun; + state_d = AccStateRun; end end - OtbnStateLocked: begin + AccStateLocked: begin insn_fetch_req_valid_raw = 1'b0; - state_d = OtbnStateLocked; + state_d = AccStateLocked; end default: begin // We should never get here. If we do (e.g. via a malicious glitch), error out immediately. // SEC_CM: CONTROLLER.FSM.LOCAL_ESC - state_d = OtbnStateLocked; + state_d = AccStateLocked; state_error = 1'b1; end endcase - // On any error immediately halt, either going to OtbnStateLocked or OtbnStateHalt depending on + // On any error immediately halt, either going to AccStateLocked or AccStateHalt depending on // whether it was a fatal error. if (err) begin insn_fetch_resp_clear_o = 1'b1; if (fatal_err) begin // SEC_CM: CONTROLLER.FSM.GLOBAL_ESC - state_d = OtbnStateLocked; + state_d = AccStateLocked; end else begin - state_d = OtbnStateHalt; + state_d = AccStateHalt; end end // Regardless of what happens above enforce staying in OtnbStateLocked. - if (state_q == OtbnStateLocked) begin - state_d = OtbnStateLocked; + if (state_q == AccStateLocked) begin + state_d = AccStateLocked; end end @@ -582,10 +582,10 @@ module otbn_controller .q_o(state_error_q) ); - `ASSERT(InsnAlwaysValidInStall, state_q == OtbnStateStall |-> insn_valid_i) + `ASSERT(InsnAlwaysValidInStall, state_q == AccStateStall |-> insn_valid_i) // Anything that moves us or keeps us in the stall state should cause `stall` to be asserted - `ASSERT(StallIfNextStateStall, insn_valid_i & (state_d == OtbnStateStall) |-> stall) + `ASSERT(StallIfNextStateStall, insn_valid_i & (state_d == AccStateStall) |-> stall) // The raw signal is needed by the instruction fetch stage for generating instruction address // errors (where instruction fetch and prefetch disagree on address). `err` will factor this in so @@ -712,7 +712,7 @@ module otbn_controller mubi4_test_true_strict(rma_req_i)}; assign recoverable_err_o = recoverable_err | (software_err & ~software_errs_fatal_i); - assign mems_sec_wipe_o = (state_d == OtbnStateLocked) & (state_q != OtbnStateLocked); + assign mems_sec_wipe_o = (state_d == AccStateLocked) & (state_q != AccStateLocked); assign internal_err = software_err | internal_fatal_err; assign err = software_err | recoverable_err | fatal_err; @@ -731,20 +731,20 @@ module otbn_controller `ASSERT(SoftwareErrIfNonInsnAddrSoftwareErr, non_insn_addr_software_err |-> software_err) `ASSERT(ControllerStateValid, - state_q inside {OtbnStateHalt, OtbnStateRun, OtbnStateStall, OtbnStateLocked}) - // Branch only takes effect in OtbnStateRun so must not go into stall state for branch + state_q inside {AccStateHalt, AccStateRun, AccStateStall, AccStateLocked}) + // Branch only takes effect in AccStateRun so must not go into stall state for branch // instructions. `ASSERT(NoStallOnBranch, - insn_valid_i & insn_dec_shared_i.branch_insn |-> state_q != OtbnStateStall) + insn_valid_i & insn_dec_shared_i.branch_insn |-> state_q != AccStateStall) // SEC_CM: CONTROLLER.FSM.SPARSE - `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, otbn_state_e, OtbnStateHalt) + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, acc_state_e, AccStateHalt) // SEC_CM: CTRL_FLOW.COUNT - // Two explicit clear controls, one comes from external to otbn_core and the other is generated - // internally (by otbn_start_stop_control). + // Two explicit clear controls, one comes from external to acc_core and the other is generated + // internally (by acc_start_stop_control). assign insn_cnt_clear = - (state_q == OtbnStateLocked) | insn_cnt_clear_ext_i | insn_cnt_clear_int_i; + (state_q == AccStateLocked) | insn_cnt_clear_ext_i | insn_cnt_clear_int_i; always_comb begin if (insn_cnt_clear) begin @@ -768,9 +768,9 @@ module otbn_controller assign loop_reset = state_reset_i | sec_wipe_zero_i; - otbn_loop_controller #( + acc_loop_controller #( .ImemAddrWidth(ImemAddrWidth) - ) u_otbn_loop_controller ( + ) u_acc_loop_controller ( .clk_i, .rst_ni, @@ -794,7 +794,7 @@ module otbn_controller .predec_err_o (loop_predec_err), .jump_or_branch_i(jump_or_branch), - .otbn_stall_i (stall), + .acc_stall_i (stall), .prefetch_loop_active_o, .prefetch_loop_iterations_o, @@ -1003,7 +1003,7 @@ module otbn_controller // Bignum RF control signals from the controller aren't actually used, instead the predecoded // one-hot versions are. The predecoded versions get checked against the signals produced here. - // Buffer them to ensure they don't get optimised away (with a functionally correct OTBN they will + // Buffer them to ensure they don't get optimised away (with a functionally correct ACC they will // always be identical). assign rf_bignum_rd_addr_a_unbuf = insn_dec_bignum_i.rf_a_indirect ? insn_bignum_rd_addr_a_q : insn_dec_bignum_i.a; @@ -1016,7 +1016,7 @@ module otbn_controller ); generate - if (OtbnPQCEn) begin : gen_bignum_rd_unbuf_pqc + if (AccPQCEn) begin : gen_bignum_rd_unbuf_pqc assign rf_bignum_rd_en_a_unbuf = insn_dec_bignum_i.rf_ren_a & insn_valid_i & (~stall | gen_kmac_nets.kmac_write_stall); @@ -1130,7 +1130,7 @@ module otbn_controller // Bignum Register file write control generate - if (OtbnPQCEn) begin : gen_bignum_wr_ctrl_pqc + if (AccPQCEn) begin : gen_bignum_wr_ctrl_pqc always_comb begin // By default write nothing rf_bignum_wr_en_unbuf = 2'b00; @@ -1173,7 +1173,7 @@ module otbn_controller // Bignum RF control signals from the controller aren't actually used, instead the predecoded // one-hot versions are. The predecoded versions get checked against the signals produced here. - // Buffer them to ensure they don't get optimised away (with a functionally correct OTBN they + // Buffer them to ensure they don't get optimised away (with a functionally correct ACC they // will always be identical). prim_buf #( .Width(2) @@ -1232,7 +1232,7 @@ module otbn_controller // Bignum RF control signals from the controller aren't actually used, instead the predecoded // one-hot versions are. The predecoded versions get checked against the signals produced here. - // Buffer them to ensure they don't get optimised away (with a functionally correct OTBN they will + // Buffer them to ensure they don't get optimised away (with a functionally correct ACC they will // always be identical). assign rf_bignum_wr_addr_unbuf = insn_dec_bignum_i.rf_d_indirect ? insn_bignum_wr_addr_q : insn_dec_bignum_i.d; @@ -1352,7 +1352,7 @@ module otbn_controller // The csr_rdata mux logic takes care of producing the 0. end CsrKmacCfg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr_base = IsprKmacCfg; ispr_word_addr_base = '0; end else begin @@ -1360,7 +1360,7 @@ module otbn_controller end end CsrKmacStatus: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr_base = IsprKmacStatus; ispr_word_addr_base = '0; end else begin @@ -1368,7 +1368,7 @@ module otbn_controller end end CsrKmacPartialW: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr_base = IsprKmacPartialW; ispr_word_addr_base = '0; end else begin @@ -1513,28 +1513,28 @@ module otbn_controller WsrUrnd: ispr_addr_bignum = IsprUrnd; WsrAcc: ispr_addr_bignum = IsprAcc; WsrKmacMsg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr_bignum = IsprKmacMsg; end else begin wsr_illegal_addr = 1'b1; end end WsrKmacCfg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr_bignum = IsprKmacCfg; end else begin wsr_illegal_addr = 1'b1; end end WsrKmacDigest: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr_bignum = IsprKmacDigest; end else begin wsr_illegal_addr = 1'b1; end end WsrAccH: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr_bignum = IsprAccH; end else begin wsr_illegal_addr = 1'b1; @@ -1619,7 +1619,7 @@ module otbn_controller // lsu_load_req_raw/lsu_store_req_raw indicate an instruction wishes to perform a store or a load. // lsu_load_req_o/lsu_store_req_o factor in whether an instruction is actually executing (it may // be suppressed due an error) and command the load or store to happen when asserted. - assign lsu_load_req_raw = insn_valid_i & insn_dec_shared_i.ld_insn & (state_q == OtbnStateRun); + assign lsu_load_req_raw = insn_valid_i & insn_dec_shared_i.ld_insn & (state_q == AccStateRun); assign lsu_load_req_o = insn_executing & lsu_load_req_raw; assign lsu_store_req_raw = insn_valid_i & insn_dec_shared_i.st_insn & ~rf_indirect_stall; @@ -1707,7 +1707,7 @@ module otbn_controller dmem_addr_unaligned_base); generate - if (OtbnPQCEn) begin : gen_kmac_raw + if (AccPQCEn) begin : gen_kmac_raw assign gen_kmac_nets.kmac_digest_req_raw = insn_valid_i & ispr_rd_insn & (ispr_addr_o == IsprKmacDigest); assign gen_kmac_nets.kmac_msg_write_req_raw = insn_valid_i & ispr_wr_insn & diff --git a/hw/ip/otbn/rtl/otbn_core.sv b/hw/ip/acc/rtl/acc_core.sv similarity index 95% rename from hw/ip/otbn/rtl/otbn_core.sv rename to hw/ip/acc/rtl/acc_core.sv index 18d4ca02431..aeb5ebe4fbf 100644 --- a/hw/ip/otbn/rtl/otbn_core.sv +++ b/hw/ip/acc/rtl/acc_core.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -12,17 +12,17 @@ `include "prim_assert.sv" /** - * OpenTitan Big Number Accelerator (OTBN) Core + * OpenTitan Big Number Accelerator (ACC) Core * - * This module is the top-level of the OTBN processing core. + * This module is the top-level of the ACC processing core. */ -// Below countermeasure (no data dependent control flow in OTBN ISA) is inherent to the design and +// Below countermeasure (no data dependent control flow in ACC ISA) is inherent to the design and // has no directly associated RTL // SEC_CM: CTRL_FLOW.SCA -module otbn_core - import otbn_pkg::*; +module acc_core + import acc_pkg::*; #( - // Register file implementation selection, see otbn_pkg.sv. + // Register file implementation selection, see acc_pkg.sv. parameter regfile_e RegFile = RegFileFF, // Size of the instruction memory, in bytes @@ -31,7 +31,7 @@ module otbn_core parameter int DmemSizeByte = 4096, // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1, + parameter bit AccPQCEn = 1'b1, // Default seed for URND PRNG parameter urnd_prng_seed_t RndCnstUrndPrngSeed = RndCnstUrndPrngSeedDefault, @@ -114,7 +114,7 @@ module otbn_core import prim_mubi_pkg::*; // Create a lint error to reduce the risk of accidentally enabling this feature. - `ASSERT_STATIC_LINT_ERROR(OtbnSecMuteUrndNonDefault, SecMuteUrnd == 0) + `ASSERT_STATIC_LINT_ERROR(AccSecMuteUrndNonDefault, SecMuteUrnd == 0) // Fetch request (the next instruction) logic [ImemAddrWidth-1:0] insn_fetch_req_addr; @@ -308,13 +308,13 @@ module otbn_core logic req_sec_wipe_urnd_keys_q; - // Start stop control start OTBN execution when requested and deals with any pre start or post + // Start stop control start ACC execution when requested and deals with any pre start or post // stop actions. - otbn_start_stop_control #( - .OtbnPQCEn(OtbnPQCEn), + acc_start_stop_control #( + .AccPQCEn(AccPQCEn), .SecMuteUrnd(SecMuteUrnd), .SecSkipUrndReseedAtStart(SecSkipUrndReseedAtStart) - ) u_otbn_start_stop_control ( + ) u_acc_start_stop_control ( .clk_i, .rst_ni, @@ -364,10 +364,10 @@ module otbn_core assign zero_flags = sec_wipe_zero | ispr_init; // Instruction fetch unit - otbn_instruction_fetch #( + acc_instruction_fetch #( .ImemSizeByte(ImemSizeByte), - .OtbnPQCEn(OtbnPQCEn) - ) u_otbn_instruction_fetch ( + .AccPQCEn(AccPQCEn) + ) u_acc_instruction_fetch ( .clk_i, .rst_ni, @@ -417,9 +417,9 @@ module otbn_core ); // Instruction decoder - otbn_decoder #( - .OtbnPQCEn(OtbnPQCEn) - ) u_otbn_decoder ( + acc_decoder #( + .AccPQCEn(AccPQCEn) + ) u_acc_decoder ( // The decoder is combinatorial; clk and rst are only used for assertions. .clk_i, .rst_ni, @@ -459,11 +459,11 @@ module otbn_core // Controller: coordinate between functional units, prepare their inputs (e.g. by muxing between // operand sources), and post-process their outputs as needed. - otbn_controller #( + acc_controller #( .ImemSizeByte(ImemSizeByte), .DmemSizeByte(DmemSizeByte), - .OtbnPQCEn(OtbnPQCEn) - ) u_otbn_controller ( + .AccPQCEn(AccPQCEn) + ) u_acc_controller ( .clk_i, .rst_ni, @@ -615,7 +615,7 @@ module otbn_core .predec_error_o (controller_predec_error) ); - `ASSERT(InsnDataStableInStall, u_otbn_controller.state_q == OtbnStateStall |-> + `ASSERT(InsnDataStableInStall, u_acc_controller.state_q == AccStateStall |-> insn_fetch_resp_data == $past(insn_fetch_resp_data)) // Spot the fatal error bits from the controller @@ -629,7 +629,7 @@ module otbn_core |{alu_bignum_reg_intg_violation_err, mac_bignum_reg_intg_violation_err, rf_base_intg_err}; - // Generate an err_bits output by combining errors from all the blocks in otbn_core + // Generate an err_bits output by combining errors from all the blocks in acc_core assign err_bits_d = '{ fatal_software: controller_err_bits.fatal_software, bad_internal_state: |{controller_err_bits.bad_internal_state, @@ -667,7 +667,7 @@ module otbn_core assign err_bits_o = err_bits_q | err_bits_d; // Pass an "escalation" signal down to the controller by ORing in error signals from the other - // modules in otbn_core. Note that each error signal except escalate_en_i that appears here also + // modules in acc_core. Note that each error signal except escalate_en_i that appears here also // appears somewhere in err_bits_o above (checked in ErrBitsIfControllerEscalate_A) assign controller_fatal_escalate_en = mubi4_or_hi(escalate_en_i, @@ -694,9 +694,9 @@ module otbn_core assign insn_cnt_o = insn_cnt; // Load store unit: read and write data from data memory - otbn_lsu #( + acc_lsu #( .DmemSizeByte(DmemSizeByte) - ) u_otbn_lsu ( + ) u_acc_lsu ( .clk_i, .rst_ni, @@ -726,9 +726,9 @@ module otbn_core // Base Instruction Subset ======================================================================= - otbn_rf_base #( + acc_rf_base #( .RegFile(RegFile) - ) u_otbn_rf_base ( + ) u_acc_rf_base ( .clk_i, .rst_ni, @@ -780,7 +780,7 @@ module otbn_core assign rf_base_wr_sec_wipe_err = sec_wipe_base & ~secure_wipe_running_o; - otbn_alu_base u_otbn_alu_base ( + acc_alu_base u_acc_alu_base ( .clk_i, .rst_ni, @@ -790,9 +790,9 @@ module otbn_core .comparison_result_o(alu_base_comparison_result) ); - otbn_rf_bignum #( + acc_rf_bignum #( .RegFile(RegFile) - ) u_otbn_rf_bignum ( + ) u_acc_rf_bignum ( .clk_i, .rst_ni, @@ -855,9 +855,9 @@ module otbn_core assign rf_bignum_wr_sec_wipe_err = sec_wipe_wdr_q & ~secure_wipe_running_o; - otbn_alu_bignum #( - .OtbnPQCEn(OtbnPQCEn) - ) u_otbn_alu_bignum ( + acc_alu_bignum #( + .AccPQCEn(AccPQCEn) + ) u_acc_alu_bignum ( .clk_i, .rst_ni, @@ -915,9 +915,9 @@ module otbn_core .ispr_predec_error_o(ispr_predec_error) ); - otbn_mac_bignum #( - .OtbnPQCEn(OtbnPQCEn) - ) u_otbn_mac_bignum ( + acc_mac_bignum #( + .AccPQCEn(AccPQCEn) + ) u_acc_mac_bignum ( .clk_i, .rst_ni, @@ -948,9 +948,9 @@ module otbn_core .ispr_acc_wr_en_i (ispr_acc_wr_en) ); - otbn_rnd #( + acc_rnd #( .RndCnstUrndPrngSeed(RndCnstUrndPrngSeed) - ) u_otbn_rnd ( + ) u_acc_rnd ( .clk_i, .rst_ni, @@ -1046,23 +1046,23 @@ module otbn_core // for URND data" and "do the secure wipe once it arrives" is duplicated in the Python model, // against which the RTL is checked. - `ASSERT(OtbnStartStopGlobalEscCntrMeasure_A, err_bits_q && mubi4_test_true_loose(escalate_en_i) + `ASSERT(AccStartStopGlobalEscCntrMeasure_A, err_bits_q && mubi4_test_true_loose(escalate_en_i) && mubi4_test_true_loose(start_stop_escalate_en)|=> ##[1:4000] - u_otbn_start_stop_control.state_q == otbn_pkg::OtbnStartStopStateLocked) + u_acc_start_stop_control.state_q == acc_pkg::AccStartStopStateLocked) - `ASSERT(OtbnStartStopLocalEscCntrMeasure_A, err_bits_q && mubi4_test_false_strict(escalate_en_i) + `ASSERT(AccStartStopLocalEscCntrMeasure_A, err_bits_q && mubi4_test_false_strict(escalate_en_i) && mubi4_test_true_loose(start_stop_escalate_en) |=> ##[1:4000] - u_otbn_start_stop_control.state_q == otbn_pkg::OtbnStartStopStateLocked) + u_acc_start_stop_control.state_q == acc_pkg::AccStartStopStateLocked) // In contrast to the start/stop FSM, the controller FSM should lock quickly after an escalation, // independent of the secure wipe. - `ASSERT(OtbnControllerGlobalEscCntrMeasure_A, err_bits_q && mubi4_test_true_loose(escalate_en_i) + `ASSERT(AccControllerGlobalEscCntrMeasure_A, err_bits_q && mubi4_test_true_loose(escalate_en_i) && mubi4_test_true_loose(controller_fatal_escalate_en)|=> ##[1:100] - u_otbn_controller.state_q == otbn_pkg::OtbnStateLocked) + u_acc_controller.state_q == acc_pkg::AccStateLocked) - `ASSERT(OtbnControllerLocalEscCntrMeasure_A, err_bits_q && mubi4_test_false_strict(escalate_en_i) + `ASSERT(AccControllerLocalEscCntrMeasure_A, err_bits_q && mubi4_test_false_strict(escalate_en_i) && mubi4_test_true_loose(controller_fatal_escalate_en) |=> ##[1:100] - u_otbn_controller.state_q == otbn_pkg::OtbnStateLocked) + u_acc_controller.state_q == acc_pkg::AccStateLocked) endmodule diff --git a/hw/ip/otbn/rtl/otbn_decoder.sv b/hw/ip/acc/rtl/acc_decoder.sv similarity index 96% rename from hw/ip/otbn/rtl/otbn_decoder.sv rename to hw/ip/acc/rtl/acc_decoder.sv index 027c9186658..fa463afff28 100644 --- a/hw/ip/otbn/rtl/otbn_decoder.sv +++ b/hw/ip/acc/rtl/acc_decoder.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -12,13 +12,13 @@ `include "prim_assert.sv" /** - * OTBN instruction Decoder + * ACC instruction Decoder */ -module otbn_decoder - import otbn_pkg::*; +module acc_decoder + import acc_pkg::*; #( // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1 + parameter bit AccPQCEn = 1'b1 ) ( // For assertions only. input logic clk_i, @@ -71,7 +71,7 @@ module otbn_decoder logic [31:0] imm_u_type_base; logic [31:0] imm_j_type_base; - // Immediates specific to OTBN encoding + // Immediates specific to ACC encoding logic [31:0] imm_l_type_base; logic [31:0] imm_x_type_base; @@ -225,7 +225,7 @@ module otbn_decoder ShamtSelBignumS: alu_shift_amt_bignum = shift_amt_s_type_bignum; // Vector is only valid case during PQC mode ShamtSelBignumV: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin alu_shift_amt_bignum = shift_amt_v_type_bignum_pqc; end else begin // Use the default case @@ -277,9 +277,9 @@ module otbn_decoder mac_flag_en: mac_flag_en_bignum, alu_op: alu_operator_bignum, // Vector assignments depend on PQC parameter - vector_type: OtbnPQCEn ? alu_vector_type_bignum_pqc : alu_vector_type_t'(2'b0), - vector_sel: OtbnPQCEn ? alu_vector_sel_bignum_pqc : 1'b0, - alu_trn_type: OtbnPQCEn ? alu_trn_type_bignum_pqc : alu_trn_type_t'(3'b0), + vector_type: AccPQCEn ? alu_vector_type_bignum_pqc : alu_vector_type_t'(2'b0), + vector_sel: AccPQCEn ? alu_vector_sel_bignum_pqc : 1'b0, + alu_trn_type: AccPQCEn ? alu_trn_type_bignum_pqc : alu_trn_type_t'(3'b0), // Normal assignments alu_op_b_sel: alu_op_b_mux_sel_bignum, mac_op_a_qw_sel: mac_op_a_qw_sel_bignum, @@ -289,13 +289,13 @@ module otbn_decoder mac_zero_acc: mac_zero_acc_bignum, mac_shift_out: mac_shift_out_bignum, // Vector assignments depend on PQC parameter - mac_mulv: OtbnPQCEn ? mac_mulv_pqc : 1'b0, - mac_data_type: OtbnPQCEn ? mac_data_type_pqc : 1'b0, - mac_sel: OtbnPQCEn ? mac_sel_pqc : 1'b0, - mac_lane_mode: OtbnPQCEn ? mac_lane_mode_pqc : 1'b0, - mac_lane_word_32: OtbnPQCEn ? mac_lane_word_32_pqc : 1'b0, - mac_lane_word_16: OtbnPQCEn ? mac_lane_word_16_pqc : 1'b0, - mac_exec_mode: OtbnPQCEn ? mac_exec_mode_pqc : 2'b00, + mac_mulv: AccPQCEn ? mac_mulv_pqc : 1'b0, + mac_data_type: AccPQCEn ? mac_data_type_pqc : 1'b0, + mac_sel: AccPQCEn ? mac_sel_pqc : 1'b0, + mac_lane_mode: AccPQCEn ? mac_lane_mode_pqc : 1'b0, + mac_lane_word_32: AccPQCEn ? mac_lane_word_32_pqc : 1'b0, + mac_lane_word_16: AccPQCEn ? mac_lane_word_16_pqc : 1'b0, + mac_exec_mode: AccPQCEn ? mac_exec_mode_pqc : 2'b00, // Normal assignments mac_en: mac_en_bignum, rf_we: rf_we_bignum, @@ -568,10 +568,10 @@ module otbn_decoder unique case(insn[14:12]) // Arithmetic opcode includes SUBV/ADDV instructions - // that should not be valid outside OtbnPQCEn + // that should not be valid outside AccPQCEn 3'b101: begin if (insn_alu[25]) begin - if (!OtbnPQCEn) begin + if (!AccPQCEn) begin illegal_insn = 1'b1; end end @@ -747,7 +747,7 @@ module otbn_decoder /////////////////////////////////////////// InsnOpcodeBignumMulv: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin unique case (insn_alu[14:12]) 3'b110: begin insn_subset = InsnSubsetBignum; @@ -788,7 +788,7 @@ module otbn_decoder //////////////////////////////////////////// InsnOpcodeBignumShiftv: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin insn_subset = InsnSubsetBignum; rf_ren_b_bignum = 1'b1; rf_wdata_sel_bignum = RfWdSelEx; @@ -804,7 +804,7 @@ module otbn_decoder //////////////////////////////////////////// InsnOpcodeBignumTrn: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin insn_subset = InsnSubsetBignum; rf_ren_a_bignum = 1'b1; rf_ren_b_bignum = 1'b1; @@ -987,7 +987,7 @@ module otbn_decoder 3'b101: begin if (insn_alu[30]) begin if (insn_alu[25]) begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin if (insn[27]) begin alu_operator_bignum = AluOpBignumSubvm; end else begin @@ -1000,7 +1000,7 @@ module otbn_decoder end end else begin if (insn_alu[25]) begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin if (insn[27]) begin alu_operator_bignum = AluOpBignumAddvm; end else begin @@ -1109,7 +1109,7 @@ module otbn_decoder //////////////////////////////////////////// InsnOpcodeBignumShiftv: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin shift_amt_mux_sel_bignum = ShamtSelBignumV; alu_operator_bignum = AluOpBignumShv; alu_op_b_mux_sel_bignum = OpBSelRegister; @@ -1123,7 +1123,7 @@ module otbn_decoder //////////////////////////////////////////// InsnOpcodeBignumTrn: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin alu_op_b_mux_sel_bignum = OpBSelRegister; alu_operator_bignum = AluOpBignumTrn; end diff --git a/hw/ip/otbn/rtl/otbn_instruction_fetch.sv b/hw/ip/acc/rtl/acc_instruction_fetch.sv similarity index 97% rename from hw/ip/otbn/rtl/otbn_instruction_fetch.sv rename to hw/ip/acc/rtl/acc_instruction_fetch.sv index 1cf46260400..b37c6846305 100644 --- a/hw/ip/otbn/rtl/otbn_instruction_fetch.sv +++ b/hw/ip/acc/rtl/acc_instruction_fetch.sv @@ -6,16 +6,16 @@ `include "prim_assert.sv" /** - * OTBN Instruction Fetch Unit + * ACC Instruction Fetch Unit * * Fetch an instruction from the instruction memory. */ -module otbn_instruction_fetch - import otbn_pkg::*; +module acc_instruction_fetch + import acc_pkg::*; #( parameter int ImemSizeByte = 4096, // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1, + parameter bit AccPQCEn = 1'b1, localparam int ImemAddrWidth = prim_util_pkg::vbits(ImemSizeByte) ) ( @@ -131,10 +131,10 @@ module otbn_instruction_fetch end // SEC_CM: DATA_REG_SW.SCA - otbn_predecode #( + acc_predecode #( .ImemSizeByte(ImemSizeByte), - .OtbnPQCEn(OtbnPQCEn) - ) u_otbn_predecode ( + .AccPQCEn(AccPQCEn) + ) u_acc_predecode ( .clk_i, .rst_ni, @@ -332,7 +332,7 @@ module otbn_instruction_fetch // important for timing reasons so errors don't factor into the `imem_addr_o` signal. if (!insn_fetch_req_valid_raw_i) begin // Keep prefetching the same instruction when a new one isn't being requested. In this - // scenario OTBN is stalled and will eventually want the prefetched instruction. + // scenario ACC is stalled and will eventually want the prefetched instruction. imem_addr_o = insn_prefetch_addr; end else if (insn_prefetch_fail) begin // When prefetching has failed prefetch the requested address @@ -354,7 +354,7 @@ module otbn_instruction_fetch // timing consistent regardless of taken/not-taken. This also applies to jumps, this avoids // the need to calculate the jump address here. // - // For x-prop reasons we do not suppress the imem_req_o here. When OTBN executes an + // For x-prop reasons we do not suppress the imem_req_o here. When ACC executes an // instruction that produces a software error it comes to an immediate halt. However only // the raw fetch request is considered here for timing reasons. So if the instruction // following the error causing instruction is X in simulation the `insn_is_branch` sees an @@ -363,7 +363,7 @@ module otbn_instruction_fetch // // The imem_rvalid_kill signal is used to avoid the X prop issue. This suppresses the // imem_rvalid signal the following cycle. Whilst imem_rvalid_kill itself will go X if - // imem_rdata_i is X, as OTBN has halted following the error this doesn't cause a problem. + // imem_rdata_i is X, as ACC has halted following the error this doesn't cause a problem. imem_rvalid_kill_d = 1'b1; insn_prefetch = 1'b0; end diff --git a/hw/ip/otbn/rtl/otbn_loop_controller.sv b/hw/ip/acc/rtl/acc_loop_controller.sv similarity index 97% rename from hw/ip/otbn/rtl/otbn_loop_controller.sv rename to hw/ip/acc/rtl/acc_loop_controller.sv index 4be687e247a..f6689c2c6e0 100644 --- a/hw/ip/otbn/rtl/otbn_loop_controller.sv +++ b/hw/ip/acc/rtl/acc_loop_controller.sv @@ -4,8 +4,8 @@ `include "prim_assert.sv" -module otbn_loop_controller - import otbn_pkg::*; +module acc_loop_controller + import acc_pkg::*; #( parameter int ImemAddrWidth = 12 ) ( @@ -37,7 +37,7 @@ module otbn_loop_controller output [ImemAddrWidth-1:0] prefetch_loop_jump_addr_o, input jump_or_branch_i, - input otbn_stall_i + input acc_stall_i ); // The ISA has a fixed 12 bits for loop_bodysize. The maximum possible address for the end of a // loop is the maximum address in Imem (2^ImemAddrWidth - 4) plus loop_bodysize instructions @@ -151,7 +151,7 @@ module otbn_loop_controller // the current loop with 1 iteration that is the end of the final iteration and the current loop // finishes. assign current_loop_finish = at_current_loop_end_insn & (current_loop.loop_iterations == 1) - & ~otbn_stall_i; + & ~acc_stall_i; // Jump to top of current loop when execution reaches the end instruction of the current loop it // isn't finished. @@ -169,14 +169,14 @@ module otbn_loop_controller loop_at_end_err; // Decrement current loop counter when execution reaches the end instruction - assign current_loop_counter_dec = ~state_reset_i & ~otbn_stall_i & at_current_loop_end_insn; + assign current_loop_counter_dec = ~state_reset_i & ~acc_stall_i & at_current_loop_end_insn; // Push current loop to the loop stack when a new loop starts (LOOP instruction executed). // loop_stack_push_req indicates a push is requested, loop_stack_commit must also be asserted // (when the loop start is committed) for it to take effect. assign loop_stack_push_req = loop_start_req_i; - // The OTBN controller must not commit a loop request if it sees a loop error. + // The ACC controller must not commit a loop request if it sees a loop error. `ASSERT(NoStartCommitIfLoopErr, loop_start_req_i && loop_start_commit_i |-> !sw_err_o) // Pop from the loop stack when the current loop finishes. Stack internally checks to see if it's @@ -189,7 +189,7 @@ module otbn_loop_controller // do. assign loop_stack_commit = loop_stack_push_req ? loop_start_commit_i : loop_stack_pop; - otbn_stack #( + acc_stack #( .StackWidth($bits(loop_addr_info_t)), .StackDepth(LoopStackDepth) ) loop_info_stack ( diff --git a/hw/ip/otbn/rtl/otbn_lsu.sv b/hw/ip/acc/rtl/acc_lsu.sv similarity index 98% rename from hw/ip/otbn/rtl/otbn_lsu.sv rename to hw/ip/acc/rtl/acc_lsu.sv index f507590e6eb..8ac01528808 100644 --- a/hw/ip/otbn/rtl/otbn_lsu.sv +++ b/hw/ip/acc/rtl/acc_lsu.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" /** - * OTBN Load-Store Unit + * ACC Load-Store Unit * * Read and write data from/to the data memory (DMEM). Used by the base and the BN instruction * subset; loads and stores are hence either 32b or WLEN bit wide. @@ -14,8 +14,8 @@ * - All requests are answered in the next cycle; the LSU must have exclusive access to the memory. * - The write mask supports aligned 32b write accesses. */ -module otbn_lsu - import otbn_pkg::*; +module acc_lsu + import acc_pkg::*; #( parameter int DmemSizeByte = 4096, diff --git a/hw/ip/otbn/rtl/otbn_mac_bignum.sv b/hw/ip/acc/rtl/acc_mac_bignum.sv similarity index 96% rename from hw/ip/otbn/rtl/otbn_mac_bignum.sv rename to hw/ip/acc/rtl/acc_mac_bignum.sv index 7e6b02e6a23..1fc8995805d 100644 --- a/hw/ip/otbn/rtl/otbn_mac_bignum.sv +++ b/hw/ip/acc/rtl/acc_mac_bignum.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -11,11 +11,11 @@ `include "prim_assert.sv" -module otbn_mac_bignum - import otbn_pkg::*; +module acc_mac_bignum + import acc_pkg::*; #( // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1 + parameter bit AccPQCEn = 1'b1 ) ( input logic clk_i, input logic rst_ni, @@ -49,11 +49,11 @@ module otbn_mac_bignum // The MAC operates on quarter-words, QWLEN gives the number of bits in a quarter-word. localparam int unsigned QWLEN = WLEN / 4; // Width of adder and mul nets based on PQC enable - localparam int ADDER_WIDTH = (OtbnPQCEn) ? 2*WLEN : WLEN; + localparam int ADDER_WIDTH = (AccPQCEn) ? 2*WLEN : WLEN; // Tie unused ports to '0 generate - if (!OtbnPQCEn) begin : gen_unused_outputs + if (!AccPQCEn) begin : gen_unused_outputs // Tie off unused inputs logic unused_bits; assign unused_bits = ^{operation_i.sel, operation_i.lane_mode, operation_i.lane_word_32, @@ -108,7 +108,7 @@ module otbn_mac_bignum assign unused_ok = ^(rst_ni); generate - if (OtbnPQCEn) begin : gen_mul_pqc + if (AccPQCEn) begin : gen_mul_pqc unified_mul mul ( // 00 = 64x64, 11 = 4x32x32, 10 = 16x16x16 .word_mode ({operation_i.mulv, operation_i.data_type}), @@ -125,7 +125,7 @@ module otbn_mac_bignum .result (mul_res_shifted) ); end else begin : gen_mul - otbn_bignum_mul mul ( + acc_bignum_mul mul ( .A (operand_a_blanked), .B (operand_b_blanked), .word_sel_A (operation_i.operand_a_qw_sel), @@ -158,7 +158,7 @@ module otbn_mac_bignum end generate - if (OtbnPQCEn) begin : gen_acch_reg + if (AccPQCEn) begin : gen_acch_reg // ECC encode and decode of accumulator high register logic [WLEN-1:0] acch_no_intg_d; logic [WLEN-1:0] acch_no_intg_q; @@ -188,7 +188,7 @@ module otbn_mac_bignum assign acc_used = mac_en_i & ~operation_i.zero_acc; generate - if (OtbnPQCEn) begin : gen_op_intg_err_pqc + if (AccPQCEn) begin : gen_op_intg_err_pqc // If the MAC is enabled then the ACCH integrity error should be propagated directly assign operation_intg_violation_err_o = (acc_used & |(acc_intg_err)) | (mac_en_i & |(gen_acch_reg.acch_intg_err)); @@ -208,7 +208,7 @@ module otbn_mac_bignum ); generate - if (OtbnPQCEn) begin : gen_acch_blanker + if (AccPQCEn) begin : gen_acch_blanker logic [WLEN-1:0] acch_blanked; prim_blanker #(.Width(WLEN)) u_acch_blanker ( @@ -222,7 +222,7 @@ module otbn_mac_bignum assign adder_op_a = mul_res_shifted; generate - if (OtbnPQCEn) begin : gen_adder_op_pqc + if (AccPQCEn) begin : gen_adder_op_pqc // Add shifted multiplier result to current accumulator. assign adder_op_b = {gen_acch_blanker.acch_blanked, acc_blanked}; end else begin : gen_adder_op @@ -232,7 +232,7 @@ module otbn_mac_bignum endgenerate generate - if (OtbnPQCEn) begin : gen_mac_adder_pqc + if (AccPQCEn) begin : gen_mac_adder_pqc vec_type_e mode; assign mode = operation_i.mulv ? (operation_i.data_type == 1'b0 ? VecType_s32 : VecType_d64) : VecType_v256; @@ -348,7 +348,7 @@ module otbn_mac_bignum // ACCH generate - if (OtbnPQCEn) begin : gen_acch_wr_en + if (AccPQCEn) begin : gen_acch_wr_en // New ACCH nets logic [ExtWLEN-1:0] acch_intg_d; logic [ExtWLEN-1:0] acch_intg_q; @@ -389,7 +389,7 @@ module otbn_mac_bignum endgenerate generate - if (OtbnPQCEn) begin : gen_op_result_pqc + if (AccPQCEn) begin : gen_op_result_pqc always_comb begin case (operation_i.mulv) 1'b0 : begin @@ -507,7 +507,7 @@ module otbn_mac_bignum endgenerate generate - if (OtbnPQCEn) begin : gen_expected_op_en_pqc + if (AccPQCEn) begin : gen_expected_op_en_pqc assign expected_op_en = mac_en_i | operation_i.mulv; end else begin : gen_expected_op_en assign expected_op_en = mac_en_i; @@ -521,7 +521,7 @@ module otbn_mac_bignum expected_acc_rd_en != mac_predec_bignum_i.acc_rd_en}; generate - if (OtbnPQCEn) begin : gen_sec_wipe_err_pqc + if (AccPQCEn) begin : gen_sec_wipe_err_pqc assign sec_wipe_err_o = (sec_wipe_acc_urnd_i | sec_wipe_acch_urnd_i) & ~sec_wipe_running_i; end else begin : gen_sec_wipe_err assign sec_wipe_err_o = sec_wipe_acc_urnd_i & ~sec_wipe_running_i; @@ -531,7 +531,7 @@ module otbn_mac_bignum `ASSERT(NoISPRAccWrAndMacEn, ~(ispr_acc_wr_en_i & mac_en_i)) generate - if (OtbnPQCEn) begin : gen_acch_assert + if (AccPQCEn) begin : gen_acch_assert `ASSERT(NoISPRAccHWrAndMacEn, ~(ispr_acch_wr_en_i & mac_en_i)) end endgenerate diff --git a/hw/ip/otbn/rtl/otbn_mul.sv b/hw/ip/acc/rtl/acc_mul.sv similarity index 99% rename from hw/ip/otbn/rtl/otbn_mul.sv rename to hw/ip/acc/rtl/acc_mul.sv index 424df8ebd89..f2c2eb54f54 100644 --- a/hw/ip/otbn/rtl/otbn_mul.sv +++ b/hw/ip/acc/rtl/acc_mul.sv @@ -6,8 +6,8 @@ `include "prim_assert.sv" -module otbn_mul - import otbn_pkg::*; +module acc_mul + import acc_pkg::*; ( input logic [WLEN/4-1:0] multiplier_op_a_i, input logic [WLEN/4-1:0] multiplier_op_b_i, diff --git a/hw/ip/otbn/rtl/otbn_pkg.sv b/hw/ip/acc/rtl/acc_pkg.sv similarity index 94% rename from hw/ip/otbn/rtl/otbn_pkg.sv rename to hw/ip/acc/rtl/acc_pkg.sv index 1373f107011..1ba95e421a4 100644 --- a/hw/ip/otbn/rtl/otbn_pkg.sv +++ b/hw/ip/acc/rtl/acc_pkg.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -11,7 +11,7 @@ `include "prim_assert.sv" -package otbn_pkg; +package acc_pkg; // Global Constants ============================================================================== @@ -63,9 +63,9 @@ package otbn_pkg; localparam logic [BaseIntgWidth-1:0] EccZeroWord = prim_secded_pkg::SecdedInv3932ZeroWord; localparam logic [ExtWLEN-1:0] EccWideZeroWord = {BaseWordsPerWLEN{EccZeroWord}}; - // Size of DMEM scratch area. The total DMEM size is OTBN_DMEM_SIZE + DmemScratchSizeByte. Note + // Size of DMEM scratch area. The total DMEM size is ACC_DMEM_SIZE + DmemScratchSizeByte. Note // that some of the Python tooling depends on this parameter (it needs to know the full DMEM size, - // but regtool only gives it OTBN_DMEM_SIZE). If changing this, you'll also need to edit + // but regtool only gives it ACC_DMEM_SIZE). If changing this, you'll also need to edit // _DmemScratchSizeBytes in util/shared/mem_layout.py parameter int DmemScratchSizeByte = 1024; @@ -80,14 +80,14 @@ package otbn_pkg; RegFileFPGA = 1 // FPGA implementation, does infer RAM primitives. } regfile_e; - // Command to execute. See the CMD register description in otbn.hjson for details. + // Command to execute. See the CMD register description in acc.hjson for details. typedef enum logic [7:0] { CmdExecute = 8'hd8, CmdSecWipeDmem = 8'hc3, CmdSecWipeImem = 8'h1e } cmd_e; - // Status register values. See the STATUS register description in otbn.hjson for details. + // Status register values. See the STATUS register description in acc.hjson for details. typedef enum logic [7:0] { StatusIdle = 8'h00, StatusBusyExecute = 8'h01, @@ -184,7 +184,7 @@ package otbn_pkg; logic bad_data_addr; } controller_err_bits_t; - // All the error signals that can be generated somewhere inside otbn_core + // All the error signals that can be generated somewhere inside acc_core typedef struct packed { logic fatal_software; logic bad_internal_state; @@ -201,7 +201,7 @@ package otbn_pkg; logic bad_data_addr; } core_err_bits_t; - // The error signals that are generated outside of otbn_core + // The error signals that are generated outside of acc_core typedef struct packed { logic lifecycle_escalation; logic illegal_bus_access; @@ -685,11 +685,11 @@ package otbn_pkg; localparam int StateControllerWidth = 5; typedef enum logic [StateControllerWidth-1:0] { - OtbnStateHalt = 5'b00100, - OtbnStateRun = 5'b01010, - OtbnStateStall = 5'b10011, - OtbnStateLocked = 5'b11101 - } otbn_state_e; + AccStateHalt = 5'b00100, + AccStateRun = 5'b01010, + AccStateStall = 5'b10011, + AccStateLocked = 5'b11101 + } acc_state_e; // States for start_stop_controller // Encoding generated with: @@ -715,16 +715,16 @@ package otbn_pkg; // localparam int StateStartStopWidth = 7; typedef enum logic [StateStartStopWidth-1:0] { - OtbnStartStopStateInitial = 7'b1010011, - OtbnStartStopStateHalt = 7'b1111001, - OtbnStartStopStateUrndRefresh = 7'b0000110, - OtbnStartStopStateRunning = 7'b1001000, - OtbnStartStopSecureWipeWdrUrnd = 7'b0101100, - OtbnStartStopSecureWipeAccModBaseUrnd = 7'b0010000, - OtbnStartStopSecureWipeAllZero = 7'b0110101, - OtbnStartStopSecureWipeComplete = 7'b0001011, - OtbnStartStopStateLocked = 7'b1101111 - } otbn_start_stop_state_e; + AccStartStopStateInitial = 7'b1010011, + AccStartStopStateHalt = 7'b1111001, + AccStartStopStateUrndRefresh = 7'b0000110, + AccStartStopStateRunning = 7'b1001000, + AccStartStopSecureWipeWdrUrnd = 7'b0101100, + AccStartStopSecureWipeAccModBaseUrnd = 7'b0010000, + AccStartStopSecureWipeAllZero = 7'b0110101, + AccStartStopSecureWipeComplete = 7'b0001011, + AccStartStopStateLocked = 7'b1101111 + } acc_start_stop_state_e; // Encoding generated with: // $ ./util/design/sparse-fsm-encode.py -d 3 -m 4 -n 5 \ @@ -760,11 +760,11 @@ typedef enum logic [StateScrambleCtrlWidth-1:0] { parameter urnd_prng_seed_t RndCnstUrndPrngSeedDefault = 256'h84ddfadaf7e1134d70aa1c59de6197ff25a4fe335d095f1e2cba89acbe4a07e9; - parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnKeyDefault = + parameter otp_ctrl_pkg::acc_key_t RndCnstAccKeyDefault = 128'h14e8cecae3040d5e12286bb3cc113298; - parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnNonceDefault = + parameter otp_ctrl_pkg::acc_nonce_t RndCnstAccNonceDefault = 64'hf79780bc735f3843; - typedef logic [63:0] otbn_dmem_nonce_t; - typedef logic [63:0] otbn_imem_nonce_t; + typedef logic [63:0] acc_dmem_nonce_t; + typedef logic [63:0] acc_imem_nonce_t; endpackage diff --git a/hw/ip/otbn/rtl/otbn_predecode.sv b/hw/ip/acc/rtl/acc_predecode.sv similarity index 96% rename from hw/ip/otbn/rtl/otbn_predecode.sv rename to hw/ip/acc/rtl/acc_predecode.sv index 1f4890c49ac..723d04ecbe4 100644 --- a/hw/ip/otbn/rtl/otbn_predecode.sv +++ b/hw/ip/acc/rtl/acc_predecode.sv @@ -3,7 +3,7 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -11,12 +11,12 @@ `include "prim_assert.sv" -module otbn_predecode - import otbn_pkg::*; +module acc_predecode + import acc_pkg::*; #( parameter int ImemSizeByte = 4096, // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1, + parameter bit AccPQCEn = 1'b1, localparam int ImemAddrWidth = prim_util_pkg::vbits(ImemSizeByte) ) ( @@ -343,10 +343,10 @@ module otbn_predecode 3'b101: begin // BN.ADDM/BN.SUBM // BN.ADDV/BN.SUBV are also predecoded here - // We check rdata[25] (Vector Enable) and OtbnPQCEn to make sure that predecode + // We check rdata[25] (Vector Enable) and AccPQCEn to make sure that predecode // flags are only set for legal instructions. - // rdata[25] can not be 1 and OtbnPQCEn be 0 - if (~imem_rdata_i[25] | OtbnPQCEn) begin + // rdata[25] can not be 1 and AccPQCEn be 0 + if (~imem_rdata_i[25] | AccPQCEn) begin rf_ren_a_bignum = 1'b1; rf_ren_b_bignum = 1'b1; rf_we_bignum = 1'b1; @@ -354,7 +354,7 @@ module otbn_predecode alu_bignum_adder_x_en = 1'b1; alu_bignum_x_res_operand_a_sel = 1'b1; alu_bignum_shift_mod_sel = 1'b0; - if (OtbnPQCEn) begin + if (AccPQCEn) begin alu_bignum_vector_type_pqc = alu_vector_type_t'(imem_rdata_i[27:26]); alu_bignum_vector_sel_pqc = imem_rdata_i[25]; end @@ -450,7 +450,7 @@ module otbn_predecode 3'b110: begin if (imem_rdata_i[31]) begin // BN.MOVR // bignum RF read and write occur in the following cycle due to the indirect - // register access so aren't set here. otbn_controller sets the appropriate read and + // register access so aren't set here. acc_controller sets the appropriate read and // write enables directly in the instruction fetch stage in the first cycle of the // instruction's execution (so they can be used in the second cycle which performs // the bignum RF access). @@ -506,7 +506,7 @@ module otbn_predecode /////////////////////////////////////////// InsnOpcodeBignumMulv: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin unique case (imem_rdata_i[14:12]) 3'b110: begin rf_ren_a_bignum = 1'b1; @@ -533,7 +533,7 @@ module otbn_predecode //////////////////////////////////////////// InsnOpcodeBignumShiftv: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin rf_we_bignum = 1'b1; rf_ren_b_bignum = 1'b1; alu_bignum_shifter_b_en = 1'b1; @@ -550,7 +550,7 @@ module otbn_predecode //////////////////////////////////////////// InsnOpcodeBignumTrn: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin rf_ren_a_bignum = 1'b1; rf_ren_b_bignum = 1'b1; rf_we_bignum = 1'b1; @@ -571,17 +571,17 @@ module otbn_predecode CsrMod0, CsrMod1, CsrMod2, CsrMod3, CsrMod4, CsrMod5, CsrMod6, CsrMod7: ispr_addr = IsprMod; CsrKmacCfg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr = IsprKmacCfg; end end CsrKmacPartialW: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr = IsprKmacPartialW; end end CsrKmacStatus: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr = IsprKmacStatus; end end @@ -597,22 +597,22 @@ module otbn_predecode WsrUrnd: ispr_addr = IsprUrnd; WsrAcc: ispr_addr = IsprAcc; WsrKmacCfg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr = IsprKmacCfg; end end WsrKmacMsg: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr = IsprKmacMsg; end end WsrKmacDigest: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr = IsprKmacDigest; end end WsrAccH: begin - if (OtbnPQCEn) begin + if (AccPQCEn) begin ispr_addr = IsprAccH; end end @@ -634,10 +634,10 @@ module otbn_predecode assign alu_predec_bignum_o.shift_right = alu_bignum_shift_right; // PQC flags are set to default if unused - assign alu_predec_bignum_o.vector_type = OtbnPQCEn ? alu_bignum_vector_type_pqc + assign alu_predec_bignum_o.vector_type = AccPQCEn ? alu_bignum_vector_type_pqc : alu_vector_type_t'(3'b000); - assign alu_predec_bignum_o.vector_sel = OtbnPQCEn ? alu_bignum_vector_sel_pqc : '0; - assign alu_predec_bignum_o.trn_type = OtbnPQCEn ? alu_bignum_trn_type_pqc + assign alu_predec_bignum_o.vector_sel = AccPQCEn ? alu_bignum_vector_sel_pqc : '0; + assign alu_predec_bignum_o.trn_type = AccPQCEn ? alu_bignum_trn_type_pqc : alu_trn_type_t'(3'b000); assign alu_predec_bignum_o.shift_amt = alu_bignum_shift_amt; diff --git a/hw/ip/acc/rtl/acc_reg_pkg.sv b/hw/ip/acc/rtl/acc_reg_pkg.sv new file mode 100644 index 00000000000..d8656c8f70d --- /dev/null +++ b/hw/ip/acc/rtl/acc_reg_pkg.sv @@ -0,0 +1,354 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package acc_reg_pkg; + + // Param list + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 17; + + // Number of registers for every interface + parameter int NumRegs = 11; + + // Alert indices + typedef enum int { + AlertFatalIdx = 0, + AlertRecovIdx = 1 + } acc_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic q; + } acc_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic q; + } acc_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic q; + logic qe; + } acc_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } recov; + struct packed { + logic q; + logic qe; + } fatal; + } acc_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [7:0] q; + logic qe; + } acc_reg2hw_cmd_reg_t; + + typedef struct packed { + logic q; + logic qe; + } acc_reg2hw_ctrl_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_software; + struct packed { + logic q; + logic qe; + } lifecycle_escalation; + struct packed { + logic q; + logic qe; + } illegal_bus_access; + struct packed { + logic q; + logic qe; + } bad_internal_state; + struct packed { + logic q; + logic qe; + } bus_intg_violation; + struct packed { + logic q; + logic qe; + } reg_intg_violation; + struct packed { + logic q; + logic qe; + } dmem_intg_violation; + struct packed { + logic q; + logic qe; + } imem_intg_violation; + struct packed { + logic q; + logic qe; + } rnd_fips_chk_fail; + struct packed { + logic q; + logic qe; + } rnd_rep_chk_fail; + struct packed { + logic q; + logic qe; + } key_invalid; + struct packed { + logic q; + logic qe; + } loop; + struct packed { + logic q; + logic qe; + } illegal_insn; + struct packed { + logic q; + logic qe; + } call_stack; + struct packed { + logic q; + logic qe; + } bad_insn_addr; + struct packed { + logic q; + logic qe; + } bad_data_addr; + } acc_reg2hw_err_bits_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } acc_reg2hw_insn_cnt_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } acc_reg2hw_load_checksum_reg_t; + + typedef struct packed { + logic d; + logic de; + } acc_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + } acc_hw2reg_ctrl_reg_t; + + typedef struct packed { + logic [7:0] d; + logic de; + } acc_hw2reg_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + } fatal_software; + struct packed { + logic d; + } lifecycle_escalation; + struct packed { + logic d; + } illegal_bus_access; + struct packed { + logic d; + } bad_internal_state; + struct packed { + logic d; + } bus_intg_violation; + struct packed { + logic d; + } reg_intg_violation; + struct packed { + logic d; + } dmem_intg_violation; + struct packed { + logic d; + } imem_intg_violation; + struct packed { + logic d; + } rnd_fips_chk_fail; + struct packed { + logic d; + } rnd_rep_chk_fail; + struct packed { + logic d; + } key_invalid; + struct packed { + logic d; + } loop; + struct packed { + logic d; + } illegal_insn; + struct packed { + logic d; + } call_stack; + struct packed { + logic d; + } bad_insn_addr; + struct packed { + logic d; + } bad_data_addr; + } acc_hw2reg_err_bits_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } fatal_software; + struct packed { + logic d; + logic de; + } lifecycle_escalation; + struct packed { + logic d; + logic de; + } illegal_bus_access; + struct packed { + logic d; + logic de; + } bad_internal_state; + struct packed { + logic d; + logic de; + } bus_intg_violation; + struct packed { + logic d; + logic de; + } reg_intg_violation; + struct packed { + logic d; + logic de; + } dmem_intg_violation; + struct packed { + logic d; + logic de; + } imem_intg_violation; + } acc_hw2reg_fatal_alert_cause_reg_t; + + typedef struct packed { + logic [31:0] d; + } acc_hw2reg_insn_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } acc_hw2reg_load_checksum_reg_t; + + // Register -> HW type + typedef struct packed { + acc_reg2hw_intr_state_reg_t intr_state; // [116:116] + acc_reg2hw_intr_enable_reg_t intr_enable; // [115:115] + acc_reg2hw_intr_test_reg_t intr_test; // [114:113] + acc_reg2hw_alert_test_reg_t alert_test; // [112:109] + acc_reg2hw_cmd_reg_t cmd; // [108:100] + acc_reg2hw_ctrl_reg_t ctrl; // [99:98] + acc_reg2hw_err_bits_reg_t err_bits; // [97:66] + acc_reg2hw_insn_cnt_reg_t insn_cnt; // [65:33] + acc_reg2hw_load_checksum_reg_t load_checksum; // [32:0] + } acc_reg2hw_t; + + // HW -> register type + typedef struct packed { + acc_hw2reg_intr_state_reg_t intr_state; // [107:106] + acc_hw2reg_ctrl_reg_t ctrl; // [105:105] + acc_hw2reg_status_reg_t status; // [104:96] + acc_hw2reg_err_bits_reg_t err_bits; // [95:80] + acc_hw2reg_fatal_alert_cause_reg_t fatal_alert_cause; // [79:64] + acc_hw2reg_insn_cnt_reg_t insn_cnt; // [63:32] + acc_hw2reg_load_checksum_reg_t load_checksum; // [31:0] + } acc_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] ACC_INTR_STATE_OFFSET = 17'h 0; + parameter logic [BlockAw-1:0] ACC_INTR_ENABLE_OFFSET = 17'h 4; + parameter logic [BlockAw-1:0] ACC_INTR_TEST_OFFSET = 17'h 8; + parameter logic [BlockAw-1:0] ACC_ALERT_TEST_OFFSET = 17'h c; + parameter logic [BlockAw-1:0] ACC_CMD_OFFSET = 17'h 10; + parameter logic [BlockAw-1:0] ACC_CTRL_OFFSET = 17'h 14; + parameter logic [BlockAw-1:0] ACC_STATUS_OFFSET = 17'h 18; + parameter logic [BlockAw-1:0] ACC_ERR_BITS_OFFSET = 17'h 1c; + parameter logic [BlockAw-1:0] ACC_FATAL_ALERT_CAUSE_OFFSET = 17'h 20; + parameter logic [BlockAw-1:0] ACC_INSN_CNT_OFFSET = 17'h 24; + parameter logic [BlockAw-1:0] ACC_LOAD_CHECKSUM_OFFSET = 17'h 28; + + // Reset values for hwext registers and their fields + parameter logic [0:0] ACC_INTR_TEST_RESVAL = 1'h 0; + parameter logic [0:0] ACC_INTR_TEST_DONE_RESVAL = 1'h 0; + parameter logic [1:0] ACC_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] ACC_ALERT_TEST_FATAL_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ALERT_TEST_RECOV_RESVAL = 1'h 0; + parameter logic [7:0] ACC_CMD_RESVAL = 8'h 0; + parameter logic [7:0] ACC_CMD_CMD_RESVAL = 8'h 0; + parameter logic [0:0] ACC_CTRL_RESVAL = 1'h 0; + parameter logic [0:0] ACC_CTRL_SOFTWARE_ERRS_FATAL_RESVAL = 1'h 0; + parameter logic [23:0] ACC_ERR_BITS_RESVAL = 24'h 0; + parameter logic [0:0] ACC_ERR_BITS_BAD_DATA_ADDR_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_BAD_INSN_ADDR_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_CALL_STACK_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_ILLEGAL_INSN_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_LOOP_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_KEY_INVALID_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_RND_REP_CHK_FAIL_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_RND_FIPS_CHK_FAIL_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_IMEM_INTG_VIOLATION_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_DMEM_INTG_VIOLATION_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_REG_INTG_VIOLATION_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_BUS_INTG_VIOLATION_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_BAD_INTERNAL_STATE_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_ILLEGAL_BUS_ACCESS_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_LIFECYCLE_ESCALATION_RESVAL = 1'h 0; + parameter logic [0:0] ACC_ERR_BITS_FATAL_SOFTWARE_RESVAL = 1'h 0; + parameter logic [31:0] ACC_INSN_CNT_RESVAL = 32'h 0; + parameter logic [31:0] ACC_INSN_CNT_INSN_CNT_RESVAL = 32'h 0; + parameter logic [31:0] ACC_LOAD_CHECKSUM_RESVAL = 32'h 0; + parameter logic [31:0] ACC_LOAD_CHECKSUM_CHECKSUM_RESVAL = 32'h 0; + + // Window parameters + parameter logic [BlockAw-1:0] ACC_IMEM_OFFSET = 17'h 8000; + parameter int unsigned ACC_IMEM_SIZE = 'h 8000; + parameter int unsigned ACC_IMEM_IDX = 0; + parameter logic [BlockAw-1:0] ACC_DMEM_OFFSET = 17'h 18000; + parameter int unsigned ACC_DMEM_SIZE = 'h 7c00; + parameter int unsigned ACC_DMEM_IDX = 1; + + // Register index + typedef enum int { + ACC_INTR_STATE, + ACC_INTR_ENABLE, + ACC_INTR_TEST, + ACC_ALERT_TEST, + ACC_CMD, + ACC_CTRL, + ACC_STATUS, + ACC_ERR_BITS, + ACC_FATAL_ALERT_CAUSE, + ACC_INSN_CNT, + ACC_LOAD_CHECKSUM + } acc_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] ACC_PERMIT [11] = '{ + 4'b 0001, // index[ 0] ACC_INTR_STATE + 4'b 0001, // index[ 1] ACC_INTR_ENABLE + 4'b 0001, // index[ 2] ACC_INTR_TEST + 4'b 0001, // index[ 3] ACC_ALERT_TEST + 4'b 0001, // index[ 4] ACC_CMD + 4'b 0001, // index[ 5] ACC_CTRL + 4'b 0001, // index[ 6] ACC_STATUS + 4'b 0111, // index[ 7] ACC_ERR_BITS + 4'b 0001, // index[ 8] ACC_FATAL_ALERT_CAUSE + 4'b 1111, // index[ 9] ACC_INSN_CNT + 4'b 1111 // index[10] ACC_LOAD_CHECKSUM + }; + +endpackage diff --git a/hw/ip/otbn/rtl/otbn_reg_top.sv b/hw/ip/acc/rtl/acc_reg_top.sv similarity index 95% rename from hw/ip/otbn/rtl/otbn_reg_top.sv rename to hw/ip/acc/rtl/acc_reg_top.sv index d895ab30a40..25a1144a24a 100644 --- a/hw/ip/otbn/rtl/otbn_reg_top.sv +++ b/hw/ip/acc/rtl/acc_reg_top.sv @@ -6,7 +6,7 @@ `include "prim_assert.sv" -module otbn_reg_top ( +module acc_reg_top ( input clk_i, input rst_ni, input tlul_pkg::tl_h2d_t tl_i, @@ -17,14 +17,14 @@ module otbn_reg_top ( input tlul_pkg::tl_d2h_t tl_win_i [2], // To HW - output otbn_reg_pkg::otbn_reg2hw_t reg2hw, // Write - input otbn_reg_pkg::otbn_hw2reg_t hw2reg, // Read + output acc_reg_pkg::acc_reg2hw_t reg2hw, // Write + input acc_reg_pkg::acc_hw2reg_t hw2reg, // Read // Integrity check errors output logic intg_err_o ); - import otbn_reg_pkg::* ; + import acc_reg_pkg::* ; localparam int AW = 17; localparam int DW = 32; @@ -946,17 +946,17 @@ module otbn_reg_top ( logic [10:0] addr_hit; always_comb begin - addr_hit[ 0] = (reg_addr == OTBN_INTR_STATE_OFFSET); - addr_hit[ 1] = (reg_addr == OTBN_INTR_ENABLE_OFFSET); - addr_hit[ 2] = (reg_addr == OTBN_INTR_TEST_OFFSET); - addr_hit[ 3] = (reg_addr == OTBN_ALERT_TEST_OFFSET); - addr_hit[ 4] = (reg_addr == OTBN_CMD_OFFSET); - addr_hit[ 5] = (reg_addr == OTBN_CTRL_OFFSET); - addr_hit[ 6] = (reg_addr == OTBN_STATUS_OFFSET); - addr_hit[ 7] = (reg_addr == OTBN_ERR_BITS_OFFSET); - addr_hit[ 8] = (reg_addr == OTBN_FATAL_ALERT_CAUSE_OFFSET); - addr_hit[ 9] = (reg_addr == OTBN_INSN_CNT_OFFSET); - addr_hit[10] = (reg_addr == OTBN_LOAD_CHECKSUM_OFFSET); + addr_hit[ 0] = (reg_addr == ACC_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == ACC_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == ACC_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == ACC_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == ACC_CMD_OFFSET); + addr_hit[ 5] = (reg_addr == ACC_CTRL_OFFSET); + addr_hit[ 6] = (reg_addr == ACC_STATUS_OFFSET); + addr_hit[ 7] = (reg_addr == ACC_ERR_BITS_OFFSET); + addr_hit[ 8] = (reg_addr == ACC_FATAL_ALERT_CAUSE_OFFSET); + addr_hit[ 9] = (reg_addr == ACC_INSN_CNT_OFFSET); + addr_hit[10] = (reg_addr == ACC_LOAD_CHECKSUM_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -964,17 +964,17 @@ module otbn_reg_top ( // Check sub-word write is permitted always_comb begin wr_err = (reg_we & - ((addr_hit[ 0] & (|(OTBN_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(OTBN_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(OTBN_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(OTBN_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(OTBN_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(OTBN_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(OTBN_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(OTBN_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(OTBN_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(OTBN_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(OTBN_PERMIT[10] & ~reg_be))))); + ((addr_hit[ 0] & (|(ACC_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(ACC_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(ACC_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(ACC_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(ACC_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(ACC_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(ACC_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(ACC_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(ACC_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(ACC_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(ACC_PERMIT[10] & ~reg_be))))); end // Generate write-enables diff --git a/hw/ip/otbn/rtl/otbn_rf_base.sv b/hw/ip/acc/rtl/acc_rf_base.sv similarity index 93% rename from hw/ip/otbn/rtl/otbn_rf_base.sv rename to hw/ip/acc/rtl/acc_rf_base.sv index 32265c45727..de91b6c51eb 100644 --- a/hw/ip/otbn/rtl/otbn_rf_base.sv +++ b/hw/ip/acc/rtl/acc_rf_base.sv @@ -7,8 +7,8 @@ /** * 32b General Purpose Register File (GPRs) with integrity code detecting triple bit errors. * - * This wraps two implementations, one for FPGA (otbn_rf_base_fpga) - * implementation the other for ASIC (otbn_rf_base_ff). + * This wraps two implementations, one for FPGA (acc_rf_base_fpga) + * implementation the other for ASIC (acc_rf_base_ff). * * Both reads and writes use a 2 signal protocol: An _en signal indicates intent to do * a read or write operation, a _commit signals the operation should proceed. A _commit without _en @@ -29,10 +29,10 @@ * for use as a call stack * - triple error detection */ -module otbn_rf_base - import otbn_pkg::*; +module acc_rf_base + import acc_pkg::*; #( - // Register file implementation selection, see otbn_pkg.sv. + // Register file implementation selection, see acc_pkg.sv. parameter regfile_e RegFile = RegFileFF )( input logic clk_i, @@ -143,7 +143,7 @@ module otbn_rf_base // New data can have its integrity from an external source or the integrity can be calculated here assign wr_data_intg_mux_out = wr_data_intg_sel_i ? wr_data_intg_i : wr_data_intg_calc; - otbn_stack #( + acc_stack #( // SEC_CM: CALL_STACK.ADDR.INTEGRITY .StackWidth(39), .StackDepth(CallStackDepth) @@ -175,14 +175,14 @@ module otbn_rf_base ); // Squash call stack read data to 0 (which means invalid ECC with the encoding we use) when - // there's nothing on the call stack. OTBN will raise an error when we read from an empty call + // there's nothing on the call stack. ACC will raise an error when we read from an empty call // stack but this prevents X propagation and exposing any previous, now invalid, stack values. assign stack_data_intg = stack_data_valid ? stack_data_intg_raw : '0; if (RegFile == RegFileFF) begin : gen_rf_base_ff - otbn_rf_base_ff #( + acc_rf_base_ff #( .WordZeroVal(prim_secded_pkg::SecdedInv3932ZeroWord) - ) u_otbn_rf_base_inner ( + ) u_acc_rf_base_inner ( .clk_i, .rst_ni, @@ -198,9 +198,9 @@ module otbn_rf_base .we_err_o(spurious_we_err_o) ); end else if (RegFile == RegFileFPGA) begin : gen_rf_base_fpga - otbn_rf_base_fpga #( + acc_rf_base_fpga #( .WordZeroVal(prim_secded_pkg::SecdedInv3932ZeroWord) - ) u_otbn_rf_base_inner ( + ) u_acc_rf_base_inner ( .clk_i, .rst_ni, @@ -240,8 +240,8 @@ module otbn_rf_base // Make sure we're not outputting X. This indicates that something went wrong during the initial // secure wipe. - `ASSERT(OtbnRfBaseRdAKnown, rd_en_a_i && !pop_stack_a |-> !$isunknown(rd_data_a_raw_intg)) - `ASSERT(OtbnRfBaseRdBKnown, rd_en_b_i && !pop_stack_b |-> !$isunknown(rd_data_b_raw_intg)) + `ASSERT(AccRfBaseRdAKnown, rd_en_a_i && !pop_stack_a |-> !$isunknown(rd_data_a_raw_intg)) + `ASSERT(AccRfBaseRdBKnown, rd_en_b_i && !pop_stack_b |-> !$isunknown(rd_data_b_raw_intg)) assign sec_wipe_err_o = sec_wipe_stack_reset_i & ~sec_wipe_running_i; endmodule diff --git a/hw/ip/otbn/rtl/otbn_rf_base_ff.sv b/hw/ip/acc/rtl/acc_rf_base_ff.sv similarity index 97% rename from hw/ip/otbn/rtl/otbn_rf_base_ff.sv rename to hw/ip/acc/rtl/acc_rf_base_ff.sv index 9b603b71cc5..b2b22541198 100644 --- a/hw/ip/otbn/rtl/otbn_rf_base_ff.sv +++ b/hw/ip/acc/rtl/acc_rf_base_ff.sv @@ -6,14 +6,14 @@ * 39b General Purpose Register File (GPRs) * * 39b to support 32b register with 7b integrity. Integrity generation/checking implemented in - * wrapping otbn_rf_base module + * wrapping acc_rf_base module * * Features: * - 2 read ports * - 1 write port */ -module otbn_rf_base_ff - import otbn_pkg::*; +module acc_rf_base_ff + import acc_pkg::*; #( parameter logic [BaseIntgWidth-1:0] WordZeroVal = '0 ) ( diff --git a/hw/ip/otbn/rtl/otbn_rf_base_fpga.sv b/hw/ip/acc/rtl/acc_rf_base_fpga.sv similarity index 97% rename from hw/ip/otbn/rtl/otbn_rf_base_fpga.sv rename to hw/ip/acc/rtl/acc_rf_base_fpga.sv index 29f3b9f8ef0..aea9a78c905 100644 --- a/hw/ip/otbn/rtl/otbn_rf_base_fpga.sv +++ b/hw/ip/acc/rtl/acc_rf_base_fpga.sv @@ -6,7 +6,7 @@ * 39b General Purpose Register File (GPRs) * * 39b to support 32b register with 7b integrity. Integrity generation/checking implemented in - * wrapping otbn_rf_base module + * wrapping acc_rf_base module * * Features: * - 2 read ports @@ -17,8 +17,8 @@ * This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx * FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested. */ -module otbn_rf_base_fpga - import otbn_pkg::*; +module acc_rf_base_fpga + import acc_pkg::*; #( parameter logic [BaseIntgWidth-1:0] WordZeroVal = '0 ) ( diff --git a/hw/ip/otbn/rtl/otbn_rf_bignum.sv b/hw/ip/acc/rtl/acc_rf_bignum.sv similarity index 91% rename from hw/ip/otbn/rtl/otbn_rf_bignum.sv rename to hw/ip/acc/rtl/acc_rf_bignum.sv index c0237942ffa..481d8e3e64d 100644 --- a/hw/ip/otbn/rtl/otbn_rf_bignum.sv +++ b/hw/ip/acc/rtl/acc_rf_bignum.sv @@ -8,8 +8,8 @@ * 256b General Purpose Register File (GPRs) with integrity code detecting triple bit errors on a * 32-bit granule (312 bits total). * - * This wraps two implementations, one for FPGA (otbn_rf_base_fpga) implementation the other for - * ASIC (otbn_rf_base_ff). + * This wraps two implementations, one for FPGA (acc_rf_base_fpga) implementation the other for + * ASIC (acc_rf_base_ff). * * Integrity protection uses an inverted (39, 32) Hsaio code providing a Hamming distance of 4. * @@ -23,10 +23,10 @@ * - triple error detection */ -module otbn_rf_bignum - import otbn_pkg::*; +module acc_rf_bignum + import acc_pkg::*; #( - // Register file implementation selection, see otbn_pkg.sv. + // Register file implementation selection, see acc_pkg.sv. parameter regfile_e RegFile = RegFileFF )( input logic clk_i, @@ -65,7 +65,7 @@ module otbn_rf_bignum assign wr_en_internal = wr_en_i & {2{wr_commit_i}}; if (RegFile == RegFileFF) begin : gen_rf_bignum_ff - otbn_rf_bignum_ff u_otbn_rf_bignum_inner ( + acc_rf_bignum_ff u_acc_rf_bignum_inner ( .clk_i, .rst_ni, @@ -84,9 +84,9 @@ module otbn_rf_bignum .we_err_o(spurious_we_err_o) ); end else if (RegFile == RegFileFPGA) begin : gen_rf_bignum_fpga - otbn_rf_bignum_fpga #( + acc_rf_bignum_fpga #( .WordZeroVal(prim_secded_pkg::SecdedInv3932ZeroWord) - ) u_otbn_rf_bignum_inner ( + ) u_acc_rf_bignum_inner ( .clk_i, .rst_ni, @@ -188,6 +188,6 @@ module otbn_rf_bignum // Make sure we're not outputting X. This indicates that something went wrong during the initial // secure wipe. - `ASSERT(OtbnRfBignumRdAKnown, rd_en_a_i && !rd_en_a_mismatch |-> !$isunknown(rd_data_a_intg_o)) - `ASSERT(OtbnRfBignumRdBKnown, rd_en_b_i && !rd_en_b_mismatch |-> !$isunknown(rd_data_b_intg_o)) + `ASSERT(AccRfBignumRdAKnown, rd_en_a_i && !rd_en_a_mismatch |-> !$isunknown(rd_data_a_intg_o)) + `ASSERT(AccRfBignumRdBKnown, rd_en_b_i && !rd_en_b_mismatch |-> !$isunknown(rd_data_b_intg_o)) endmodule diff --git a/hw/ip/otbn/rtl/otbn_rf_bignum_ff.sv b/hw/ip/acc/rtl/acc_rf_bignum_ff.sv similarity index 96% rename from hw/ip/otbn/rtl/otbn_rf_bignum_ff.sv rename to hw/ip/acc/rtl/acc_rf_bignum_ff.sv index ba35e0842f4..b630a77c5fd 100644 --- a/hw/ip/otbn/rtl/otbn_rf_bignum_ff.sv +++ b/hw/ip/acc/rtl/acc_rf_bignum_ff.sv @@ -8,15 +8,15 @@ * ExtWLEN (312b) Wide Register File (WDRs) * * ExtWLEN allows bits to provide integrity checking to WLEN words on a 32-bit granule. Integrity - * generation/checking implemented in wrapping otbn_rf_bignum module + * generation/checking implemented in wrapping acc_rf_bignum module * * Features: * - 2 read ports * - 1 write port * - Half (WLEN) word write enables */ -module otbn_rf_bignum_ff - import otbn_pkg::*; +module acc_rf_bignum_ff + import acc_pkg::*; ( input logic clk_i, input logic rst_ni, diff --git a/hw/ip/otbn/rtl/otbn_rf_bignum_fpga.sv b/hw/ip/acc/rtl/acc_rf_bignum_fpga.sv similarity index 96% rename from hw/ip/otbn/rtl/otbn_rf_bignum_fpga.sv rename to hw/ip/acc/rtl/acc_rf_bignum_fpga.sv index 09df546fdc9..4aa42e48a53 100644 --- a/hw/ip/otbn/rtl/otbn_rf_bignum_fpga.sv +++ b/hw/ip/acc/rtl/acc_rf_bignum_fpga.sv @@ -6,7 +6,7 @@ * ExtWLEN (312b) Wide Register File (WDRs) * * ExtWLEN allows bits to provide integrity checking to WLEN words on a 32-bit granule. Integrity - * generation/checking implemented in wrapping otbn_rf_bignum module + * generation/checking implemented in wrapping acc_rf_bignum module * * Features: * - 2 read ports @@ -16,8 +16,8 @@ * This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx * FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested. */ -module otbn_rf_bignum_fpga - import otbn_pkg::*; +module acc_rf_bignum_fpga + import acc_pkg::*; #( parameter logic [BaseIntgWidth-1:0] WordZeroVal = '0 ) ( diff --git a/hw/ip/otbn/rtl/otbn_rnd.sv b/hw/ip/acc/rtl/acc_rnd.sv similarity index 95% rename from hw/ip/otbn/rtl/otbn_rnd.sv rename to hw/ip/acc/rtl/acc_rnd.sv index 493ddf69299..d8c5282d69e 100644 --- a/hw/ip/otbn/rtl/otbn_rnd.sv +++ b/hw/ip/acc/rtl/acc_rnd.sv @@ -5,7 +5,7 @@ `include "prim_assert.sv" /** - * OTBN random number coordination + * ACC random number coordination * * This module implements the RND, RND_PREFETCH and URND CSRs/WSRs. The EDN (entropy distribution * network) provides the bits for random numbers. RND gives direct access to EDN bits. URND provides @@ -16,12 +16,12 @@ // IMPORTANT NOTE: // // DO NOT USE THIS BLINDLY! // // // -// This is an initial prototype of the random number functionality in OTBN. Details are still // +// This is an initial prototype of the random number functionality in ACC. Details are still // // under discussion and subject to change. It has not yet been verified this provides the // -// necessary guarantees required for the various uses of random numbers in OTBN software. // +// necessary guarantees required for the various uses of random numbers in ACC software. // //////////////////////////////////////////////////////////////////////////////////////////////////// -module otbn_rnd import otbn_pkg::*; +module acc_rnd import acc_pkg::*; #( parameter urnd_prng_seed_t RndCnstUrndPrngSeed = RndCnstUrndPrngSeedDefault ) ( @@ -85,8 +85,8 @@ module otbn_rnd import otbn_pkg::*; assign rnd_data_en = edn_rnd_req_complete & ~edn_rnd_data_ignore_q; - // RND becomes valid when EDN request completes and provides new bits. Valid is cleared when OTBN - // starts a new run (opn_start_i) or when OTBN reads RND (rnd_req_complete). + // RND becomes valid when EDN request completes and provides new bits. Valid is cleared when ACC + // starts a new run (opn_start_i) or when ACC reads RND (rnd_req_complete). assign rnd_valid_d = opn_start_i || rnd_req_complete ? 1'b0 : edn_rnd_req_complete && !edn_rnd_data_ignore_q ? 1'b1 : rnd_valid_q; @@ -96,9 +96,9 @@ module otbn_rnd import otbn_pkg::*; // Start an EDN request when there is a prefetch or an attempt at reading RND when RND data is // not available. Signalling `edn_rnd_req_start` whilst there is an outstanding request is - // harmless. However, a prefetch may still be outstanding from the last OTBN run which may have + // harmless. However, a prefetch may still be outstanding from the last ACC run which may have // used a different configuration for EDN, CSRNG or the entropy source. At the start of a new - // OTBN run, RND data is thus always invalidated and outstanding prefetches are marked such that + // ACC run, RND data is thus always invalidated and outstanding prefetches are marked such that // the RND data returned for the first prefetch is thrown away. When throwing away data, we need // to keep requesting RND data from EDN if another request got queued in the meantime. assign edn_rnd_req_start = (rnd_prefetch_req_i | rnd_req_i | rnd_req_queued_q) & ~rnd_valid_q; diff --git a/hw/ip/otbn/rtl/otbn_scramble_ctrl.sv b/hw/ip/acc/rtl/acc_scramble_ctrl.sv similarity index 67% rename from hw/ip/otbn/rtl/otbn_scramble_ctrl.sv rename to hw/ip/acc/rtl/acc_scramble_ctrl.sv index e0b42bceb94..ab4a3c05684 100644 --- a/hw/ip/otbn/rtl/otbn_scramble_ctrl.sv +++ b/hw/ip/acc/rtl/acc_scramble_ctrl.sv @@ -3,19 +3,19 @@ // SPDX-License-Identifier: Apache-2.0 /** - * Scramble control for OTBN + * Scramble control for ACC * - * This provides a key and nonce for scrambling the OTBN IMem and DMem. The OTP + * This provides a key and nonce for scrambling the ACC IMem and DMem. The OTP * key interface is used to request a new key and nonce when they are requested. */ -module otbn_scramble_ctrl - import otbn_pkg::*; +module acc_scramble_ctrl + import acc_pkg::*; #( // Default seed and nonce for scrambling - parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnKey = otbn_pkg::RndCnstOtbnKeyDefault, - parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnNonce = otbn_pkg::RndCnstOtbnNonceDefault + parameter otp_ctrl_pkg::acc_key_t RndCnstAccKey = acc_pkg::RndCnstAccKeyDefault, + parameter otp_ctrl_pkg::acc_nonce_t RndCnstAccNonce = acc_pkg::RndCnstAccNonceDefault ) ( - // OTBN clock + // ACC clock input clk_i, input rst_ni, @@ -24,26 +24,26 @@ module otbn_scramble_ctrl input rst_otp_ni, // OTP key interface - output otp_ctrl_pkg::otbn_otp_key_req_t otbn_otp_key_o, - input otp_ctrl_pkg::otbn_otp_key_rsp_t otbn_otp_key_i, + output otp_ctrl_pkg::acc_otp_key_req_t acc_otp_key_o, + input otp_ctrl_pkg::acc_otp_key_rsp_t acc_otp_key_i, - output otp_ctrl_pkg::otbn_key_t otbn_dmem_scramble_key_o, - output otbn_dmem_nonce_t otbn_dmem_scramble_nonce_o, - output logic otbn_dmem_scramble_valid_o, - output logic otbn_dmem_scramble_key_seed_valid_o, + output otp_ctrl_pkg::acc_key_t acc_dmem_scramble_key_o, + output acc_dmem_nonce_t acc_dmem_scramble_nonce_o, + output logic acc_dmem_scramble_valid_o, + output logic acc_dmem_scramble_key_seed_valid_o, - output otp_ctrl_pkg::otbn_key_t otbn_imem_scramble_key_o, - output otbn_imem_nonce_t otbn_imem_scramble_nonce_o, - output logic otbn_imem_scramble_valid_o, - output logic otbn_imem_scramble_key_seed_valid_o, + output otp_ctrl_pkg::acc_key_t acc_imem_scramble_key_o, + output acc_imem_nonce_t acc_imem_scramble_nonce_o, + output logic acc_imem_scramble_valid_o, + output logic acc_imem_scramble_key_seed_valid_o, - input logic otbn_dmem_scramble_sec_wipe_i, - input otp_ctrl_pkg::otbn_key_t otbn_dmem_scramble_sec_wipe_key_i, - input logic otbn_imem_scramble_sec_wipe_i, - input otp_ctrl_pkg::otbn_key_t otbn_imem_scramble_sec_wipe_key_i, + input logic acc_dmem_scramble_sec_wipe_i, + input otp_ctrl_pkg::acc_key_t acc_dmem_scramble_sec_wipe_key_i, + input logic acc_imem_scramble_sec_wipe_i, + input otp_ctrl_pkg::acc_key_t acc_imem_scramble_sec_wipe_key_i, - output logic otbn_dmem_scramble_key_req_busy_o, - output logic otbn_imem_scramble_key_req_busy_o, + output logic acc_dmem_scramble_key_req_busy_o, + output logic acc_imem_scramble_key_req_busy_o, output logic state_error_o ); @@ -65,23 +65,23 @@ module otbn_scramble_ctrl logic dmem_key_sel_otp; logic imem_key_sel_otp; - otp_ctrl_pkg::otbn_key_t dmem_key_q, dmem_key_d; - otp_ctrl_pkg::otbn_key_t imem_key_q, imem_key_d; + otp_ctrl_pkg::acc_key_t dmem_key_q, dmem_key_d; + otp_ctrl_pkg::acc_key_t imem_key_q, imem_key_d; - otbn_dmem_nonce_t dmem_nonce_q; - otbn_imem_nonce_t imem_nonce_q; + acc_dmem_nonce_t dmem_nonce_q; + acc_imem_nonce_t imem_nonce_q; logic otp_key_req, otp_key_ack; - otp_ctrl_pkg::otbn_key_t otp_key; - otp_ctrl_pkg::otbn_nonce_t otp_nonce; + otp_ctrl_pkg::acc_key_t otp_key; + otp_ctrl_pkg::acc_nonce_t otp_nonce; logic otp_key_seed_valid; - assign dmem_key_d = dmem_key_sel_otp ? otp_key : otbn_dmem_scramble_sec_wipe_key_i; - assign imem_key_d = imem_key_sel_otp ? otp_key : otbn_imem_scramble_sec_wipe_key_i; + assign dmem_key_d = dmem_key_sel_otp ? otp_key : acc_dmem_scramble_sec_wipe_key_i; + assign imem_key_d = imem_key_sel_otp ? otp_key : acc_imem_scramble_sec_wipe_key_i; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - dmem_key_q <= RndCnstOtbnKey; + dmem_key_q <= RndCnstAccKey; end else if (dmem_key_en) begin dmem_key_q <= dmem_key_d; end @@ -89,7 +89,7 @@ module otbn_scramble_ctrl always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - dmem_nonce_q <= RndCnstOtbnNonce; + dmem_nonce_q <= RndCnstAccNonce; end else if (dmem_nonce_en) begin dmem_nonce_q <= otp_nonce; end @@ -97,7 +97,7 @@ module otbn_scramble_ctrl always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - imem_key_q <= RndCnstOtbnKey; + imem_key_q <= RndCnstAccKey; end else if (imem_key_en) begin imem_key_q <= imem_key_d; end @@ -105,7 +105,7 @@ module otbn_scramble_ctrl always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - imem_nonce_q <= RndCnstOtbnNonce; + imem_nonce_q <= RndCnstAccNonce; end else if (imem_nonce_en) begin imem_nonce_q <= otp_nonce; end @@ -153,7 +153,7 @@ module otbn_scramble_ctrl // Action dmem secure wipe request unless a new key request is already ongoing // SEC_CM: DATA.MEM.SEC_WIPE - if (otbn_dmem_scramble_sec_wipe_i && state_q != ScrambleCtrlDmemReq) begin + if (acc_dmem_scramble_sec_wipe_i && state_q != ScrambleCtrlDmemReq) begin dmem_key_valid_d = 1'b0; dmem_key_en = 1'b1; dmem_key_sel_otp = 1'b0; @@ -162,7 +162,7 @@ module otbn_scramble_ctrl // Action imem secure wipe request unless a new key request is already ongoing // SEC_CM: INSTRUCTION.MEM.SEC_WIPE - if (otbn_imem_scramble_sec_wipe_i && state_q != ScrambleCtrlImemReq) begin + if (acc_imem_scramble_sec_wipe_i && state_q != ScrambleCtrlImemReq) begin imem_key_valid_d = 1'b0; imem_key_en = 1'b1; imem_key_sel_otp = 1'b0; @@ -217,14 +217,14 @@ module otbn_scramble_ctrl endcase end - assign otbn_dmem_scramble_key_req_busy_o = + assign acc_dmem_scramble_key_req_busy_o = (state_d == ScrambleCtrlDmemReq) | dmem_scramble_req_pending_d; - assign otbn_imem_scramble_key_req_busy_o = + assign acc_imem_scramble_key_req_busy_o = (state_d == ScrambleCtrlImemReq) | imem_scramble_req_pending_d; prim_sync_reqack_data #( - .Width($bits(otp_ctrl_pkg::otbn_otp_key_rsp_t)-1), + .Width($bits(otp_ctrl_pkg::acc_otp_key_rsp_t)-1), .EnRstChks(1'b1), .DataSrc2Dst(1'b0) ) u_otp_key_req_sync ( @@ -235,26 +235,26 @@ module otbn_scramble_ctrl .req_chk_i (1'b1), .src_req_i (otp_key_req), .src_ack_o (otp_key_ack), - .dst_req_o (otbn_otp_key_o.req), - .dst_ack_i (otbn_otp_key_i.ack), - .data_i ({otbn_otp_key_i.key, - otbn_otp_key_i.nonce, - otbn_otp_key_i.seed_valid}), + .dst_req_o (acc_otp_key_o.req), + .dst_ack_i (acc_otp_key_i.ack), + .data_i ({acc_otp_key_i.key, + acc_otp_key_i.nonce, + acc_otp_key_i.seed_valid}), .data_o ({otp_key, otp_nonce, otp_key_seed_valid}) ); - assign otbn_dmem_scramble_key_o = dmem_key_q; - assign otbn_dmem_scramble_nonce_o = dmem_nonce_q; - assign otbn_dmem_scramble_valid_o = dmem_key_valid_q; - assign otbn_dmem_scramble_key_seed_valid_o = dmem_key_seed_valid_q; + assign acc_dmem_scramble_key_o = dmem_key_q; + assign acc_dmem_scramble_nonce_o = dmem_nonce_q; + assign acc_dmem_scramble_valid_o = dmem_key_valid_q; + assign acc_dmem_scramble_key_seed_valid_o = dmem_key_seed_valid_q; - assign otbn_imem_scramble_key_o = imem_key_q; - assign otbn_imem_scramble_nonce_o = imem_nonce_q; - assign otbn_imem_scramble_valid_o = imem_key_valid_q; - assign otbn_imem_scramble_key_seed_valid_o = imem_key_seed_valid_q; + assign acc_imem_scramble_key_o = imem_key_q; + assign acc_imem_scramble_nonce_o = imem_nonce_q; + assign acc_imem_scramble_valid_o = imem_key_valid_q; + assign acc_imem_scramble_key_seed_valid_o = imem_key_seed_valid_q; - `ASSERT(OtbnScrambleCtrlLocalEscCntrMeasure_A, state_error_o |=> state_q == ScrambleCtrlError) + `ASSERT(AccScrambleCtrlLocalEscCntrMeasure_A, state_error_o |=> state_q == ScrambleCtrlError) endmodule diff --git a/hw/ip/otbn/rtl/otbn_stack.sv b/hw/ip/acc/rtl/acc_stack.sv similarity index 99% rename from hw/ip/otbn/rtl/otbn_stack.sv rename to hw/ip/acc/rtl/acc_stack.sv index 5006f1f9ac1..a4cf41f5444 100644 --- a/hw/ip/otbn/rtl/otbn_stack.sv +++ b/hw/ip/acc/rtl/acc_stack.sv @@ -19,8 +19,8 @@ * `commit_i` is set. This is to enable users to extend the stack in case where it's not a simple * matter of adding extra data bits (e.g. where this is a prim_count instance per stack entry). */ -module otbn_stack - import otbn_pkg::*; +module acc_stack + import acc_pkg::*; #( parameter int unsigned StackWidth = 32, parameter int unsigned StackDepth = 4, diff --git a/hw/ip/otbn/rtl/otbn_start_stop_control.sv b/hw/ip/acc/rtl/acc_start_stop_control.sv similarity index 85% rename from hw/ip/otbn/rtl/otbn_start_stop_control.sv rename to hw/ip/acc/rtl/acc_start_stop_control.sv index 8778937e3b5..19c524f697c 100644 --- a/hw/ip/otbn/rtl/otbn_start_stop_control.sv +++ b/hw/ip/acc/rtl/acc_start_stop_control.sv @@ -3,14 +3,14 @@ // Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). // Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 /** - * State machine to handle actions that occur around the start and stop of OTBN. + * State machine to handle actions that occur around the start and stop of ACC. * * This receives the start signals from the top-level and passes them on to the * controller to begin execution when pre-start actions have finished. @@ -29,12 +29,12 @@ `include "prim_assert.sv" -module otbn_start_stop_control - import otbn_pkg::*; +module acc_start_stop_control + import acc_pkg::*; import prim_mubi_pkg::*; #( // Enabling PQC hardware support with vector ISA extension - parameter bit OtbnPQCEn = 1'b1, + parameter bit AccPQCEn = 1'b1, // Disable URND advance when not in use. Useful for SCA only. parameter bit SecMuteUrnd = 1'b0, // Skip URND re-seed at the start of the operation. Useful for SCA only. @@ -79,10 +79,10 @@ module otbn_start_stop_control ); // Create lint errors to reduce the risk of accidentally enabling these features. - `ASSERT_STATIC_LINT_ERROR(OtbnSecMuteUrndNonDefault, SecMuteUrnd == 0) - `ASSERT_STATIC_LINT_ERROR(OtbnSecSkipUrndReseedAtStartNonDefault, SecSkipUrndReseedAtStart == 0) + `ASSERT_STATIC_LINT_ERROR(AccSecMuteUrndNonDefault, SecMuteUrnd == 0) + `ASSERT_STATIC_LINT_ERROR(AccSecSkipUrndReseedAtStartNonDefault, SecSkipUrndReseedAtStart == 0) - otbn_start_stop_state_e state_q, state_d; + acc_start_stop_state_e state_q, state_d; logic init_sec_wipe_done_q, init_sec_wipe_done_d; mubi4_t wipe_after_urnd_refresh_q, wipe_after_urnd_refresh_d; mubi4_t rma_ack_d, rma_ack_q; @@ -123,7 +123,7 @@ module otbn_start_stop_control if (SecSkipUrndReseedAtStart) begin: gen_skip_reseed logic skip_reseed_d; - assign skip_reseed_d = ((state_q == OtbnStartStopStateHalt) & start_i & ~stop); + assign skip_reseed_d = ((state_q == AccStartStopStateHalt) & start_i & ~stop); always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin @@ -159,7 +159,7 @@ module otbn_start_stop_control // SEC_CM: START_STOP_CTRL.FSM.SPARSE `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, - otbn_start_stop_state_e, OtbnStartStopStateInitial) + acc_start_stop_state_e, AccStartStopStateInitial) always_comb begin urnd_reseed_req_o = 1'b0; @@ -189,28 +189,28 @@ module otbn_start_stop_control mubi_err_d = mubi_err_q; unique case (state_q) - OtbnStartStopStateInitial: begin + AccStartStopStateInitial: begin secure_wipe_running_d = 1'b1; urnd_reseed_req_o = 1'b1; if (rma_request) begin // If we get an RMA request before the URND got reseeded, proceed with the initial secure // wipe, as the entropy complex may not be able to provide entropy at this point. - state_d = OtbnStartStopSecureWipeWdrUrnd; + state_d = AccStartStopSecureWipeWdrUrnd; // As we don't reseed URND, there's no point in doing two rounds of wiping, so we pretend // that the first round is already the second round. wipe_after_urnd_refresh_d = MuBi4True; end else if (urnd_reseed_ack_i) begin urnd_advance_o = 1'b1; - state_d = OtbnStartStopSecureWipeWdrUrnd; + state_d = AccStartStopSecureWipeWdrUrnd; end end - OtbnStartStopStateHalt: begin + AccStartStopStateHalt: begin // Keep start_reset_o asserted whilst in this state. We want to keep this signal early so do // not want to factor further logic into it. state_reset_o = 1'b1; if (stop && !rma_request) begin - state_d = OtbnStartStopStateLocked; + state_d = AccStartStopStateLocked; end else if (start_i || rma_request) begin ispr_init_o = 1'b1; insn_cnt_clear_int_o = 1'b1; @@ -218,23 +218,23 @@ module otbn_start_stop_control // Do not reseed URND before secure wipe for RMA, as the entropy complex may not be able // to provide entropy at this point. secure_wipe_running_d = 1'b1; - state_d = OtbnStartStopSecureWipeWdrUrnd; + state_d = AccStartStopSecureWipeWdrUrnd; // As we don't reseed URND, there's no point in doing two rounds of wiping, so we // pretend that the first round is already the second round. wipe_after_urnd_refresh_d = MuBi4True; end else begin // start_i urnd_reseed_req_o = ~SecSkipUrndReseedAtStart; - state_d = OtbnStartStopStateUrndRefresh; + state_d = AccStartStopStateUrndRefresh; end end end - OtbnStartStopStateUrndRefresh: begin + AccStartStopStateUrndRefresh: begin urnd_reseed_req_o = ~skip_reseed_q; if (stop) begin if (mubi4_test_false_strict(wipe_after_urnd_refresh_q)) begin // We are told to stop and don't have to wipe after the current URND refresh is ack'd, // so we lock immediately. - state_d = OtbnStartStopStateLocked; + state_d = AccStartStopStateLocked; end else begin // We are told to stop but should wipe after the current URND refresh is ack'd, so we // wait for the ACK and then do a secure wipe. @@ -242,7 +242,7 @@ module otbn_start_stop_control expect_secure_wipe = 1'b1; secure_wipe_running_d = 1'b1; if (urnd_reseed_ack_i) begin - state_d = OtbnStartStopSecureWipeWdrUrnd; + state_d = AccStartStopSecureWipeWdrUrnd; end end end else begin @@ -250,7 +250,7 @@ module otbn_start_stop_control // We are not stopping and we don't have to wipe after the current URND refresh is // ack'd, so we wait for the ACK and then start executing. if (urnd_reseed_ack_i || skip_reseed_q) begin - state_d = OtbnStartStopStateRunning; + state_d = AccStartStopStateRunning; end end else begin // We are not stopping but should wipe after the current URND refresh is ack'd, so we @@ -259,23 +259,23 @@ module otbn_start_stop_control expect_secure_wipe = 1'b1; secure_wipe_running_d = 1'b1; if (urnd_reseed_ack_i) begin - state_d = OtbnStartStopSecureWipeWdrUrnd; + state_d = AccStartStopSecureWipeWdrUrnd; end end end end - OtbnStartStopStateRunning: begin + AccStartStopStateRunning: begin urnd_advance_o = ~SecMuteUrnd; allow_secure_wipe = 1'b1; if (stop) begin secure_wipe_running_d = 1'b1; - state_d = OtbnStartStopSecureWipeWdrUrnd; + state_d = AccStartStopSecureWipeWdrUrnd; end end // SEC_CM: DATA_REG_SW.SEC_WIPE // Writing random numbers to the wide data registers. - OtbnStartStopSecureWipeWdrUrnd: begin + AccStartStopSecureWipeWdrUrnd: begin urnd_advance_o = 1'b1; addr_cnt_inc = 1'b1; sec_wipe_wdr_o = 1'b1; @@ -296,13 +296,13 @@ module otbn_start_stop_control // cycle early here. sec_wipe_wdr_o = 1'b0; sec_wipe_wdr_urnd_o = 1'b0; - state_d = OtbnStartStopSecureWipeAccModBaseUrnd; + state_d = AccStartStopSecureWipeAccModBaseUrnd; end end // Writing random numbers to the accumulator, modulus and the base registers. // addr_cnt_q wraps around to 0 when first moving to this state, and we need to // supress writes to the zero register and the call stack. - OtbnStartStopSecureWipeAccModBaseUrnd: begin + AccStartStopSecureWipeAccModBaseUrnd: begin urnd_advance_o = 1'b1; addr_cnt_inc = 1'b1; allow_secure_wipe = 1'b1; @@ -312,7 +312,7 @@ module otbn_start_stop_control // accumulators, modulus, and kmac WSR registers. sec_wipe_acc_urnd_o = (addr_cnt_q == 6'b000000); sec_wipe_mod_urnd_o = (addr_cnt_q == 6'b000001); - if (OtbnPQCEn) begin + if (AccPQCEn) begin sec_wipe_kmac_regs_urnd_o = (addr_cnt_q == 6'b000010); sec_wipe_acch_urnd_o = (addr_cnt_q == 6'b000011); end @@ -320,12 +320,12 @@ module otbn_start_stop_control sec_wipe_base_o = (addr_cnt_q > 6'b000001); sec_wipe_base_urnd_o = (addr_cnt_q > 6'b000001); if (addr_cnt_q == 6'b011111) begin - state_d = OtbnStartStopSecureWipeAllZero; + state_d = AccStartStopSecureWipeAllZero; end end // Writing zeros to the CSRs and reset the stack. The other registers are intentionally not // overwritten with zero. - OtbnStartStopSecureWipeAllZero: begin + AccStartStopSecureWipeAllZero: begin sec_wipe_zero_o = 1'b1; allow_secure_wipe = 1'b1; expect_secure_wipe = 1'b1; @@ -335,24 +335,24 @@ module otbn_start_stop_control if (mubi4_test_false_strict(wipe_after_urnd_refresh_q)) begin // This is the first round of wiping with random numbers, refresh URND and do a second // round. - state_d = OtbnStartStopStateUrndRefresh; + state_d = AccStartStopStateUrndRefresh; secure_wipe_running_d = 1'b1; wipe_after_urnd_refresh_d = MuBi4True; end else begin // This is the second round of wiping with random numbers, so the secure wipe is // complete. - state_d = OtbnStartStopSecureWipeComplete; + state_d = AccStartStopSecureWipeComplete; secure_wipe_running_d = 1'b0; secure_wipe_ack_o = 1'b1; end end - OtbnStartStopSecureWipeComplete: begin + AccStartStopSecureWipeComplete: begin urnd_advance_o = 1'b1; rma_ack_d = rma_req_i; - state_d = should_lock_d ? OtbnStartStopStateLocked : OtbnStartStopStateHalt; + state_d = should_lock_d ? AccStartStopStateLocked : AccStartStopStateHalt; wipe_after_urnd_refresh_d = MuBi4False; end - OtbnStartStopStateLocked: begin + AccStartStopStateLocked: begin // SEC_CM: START_STOP_CTRL.FSM.GLOBAL_ESC // SEC_CM: START_STOP_CTRL.FSM.LOCAL_ESC // @@ -363,16 +363,16 @@ module otbn_start_stop_control // We should never get here. If we do (e.g. via a malicious glitch), error out immediately. state_error_d = 1'b1; rma_ack_d = MuBi4False; - state_d = OtbnStartStopStateLocked; + state_d = AccStartStopStateLocked; end endcase if (urnd_reseed_ack_i && - !(state_q inside {OtbnStartStopStateInitial, OtbnStartStopStateUrndRefresh})) begin + !(state_q inside {AccStartStopStateInitial, AccStartStopStateUrndRefresh})) begin // We should never receive an ACK from URND when we're not refreshing the URND. Signal an // error if we see a stray ACK and lock the FSM. spurious_urnd_ack_error = 1'b1; - state_d = OtbnStartStopStateLocked; + state_d = AccStartStopStateLocked; end // If the MuBi signals take on invalid values, something bad is happening. Put them back to @@ -383,35 +383,35 @@ module otbn_start_stop_control // time rma_req_i has for sure stabilized. if (mubi4_test_invalid(escalate_en_i)) begin mubi_err_d = 1'b1; - state_d = OtbnStartStopStateLocked; + state_d = AccStartStopStateLocked; end if (mubi4_test_invalid(wipe_after_urnd_refresh_q)) begin wipe_after_urnd_refresh_d = MuBi4False; mubi_err_d = 1'b1; - state_d = OtbnStartStopStateLocked; + state_d = AccStartStopStateLocked; end if (mubi4_test_invalid(rma_ack_q)) begin rma_ack_d = MuBi4False; mubi_err_d = 1'b1; - state_d = OtbnStartStopStateLocked; + state_d = AccStartStopStateLocked; end end // Latch initial secure wipe done. - assign init_sec_wipe_done_d = (state_q == OtbnStartStopSecureWipeComplete) ? 1'b1 : // set + assign init_sec_wipe_done_d = (state_q == AccStartStopSecureWipeComplete) ? 1'b1 : // set init_sec_wipe_done_q; // keep // Logic separate from main FSM code to avoid false combinational loop warning from verilator assign controller_start_o = // The controller start pulse is fired when finishing the initial URND reseed. - ((state_q == OtbnStartStopStateUrndRefresh) & (urnd_reseed_ack_i | skip_reseed_q) & + ((state_q == AccStartStopStateUrndRefresh) & (urnd_reseed_ack_i | skip_reseed_q) & mubi4_test_false_strict(wipe_after_urnd_refresh_q)); - assign done_o = ((state_q == OtbnStartStopSecureWipeComplete && init_sec_wipe_done_q) || - (stop && (state_q == OtbnStartStopStateUrndRefresh) && + assign done_o = ((state_q == AccStartStopSecureWipeComplete && init_sec_wipe_done_q) || + (stop && (state_q == AccStartStopStateUrndRefresh) && mubi4_test_false_strict(wipe_after_urnd_refresh_q)) || - (spurious_urnd_ack_error && !(state_q inside {OtbnStartStopStateHalt, - OtbnStartStopStateLocked}) && + (spurious_urnd_ack_error && !(state_q inside {AccStartStopStateHalt, + AccStartStopStateLocked}) && init_sec_wipe_done_q) || (mubi_err_d && !mubi_err_q)); assign addr_cnt_d = addr_cnt_inc ? (addr_cnt_q + 6'd1) : 6'd0; @@ -453,7 +453,7 @@ module otbn_start_stop_control assign dropped_secure_wipe_req = expect_secure_wipe & init_sec_wipe_done_d & ~secure_wipe_req_i; // Delay the "glitch req/ack" error signal by a cycle. Otherwise, you end up with a combinatorial - // loop through the escalation signal that our fatal_error_o causes otbn_core to pass to the + // loop through the escalation signal that our fatal_error_o causes acc_core to pass to the // controller. assign secure_wipe_error_d = spurious_secure_wipe_req | dropped_secure_wipe_req; always_ff @(posedge clk_i or negedge rst_ni) begin @@ -481,17 +481,17 @@ module otbn_start_stop_control assign secure_wipe_running_o = secure_wipe_running_q; `ASSERT(StartStopStateValid_A, - state_q inside {OtbnStartStopStateInitial, - OtbnStartStopStateHalt, - OtbnStartStopStateUrndRefresh, - OtbnStartStopStateRunning, - OtbnStartStopSecureWipeWdrUrnd, - OtbnStartStopSecureWipeAccModBaseUrnd, - OtbnStartStopSecureWipeAllZero, - OtbnStartStopSecureWipeComplete, - OtbnStartStopStateLocked}) + state_q inside {AccStartStopStateInitial, + AccStartStopStateHalt, + AccStartStopStateUrndRefresh, + AccStartStopStateRunning, + AccStartStopSecureWipeWdrUrnd, + AccStartStopSecureWipeAccModBaseUrnd, + AccStartStopSecureWipeAllZero, + AccStartStopSecureWipeComplete, + AccStartStopStateLocked}) `ASSERT(StartSecureWipeImpliesRunning_A, - $rose(secure_wipe_req_i) |-> (state_q == OtbnStartStopStateRunning)) + $rose(secure_wipe_req_i) |-> (state_q == AccStartStopStateRunning)) endmodule diff --git a/hw/ip/otbn/rtl/bn_vec_core/otbn_bignum_mul.sv b/hw/ip/acc/rtl/bn_vec_core/acc_bignum_mul.sv similarity index 97% rename from hw/ip/otbn/rtl/bn_vec_core/otbn_bignum_mul.sv rename to hw/ip/acc/rtl/bn_vec_core/acc_bignum_mul.sv index c6532aa09d0..bbb98de243a 100644 --- a/hw/ip/otbn/rtl/bn_vec_core/otbn_bignum_mul.sv +++ b/hw/ip/acc/rtl/bn_vec_core/acc_bignum_mul.sv @@ -1,13 +1,13 @@ // Copyright lowRISC contributors (OpenTitan project). // Copyright zeroRISC Inc. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module otbn_bignum_mul +module acc_bignum_mul ( input logic [256-1:0] A, input logic [256-1:0] B, diff --git a/hw/ip/otbn/rtl/bn_vec_core/buffer_bit.sv b/hw/ip/acc/rtl/bn_vec_core/buffer_bit.sv similarity index 97% rename from hw/ip/otbn/rtl/bn_vec_core/buffer_bit.sv rename to hw/ip/acc/rtl/bn_vec_core/buffer_bit.sv index f8846461724..c55aa1da73e 100644 --- a/hw/ip/otbn/rtl/bn_vec_core/buffer_bit.sv +++ b/hw/ip/acc/rtl/bn_vec_core/buffer_bit.sv @@ -1,6 +1,6 @@ // Copyright zeroRISC Inc. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -14,7 +14,7 @@ // compute in_A + in_B (A + B) or in_A + ~in_B + 1 (A + B + cin). module buffer_bit - import otbn_pkg::*; + import acc_pkg::*; ( input logic [WLEN-1:0] A, input logic [WLEN-1:0] B, diff --git a/hw/ip/otbn/rtl/bn_vec_core/unified_mul.sv b/hw/ip/acc/rtl/bn_vec_core/unified_mul.sv similarity index 99% rename from hw/ip/otbn/rtl/bn_vec_core/unified_mul.sv rename to hw/ip/acc/rtl/bn_vec_core/unified_mul.sv index b39bfa4f6e3..98b56919104 100644 --- a/hw/ip/otbn/rtl/bn_vec_core/unified_mul.sv +++ b/hw/ip/acc/rtl/bn_vec_core/unified_mul.sv @@ -1,6 +1,6 @@ // Copyright zeroRISC Inc. // Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +// "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" // (https://eprint.iacr.org/2025/2028). // Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. // Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/hw/ip/otbn/syn/otbn_gtech_syn_cfg.hjson b/hw/ip/acc/syn/acc_gtech_syn_cfg.hjson similarity index 98% rename from hw/ip/otbn/syn/otbn_gtech_syn_cfg.hjson rename to hw/ip/acc/syn/acc_gtech_syn_cfg.hjson index f21e6abc542..cf029fd9e19 100644 --- a/hw/ip/otbn/syn/otbn_gtech_syn_cfg.hjson +++ b/hw/ip/acc/syn/acc_gtech_syn_cfg.hjson @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 { // Top level dut name (sv module). - name: otbn + name: acc // Fusesoc core file used for building the file list. fusesoc_core: lowrisc:ip:{name}:0.1 diff --git a/hw/ip/otbn/syn/otbn_syn_cfg.hjson b/hw/ip/acc/syn/acc_syn_cfg.hjson similarity index 97% rename from hw/ip/otbn/syn/otbn_syn_cfg.hjson rename to hw/ip/acc/syn/acc_syn_cfg.hjson index 7c309708c38..6e96814c4c4 100644 --- a/hw/ip/otbn/syn/otbn_syn_cfg.hjson +++ b/hw/ip/acc/syn/acc_syn_cfg.hjson @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 { // Top level dut name (sv module). - name: otbn + name: acc // Fusesoc core file used for building the file list. fusesoc_core: lowrisc:ip:{name}:0.1 diff --git a/hw/ip/otbn/syn/constraints.sdc b/hw/ip/acc/syn/constraints.sdc similarity index 100% rename from hw/ip/otbn/syn/constraints.sdc rename to hw/ip/acc/syn/constraints.sdc diff --git a/hw/ip/otbn/syn/post_elab_gtech.tcl b/hw/ip/acc/syn/post_elab_gtech.tcl similarity index 100% rename from hw/ip/otbn/syn/post_elab_gtech.tcl rename to hw/ip/acc/syn/post_elab_gtech.tcl diff --git a/hw/ip/acc/util/BUILD b/hw/ip/acc/util/BUILD new file mode 100644 index 00000000000..22233f25c77 --- /dev/null +++ b/hw/ip/acc/util/BUILD @@ -0,0 +1,83 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +load("@rules_python//python:defs.bzl", "py_binary") +load("@ot_python_deps//:requirements.bzl", "requirement") + +package(default_visibility = ["//visibility:public"]) + +py_binary( + name = "acc_as", + srcs = ["acc_as.py"], + deps = [ + "//hw/ip/acc/util/shared:bit_ranges", + "//hw/ip/acc/util/shared:encoding", + "//hw/ip/acc/util/shared:insn_yaml", + "//hw/ip/acc/util/shared:operand", + "//hw/ip/acc/util/shared:toolchain", + ], +) + +py_binary( + name = "acc_ld", + srcs = ["acc_ld.py"], + deps = [ + "//hw/ip/acc/util/shared:mem_layout", + "//hw/ip/acc/util/shared:toolchain", + requirement("mako"), + ], +) + +py_binary( + name = "acc_objdump", + srcs = ["acc_objdump.py"], + deps = [ + "//hw/ip/acc/util/shared:insn_yaml", + "//hw/ip/acc/util/shared:toolchain", + ], +) + +py_binary( + name = "check_const_time", + srcs = ["check_const_time.py"], + deps = [ + "//hw/ip/acc/util/shared:check", + "//hw/ip/acc/util/shared:control_flow", + "//hw/ip/acc/util/shared:decode", + "//hw/ip/acc/util/shared:information_flow_analysis", + requirement("pyelftools"), + ], +) + +py_binary( + name = "get_instruction_count_range", + srcs = ["get_instruction_count_range.py"], + deps = [ + "//hw/ip/acc/util/shared:decode", + "//hw/ip/acc/util/shared:instruction_count_range", + ], +) + +py_binary( + name = "gen_instruction_count_header", + srcs = ["gen_instruction_count_header.py"], + deps = [ + "//hw/ip/acc/util/shared:decode", + "//hw/ip/acc/util/shared:instruction_count_range", + requirement("mako"), + requirement("pyelftools"), + ], +) + +py_binary( + name = "acc_sim_test", + srcs = ["acc_sim_test.py"], + deps = [ + "//hw/ip/acc/util/shared:check", + "//hw/ip/acc/util/shared:mem_layout", + "//hw/ip/acc/util/shared:reg_dump", + requirement("pyelftools"), + ], +) diff --git a/hw/ip/otbn/util/Makefile b/hw/ip/acc/util/Makefile similarity index 70% rename from hw/ip/otbn/util/Makefile rename to hw/ip/acc/util/Makefile index ab2bc4495c1..86b6f5678ae 100644 --- a/hw/ip/otbn/util/Makefile +++ b/hw/ip/acc/util/Makefile @@ -5,10 +5,10 @@ .PHONY: all all: lint asm-check -# We need a directory to build stuff and use the "otbn/util" namespace +# We need a directory to build stuff and use the "acc/util" namespace # in the top-level build-bin directory. repo-top := ../../../.. -build-dir := $(repo-top)/build-bin/otbn/util +build-dir := $(repo-top)/build-bin/acc/util cs-build-dir := $(build-dir)/code-snippets lint-build-dir := $(build-dir)/lint @@ -16,7 +16,7 @@ $(build-dir) $(lint-build-dir): mkdir -p $@ pylibs := $(wildcard shared/*.py docs/*.py) -pyscripts := yaml_to_doc.py otbn_as.py otbn_ld.py otbn_objdump.py docs/md_isrs.py +pyscripts := yaml_to_doc.py acc_as.py acc_ld.py acc_objdump.py docs/md_isrs.py lint-stamps := $(foreach s,$(pyscripts),$(lint-build-dir)/$(s).stamp) $(lint-build-dir)/%.stamp: % $(pylibs) | $(lint-build-dir) @@ -30,12 +30,12 @@ lint: $(lint-stamps) # Target that assembles and links each of the code snippets to make # sure the toolchain is in a reasonable shape. -otbn-code-snippets-obj-dir := $(cs-build-dir) -otbn-code-snippets-bin-dir := $(cs-build-dir) -otbn-code-snippets-util-dir := . +acc-code-snippets-obj-dir := $(cs-build-dir) +acc-code-snippets-bin-dir := $(cs-build-dir) +acc-code-snippets-util-dir := . .PHONY: asm-check -asm-check: $(otbn-code-snippets-elfs) +asm-check: $(acc-code-snippets-elfs) .PHONY: clean clean: diff --git a/hw/ip/otbn/util/otbn_as.py b/hw/ip/acc/util/acc_as.py similarity index 97% rename from hw/ip/otbn/util/otbn_as.py rename to hw/ip/acc/util/acc_as.py index 062cffad793..cfe538afc6b 100755 --- a/hw/ip/otbn/util/otbn_as.py +++ b/hw/ip/acc/util/acc_as.py @@ -5,16 +5,16 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028) # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. -'''A wrapper around riscv32-unknown-elf-as for OTBN +'''A wrapper around riscv32-unknown-elf-as for ACC Partial support: - This doesn't currently support .include directives fully (the included file - will not be transformed, so OTBN instructions won't work there). + will not be transformed, so ACC instructions won't work there). - .file support assumes we're not using DWARF2 file numbers. @@ -409,8 +409,8 @@ def parse_positionals( # argument). space_args = ['--debug-prefix-map', '--defsym', '-I', '-o'] - # OTBN-specific flags - otbn_flags = ['--otbn-translate'] + # ACC-specific flags + acc_flags = ['--acc-translate'] flags = set() @@ -421,7 +421,7 @@ def parse_positionals( expecting_arg = False continue - if arg in otbn_flags: + if arg in acc_flags: flags.add(arg) if arg in space_args: @@ -436,12 +436,12 @@ def parse_positionals( positionals.append(arg) if '-h' in others or '--help' in others: - print('otbn_as.py:\n\n' - 'A wrapper around riscv32-unknown-elf-as for OTBN.\n' + print('acc_as.py:\n\n' + 'A wrapper around riscv32-unknown-elf-as for ACC.\n' 'Most arguments are passed through: see "man as" ' 'for more information.\n' '\n' - ' --otbn-translate: Translate the input and dump to ' + ' --acc-translate: Translate the input and dump to ' 'stdout rather than calling as.\n') sys.exit(0) @@ -456,7 +456,7 @@ def _unpack_lx(where: str, mnemonic: str, keys_list = list(op_to_expr.keys()) raise RuntimeError(f'When expanding {umnem}, got wrong op_to_expr ' f'keys ({keys_list}). This is a mismatch between ' - f'expand_{mnemonic} in otbn_as.py and the operands ' + f'expand_{mnemonic} in acc_as.py and the operands ' f'for {umnem} in insns.yml.') grd = op_to_expr['grd'] @@ -488,7 +488,7 @@ def expand_li(where: str, op_to_expr: Dict[str, Optional[str]]) -> List[str]: # This logic is slightly complicated so it has some associated tests in the # ISS testsuite (where we can run the results). If adding more cleverness # to this or fixing bugs, we should also add a check at - # hw/ip/otbn/dv/otbnsim/test/simple/pseudos/li.s. + # hw/ip/acc/dv/accsim/test/simple/pseudos/li.s. grd_txt, imm = _unpack_lx(where, 'li', op_to_expr) try: @@ -555,7 +555,7 @@ def expand_la(where: str, op_to_expr: Dict[str, Optional[str]]) -> List[str]: # # where delta = symbol - pc. # - # For OTBN, both IMEM and DMEM are small. This means that we can represent + # For ACC, both IMEM and DMEM are small. This means that we can represent # every symbol in 12 bits, so "la rd, symbol" can expand to: # # addi rd, x0, %lo(symbol) @@ -572,7 +572,7 @@ def expand_la(where: str, op_to_expr: Dict[str, Optional[str]]) -> List[str]: class Transformer: - '''A simple parser/transformer for OTBN input files + '''A simple parser/transformer for ACC input files We have to do some basic tokenization to understand things like comments and strings (which can contain embedded newlines). We don't want to perturb @@ -698,7 +698,7 @@ def mk_raw_line(self, insn: Insn, op_to_expr: Dict[str, raise RuntimeError( '{}:{}: Cannot encode {!r} operand for ' '{!r} instruction without a current PC ' - '(which is not known to otbn_as.py).'.format( + '(which is not known to acc_as.py).'.format( self.in_path, self.line_number, expr, insn.mnemonic)) from None @@ -1254,12 +1254,12 @@ def run_binutils_as(other_args: List[str], inputs: List[str]) -> int: default_args = [ # Don't ask the linker to do relaxation because, in some cases, this - # might generate a GP-relative load. OTBN doesn't treat x3 (gp) + # might generate a GP-relative load. ACC doesn't treat x3 (gp) # specially, so this won't work. '-mno-relax', - # OTBN isn't a standard RISC-V architecture, disable .riscv.attributes. + # ACC isn't a standard RISC-V architecture, disable .riscv.attributes. '-mno-arch-attr', - # OTBN is based on RV32I without any hard float support. + # ACC is based on RV32I without any hard float support. '-mabi=ilp32', # Produce debug info for source line mapping. '-g', @@ -1276,7 +1276,7 @@ def run_binutils_as(other_args: List[str], inputs: List[str]) -> int: def main(argv: List[str]) -> int: files, other_args, flags = parse_positionals(argv) files = files or ['--'] - just_translate = '--otbn-translate' in flags + just_translate = '--acc-translate' in flags copts = [] for arg in other_args: @@ -1288,7 +1288,7 @@ def main(argv: List[str]) -> int: # files is now a nonempty list of input files. Rather unusually, '--' # (rather than '-') denotes standard input. - with tempfile.TemporaryDirectory(suffix='.otbn-gcc') as tmpdir: + with tempfile.TemporaryDirectory(suffix='.acc-gcc') as tmpdir: try: files = run_c_preprocessor(tmpdir, files, copts) # add copts = -D for preprocessor except RuntimeError as err: @@ -1319,15 +1319,15 @@ def main(argv: List[str]) -> int: if insn.mnemonic not in _PSEUDO_OP_ASSEMBLERS: sys.stderr.write( "Instruction {!r} has python-pseudo-op true, " - "but otbn_as.py doesn't have a custom assembler " + "but acc_as.py doesn't have a custom assembler " "for it.\n".format(insn.mnemonic)) return 1 - # Try to match up OTBN instruction encodings with .insn schemes (as stored + # Try to match up ACC instruction encodings with .insn schemes (as stored # in RISCV_FORMATS). mnem_to_rve = find_insn_schemes(insns_file.mnemonic_to_insn) - with tempfile.TemporaryDirectory(suffix='.otbn-as') as tmpdir: + with tempfile.TemporaryDirectory(suffix='.acc-as') as tmpdir: try: transformed = transform_inputs(tmpdir, files, insns_file, mnem_to_rve, glued_insns_dec_len, diff --git a/hw/ip/otbn/util/otbn_ld.py b/hw/ip/acc/util/acc_ld.py similarity index 91% rename from hw/ip/otbn/util/otbn_ld.py rename to hw/ip/acc/util/acc_ld.py index 2aa7e1958e6..05ded2a0d0a 100755 --- a/hw/ip/otbn/util/otbn_ld.py +++ b/hw/ip/acc/util/acc_ld.py @@ -2,9 +2,9 @@ # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''A wrapper around riscv32-unknown-elf-ld for OTBN +'''A wrapper around riscv32-unknown-elf-ld for ACC -This just adds the OTBN linker script and calls the underlying +This just adds the ACC linker script and calls the underlying linker.''' import os @@ -46,9 +46,9 @@ def interpolate_linker_script(in_path: str, out_path: str) -> None: @contextmanager def mk_linker_script() -> Iterator[str]: ld_in = os.path.abspath( - os.path.join(os.path.dirname(__file__), '..', 'data', 'otbn.ld.tpl')) - with tempfile.TemporaryDirectory(prefix='otbn-ld-') as tmpdir: - ld_out = os.path.join(tmpdir, 'otbn.ld') + os.path.join(os.path.dirname(__file__), '..', 'data', 'acc.ld.tpl')) + with tempfile.TemporaryDirectory(prefix='acc-ld-') as tmpdir: + ld_out = os.path.join(tmpdir, 'acc.ld') try: interpolate_linker_script(ld_in, ld_out) except RuntimeError as err: diff --git a/hw/ip/otbn/util/otbn_objdump.py b/hw/ip/acc/util/acc_objdump.py similarity index 95% rename from hw/ip/otbn/util/otbn_objdump.py rename to hw/ip/acc/util/acc_objdump.py index 6a4d01dc93c..3dbdf343966 100755 --- a/hw/ip/otbn/util/otbn_objdump.py +++ b/hw/ip/acc/util/acc_objdump.py @@ -3,7 +3,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''A wrapper around riscv32-unknown-elf-objdump for OTBN''' +'''A wrapper around riscv32-unknown-elf-objdump for ACC''' import re import subprocess @@ -41,7 +41,7 @@ def snoop_disasm_flags(argv: List[str]) -> bool: return False -# OTBN instructions are 32 bit wide, so there's just one "word" in the second +# ACC instructions are 32 bit wide, so there's just one "word" in the second # column. The stuff that gets passed through looks like this: # # 84: 8006640b 0x8006640b @@ -56,7 +56,7 @@ def snoop_disasm_flags(argv: List[str]) -> bool: def transform_disasm_line(line: str, insns_file: InsnsFile) -> str: - '''Transform filter to insert OTBN disasm as needed''' + '''Transform filter to insert ACC disasm as needed''' match = _RAW_INSN_RE.match(line) if match is None: return line diff --git a/hw/ip/otbn/util/otbn_profile.py b/hw/ip/acc/util/acc_profile.py similarity index 96% rename from hw/ip/otbn/util/otbn_profile.py rename to hw/ip/acc/util/acc_profile.py index 54f3cd46008..5351ceaaaf2 100755 --- a/hw/ip/otbn/util/otbn_profile.py +++ b/hw/ip/acc/util/acc_profile.py @@ -54,7 +54,7 @@ def pretty_print_profile(stats): parser = argparse.ArgumentParser() parser.add_argument( 'stats', type=argparse.FileType('r'), - help=('Statistics as dumped by the OTBN simulator.')) + help=('Statistics as dumped by the ACC simulator.')) args = parser.parse_args() stats = parse_function_stats(args.stats) diff --git a/hw/ip/otbn/util/otbn_sim_test.py b/hw/ip/acc/util/acc_sim_test.py similarity index 94% rename from hw/ip/otbn/util/otbn_sim_test.py rename to hw/ip/acc/util/acc_sim_test.py index 99d740b87da..6db33c0dfeb 100755 --- a/hw/ip/otbn/util/otbn_sim_test.py +++ b/hw/ip/acc/util/acc_sim_test.py @@ -4,7 +4,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''Run a test on the OTBN simulator.''' +'''Run a test on the ACC simulator.''' import argparse import subprocess @@ -17,7 +17,7 @@ from shared.elf import read_elf from shared.reg_dump import parse_reg_dump from shared.dmem_dump import parse_dmem_exp, parse_actual_dmem -from shared.testcase import OtbnTestCase +from shared.testcase import AccTestCase # Names of special registers ERR_BITS = 'ERR_BITS' @@ -25,7 +25,7 @@ STOP_PC = 'STOP_PC' -# copied from hw/ip/otbn/dv/otbnsim/sim/constants.py +# copied from hw/ip/acc/dv/accsim/sim/constants.py class ErrBits(IntEnum): '''A copy of the list of bits in the ERR_BITS register.''' BAD_DATA_ADDR = 1 << 0 @@ -58,7 +58,7 @@ def get_err_names(err: int) -> List[str]: def main() -> int: parser = argparse.ArgumentParser() parser.add_argument('simulator', - help='Path to the standalone OTBN simulator.') + help='Path to the standalone ACC simulator.') parser.add_argument('--expected_regs', metavar='FILE', type=argparse.FileType('r'), @@ -85,7 +85,7 @@ def main() -> int: action='store_true', help='Print statistics (makes test run slower).') parser.add_argument('elf', - help='Path to the .elf file for the OTBN program.') + help='Path to the .elf file for the ACC program.') parser.add_argument('-v', '--verbose', action='store_true') args = parser.parse_args() @@ -101,7 +101,7 @@ def main() -> int: testcase = None if args.testcase: - testcase = OtbnTestCase.from_hjson(args.testcase.read(), symbols) + testcase = AccTestCase.from_hjson(args.testcase.read(), symbols) cmd_flags.extend([ "--testcase", args.testcase.name, @@ -168,7 +168,7 @@ def main() -> int: # mismatched registers. if actual_err != 0: err_names = ", ".join(get_err_names(actual_err)) - result.err(f"OTBN encountered an unexpected error: {err_names}.\n" + result.err(f"ACC encountered an unexpected error: {err_names}.\n" f" {ERR_BITS}\t= {actual_err:#010x}\n" f" {INSN_CNT}\t= {insn_cnt:#010x}\n" f" {STOP_PC}\t= {stop_pc:#010x}") diff --git a/hw/ip/otbn/util/analyze_information_flow.py b/hw/ip/acc/util/analyze_information_flow.py similarity index 98% rename from hw/ip/otbn/util/analyze_information_flow.py rename to hw/ip/acc/util/analyze_information_flow.py index 4699d5016c2..69459faf752 100755 --- a/hw/ip/otbn/util/analyze_information_flow.py +++ b/hw/ip/acc/util/analyze_information_flow.py @@ -17,7 +17,7 @@ def main() -> int: parser = argparse.ArgumentParser(description=( - 'Analyze the control flow and information flow of an OTBN ' + 'Analyze the control flow and information flow of an ACC ' 'program or subroutine.')) parser.add_argument('elf', help=('The .elf file to check.')) parser.add_argument( diff --git a/hw/ip/otbn/util/check_call_stack.py b/hw/ip/acc/util/check_call_stack.py similarity index 94% rename from hw/ip/otbn/util/check_call_stack.py rename to hw/ip/acc/util/check_call_stack.py index 5a18daf9ea5..672671b83e3 100755 --- a/hw/ip/otbn/util/check_call_stack.py +++ b/hw/ip/acc/util/check_call_stack.py @@ -8,7 +8,7 @@ from typing import Dict from shared.check import CheckResult -from shared.decode import OTBNProgram, decode_elf +from shared.decode import ACCProgram, decode_elf from shared.insn_yaml import Insn from shared.operand import RegOperandType @@ -29,7 +29,7 @@ def _check_call_stack_insn(insn: Insn, operands: Dict[str, int]) -> bool: return True -def check_call_stack(program: OTBNProgram) -> CheckResult: +def check_call_stack(program: ACCProgram) -> CheckResult: '''Check that the special register x1 is used safely. If x1 is used for purposes unrelated to the call stack, it can trigger a diff --git a/hw/ip/otbn/util/check_const_time.py b/hw/ip/acc/util/check_const_time.py similarity index 99% rename from hw/ip/otbn/util/check_const_time.py rename to hw/ip/acc/util/check_const_time.py index 88db042d499..f278de69907 100755 --- a/hw/ip/otbn/util/check_const_time.py +++ b/hw/ip/acc/util/check_const_time.py @@ -18,7 +18,7 @@ def main() -> int: parser = argparse.ArgumentParser( description='Analyze whether secret data affects the control flow of ' - 'an OTBN program or subroutine.') + 'an ACC program or subroutine.') parser.add_argument('elf', help=('The .elf file to check.')) parser.add_argument('--verbose', action='store_true') parser.add_argument( diff --git a/hw/ip/otbn/util/check_loop.py b/hw/ip/acc/util/check_loop.py similarity index 93% rename from hw/ip/otbn/util/check_loop.py rename to hw/ip/acc/util/check_loop.py index 8b21337bb34..b42311ab7e8 100755 --- a/hw/ip/otbn/util/check_loop.py +++ b/hw/ip/acc/util/check_loop.py @@ -8,11 +8,11 @@ from typing import List from shared.check import CheckResult -from shared.decode import OTBNProgram, decode_elf +from shared.decode import ACCProgram, decode_elf from shared.section import CodeSection -def _get_pcs_for_mnemonics(program: OTBNProgram, +def _get_pcs_for_mnemonics(program: ACCProgram, mnems: List[str]) -> List[int]: '''Gets all PCs in the program holding the given instruction.''' return [ @@ -21,17 +21,17 @@ def _get_pcs_for_mnemonics(program: OTBNProgram, ] -def _get_branches(program: OTBNProgram) -> List[int]: +def _get_branches(program: ACCProgram) -> List[int]: '''Gets the PCs of all branch instructions (BEQ and BNE) in the program.''' return _get_pcs_for_mnemonics(program, ['bne', 'beq']) -def _get_loop_starts(program: OTBNProgram) -> List[int]: +def _get_loop_starts(program: ACCProgram) -> List[int]: '''Gets the start PCs of all loops (LOOP and LOOPI) in the program.''' return _get_pcs_for_mnemonics(program, ['loop', 'loopi']) -def _get_loops(program: OTBNProgram) -> List[CodeSection]: +def _get_loops(program: ACCProgram) -> List[CodeSection]: '''Gets the PC ranges of all loops (LOOP and LOOPI) in the program.''' loop_starts = _get_loop_starts(program) loops = [] @@ -42,7 +42,7 @@ def _get_loops(program: OTBNProgram) -> List[CodeSection]: return loops -def _check_loop_iterations(program: OTBNProgram, +def _check_loop_iterations(program: ACCProgram, loops: List[CodeSection]) -> CheckResult: '''Checks number of iterations for loopi. @@ -64,7 +64,7 @@ def _check_loop_iterations(program: OTBNProgram, return out -def _check_loop_end_insns(program: OTBNProgram, +def _check_loop_end_insns(program: ACCProgram, loops: List[CodeSection]) -> CheckResult: '''Checks that loops do not end in control flow instructions. @@ -80,7 +80,7 @@ def _check_loop_end_insns(program: OTBNProgram, return out -def _check_loop_inclusion(program: OTBNProgram, +def _check_loop_inclusion(program: ACCProgram, loops: List[CodeSection]) -> CheckResult: '''Checks that inner loops are fully contained within outer loops. @@ -97,7 +97,7 @@ def _check_loop_inclusion(program: OTBNProgram, return out -def _check_loop_branching(program: OTBNProgram, +def _check_loop_branching(program: ACCProgram, loops: List[CodeSection]) -> CheckResult: '''Checks that there are no branches into or out of loop bodies. @@ -154,11 +154,11 @@ def _check_loop_branching(program: OTBNProgram, return out -def _check_loop_stack(program: OTBNProgram, +def _check_loop_stack(program: ACCProgram, loops: List[CodeSection]) -> CheckResult: '''Checks that loops will likely be properly cleared from loop stack. - The checks here are based on the OTBN hardware IP documentation on loop + The checks here are based on the ACC hardware IP documentation on loop nesting. From the docs: To avoid polluting the loop stack and avoid surprising behaviour, the @@ -197,7 +197,7 @@ def _check_loop_stack(program: OTBNProgram, return out -def check_loop(program: OTBNProgram) -> CheckResult: +def check_loop(program: ACCProgram) -> CheckResult: '''Check that loops are properly formed. Performs three checks to rule out certain classes of loop errors and diff --git a/hw/ip/otbn/util/docs/get_impl.py b/hw/ip/acc/util/docs/get_impl.py similarity index 100% rename from hw/ip/otbn/util/docs/get_impl.py rename to hw/ip/acc/util/docs/get_impl.py diff --git a/hw/ip/otbn/util/docs/md_isrs.py b/hw/ip/acc/util/docs/md_isrs.py similarity index 100% rename from hw/ip/otbn/util/docs/md_isrs.py rename to hw/ip/acc/util/docs/md_isrs.py diff --git a/hw/ip/otbn/util/gen_instruction_count_header.py b/hw/ip/acc/util/gen_instruction_count_header.py similarity index 94% rename from hw/ip/otbn/util/gen_instruction_count_header.py rename to hw/ip/acc/util/gen_instruction_count_header.py index c28bfc1eed1..b7550b332a0 100644 --- a/hw/ip/otbn/util/gen_instruction_count_header.py +++ b/hw/ip/acc/util/gen_instruction_count_header.py @@ -12,7 +12,7 @@ from shared.decode import decode_elf from shared.instruction_count_range import program_insn_count_range ''' -Compute the range of instruction counts for each OTBN program mode, and +Compute the range of instruction counts for each ACC program mode, and generate a header file with these ranges. ''' @@ -20,7 +20,7 @@ def main() -> int: parser = argparse.ArgumentParser(description=( 'Get the range of possible instruction counts for a top-level ' - 'OTBN program for various provided modes, storing the results in an ' + 'ACC program for various provided modes, storing the results in an ' 'auto-generated header. At runtime, one can read the instruction ' 'count register and make sure the values fall within the correct ' 'range to protect against certain fault injection attacks.')) diff --git a/hw/ip/otbn/util/get_instruction_count_range.py b/hw/ip/acc/util/get_instruction_count_range.py similarity index 96% rename from hw/ip/otbn/util/get_instruction_count_range.py rename to hw/ip/acc/util/get_instruction_count_range.py index a298b2e0538..30b4877ee3c 100755 --- a/hw/ip/otbn/util/get_instruction_count_range.py +++ b/hw/ip/acc/util/get_instruction_count_range.py @@ -13,7 +13,7 @@ def main() -> int: parser = argparse.ArgumentParser(description=( - 'Get the range of possible instruction counts for an OTBN program or ' + 'Get the range of possible instruction counts for an ACC program or ' 'across all valid control-flow paths. At runtime, one can read the ' 'instruction count register and make sure the values fall within this ' 'range to protect against certain fault injection attacks.')) diff --git a/hw/ip/otbn/util/make_mulqacc.py b/hw/ip/acc/util/make_mulqacc.py similarity index 99% rename from hw/ip/otbn/util/make_mulqacc.py rename to hw/ip/acc/util/make_mulqacc.py index b27e7b11d0d..b9730a893df 100755 --- a/hw/ip/otbn/util/make_mulqacc.py +++ b/hw/ip/acc/util/make_mulqacc.py @@ -8,7 +8,7 @@ import sys from typing import List, Optional -# Size of OTBN wide data registers. +# Size of ACC wide data registers. WDR_SIZE = 256 # Size of bn.mulqacc multiplier. LIMB_SIZE = 64 diff --git a/hw/ip/otbn/util/mypy.ini b/hw/ip/acc/util/mypy.ini similarity index 100% rename from hw/ip/otbn/util/mypy.ini rename to hw/ip/acc/util/mypy.ini diff --git a/hw/ip/otbn/util/shared/BUILD b/hw/ip/acc/util/shared/BUILD similarity index 96% rename from hw/ip/otbn/util/shared/BUILD rename to hw/ip/acc/util/shared/BUILD index ebf1a162649..04408ccfd88 100644 --- a/hw/ip/otbn/util/shared/BUILD +++ b/hw/ip/acc/util/shared/BUILD @@ -149,7 +149,7 @@ py_library( name = "mem_layout", srcs = ["mem_layout.py"], deps = [ - ":otbn_reggen", + ":acc_reggen", "//util/reggen:reg_block", ], ) @@ -166,9 +166,9 @@ py_library( ) py_library( - name = "otbn_reggen", - srcs = ["otbn_reggen.py"], - data = ["//hw/ip/otbn/data:all_files"], + name = "acc_reggen", + srcs = ["acc_reggen.py"], + data = ["//hw/ip/acc/data:all_files"], deps = [ "//util/reggen:ip_block", "//util/reggen:reg_block", diff --git a/hw/ip/otbn/util/shared/__init__.py b/hw/ip/acc/util/shared/__init__.py similarity index 83% rename from hw/ip/otbn/util/shared/__init__.py rename to hw/ip/acc/util/shared/__init__.py index 7fe779e80bf..fe704197761 100644 --- a/hw/ip/otbn/util/shared/__init__.py +++ b/hw/ip/acc/util/shared/__init__.py @@ -12,7 +12,7 @@ # this in a library __init__ file can cause havoc with paths. *But* doing it # properly would either mean installing Python libraries or pasting the lines # below into every script that wanted to use the utility code. -_OTBN_DIR = os.path.normpath(os.path.join(os.path.dirname(__file__), '../..')) -_OT_DIR = os.path.normpath(os.path.join(_OTBN_DIR, '../../..')) +_ACC_DIR = os.path.normpath(os.path.join(os.path.dirname(__file__), '../..')) +_OT_DIR = os.path.normpath(os.path.join(_ACC_DIR, '../../..')) _OT_UTIL_DIR = os.path.join(_OT_DIR, 'util') sys.path.append(_OT_UTIL_DIR) diff --git a/hw/ip/otbn/util/shared/otbn_reggen.py b/hw/ip/acc/util/shared/acc_reggen.py similarity index 88% rename from hw/ip/otbn/util/shared/otbn_reggen.py rename to hw/ip/acc/util/shared/acc_reggen.py index e66b9868dc1..0cd286966f3 100644 --- a/hw/ip/otbn/util/shared/otbn_reggen.py +++ b/hw/ip/acc/util/shared/acc_reggen.py @@ -2,7 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''A wrapper around reggen for otbn.hjson''' +'''A wrapper around reggen for acc.hjson''' import os from typing import Optional, Tuple @@ -13,7 +13,7 @@ def load_registers() -> Tuple[int, object]: - '''Load otbn.hjson with reggen + '''Load acc.hjson with reggen Returns (width, regs) where width is the register width and regs is a list of Register, MultiRegister or Window objects. Memoized. @@ -24,7 +24,7 @@ def load_registers() -> Tuple[int, object]: return _LR_RETVAL path = os.path.join(os.path.dirname(__file__), - '..', '..', 'data', 'otbn.hjson') + '..', '..', 'data', 'acc.hjson') try: obj = ip_block.IpBlock.from_path(path, []) diff --git a/hw/ip/otbn/util/shared/bit_ranges.py b/hw/ip/acc/util/shared/bit_ranges.py similarity index 100% rename from hw/ip/otbn/util/shared/bit_ranges.py rename to hw/ip/acc/util/shared/bit_ranges.py diff --git a/hw/ip/otbn/util/shared/bool_literal.py b/hw/ip/acc/util/shared/bool_literal.py similarity index 100% rename from hw/ip/otbn/util/shared/bool_literal.py rename to hw/ip/acc/util/shared/bool_literal.py diff --git a/hw/ip/otbn/util/shared/cache.py b/hw/ip/acc/util/shared/cache.py similarity index 100% rename from hw/ip/otbn/util/shared/cache.py rename to hw/ip/acc/util/shared/cache.py diff --git a/hw/ip/otbn/util/shared/check.py b/hw/ip/acc/util/shared/check.py similarity index 100% rename from hw/ip/otbn/util/shared/check.py rename to hw/ip/acc/util/shared/check.py diff --git a/hw/ip/otbn/util/shared/constants.py b/hw/ip/acc/util/shared/constants.py similarity index 100% rename from hw/ip/otbn/util/shared/constants.py rename to hw/ip/acc/util/shared/constants.py diff --git a/hw/ip/otbn/util/shared/control_flow.py b/hw/ip/acc/util/shared/control_flow.py similarity index 96% rename from hw/ip/otbn/util/shared/control_flow.py rename to hw/ip/acc/util/shared/control_flow.py index 263234dd861..a2f79a21ed0 100644 --- a/hw/ip/otbn/util/shared/control_flow.py +++ b/hw/ip/acc/util/shared/control_flow.py @@ -6,7 +6,7 @@ from typing import Dict, List, Set, Tuple -from .decode import OTBNProgram +from .decode import ACCProgram from .insn_yaml import Insn from .section import CodeSection @@ -124,7 +124,7 @@ def pretty(self) -> str: class ControlGraph: - '''Represents the control flow graph of (part of) an OTBN program. + '''Represents the control flow graph of (part of) an ACC program. The `start` PC is the entrypoint of the control-flow graph. @@ -185,7 +185,7 @@ def get_cycle_starts(self) -> Set[int]: return out def _pretty_lines(self, - program: OTBNProgram, + program: ACCProgram, entry_pc: int, concise: bool, already_printed: Set[int], @@ -263,7 +263,7 @@ def _pretty_lines(self, return out def pretty(self, - program: OTBNProgram, + program: ACCProgram, indent: int = 0, concise: bool = False) -> str: '''Returns string for pretty-printing.''' @@ -301,12 +301,12 @@ def _get_next_control_locations(insn: Insn, operands: Dict[str, int], raise RuntimeError( 'Cannot create control graph because of a function ' 'call from a pointer at PC {:#x}: {}\nThis is ' - 'permitted by OTBN but not supported by this check.'.format( + 'permitted by ACC but not supported by this check.'.format( pc, insn.disassemble(pc, operands))) if operands['offset'] != 0: raise RuntimeError( 'Cannot create control graph because of a nonzero offset for ' - 'JALR at PC {:#x}: {}.\nThis is permitted by OTBN but not ' + 'JALR at PC {:#x}: {}.\nThis is permitted by ACC but not ' 'supported by this check.'.format( pc, insn.disassemble(pc, operands))) # This jump returns to whatever's on top of the call stack @@ -326,7 +326,7 @@ def _get_next_control_locations(insn: Insn, operands: Dict[str, int], pc, insn.disassemble(pc, operands))) -def _populate_control_graph(graph: ControlGraph, program: OTBNProgram, +def _populate_control_graph(graph: ControlGraph, program: ACCProgram, start_pc: int, loop_stack: List[LoopStart]) -> None: '''Populates input control flow graph starting from start_pc. @@ -417,7 +417,7 @@ def _populate_control_graph(graph: ControlGraph, program: OTBNProgram, return -def _label_cycles(program: OTBNProgram, graph: ControlGraph, start_pc: int, +def _label_cycles(program: ACCProgram, graph: ControlGraph, start_pc: int, visited_pcs: Set[int]) -> None: '''Creates Cycle edges to remove cyclic control flow from the graph. @@ -452,7 +452,7 @@ def _label_cycles(program: OTBNProgram, graph: ControlGraph, start_pc: int, _label_cycles(program, graph, edge.pc, visited_pcs.copy()) -def _fix_cycles(program: OTBNProgram, graph: ControlGraph) -> None: +def _fix_cycles(program: ACCProgram, graph: ControlGraph) -> None: '''Labels cycles and splits them from other CodeSections in the graph. Modifies graph in place. @@ -472,7 +472,7 @@ def _fix_cycles(program: OTBNProgram, graph: ControlGraph) -> None: graph.graph.update(new_entries) -def _make_control_graph(program: OTBNProgram, start_pc: int) -> ControlGraph: +def _make_control_graph(program: ACCProgram, start_pc: int) -> ControlGraph: '''Constructs a control flow graph with start_pc as the entrypoint. Assumes the loop stack is empty at start_pc. @@ -483,12 +483,12 @@ def _make_control_graph(program: OTBNProgram, start_pc: int) -> ControlGraph: return graph -def program_control_graph(program: OTBNProgram) -> ControlGraph: +def program_control_graph(program: ACCProgram) -> ControlGraph: '''Constructs a control flow graph representing an entire program.''' return _make_control_graph(program, program.min_pc()) -def subroutine_control_graph(program: OTBNProgram, +def subroutine_control_graph(program: ACCProgram, subroutine: str) -> ControlGraph: '''Control flow graph from the given symbol to the first unmatched `ret`. diff --git a/hw/ip/otbn/util/shared/decode.py b/hw/ip/acc/util/shared/decode.py similarity index 90% rename from hw/ip/otbn/util/shared/decode.py rename to hw/ip/acc/util/shared/decode.py index 999fbdda443..556f4da1946 100644 --- a/hw/ip/otbn/util/shared/decode.py +++ b/hw/ip/acc/util/shared/decode.py @@ -18,7 +18,7 @@ sys.exit(1) -class OTBNProgram: +class ACCProgram: def __init__(self, symbols: Dict[str, int], insns: Dict[int, int], data: Dict[int, int]): self.symbols = symbols # label -> PC @@ -69,14 +69,14 @@ def _decode_mem(base_addr: int, data: bytes) -> Dict[int, int]: for offset, int_val in enumerate(struct.iter_unpack(' OTBNProgram: - '''Read ELF file at path and decode contents into an OTBNProgram instance +def decode_elf(path: str) -> ACCProgram: + '''Read ELF file at path and decode contents into an ACCProgram instance - Returns the OTBNProgram instance representing the program in the ELF file. + Returns the ACCProgram instance representing the program in the ELF file. ''' (imem_bytes, dmem_bytes, symbols) = read_elf(path) insns = _decode_mem(0, imem_bytes) data = _decode_mem(0, dmem_bytes) - return OTBNProgram(symbols, insns, data) + return ACCProgram(symbols, insns, data) diff --git a/hw/ip/otbn/util/shared/dmem_dump.py b/hw/ip/acc/util/shared/dmem_dump.py similarity index 100% rename from hw/ip/otbn/util/shared/dmem_dump.py rename to hw/ip/acc/util/shared/dmem_dump.py diff --git a/hw/ip/otbn/util/shared/elf.py b/hw/ip/acc/util/shared/elf.py similarity index 99% rename from hw/ip/otbn/util/shared/elf.py rename to hw/ip/acc/util/shared/elf.py index 47cff3a6fa6..8282018b6a7 100644 --- a/hw/ip/otbn/util/shared/elf.py +++ b/hw/ip/acc/util/shared/elf.py @@ -2,7 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''OTBN ELF file handling''' +'''ACC ELF file handling''' from typing import List, Optional, Tuple, Dict diff --git a/hw/ip/otbn/util/shared/encoding.py b/hw/ip/acc/util/shared/encoding.py similarity index 99% rename from hw/ip/otbn/util/shared/encoding.py rename to hw/ip/acc/util/shared/encoding.py index 2bd07144bf3..b032925d2bc 100644 --- a/hw/ip/otbn/util/shared/encoding.py +++ b/hw/ip/acc/util/shared/encoding.py @@ -170,7 +170,7 @@ def assemble(self, op_to_idx: Dict[str, int]) -> int: assert field_val >= 0 # Is the number too big? At the moment, we are assuming immediates - # are unsigned (because the OTBN big number instructions all have + # are unsigned (because the ACC big number instructions all have # unsigned immediates). if field_val >> field.scheme_field.bits.width: raise ValueError("operand field {} has a width of {}, " diff --git a/hw/ip/otbn/util/shared/encoding_scheme.py b/hw/ip/acc/util/shared/encoding_scheme.py similarity index 100% rename from hw/ip/otbn/util/shared/encoding_scheme.py rename to hw/ip/acc/util/shared/encoding_scheme.py diff --git a/hw/ip/otbn/util/shared/information_flow.py b/hw/ip/acc/util/shared/information_flow.py similarity index 99% rename from hw/ip/otbn/util/shared/information_flow.py rename to hw/ip/acc/util/shared/information_flow.py index 2c598b25f4f..1b1ba7d5412 100644 --- a/hw/ip/otbn/util/shared/information_flow.py +++ b/hw/ip/acc/util/shared/information_flow.py @@ -1,7 +1,7 @@ # Copyright lowRISC contributors (OpenTitan project). # Copyright zeroRISC Inc. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028). # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. # Licensed under the Apache License, Version 2.0, see LICENSE for details. diff --git a/hw/ip/otbn/util/shared/information_flow_analysis.py b/hw/ip/acc/util/shared/information_flow_analysis.py similarity index 98% rename from hw/ip/otbn/util/shared/information_flow_analysis.py rename to hw/ip/acc/util/shared/information_flow_analysis.py index bfcb076a695..43e975ba4e1 100755 --- a/hw/ip/otbn/util/shared/information_flow_analysis.py +++ b/hw/ip/acc/util/shared/information_flow_analysis.py @@ -11,7 +11,7 @@ from .constants import ConstantContext, get_op_val_str from .control_flow import (ControlLoc, ControlGraph, Cycle, Ecall, ImemEnd, LoopStart, Ret) -from .decode import OTBNProgram +from .decode import ACCProgram from .information_flow import InformationFlowGraph from .insn_yaml import Insn @@ -143,7 +143,7 @@ def _get_insn_control_deps(insn: Insn, op_vals: Dict[str, int]) -> Set[str]: def _build_iflow_straightline( - program: OTBNProgram, start_pc: int, end_pc: int, + program: ACCProgram, start_pc: int, end_pc: int, constants: ConstantContext) -> Tuple[Set[str], InformationFlowGraph]: '''Constructs the information-flow graph for a straightline code section. @@ -286,7 +286,7 @@ def _get_iflow_update_state( return iflow.seq(rec_return_iflow) -def _get_iflow(program: OTBNProgram, graph: ControlGraph, start_pc: int, +def _get_iflow(program: ACCProgram, graph: ControlGraph, start_pc: int, start_constants: ConstantContext, loop_end_pc: Optional[int], cache: IFlowCache) -> IFlowResult: '''Gets the information-flow graphs for paths starting at start_pc. @@ -549,7 +549,7 @@ def _get_iflow(program: OTBNProgram, graph: ControlGraph, start_pc: int, return out -def get_subroutine_iflow(program: OTBNProgram, graph: ControlGraph, +def get_subroutine_iflow(program: ACCProgram, graph: ControlGraph, subroutine_name: str, start_constants: Dict[str, int]) -> SubroutineIFlow: '''Gets the information-flow graphs for the subroutine. @@ -583,7 +583,7 @@ def get_subroutine_iflow(program: OTBNProgram, graph: ControlGraph, return ret_iflow, end_iflow, control_deps -def get_program_iflow(program: OTBNProgram, +def get_program_iflow(program: ACCProgram, graph: ControlGraph) -> ProgramIFlow: '''Gets the information-flow graph for the whole program. @@ -608,7 +608,7 @@ def get_program_iflow(program: OTBNProgram, def get_subroutine_loop_iters( - program: OTBNProgram, graph: ControlGraph, subroutine_name: str, + program: ACCProgram, graph: ControlGraph, subroutine_name: str, start_constants: Dict[str, int]) -> Dict[int, int]: '''Gets the loop iteration counts for the subroutine. @@ -638,7 +638,7 @@ def get_subroutine_loop_iters( return loop_iters -def stringify_control_deps(program: OTBNProgram, +def stringify_control_deps(program: ACCProgram, control_deps: Dict[str, Set[int]]) -> List[str]: '''Compute string representations of nodes that influence control flow. diff --git a/hw/ip/otbn/util/shared/insn_yaml.py b/hw/ip/acc/util/shared/insn_yaml.py similarity index 99% rename from hw/ip/otbn/util/shared/insn_yaml.py rename to hw/ip/acc/util/shared/insn_yaml.py index c49e0123ce6..ed7ecb9603b 100644 --- a/hw/ip/otbn/util/shared/insn_yaml.py +++ b/hw/ip/acc/util/shared/insn_yaml.py @@ -310,7 +310,7 @@ def __init__(self, isrs) # The instructions are grouped by instruction group and stored in - # self.groups. Most of the time, however, we just want "an OTBN + # self.groups. Most of the time, however, we just want "an ACC # instruction" and don't care about the group. Retrieve them here. self.insns = [] for grp in self.groups.groups: diff --git a/hw/ip/otbn/util/shared/instruction_count_range.py b/hw/ip/acc/util/shared/instruction_count_range.py similarity index 98% rename from hw/ip/otbn/util/shared/instruction_count_range.py rename to hw/ip/acc/util/shared/instruction_count_range.py index 02323895317..0a0e107e645 100755 --- a/hw/ip/otbn/util/shared/instruction_count_range.py +++ b/hw/ip/acc/util/shared/instruction_count_range.py @@ -11,7 +11,7 @@ from .control_flow import (ControlGraph, Cycle, Ecall, ImemEnd, LoopEnd, LoopStart, Ret, program_control_graph, subroutine_control_graph) -from .decode import OTBNProgram +from .decode import ACCProgram from .information_flow_analysis import get_subroutine_loop_iters @@ -22,7 +22,7 @@ class StopPoint(Enum): def _get_insn_count_range( - program: OTBNProgram, graph: ControlGraph, start_pc: int, + program: ACCProgram, graph: ControlGraph, start_pc: int, stop_at: StopPoint, loop_iters: Optional[Dict[int, int]], thru_label: Optional[str], exclude_labels: list[str]) -> Optional[Tuple[int, int]]: @@ -187,7 +187,7 @@ def _get_insn_count_range( return (min(min_counts), max(max_counts)) -def program_insn_count_range(program: OTBNProgram, +def program_insn_count_range(program: ACCProgram, thru_label: Optional[str], exclude_labels) -> Tuple[int, Optional[int]]: '''Return minimum and maximum instruction counts for the program. @@ -214,7 +214,7 @@ def program_insn_count_range(program: OTBNProgram, return min_count, max_count -def subroutine_insn_count_range(program: OTBNProgram, +def subroutine_insn_count_range(program: ACCProgram, subroutine: str) -> Tuple[int, Optional[int]]: '''Return minimum and maximum instruction counts for the subroutine. diff --git a/hw/ip/otbn/util/shared/isr.py b/hw/ip/acc/util/shared/isr.py similarity index 100% rename from hw/ip/otbn/util/shared/isr.py rename to hw/ip/acc/util/shared/isr.py diff --git a/hw/ip/otbn/util/shared/lsu_desc.py b/hw/ip/acc/util/shared/lsu_desc.py similarity index 100% rename from hw/ip/otbn/util/shared/lsu_desc.py rename to hw/ip/acc/util/shared/lsu_desc.py diff --git a/hw/ip/otbn/util/shared/mem_layout.py b/hw/ip/acc/util/shared/mem_layout.py similarity index 74% rename from hw/ip/otbn/util/shared/mem_layout.py rename to hw/ip/acc/util/shared/mem_layout.py index 0fe47b79f77..3c410d29b35 100644 --- a/hw/ip/otbn/util/shared/mem_layout.py +++ b/hw/ip/acc/util/shared/mem_layout.py @@ -2,18 +2,18 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -'''Simple code that understands enough of otbn.hjson to get a memory layout +'''Simple code that understands enough of acc.hjson to get a memory layout Each memory will have an associated "window" entry, which has an offset from the start of the IP block's register space. This offset will be treated as an LMA for this memory and these memory LMAs will be used uniformly in -OTBN-specific tooling. This avoids the result depending on the address layout +ACC-specific tooling. This avoids the result depending on the address layout of the wider chip. -In particular, note that OTBN ELF binaries will use these LMAs (the VMAs are in -OTBN's address space, with both IMEM and DMEM starting at 0). A tool that takes +In particular, note that ACC ELF binaries will use these LMAs (the VMAs are in +ACC's address space, with both IMEM and DMEM starting at 0). A tool that takes such binaries and incorporates them into a top-level image will need to do -address translation (essentially, just adding the base address of the OTBN IP +address translation (essentially, just adding the base address of the ACC IP block). ''' @@ -22,13 +22,13 @@ from reggen.reg_block import RegBlock -from .otbn_reggen import load_registers +from .acc_reggen import load_registers # A window is represented as (offset, size) _Window = Tuple[int, int] # This needs to be kept in sync with the parameter of the same name in -# otbn_pkg.sv +# acc_pkg.sv _DmemScratchSizeBytes = 1024 @@ -49,15 +49,15 @@ def extract_windows(reg_byte_width: int, regs: object) -> Dict[str, _Window]: return windows -class OtbnMemoryLayout: +class AccMemoryLayout: def __init__(self, windows: Dict[str, _Window]): imem_window = windows.get('IMEM') if imem_window is None: - raise RuntimeError('otbn.hjson has no IMEM window') + raise RuntimeError('acc.hjson has no IMEM window') dmem_window = windows.get('DMEM') if dmem_window is None: - raise RuntimeError('otbn.hjson has no DMEM window') + raise RuntimeError('acc.hjson has no DMEM window') self.imem_address = imem_window[0] self.imem_size_bytes = imem_window[1] @@ -67,11 +67,11 @@ def __init__(self, windows: Dict[str, _Window]): self.dmem_size_bytes = dmem_window[1] + _DmemScratchSizeBytes -_LAYOUT: Optional[OtbnMemoryLayout] = None +_LAYOUT: Optional[AccMemoryLayout] = None -def get_memory_layout() -> OtbnMemoryLayout: - '''Read otbn.hjson to get IMEM / DMEM layout +def get_memory_layout() -> AccMemoryLayout: + '''Read acc.hjson to get IMEM / DMEM layout Returns a dictionary with two entries, keyed 'IMEM' and 'DMEM'. The value at each entry is a pair (offset, size_in_bytes). @@ -84,5 +84,5 @@ def get_memory_layout() -> OtbnMemoryLayout: reg_byte_width, registers = load_registers() windows = extract_windows(reg_byte_width, registers) - _LAYOUT = OtbnMemoryLayout(windows) + _LAYOUT = AccMemoryLayout(windows) return _LAYOUT diff --git a/hw/ip/otbn/util/shared/operand.py b/hw/ip/acc/util/shared/operand.py similarity index 99% rename from hw/ip/otbn/util/shared/operand.py rename to hw/ip/acc/util/shared/operand.py index c2cc4ec9de2..2c03f92553e 100644 --- a/hw/ip/otbn/util/shared/operand.py +++ b/hw/ip/acc/util/shared/operand.py @@ -23,8 +23,8 @@ class OperandType: - Encoded value The string representation is the string that you expect to see in an - assembly listing (either fed into otbn_as.py, or generated by - otbn_objdump.py). The encoded value is the non-negative integer value that + assembly listing (either fed into acc_as.py, or generated by + acc_objdump.py). The encoded value is the non-negative integer value that is encoded in the bits of the instruction. The operand value is the notional value of the operand. This might be a @@ -104,7 +104,7 @@ def op_val_to_enc_val(self, op_val: int, '''Convert the operand value to an encoded value This expects a current PC in cur_pc. If we don't know that (because - this is otbn_as.py, and we don't know our eventual current address), a + this is acc_as.py, and we don't know our eventual current address), a pc_rel immediate will return None. Similarly, if we don't know our width, we should return None. diff --git a/hw/ip/otbn/util/shared/reg_dump.py b/hw/ip/acc/util/shared/reg_dump.py similarity index 100% rename from hw/ip/otbn/util/shared/reg_dump.py rename to hw/ip/acc/util/shared/reg_dump.py diff --git a/hw/ip/otbn/util/shared/section.py b/hw/ip/acc/util/shared/section.py similarity index 89% rename from hw/ip/otbn/util/shared/section.py rename to hw/ip/acc/util/shared/section.py index ea1cfa95b77..c70d871d479 100644 --- a/hw/ip/otbn/util/shared/section.py +++ b/hw/ip/acc/util/shared/section.py @@ -5,7 +5,7 @@ from typing import Iterator, List -from shared.decode import OTBNProgram +from shared.decode import ACCProgram from shared.insn_yaml import Insn @@ -18,7 +18,7 @@ def __init__(self, start: int, end: int): self.start = start self.end = end - def get_insn_sequence(self, program: OTBNProgram) -> List[Insn]: + def get_insn_sequence(self, program: ACCProgram) -> List[Insn]: return [program.get_insn(pc) for pc in self.__iter__()] def pretty(self) -> str: diff --git a/hw/ip/otbn/util/shared/syntax.py b/hw/ip/acc/util/shared/syntax.py similarity index 100% rename from hw/ip/otbn/util/shared/syntax.py rename to hw/ip/acc/util/shared/syntax.py diff --git a/hw/ip/otbn/util/shared/testcase.py b/hw/ip/acc/util/shared/testcase.py similarity index 95% rename from hw/ip/otbn/util/shared/testcase.py rename to hw/ip/acc/util/shared/testcase.py index 3122fcd381e..e7172a2e6ba 100644 --- a/hw/ip/otbn/util/shared/testcase.py +++ b/hw/ip/acc/util/shared/testcase.py @@ -73,16 +73,16 @@ def _from_dict(data: Dict[str, object], @dataclass -class OtbnTestCase: +class AccTestCase: entrypoint: int input: StateExpectations output: StateExpectations @staticmethod def from_hjson(hjson_str: str, - symbols: Dict[str, int]) -> 'OtbnTestCase': + symbols: Dict[str, int]) -> 'AccTestCase': """ - Parse a testcase HJSON string into a OtbnTestCase object. + Parse a testcase HJSON string into a AccTestCase object. The HJSON schema is defined as follows: ``` @@ -124,7 +124,7 @@ def from_hjson(hjson_str: str, all symbols from the program being tested. Returns: - A OtbnTestCase object representing the parsed testcase. + A AccTestCase object representing the parsed testcase. """ data: Dict[str, object] = hjson.loads(hjson_str) @@ -143,7 +143,7 @@ def from_hjson(hjson_str: str, else: raise ValueError(f'Entrypoint must be int or str, got {type(entrypoint)}') - return OtbnTestCase( + return AccTestCase( entrypoint=entrypoint_addr, input=StateExpectations._from_dict(_get_str_keyed_dict(data, 'input'), symbols), output=StateExpectations._from_dict(_get_str_keyed_dict(data, 'output'), symbols), diff --git a/hw/ip/otbn/util/shared/testgen.py b/hw/ip/acc/util/shared/testgen.py similarity index 97% rename from hw/ip/otbn/util/shared/testgen.py rename to hw/ip/acc/util/shared/testgen.py index 08b611811ac..bf8a1a4b92e 100644 --- a/hw/ip/otbn/util/shared/testgen.py +++ b/hw/ip/acc/util/shared/testgen.py @@ -49,7 +49,7 @@ def write_test_dexp(dexp: Dict[str, bytes], dexp_file: TextIO) -> None: '''Write the expected memory values file for the test.''' for name in dexp: value = dexp[name] - # TODO: change this behavior in otbn_sim_test so raw bytes work + # TODO: change this behavior in acc_sim_test so raw bytes work # dexp_file.write(f'{name}: {value.hex()}\n') # reverse the byte order of each word hexstr = '' diff --git a/hw/ip/otbn/util/shared/toolchain.py b/hw/ip/acc/util/shared/toolchain.py similarity index 100% rename from hw/ip/otbn/util/shared/toolchain.py rename to hw/ip/acc/util/shared/toolchain.py diff --git a/hw/ip/otbn/util/yaml_to_doc.py b/hw/ip/acc/util/yaml_to_doc.py similarity index 100% rename from hw/ip/otbn/util/yaml_to_doc.py rename to hw/ip/acc/util/yaml_to_doc.py diff --git a/hw/ip/edn/doc/edn_top_diag.svg b/hw/ip/edn/doc/edn_top_diag.svg index eb63517b7d5..277fcb2a5f4 100644 --- a/hw/ip/edn/doc/edn_top_diag.svg +++ b/hw/ip/edn/doc/edn_top_diag.svg @@ -723,7 +723,7 @@ Sheet.127 otbn + id="desc209">acc aes_key_exp.valid == aes_key.valid) - `ASSERT_IFF_KEYMGR_LEGAL(CheckOtbnKey, otbn_sideload_status == SideLoadAvail && otbn_key_exp.valid - -> otbn_key == otbn_key_exp) - `ASSERT_IFF_KEYMGR_LEGAL(CheckOtbnKeyValid, otbn_sideload_status != SideLoadClear -> - otbn_key_exp.valid == otbn_key.valid) + `ASSERT_IFF_KEYMGR_LEGAL(CheckAccKey, acc_sideload_status == SideLoadAvail && acc_key_exp.valid + -> acc_key == acc_key_exp) + `ASSERT_IFF_KEYMGR_LEGAL(CheckAccKeyValid, acc_sideload_status != SideLoadClear -> + acc_key_exp.valid == acc_key.valid) // for EDN assertion // sync req/ack to core clk domain diff --git a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv index cdacb632f0a..0373fc610d4 100644 --- a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv +++ b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv @@ -426,7 +426,7 @@ class keymgr_scoreboard extends cip_base_scoreboard #( get_operation(), cfg.keymgr_vif.aes_sideload_status == SideLoadAvail, cfg.keymgr_vif.kmac_sideload_status == SideLoadAvail, - cfg.keymgr_vif.otbn_sideload_status == SideLoadAvail, + cfg.keymgr_vif.acc_sideload_status == SideLoadAvail, cfg_regwen); end else if (csr.get_name() != "control_shadowed") begin cov.sw_input_cg_wrap[csr.get_name()].sample(item.a_data, cfg_regwen); @@ -1182,7 +1182,7 @@ class keymgr_scoreboard extends cip_base_scoreboard #( case (dest) keymgr_pkg::Kmac: exp.KeyID = keymgr_pkg::RndCnstKmacSeedDefault; keymgr_pkg::Aes: exp.KeyID = keymgr_pkg::RndCnstAesSeedDefault; - keymgr_pkg::Otbn: exp.KeyID = keymgr_pkg::RndCnstOtbnSeedDefault; + keymgr_pkg::Acc: exp.KeyID = keymgr_pkg::RndCnstAccSeedDefault; keymgr_pkg::None: exp.KeyID = keymgr_pkg::RndCnstNoneSeedDefault; default: `uvm_fatal(`gfn, $sformatf("Unexpected dest_sel: %0s", dest.name)) endcase diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_sideload_protect_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_sideload_protect_vseq.sv index c2a6eddf4af..bbb5bc9d134 100644 --- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_sideload_protect_vseq.sv +++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_sideload_protect_vseq.sv @@ -42,9 +42,9 @@ class keymgr_sideload_protect_vseq extends keymgr_random_vseq; case (key_dest) keymgr_pkg::Aes: hw_key = cfg.keymgr_vif.aes_key.key; keymgr_pkg::Kmac: hw_key = cfg.keymgr_vif.kmac_key.key; - keymgr_pkg::Otbn: begin - // truncate otbn key from 386 to 256 bits - foreach (hw_key.key[i]) hw_key.key[i] = cfg.keymgr_vif.otbn_key.key[i]; + keymgr_pkg::Acc: begin + // truncate acc key from 386 to 256 bits + foreach (hw_key.key[i]) hw_key.key[i] = cfg.keymgr_vif.acc_key.key[i]; end default: `uvm_fatal(`gfn, "invalid value") endcase diff --git a/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson b/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson index d1dc0e040c9..8dccc88e4fb 100644 --- a/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson +++ b/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson @@ -86,9 +86,9 @@ } { - name: keymgr_sideload_otbn + name: keymgr_sideload_acc uvm_test_seq: keymgr_sideload_one_intf_vseq - run_opts: ["+sideload_dest=Otbn"] + run_opts: ["+sideload_dest=Acc"] } { diff --git a/hw/ip/keymgr/dv/tb.sv b/hw/ip/keymgr/dv/tb.sv index 69528e41635..33a20c9923d 100644 --- a/hw/ip/keymgr/dv/tb.sv +++ b/hw/ip/keymgr/dv/tb.sv @@ -51,7 +51,7 @@ module tb; .clk_edn_i (edn_clk ), .rst_edn_ni (edn_rst_n ), .aes_key_o (keymgr_if.aes_key), - .otbn_key_o (keymgr_if.otbn_key), + .acc_key_o (keymgr_if.acc_key), .kmac_key_o (keymgr_if.kmac_key), .kmac_data_o (keymgr_kmac_intf.kmac_data_req), .kmac_data_i (keymgr_kmac_intf.kmac_data_rsp), diff --git a/hw/ip/keymgr/rtl/keymgr.sv b/hw/ip/keymgr/rtl/keymgr.sv index d458e5eb471..f1a4caf848b 100644 --- a/hw/ip/keymgr/rtl/keymgr.sv +++ b/hw/ip/keymgr/rtl/keymgr.sv @@ -29,7 +29,7 @@ module keymgr parameter seed_t RndCnstHardOutputSeed = RndCnstHardOutputSeedDefault, parameter seed_t RndCnstNoneSeed = RndCnstNoneSeedDefault, parameter seed_t RndCnstAesSeed = RndCnstAesSeedDefault, - parameter seed_t RndCnstOtbnSeed = RndCnstOtbnSeedDefault, + parameter seed_t RndCnstAccSeed = RndCnstAccSeedDefault, parameter seed_t RndCnstKmacSeed = RndCnstKmacSeedDefault, parameter seed_t RndCnstCdi = RndCnstCdiDefault ) ( @@ -46,7 +46,7 @@ module keymgr // key interface to crypto modules output hw_key_req_t aes_key_o, output hw_key_req_t kmac_key_o, - output otbn_key_req_t otbn_key_o, + output acc_key_req_t acc_key_o, // data interface to/from crypto modules output kmac_pkg::app_req_t kmac_data_o, @@ -103,7 +103,7 @@ module keymgr seed_t soft_output_seed; seed_t hard_output_seed; seed_t aes_seed; - seed_t otbn_seed; + seed_t acc_seed; seed_t kmac_seed; seed_t none_seed; @@ -117,7 +117,7 @@ module keymgr RndCnstSoftOutputSeed, RndCnstHardOutputSeed, RndCnstAesSeed, - RndCnstOtbnSeed, + RndCnstAccSeed, RndCnstKmacSeed, RndCnstNoneSeed}), .out_o({revision_seed, @@ -127,7 +127,7 @@ module keymgr soft_output_seed, hard_output_seed, aes_seed, - otbn_seed, + acc_seed, kmac_seed, none_seed}) ); @@ -486,7 +486,7 @@ module keymgr assign dest_sel = keymgr_key_dest_e'(reg2hw.control_shadowed.dest_sel.q); assign dest_seed = dest_sel == Aes ? aes_seed : dest_sel == Kmac ? kmac_seed : - dest_sel == Otbn ? otbn_seed : none_seed; + dest_sel == Acc ? acc_seed : none_seed; assign output_key = mubi4_test_true_strict(hw_key_sel) ? hard_output_seed : soft_output_seed; assign gen_in = invalid_stage_sel ? {GenLfsrCopies{lfsr[31:0]}} : {reg2hw.key_version, @@ -605,7 +605,7 @@ module keymgr .data_i(kmac_data), .prng_en_o(sideload_lfsr_en), .aes_key_o, - .otbn_key_o, + .acc_key_o, .kmac_key_o, .sideload_sel_err_o(sideload_sel_err), .fsm_err_o(sideload_fsm_err) @@ -778,7 +778,7 @@ module keymgr `ASSERT_KNOWN(AesKeyKnownO_A, aes_key_o) `ASSERT_KNOWN(KmacKeyKnownO_A, kmac_key_o) - `ASSERT_KNOWN(OtbnKeyKnownO_A, otbn_key_o) + `ASSERT_KNOWN(AccKeyKnownO_A, acc_key_o) `ASSERT_KNOWN(KmacDataKnownO_A, kmac_data_o) diff --git a/hw/ip/keymgr/rtl/keymgr_kmac_if.sv b/hw/ip/keymgr/rtl/keymgr_kmac_if.sv index e690e521101..d973343b4ce 100644 --- a/hw/ip/keymgr/rtl/keymgr_kmac_if.sv +++ b/hw/ip/keymgr/rtl/keymgr_kmac_if.sv @@ -344,7 +344,7 @@ module keymgr_kmac_if assign kmac_data_o.valid = valid; assign kmac_data_o.last = last; assign kmac_data_o.strb = strb; - assign kmac_data_o.next = 1'b0; // Tied to 1'b0 outside of OTBN mode + assign kmac_data_o.next = 1'b0; // Tied to 1'b0 outside of ACC mode assign kmac_data_o.hold = 1'b0; // Not used in KeyMgr mode // kmac done is asserted outside of expected window diff --git a/hw/ip/keymgr/rtl/keymgr_pkg.sv b/hw/ip/keymgr/rtl/keymgr_pkg.sv index f56522fc43e..d2ad53549f8 100644 --- a/hw/ip/keymgr/rtl/keymgr_pkg.sv +++ b/hw/ip/keymgr/rtl/keymgr_pkg.sv @@ -10,7 +10,7 @@ package keymgr_pkg; parameter int KeyWidth = 256; parameter int CDIs = 2; // 2 different CDIs, sealing / attestation parameter int CdiWidth = prim_util_pkg::vbits(CDIs); - parameter int OtbnKeyWidth = 384; + parameter int AccKeyWidth = 384; parameter int DigestWidth = 128; // uses truncated hash parameter int KmacDataIfWidth = 64; // KMAC interface data width parameter int KeyMgrStages = 3; // Number of key manager stages (creator, ownerInt, owner) @@ -51,7 +51,7 @@ package keymgr_pkg; 256'he16a8fa9_5b613cd5_fb9ad23f_bd8347e1_64e45dac_5d08a41b_e83caa37_e03d9482; parameter seed_t RndCnstKmacSeedDefault = 256'hc57f4c0b_b308e83f_3fc4bc63_d87dd67d_9071dc1c_e19484c8_3c94fb97_dd634369; - parameter seed_t RndCnstOtbnSeedDefault = + parameter seed_t RndCnstAccSeedDefault = 256'hcbcb4d2d_0abeb81b_ca7451ae_d1e2479d_ba13530a_d046b945_646aa127_bd4f6a38; parameter seed_t RndCnstCdiDefault = 256'h54180905_d14c1d2f_2dda1522_f332bc0e_fcd6b92f_f0f9db75_3a9a9544_26a42eab; @@ -101,14 +101,14 @@ package keymgr_pkg; None, Aes, Kmac, - Otbn + Acc } keymgr_key_dest_e; // Enumeration for actual key slot idx typedef enum logic [1:0] { AesIdx, KmacIdx, - OtbnIdx, + AccIdx, LastIdx } keymgr_sideload_slot_idx_e; @@ -226,7 +226,7 @@ package keymgr_pkg; SideLoadClrIdle, SideLoadClrAes, SideLoadClrKmac, - SideLoadClrOtbn + SideLoadClrAcc } keymgr_sideload_clr_e; // Key connection to various symmetric modules @@ -235,20 +235,20 @@ package keymgr_pkg; logic [Shares-1:0][KeyWidth-1:0] key; } hw_key_req_t; - // Key connection to otbn + // Key connection to acc typedef struct packed { logic valid; - logic [Shares-1:0][OtbnKeyWidth-1:0] key; - } otbn_key_req_t; + logic [Shares-1:0][AccKeyWidth-1:0] key; + } acc_key_req_t; parameter hw_key_req_t HW_KEY_REQ_DEFAULT = '{ valid: 1'b0, key: {Shares{KeyWidth'(32'hDEADBEEF)}} }; - parameter otbn_key_req_t OTBN_KEY_REQ_DEFAULT = '{ + parameter acc_key_req_t ACC_KEY_REQ_DEFAULT = '{ valid: 1'b0, - key: {Shares{OtbnKeyWidth'(32'hDEADBEEF)}} + key: {Shares{AccKeyWidth'(32'hDEADBEEF)}} }; // The following structs should be sourced from other modules diff --git a/hw/ip/keymgr/rtl/keymgr_sideload_key_ctrl.sv b/hw/ip/keymgr/rtl/keymgr_sideload_key_ctrl.sv index d8944b718bf..8a6da49cca1 100644 --- a/hw/ip/keymgr/rtl/keymgr_sideload_key_ctrl.sv +++ b/hw/ip/keymgr/rtl/keymgr_sideload_key_ctrl.sv @@ -22,7 +22,7 @@ module keymgr_sideload_key_ctrl import keymgr_pkg::*;( output logic prng_en_o, output hw_key_req_t aes_key_o, output hw_key_req_t kmac_key_o, - output otbn_key_req_t otbn_key_o, + output acc_key_req_t acc_key_o, output logic sideload_sel_err_o, output logic fsm_err_o ); @@ -79,11 +79,11 @@ module keymgr_sideload_key_ctrl import keymgr_pkg::*;( !(clr_key_i inside {SideLoadClrIdle, SideLoadClrAes, SideLoadClrKmac, - SideLoadClrOtbn}); + SideLoadClrAcc}); assign slot_clr[AesIdx] = clr_all_keys | (clr_key_i == SideLoadClrAes); assign slot_clr[KmacIdx] = clr_all_keys | (clr_key_i == SideLoadClrKmac); - assign slot_clr[OtbnIdx] = clr_all_keys | (clr_key_i == SideLoadClrOtbn); + assign slot_clr[AccIdx] = clr_all_keys | (clr_key_i == SideLoadClrAcc); logic clr; assign clr = |slot_clr; @@ -143,7 +143,7 @@ module keymgr_sideload_key_ctrl import keymgr_pkg::*;( logic [LastIdx-1:0] slot_sel; assign slot_sel[AesIdx] = (dest_sel_i == Aes) & mubi4_test_true_strict(hw_key_sel[AesIdx]); assign slot_sel[KmacIdx] = (dest_sel_i == Kmac) & mubi4_test_true_strict(hw_key_sel[KmacIdx]); - assign slot_sel[OtbnIdx] = (dest_sel_i == Otbn) & mubi4_test_true_strict(hw_key_sel[OtbnIdx]); + assign slot_sel[AccIdx] = (dest_sel_i == Acc) & mubi4_test_true_strict(hw_key_sel[AccIdx]); keymgr_sideload_key u_aes_key ( .clk_i, @@ -159,18 +159,18 @@ module keymgr_sideload_key_ctrl import keymgr_pkg::*;( ); keymgr_sideload_key #( - .Width(OtbnKeyWidth) - ) u_otbn_key ( + .Width(AccKeyWidth) + ) u_acc_key ( .clk_i, .rst_ni, .en_i(keys_en), .set_en_i(data_en_i), - .set_i(data_valid_i & slot_sel[OtbnIdx]), - .clr_i(slot_clr[OtbnIdx]), + .set_i(data_valid_i & slot_sel[AccIdx]), + .clr_i(slot_clr[AccIdx]), .entropy_i(entropy_i), .key_i(data_i), - .valid_o(otbn_key_o.valid), - .key_o(otbn_key_o.key) + .valid_o(acc_key_o.valid), + .key_o(acc_key_o.key) ); hw_key_req_t kmac_sideload_key; @@ -204,7 +204,7 @@ module keymgr_sideload_key_ctrl import keymgr_pkg::*;( logic [LastIdx-1:0] valids; assign valids[AesIdx] = aes_key_o.valid; assign valids[KmacIdx] = kmac_sideload_key.valid; - assign valids[OtbnIdx] = otbn_key_o.valid; + assign valids[AccIdx] = acc_key_o.valid; // If valid tracking claims a valid should be 0 but 1 is observed, it is // an error. diff --git a/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson b/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson index 15302819022..5aead6ad143 100644 --- a/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson +++ b/hw/ip/keymgr_dpe/data/keymgr_dpe.hjson @@ -65,9 +65,9 @@ act: "req", package: "keymgr_pkg", // Origin package (only needs for the requester) }, - { struct: "otbn_key_req", + { struct: "acc_key_req", type: "uni", - name: "otbn_key", + name: "acc_key", act: "req", package: "keymgr_pkg", }, @@ -179,8 +179,8 @@ randtype: "data", }, - { name: "RndCnstOtbnSeed", - desc: "Compile-time random bits for generation seed when otbn destination selected", + { name: "RndCnstAccSeed", + desc: "Compile-time random bits for generation seed when acc destination selected", type: "keymgr_pkg::seed_t" randcount: "256", randtype: "data", @@ -503,12 +503,12 @@ countermeasures: [ ''' }, { value: "3", - name: "OTBN", + name: "ACC", desc: ''' - OTBN selected. Note for OTBN hardware operations, the generated output is 384-bits, while for all - other operations (including OTBN software), it is 256-bits. + ACC selected. Note for ACC hardware operations, the generated output is 384-bits, while for all + other operations (including ACC software), it is 256-bits. - Generating a hardware 384-bit seed directly for OTBN sideload reduces some of the OTBN code burden for entropy expansion. + Generating a hardware 384-bit seed directly for ACC sideload reduces some of the ACC code burden for entropy expansion. When generating for software, this is not a concern. ''' }, @@ -576,9 +576,9 @@ countermeasures: [ ''' }, { value: "3", - name: "OTBN", + name: "ACC", desc: ''' - The OTBN sideload key is continuously cleared with entropy. + The ACC sideload key is continuously cleared with entropy. ''' }, ] diff --git a/hw/ip/keymgr_dpe/doc/interfaces.md b/hw/ip/keymgr_dpe/doc/interfaces.md index 6c7abe5d444..6ec6243b7db 100644 --- a/hw/ip/keymgr_dpe/doc/interfaces.md +++ b/hw/ip/keymgr_dpe/doc/interfaces.md @@ -15,7 +15,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | edn | edn_pkg::edn | req_rsp | req | 1 | | | aes_key | keymgr_pkg::hw_key_req | uni | req | 1 | | | kmac_key | keymgr_pkg::hw_key_req | uni | req | 1 | | -| otbn_key | keymgr_pkg::otbn_key_req | uni | req | 1 | | +| acc_key | keymgr_pkg::acc_key_req | uni | req | 1 | | | kmac_data | kmac_pkg::app | req_rsp | req | 1 | | | otp_key | otp_ctrl_pkg::otp_keymgr_key | uni | rcv | 1 | | | otp_device_id | otp_ctrl_pkg::otp_device_id | uni | rcv | 1 | | diff --git a/hw/ip/keymgr_dpe/doc/programmers_guide.md b/hw/ip/keymgr_dpe/doc/programmers_guide.md index 6fa0d7f570c..154252d7173 100644 --- a/hw/ip/keymgr_dpe/doc/programmers_guide.md +++ b/hw/ip/keymgr_dpe/doc/programmers_guide.md @@ -55,7 +55,7 @@ The software is able to read the current state of key manager, however it never ## Versioned Key Generation SW needs to configure the following registers: -* Set `CONTROL_SHADOWED.DST_SEL` for either of of the use cases {`AES`, `KMAC`, `OTBN`}. +* Set `CONTROL_SHADOWED.DST_SEL` for either of of the use cases {`AES`, `KMAC`, `ACC`}. * Set `CONTROL_SHADOWED.OPERATION` to either of {Generate SW Operation, Generate HW Operation}. * Set `CONTROL_SHADOWED.SLOT_SRC_SEL` to select the source slot whose secret will be used to generate the key. * Set `SALT` and `KEY_VERSION` registers. diff --git a/hw/ip/keymgr_dpe/doc/registers.md b/hw/ip/keymgr_dpe/doc/registers.md index fe83b348641..f644490a202 100644 --- a/hw/ip/keymgr_dpe/doc/registers.md +++ b/hw/ip/keymgr_dpe/doc/registers.md @@ -214,12 +214,12 @@ the target cryptograhic use of the key. This field should be programmed for both HW / SW generation, as this helps diversify the output. -| Value | Name | Description | -|:--------|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 0x0 | None | No target selected | -| 0x1 | AES | AES selected | -| 0x2 | KMAC | KMAC selected | -| 0x3 | OTBN | OTBN selected. Note for OTBN hardware operations, the generated output is 384-bits, while for all other operations (including OTBN software), it is 256-bits. Generating a hardware 384-bit seed directly for OTBN sideload reduces some of the OTBN code burden for entropy expansion. When generating for software, this is not a concern. | +| Value | Name | Description | +|:--------|:-------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | None | No target selected | +| 0x1 | AES | AES selected | +| 0x2 | KMAC | KMAC selected | +| 0x3 | ACC | ACC selected. Note for ACC hardware operations, the generated output is 384-bits, while for all other operations (including ACC software), it is 256-bits. Generating a hardware 384-bit seed directly for ACC sideload reduces some of the ACC code burden for entropy expansion. When generating for software, this is not a concern. | ### CONTROL_SHADOWED . OPERATION @@ -265,7 +265,7 @@ toggle the clear bit again (i.e. disable continuous clearing). | 0x0 | None | No sideload keys cleared. | | 0x1 | AES | The AES sideload key is continuously cleared with entropy. | | 0x2 | KMAC | The KMAC sideload key is continuously cleared with entropy. | -| 0x3 | OTBN | The OTBN sideload key is continuously cleared with entropy. | +| 0x3 | ACC | The ACC sideload key is continuously cleared with entropy. | Other values are reserved. diff --git a/hw/ip/keymgr_dpe/doc/theory_of_operation.md b/hw/ip/keymgr_dpe/doc/theory_of_operation.md index fb4adae0535..54be25f721a 100644 --- a/hw/ip/keymgr_dpe/doc/theory_of_operation.md +++ b/hw/ip/keymgr_dpe/doc/theory_of_operation.md @@ -167,17 +167,17 @@ When there is no fault and the enable signal is active by life cycle controller, ### Versioned Key Generation A versioned key generation operation uses the following registers: -* `CONTROL_SHADOWED.DST_SEL` determines the target use for the generated key, and that is either one of {`AES`, `KMAC`, `OTBN`}. +* `CONTROL_SHADOWED.DST_SEL` determines the target use for the generated key, and that is either one of {`AES`, `KMAC`, `ACC`}. * `CONTROL_SHADOWED.SLOT_SRC_SEL` determines the source slot whose key should be used for the key derivation. * `SALT` is used as a part of the message during the key derivation. * `KEY_VERSION` is the target key value, and it also becomes the part of the message for KDF call. During the generate operation, a versioned key is generated from the secret of the source slot selected by `SLOT_SRC_SEL`. -After a successful key generation operation, if the generated key is requested for HW use, then the generated key is loaded into the sideload slot that drives the specified target peripheral port (`DST_SEL` being either one of {`AES`, `KMAC`, `OTBN`}). +After a successful key generation operation, if the generated key is requested for HW use, then the generated key is loaded into the sideload slot that drives the specified target peripheral port (`DST_SEL` being either one of {`AES`, `KMAC`, `ACC`}). In the case of SW key, the generated key is loaded into a CSR (see `SW_SHARE0_OUTPUT` and `SW_SHARE1_OUTPUT` registers). The key is generated with a KDF call, where the secret key is read from source slot. -Then, `generated_key = KDF(parent_key, KEY_VERSION || SALT || dest_seed || output_key)` where `dest_seed` and `output_key` are domain separators (i.e. diversification values from netlist) to distinguish SW/HW outputs as well as the target HWIP peripheral {`AES`, `KMAC`, `OTBN`}. +Then, `generated_key = KDF(parent_key, KEY_VERSION || SALT || dest_seed || output_key)` where `dest_seed` and `output_key` are domain separators (i.e. diversification values from netlist) to distinguish SW/HW outputs as well as the target HWIP peripheral {`AES`, `KMAC`, `ACC`}. KDF used for key generation calls is the same KMAC instance used in advance calls. The only difference is that the input messages are 0-padded to another length parameter, `GenDataWidth`. @@ -217,7 +217,7 @@ During advance operations, KDF inputs are 0 padded to `AdvDataWidth` bits. Depen * `owner_seed` is 256-bit owner secret received from the `SECRET3` OTP partition. During key generation operations, KDF inputs are 0 padded to `GenDataWidth` bits. Some diversification constants are: -* `dest_seed` is a 256-bit diversification value for each cryptographic key type {AES, KMAC, OTBN}. +* `dest_seed` is a 256-bit diversification value for each cryptographic key type {AES, KMAC, ACC}. * `output_key` is a 256-bit diversification value for distinguishing software and sideload keys. ### Life Cycle Connection diff --git a/hw/ip/keymgr_dpe/dv/README.md b/hw/ip/keymgr_dpe/dv/README.md index fa1e00bd94f..e0a88f2d055 100644 --- a/hw/ip/keymgr_dpe/dv/README.md +++ b/hw/ip/keymgr_dpe/dv/README.md @@ -92,7 +92,7 @@ It creates the following analysis ports to retrieve the data monitored by corres #### Assertions * TLUL assertions: The `tb/keymgr_dpe_bind.sv` binds the `tlul_assert` [assertions](../../tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. * Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. -* Check(Kmac|Aes|Otbn)Key: Check keys on the 3 sideload interfaces. +* Check(Kmac|Aes|Acc)Key: Check keys on the 3 sideload interfaces. * CheckEdn1stReq / CheckEdn2ndReq: Check KEYMGR_DPE sends 2 EDN request periodically based on the CSR `reseed_interval`. ## Building and running tests diff --git a/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_env_cov.sv b/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_env_cov.sv index 50725abb9aa..980cf6140de 100644 --- a/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_env_cov.sv +++ b/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_env_cov.sv @@ -87,7 +87,7 @@ class keymgr_dpe_env_cov extends cip_base_env_cov #(.CFG_T(keymgr_dpe_env_cfg)); keymgr_dpe_pkg::keymgr_dpe_ops_e op, bit aes_sl_avail, bit kmac_sl_avail, - bit otbn_sl_avail, + bit acc_sl_avail, bit regwen ); sideload_clear_cp: coverpoint sideload_clear { @@ -101,12 +101,12 @@ class keymgr_dpe_env_cov extends cip_base_env_cov #(.CFG_T(keymgr_dpe_env_cfg)); op_cp: coverpoint op; aes_sl_avail_cp: coverpoint aes_sl_avail; kmac_sl_avail_cp: coverpoint kmac_sl_avail; - otbn_sl_avail_cp: coverpoint otbn_sl_avail; + acc_sl_avail_cp: coverpoint acc_sl_avail; regwen_cp: coverpoint regwen; sideload_clear_x_state_op_cross: cross sideload_clear, state, op; sideload_clear_x_sl_avail_cross: cross sideload_clear_cp, aes_sl_avail, kmac_sl_avail, - otbn_sl_avail; + acc_sl_avail; sideload_clear_x_regwen_cross: cross sideload_clear_cp, regwen_cp; endgroup diff --git a/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_if.sv b/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_if.sv index 5127b96241e..7884fccc790 100644 --- a/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_if.sv +++ b/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_if.sv @@ -24,11 +24,11 @@ interface keymgr_dpe_if(input clk, input rst_n); keymgr_pkg::hw_key_req_t kmac_key; keymgr_pkg::hw_key_req_t aes_key; - keymgr_pkg::otbn_key_req_t otbn_key; + keymgr_pkg::acc_key_req_t acc_key; keymgr_pkg::hw_key_req_t kmac_key_exp; keymgr_pkg::hw_key_req_t aes_key_exp; - keymgr_pkg::otbn_key_req_t otbn_key_exp; + keymgr_pkg::acc_key_req_t acc_key_exp; // connect KDF interface for assertion check wire kmac_pkg::app_req_t kmac_data_req; @@ -55,7 +55,7 @@ interface keymgr_dpe_if(input clk, input rst_n); // sideload status keymgr_dpe_sideload_status_e aes_sideload_status; - keymgr_dpe_sideload_status_e otbn_sideload_status; + keymgr_dpe_sideload_status_e acc_sideload_status; // When kmac sideload key is generated, `kmac_key` becomes valid with the generated digest data. // If SW requests keymgr_dpe to do another operation, kmac_key will be updated to the internal key @@ -140,12 +140,12 @@ interface keymgr_dpe_if(input clk, input rst_n); keymgr_dpe_en = lc_ctrl_pkg::lc_tx_t'($urandom); kmac_key_exp = '0; aes_key_exp = '0; - otbn_key_exp = '0; + acc_key_exp = '0; is_kmac_key_good = 0; is_kmac_data_good = 0; kmac_sideload_status = SideLoadNotAvail; aes_sideload_status = SideLoadNotAvail; - otbn_sideload_status = SideLoadNotAvail; + acc_sideload_status = SideLoadNotAvail; // edn related edn_interval = 'h100; @@ -295,11 +295,11 @@ interface keymgr_dpe_if(input clk, input rst_n); aes_sideload_status <= SideLoadAvail; end end - keymgr_pkg::Otbn: begin - if (otbn_sideload_status != SideLoadClear) begin - // only otbn uses full 384 bits digest data - otbn_key_exp <= '{1'b1, key_shares}; - otbn_sideload_status <= SideLoadAvail; + keymgr_pkg::Acc: begin + if (acc_sideload_status != SideLoadClear) begin + // only acc uses full 384 bits digest data + acc_key_exp <= '{1'b1, key_shares}; + acc_sideload_status <= SideLoadAvail; end end default: `uvm_fatal("keymgr_dpe_if", $sformatf("Unexpect dest type %0s", dest.name)) @@ -312,17 +312,17 @@ interface keymgr_dpe_if(input clk, input rst_n); // reset from Clear to NotAvail if (kmac_sideload_status == SideLoadClear) kmac_sideload_status <= SideLoadNotAvail; if (aes_sideload_status == SideLoadClear) aes_sideload_status <= SideLoadNotAvail; - if (otbn_sideload_status == SideLoadClear) otbn_sideload_status <= SideLoadNotAvail; + if (acc_sideload_status == SideLoadClear) acc_sideload_status <= SideLoadNotAvail; case (clear_dest) keymgr_pkg::SideLoadClrIdle: ; // do nothing - keymgr_pkg::SideLoadClrAes, keymgr_pkg::SideLoadClrKmac, keymgr_pkg::SideLoadClrOtbn: begin + keymgr_pkg::SideLoadClrAes, keymgr_pkg::SideLoadClrKmac, keymgr_pkg::SideLoadClrAcc: begin clear_one_sideload_key(clear_dest); end // clear all default: begin clear_one_sideload_key(keymgr_pkg::SideLoadClrAes); clear_one_sideload_key(keymgr_pkg::SideLoadClrKmac); - clear_one_sideload_key(keymgr_pkg::SideLoadClrOtbn); + clear_one_sideload_key(keymgr_pkg::SideLoadClrAcc); end endcase endfunction @@ -338,9 +338,9 @@ interface keymgr_dpe_if(input clk, input rst_n); kmac_key_exp.valid <= 0; kmac_sideload_status <= SideLoadClear; end - keymgr_pkg::SideLoadClrOtbn: begin - otbn_sideload_status <= SideLoadClear; - otbn_key_exp.valid <= 0; + keymgr_pkg::SideLoadClrAcc: begin + acc_sideload_status <= SideLoadClear; + acc_key_exp.valid <= 0; end default: begin `uvm_fatal(msg_id, $sformatf("Unexpected clear_dest %0d", clear_dest)) @@ -357,11 +357,11 @@ interface keymgr_dpe_if(input clk, input rst_n); aes_key_exp.valid <= 0; kmac_key_exp.valid <= 0; - otbn_key_exp.valid <= 0; + acc_key_exp.valid <= 0; aes_sideload_status <= SideLoadClear; kmac_sideload_status <= SideLoadClear; - otbn_sideload_status <= SideLoadClear; + acc_sideload_status <= SideLoadClear; endfunction function automatic void update_edn_tolerance_upd(int edn_clk, int main_clk); @@ -587,10 +587,10 @@ interface keymgr_dpe_if(input clk, input rst_n); if (aes_sideload_status != SideLoadAvail) check_invalid_key(aes_key, "AES"); end forever begin - @(otbn_key or otbn_sideload_status); + @(acc_key or acc_sideload_status); // one cycle to sync with clock, one cycle to allow design to clear the key repeat (2) @(posedge clk); - if (otbn_sideload_status != SideLoadAvail) check_invalid_key(otbn_key, "OTBN"); + if (acc_sideload_status != SideLoadAvail) check_invalid_key(acc_key, "ACC"); end join end @@ -637,13 +637,13 @@ interface keymgr_dpe_if(input clk, input rst_n); ) `ASSERT_IFF_KEYMGR_DPE_LEGAL( - CheckOtbnKey, otbn_sideload_status == SideLoadAvail && - otbn_key_exp.valid -> otbn_key == otbn_key_exp + CheckAccKey, acc_sideload_status == SideLoadAvail && + acc_key_exp.valid -> acc_key == acc_key_exp ) `ASSERT_IFF_KEYMGR_DPE_LEGAL( - CheckOtbnKeyValid, - otbn_sideload_status != SideLoadClear -> - otbn_key_exp.valid == otbn_key.valid + CheckAccKeyValid, + acc_sideload_status != SideLoadClear -> + acc_key_exp.valid == acc_key.valid ) // for EDN assertion diff --git a/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_scoreboard.sv b/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_scoreboard.sv index 15c0469168f..1365b965b23 100644 --- a/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_scoreboard.sv +++ b/hw/ip/keymgr_dpe/dv/env/keymgr_dpe_scoreboard.sv @@ -481,7 +481,7 @@ class keymgr_dpe_scoreboard extends cip_base_scoreboard #( get_operation(), cfg.keymgr_dpe_vif.aes_sideload_status == SideLoadAvail, cfg.keymgr_dpe_vif.kmac_sideload_status == SideLoadAvail, - cfg.keymgr_dpe_vif.otbn_sideload_status == SideLoadAvail, + cfg.keymgr_dpe_vif.acc_sideload_status == SideLoadAvail, cfg_regwen); end else if (csr.get_name() != "control_shadowed") begin cov.sw_input_cg_wrap[csr.get_name()].sample(item.a_data, cfg_regwen); @@ -572,11 +572,11 @@ class keymgr_dpe_scoreboard extends cip_base_scoreboard #( cfg.keymgr_dpe_vif.aes_key_exp, cfg.keymgr_dpe_vif.aes_key)) end - if (cfg.keymgr_dpe_vif.otbn_key_exp != cfg.keymgr_dpe_vif.otbn_key) begin + if (cfg.keymgr_dpe_vif.acc_key_exp != cfg.keymgr_dpe_vif.acc_key) begin `uvm_error(`gfn, - $sformatf({"After a disable otbn sideload key was not preseved", + $sformatf({"After a disable acc sideload key was not preseved", "exp 'h%0h vs. act 'h%0h"}, - cfg.keymgr_dpe_vif.otbn_key_exp, cfg.keymgr_dpe_vif.otbn_key)) + cfg.keymgr_dpe_vif.acc_key_exp, cfg.keymgr_dpe_vif.acc_key)) end if (cfg.keymgr_dpe_vif.kmac_key_exp != cfg.keymgr_dpe_vif.kmac_key) begin @@ -1401,7 +1401,7 @@ class keymgr_dpe_scoreboard extends cip_base_scoreboard #( case (dest) keymgr_pkg::Kmac: exp.KeyID = keymgr_pkg::RndCnstKmacSeedDefault; keymgr_pkg::Aes: exp.KeyID = keymgr_pkg::RndCnstAesSeedDefault; - keymgr_pkg::Otbn: exp.KeyID = keymgr_pkg::RndCnstOtbnSeedDefault; + keymgr_pkg::Acc: exp.KeyID = keymgr_pkg::RndCnstAccSeedDefault; keymgr_pkg::None: exp.KeyID = keymgr_pkg::RndCnstNoneSeedDefault; default: `uvm_fatal(`gfn, $sformatf("Unexpected dest_sel: %0s", dest.name)) endcase diff --git a/hw/ip/keymgr_dpe/dv/tb.sv b/hw/ip/keymgr_dpe/dv/tb.sv index ac5c6167fb3..d66b8425a40 100644 --- a/hw/ip/keymgr_dpe/dv/tb.sv +++ b/hw/ip/keymgr_dpe/dv/tb.sv @@ -51,7 +51,7 @@ module tb; .clk_edn_i (edn_clk ), .rst_edn_ni (edn_rst_n ), .aes_key_o (keymgr_dpe_if.aes_key), - .otbn_key_o (keymgr_dpe_if.otbn_key), + .acc_key_o (keymgr_dpe_if.acc_key), .kmac_key_o (keymgr_dpe_if.kmac_key), .kmac_data_o (keymgr_dpe_kmac_intf.kmac_data_req), .kmac_data_i (keymgr_dpe_kmac_intf.kmac_data_rsp), diff --git a/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv b/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv index 8d927b3ff98..9eea095dffa 100644 --- a/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv +++ b/hw/ip/keymgr_dpe/rtl/keymgr_dpe.sv @@ -24,7 +24,7 @@ module keymgr_dpe parameter seed_t RndCnstHardOutputSeed = RndCnstHardOutputSeedDefault, parameter seed_t RndCnstNoneSeed = RndCnstNoneSeedDefault, parameter seed_t RndCnstAesSeed = RndCnstAesSeedDefault, - parameter seed_t RndCnstOtbnSeed = RndCnstOtbnSeedDefault, + parameter seed_t RndCnstAccSeed = RndCnstAccSeedDefault, parameter seed_t RndCnstKmacSeed = RndCnstKmacSeedDefault ) ( input clk_i, @@ -40,7 +40,7 @@ module keymgr_dpe // key interface to crypto modules output hw_key_req_t aes_key_o, output hw_key_req_t kmac_key_o, - output otbn_key_req_t otbn_key_o, + output acc_key_req_t acc_key_o, // data interface to/from crypto modules output kmac_pkg::app_req_t kmac_data_o, @@ -90,7 +90,7 @@ module keymgr_dpe seed_t soft_output_seed; seed_t hard_output_seed; seed_t aes_seed; - seed_t otbn_seed; + seed_t acc_seed; seed_t kmac_seed; seed_t none_seed; @@ -102,7 +102,7 @@ module keymgr_dpe RndCnstSoftOutputSeed, RndCnstHardOutputSeed, RndCnstAesSeed, - RndCnstOtbnSeed, + RndCnstAccSeed, RndCnstKmacSeed, RndCnstNoneSeed }), @@ -111,7 +111,7 @@ module keymgr_dpe soft_output_seed, hard_output_seed, aes_seed, - otbn_seed, + acc_seed, kmac_seed, none_seed }) @@ -490,7 +490,7 @@ module keymgr_dpe assign dest_sel = keymgr_key_dest_e'(reg2hw.control_shadowed.dest_sel.q); assign dest_seed = dest_sel == Aes ? aes_seed : dest_sel == Kmac ? kmac_seed : - dest_sel == Otbn ? otbn_seed : none_seed; + dest_sel == Acc ? acc_seed : none_seed; assign output_key = mubi4_test_true_strict(hw_key_sel) ? hard_output_seed : soft_output_seed; assign gen_in = active_key_slot.valid ? {reg2hw.key_version, @@ -629,7 +629,7 @@ module keymgr_dpe .data_i(kmac_data), .prng_en_o(sideload_lfsr_en), .aes_key_o, - .otbn_key_o, + .acc_key_o, .kmac_key_o, .sideload_sel_err_o(sideload_sel_err), .fsm_err_o(sideload_fsm_err) @@ -802,7 +802,7 @@ module keymgr_dpe `ASSERT_KNOWN(AesKeyKnownO_A, aes_key_o) `ASSERT_KNOWN(KmacKeyKnownO_A, kmac_key_o) - `ASSERT_KNOWN(OtbnKeyKnownO_A, otbn_key_o) + `ASSERT_KNOWN(AccKeyKnownO_A, acc_key_o) `ASSERT_KNOWN(KmacDataKnownO_A, kmac_data_o) diff --git a/hw/ip/kmac/data/kmac.hjson b/hw/ip/kmac/data/kmac.hjson index 90868b4d559..0da22d61ec5 100644 --- a/hw/ip/kmac/data/kmac.hjson +++ b/hw/ip/kmac/data/kmac.hjson @@ -137,7 +137,7 @@ ''' type: "kmac_pkg::app_config_t" unpacked_dimensions: "[KmacNumAppIntf]" - default: "'{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgOTBN}" + default: "'{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgACC}" local: "false" expose: "true" } diff --git a/hw/ip/kmac/doc/theory_of_operation.md b/hw/ip/kmac/doc/theory_of_operation.md index 0302bca8e88..24f93cab75d 100644 --- a/hw/ip/kmac/doc/theory_of_operation.md +++ b/hw/ip/kmac/doc/theory_of_operation.md @@ -216,14 +216,14 @@ The type of the hashing operation is determined in the compile-time parameter `k | 0 | KeyMgr | KMAC | CSR prefix | 1 | LC_CTRL | cSHAKE128 | "LC_CTRL" | 2 | ROM_CTRL | cSHAKE256 | "ROM_CTRL" -| 3 | OTBN | Configurable | N/A +| 3 | ACC | Configurable | N/A -In the current version of IP, the IP has four application interfaces, which are KeyMgr, LC_CTRL, ROM_CTRL, and OTBN. +In the current version of IP, the IP has four application interfaces, which are KeyMgr, LC_CTRL, ROM_CTRL, and ACC. KeyMgr uses the KMAC operation with CSR prefix value. LC_CTRL and ROM_CTRL use the cSHAKE operation with the compile-time parameter prefixes. -The OTBN AppIntf does not use a prefix value but is configurable to select between different operations. -OTBN will use the SHA3-256, SHA3-512, SHAKE128, and SHAKE256 algorithms. +The ACC AppIntf does not use a prefix value but is configurable to select between different operations. +ACC will use the SHA3-256, SHA3-512, SHAKE128, and SHAKE256 algorithms. Other configurations are considered invalid and KMAC will respond with the response error flag. The app sends 64-bit data (`MsgWidth`) in a beat with the message strobe signal. @@ -232,12 +232,12 @@ The AppIntf module chooses the winner based on the following fixed priority: 1. KeyMgr 2. LC_CTRL 3. ROM_CTRL -4. OTBN +4. ACC Then it forwards the selected App to the next stage. Because this logic sees the first valid data as an initiator, the Apps cannot run the hashing operation with an empty message. After the logic switches to accept the message bitstream from the selected App, if the hashing operation is KMAC, the logic forces the sideloaded key to be used as a secret. -In OTBN mode the first word of the message request configures the drive strength and operation. +In ACC mode the first word of the message request configures the drive strength and operation. Bits [4:2] configure the Keccak drive strength and bits [1:0] select the appropriate SHA3/cSHAKE/SHAKE operation. Also it ignores the command issued from the software. Instead it generates the commands and sends them to the KMAC core. @@ -257,19 +257,19 @@ After hashing operation is completed, KMAC does not raise a `kmac_done` interrup The result digest always comes in two shares. If the `EnMasking` parameter is not set, the second share is always zero. -#### OTBN Interface Connection +#### ACC Interface Connection -OTBN initiated SHA3/SHAKE algorithms over the AppIntf may require multiple permutations for the resulting digest with a single function call. -Support for the OTBN application interface introduced the `next` and `hold` signals in the AppIntf request channel. -The `hold` signal is asserted `1'b1` for the duration of an OTBN initiated operation. This prevents KMAC from finishing its hashing computation until OTBN has received enough digest words. +ACC initiated SHA3/SHAKE algorithms over the AppIntf may require multiple permutations for the resulting digest with a single function call. +Support for the ACC application interface introduced the `next` and `hold` signals in the AppIntf request channel. +The `hold` signal is asserted `1'b1` for the duration of an ACC initiated operation. This prevents KMAC from finishing its hashing computation until ACC has received enough digest words. While remaining digest words exist, the `next` signal is asserted `1'b1` for a single clock cycle following a response `done` signal from KMAC. -Given the `hold` and `next` signals are only required by the AppIntf state machine for OTBN initiated functions, both signals are held inactive for the three previously existing interfaces. -The OTBN application interface uses the same AppIntf state machine as KeyMgr, LC_CTRL, and ROM_CTRL which a seperate internal state path. +Given the `hold` and `next` signals are only required by the AppIntf state machine for ACC initiated functions, both signals are held inactive for the three previously existing interfaces. +The ACC application interface uses the same AppIntf state machine as KeyMgr, LC_CTRL, and ROM_CTRL which a seperate internal state path. -The OTBN expects a 256-bit digest in the response channel from KMAC. +The ACC expects a 256-bit digest in the response channel from KMAC. The digest shares in `app_rsp_t` are both 384-bits wide. A 256-bit `prim_packer` FIFO takes the computed 256-bit digest from the Keccak state and buffers for sending it on the AppIntf response channel. -The FIFO should only be read from when an AppIntf response is active for an OTBN request. +The FIFO should only be read from when an AppIntf response is active for an ACC request. FIFO writes are controlled by the state machine and should occur when the FIFO is ready with an available digest. The Keccak state should not change while digest words from the current permutation are still being packed/squeezed into the FIFO. diff --git a/hw/ip/kmac/dv/env/kmac_env_pkg.sv b/hw/ip/kmac/dv/env/kmac_env_pkg.sv index 47d0a969c34..42dc7cb8eec 100644 --- a/hw/ip/kmac/dv/env/kmac_env_pkg.sv +++ b/hw/ip/kmac/dv/env/kmac_env_pkg.sv @@ -75,7 +75,7 @@ package kmac_env_pkg; // Earlgrey has 4 application interfaces parameter app_config_t APP_CFG[kmac_app_agent_pkg::NUM_APP_INTF] = '{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, - kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgOTBN}; + kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgACC}; ///////////////////////////// // Timing Model Parameters // diff --git a/hw/ip/kmac/dv/env/kmac_if.sv b/hw/ip/kmac/dv/env/kmac_if.sv index 13b41ff5b37..2e5ae90a63c 100644 --- a/hw/ip/kmac/dv/env/kmac_if.sv +++ b/hw/ip/kmac/dv/env/kmac_if.sv @@ -31,16 +31,16 @@ interface kmac_if(input clk_i, input rst_ni); app_rsp[kmac_app_agent_pkg::AppRom].digest_share0 == 0 && app_rsp[kmac_app_agent_pkg::AppRom].digest_share1 == 0) - `ASSERT(AppOtbnErrOutputZeros_A, app_rsp[kmac_app_agent_pkg::AppOtbn].error |-> - app_rsp[kmac_app_agent_pkg::AppOtbn].digest_share0 == 0 && - app_rsp[kmac_app_agent_pkg::AppOtbn].digest_share1 == 0) + `ASSERT(AppAccErrOutputZeros_A, app_rsp[kmac_app_agent_pkg::AppAcc].error |-> + app_rsp[kmac_app_agent_pkg::AppAcc].digest_share0 == 0 && + app_rsp[kmac_app_agent_pkg::AppAcc].digest_share1 == 0) - // Assertions to check if hold is high outside of OTBN mode + // Assertions to check if hold is high outside of ACC mode `ASSERT(AppKeymgrHoldNever_A, !app_req[kmac_app_agent_pkg::AppKeymgr].hold) `ASSERT(AppLcHoldNever_A, !app_req[kmac_app_agent_pkg::AppLc].hold) `ASSERT(AppRomHoldNever_A, !app_req[kmac_app_agent_pkg::AppRom].hold) - // Assertions to check if next is high outside of OTBN mode + // Assertions to check if next is high outside of ACC mode `ASSERT(AppKeymgrNextNever_A, !app_req[kmac_app_agent_pkg::AppKeymgr].next) `ASSERT(AppLcNextNever_A, !app_req[kmac_app_agent_pkg::AppLc].next) `ASSERT(AppRomNextNever_A, !app_req[kmac_app_agent_pkg::AppRom].next) diff --git a/hw/ip/kmac/dv/env/kmac_scoreboard.sv b/hw/ip/kmac/dv/env/kmac_scoreboard.sv index 8274e2cb76b..83210fa9af9 100644 --- a/hw/ip/kmac/dv/env/kmac_scoreboard.sv +++ b/hw/ip/kmac/dv/env/kmac_scoreboard.sv @@ -83,7 +83,7 @@ class kmac_scoreboard extends cip_base_scoreboard #( bit sha3_squeeze; bit sha3_manual; - // OTBN AppIntf status + // ACC AppIntf status bit [2:0] digest_word_idx, max_digest_words; bit [2:0] permutation_ctr_idx; bit [3:0] digest_word_ctr; @@ -330,7 +330,7 @@ class kmac_scoreboard extends cip_base_scoreboard #( (`KMAC_APP_VALID_TRANS(AppKeymgr) || `KMAC_APP_VALID_TRANS(AppLc) || `KMAC_APP_VALID_TRANS(AppRom) || - `KMAC_APP_VALID_TRANS(AppOtbn))); + `KMAC_APP_VALID_TRANS(AppAcc))); in_kmac_app = 1; sha3_idle = 0; sha3_absorb = 1; @@ -348,13 +348,13 @@ class kmac_scoreboard extends cip_base_scoreboard #( end else if (`KMAC_APP_VALID_TRANS(AppRom)) begin app_mode = AppRom; strength = sha3_pkg::L256; - end else if (`KMAC_APP_VALID_TRANS(AppOtbn)) begin - app_mode = AppOtbn; + end else if (`KMAC_APP_VALID_TRANS(AppAcc)) begin + app_mode = AppAcc; // Set the sha3 mode and keccak strength from cfg word // Bits [8:0] contain strb and last // Bits [72:9] contain the msg/cfg - strength = cfg.m_kmac_app_agent_cfg[AppOtbn].vif.req_data_if.h_data[13:11]; - dynamic_hash_mode = cfg.m_kmac_app_agent_cfg[AppOtbn].vif.req_data_if.h_data[10:9]; + strength = cfg.m_kmac_app_agent_cfg[AppAcc].vif.req_data_if.h_data[13:11]; + dynamic_hash_mode = cfg.m_kmac_app_agent_cfg[AppAcc].vif.req_data_if.h_data[10:9]; max_digest_words = kmac_pkg::compute_max_digest(strength); //compute_max_digest(strength, max_digest_words); end @@ -415,7 +415,7 @@ class kmac_scoreboard extends cip_base_scoreboard #( (cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.req_data_if.valid || cfg.m_kmac_app_agent_cfg[AppLc].vif.req_data_if.valid || cfg.m_kmac_app_agent_cfg[AppRom].vif.req_data_if.valid || - cfg.m_kmac_app_agent_cfg[AppOtbn].vif.req_data_if.valid)) begin + cfg.m_kmac_app_agent_cfg[AppAcc].vif.req_data_if.valid)) begin app_st = StAppCfg; app_fsm_active = 1; end else if (checked_kmac_cmd == CmdStart) begin @@ -426,7 +426,7 @@ class kmac_scoreboard extends cip_base_scoreboard #( if (app_mode == AppKeymgr && !cfg.keymgr_sideload_agent_cfg.vif.sideload_key.valid) begin app_st = StKeyMgrErrKeyNotValid; - end else if (app_mode == AppOtbn) begin + end else if (app_mode == AppAcc) begin app_st = StAppDynamicCfg; end else begin app_st = StAppMsg; @@ -547,13 +547,13 @@ class kmac_scoreboard extends cip_base_scoreboard #( push_pull_agent_pkg::push_pull_item#( .HostDataWidth(kmac_app_agent_pkg::KMAC_REQ_DATA_WIDTH)) kmac_app_block_item; - bit otbn_mode_skip = 0; + bit acc_mode_skip = 0; forever begin wait(!cfg.under_reset); @(posedge in_kmac_app); `uvm_info(`gfn, $sformatf("req app_mode: %0s", app_mode.name()), UVM_HIGH) - otbn_mode_skip = (app_mode == AppOtbn); + acc_mode_skip = (app_mode == AppAcc); `DV_SPINWAIT_EXIT( forever begin kmac_app_req_fifo[app_mode].get(kmac_app_block_item); @@ -574,8 +574,8 @@ class kmac_scoreboard extends cip_base_scoreboard #( in_keccak_rounds); end - // first word in AppOtbn is configuration not msg - if (!otbn_mode_skip) begin + // first word in AppAcc is configuration not msg + if (!acc_mode_skip) begin while (kmac_app_block_strb > 0) begin if (kmac_app_block_strb[0]) begin kmac_app_msg.push_back(kmac_app_block_data[7:0]); @@ -584,7 +584,7 @@ class kmac_scoreboard extends cip_base_scoreboard #( kmac_app_block_strb = kmac_app_block_strb >> 1; end end else begin - otbn_mode_skip = 0; + acc_mode_skip = 0; end `uvm_info(`gfn, $sformatf("kmac_app_msg: %0p", kmac_app_msg), UVM_HIGH) @@ -670,20 +670,20 @@ class kmac_scoreboard extends cip_base_scoreboard #( if (do_check_digest) check_digest(); end - // Check if in OTBN mode a new rsp is captured before hold is asserted low + // Check if in ACC mode a new rsp is captured before hold is asserted low // When hold == 0 transaction is over - if (app_mode == AppOtbn) begin + if (app_mode == AppAcc) begin fork begin - @(posedge cfg.m_kmac_app_agent_cfg[AppOtbn].vif.rsp_done); + @(posedge cfg.m_kmac_app_agent_cfg[AppAcc].vif.rsp_done); end begin - wait (cfg.m_kmac_app_agent_cfg[AppOtbn].vif.hold == 0); + wait (cfg.m_kmac_app_agent_cfg[AppAcc].vif.hold == 0); end join_any disable fork; end - end while (cfg.m_kmac_app_agent_cfg[AppOtbn].vif.hold == 1); // Non-OTBN modes are always 1'b0 and will run once + end while (cfg.m_kmac_app_agent_cfg[AppAcc].vif.hold == 1); // Non-ACC modes are always 1'b0 and will run once in_kmac_app = 0; sha3_squeeze = 0; @@ -1519,8 +1519,8 @@ class kmac_scoreboard extends cip_base_scoreboard #( // Array to hold the expected digest calculated by DPI model bit [7:0] dpi_digest[]; - // Otbn mode flag - bit otbn_mode; + // Acc mode flag + bit acc_mode; // Length of produced dpi digest int loop_len; @@ -1550,7 +1550,7 @@ class kmac_scoreboard extends cip_base_scoreboard #( int key_word_len, key_byte_len; // Actual hash_mode based on interface or SW register - sha3_pkg::sha3_mode_e actual_hash_mode = in_kmac_app ? ((app_mode == AppOtbn) ? dynamic_hash_mode : sha3_pkg::CShake ) : hash_mode; + sha3_pkg::sha3_mode_e actual_hash_mode = in_kmac_app ? ((app_mode == AppAcc) ? dynamic_hash_mode : sha3_pkg::CShake ) : hash_mode; bit use_keymgr_keys = sideload_en || (in_kmac_app && app_mode == AppKeymgr); @@ -1567,8 +1567,8 @@ class kmac_scoreboard extends cip_base_scoreboard #( // - the expected output length in bytes // - if we are using the xof version of kmac if (in_kmac_app) begin - // KMAC_APP output will always be 384 bits (48 bytes) unless AppOtbn - if (app_mode == AppOtbn) begin + // KMAC_APP output will always be 384 bits (48 bytes) unless AppAcc + if (app_mode == AppAcc) begin output_len_bytes = 32 * digest_word_ctr; end else begin output_len_bytes = AppDigestW / 8; @@ -1761,9 +1761,9 @@ class kmac_scoreboard extends cip_base_scoreboard #( ///////////////////////////////////////// // Compare actual and expected digests // ///////////////////////////////////////// - otbn_mode = (app_mode == AppOtbn && in_kmac_app); - loop_len = otbn_mode ? 32 : output_len_bytes; - base_idx = otbn_mode ? (32 * (digest_word_ctr -1)) : 0; + acc_mode = (app_mode == AppAcc && in_kmac_app); + loop_len = acc_mode ? 32 : output_len_bytes; + base_idx = acc_mode ? (32 * (digest_word_ctr -1)) : 0; for (int i = 0; i < loop_len; i++) begin dpi_idx = base_idx + i; diff --git a/hw/ip/kmac/dv/env/seq_lib/kmac_smoke_vseq.sv b/hw/ip/kmac/dv/env/seq_lib/kmac_smoke_vseq.sv index 952f86fc6cb..fd4262f0b4c 100644 --- a/hw/ip/kmac/dv/env/seq_lib/kmac_smoke_vseq.sv +++ b/hw/ip/kmac/dv/env/seq_lib/kmac_smoke_vseq.sv @@ -22,7 +22,7 @@ class kmac_smoke_vseq extends kmac_base_vseq; bit entropy_fetched; constraint app_mode_c { - app_mode inside {AppKeymgr, AppLc, AppRom, AppOtbn}; + app_mode inside {AppKeymgr, AppLc, AppRom, AppAcc}; } constraint num_trans_c { @@ -244,7 +244,7 @@ class kmac_smoke_vseq extends kmac_base_vseq; // Wait until the KMAC engine has completely finished `uvm_info(`gfn, "waiting for kmac_app operation to finish", UVM_HIGH) wait (cfg.m_kmac_app_agent_cfg[app_mode].vif.rsp_done == 1); - wait (cfg.m_kmac_app_agent_cfg[app_mode].vif.hold == 0); // OTBN mode has multiple rsp + wait (cfg.m_kmac_app_agent_cfg[app_mode].vif.hold == 0); // ACC mode has multiple rsp `uvm_info(`gfn, "finished waiting for kmac_app operation", UVM_HIGH) if (kmac_err_type inside diff --git a/hw/ip/kmac/rtl/kmac.sv b/hw/ip/kmac/rtl/kmac.sv index 791bb5629d6..96f20953853 100644 --- a/hw/ip/kmac/rtl/kmac.sv +++ b/hw/ip/kmac/rtl/kmac.sv @@ -34,7 +34,7 @@ module kmac parameter bit SecIdleAcceptSwMsg = 1'b0, parameter int unsigned NumAppIntf = 4, parameter app_config_t AppCfg[NumAppIntf] = '{AppCfgKeyMgr, AppCfgLcCtrl, - AppCfgRomCtrl, AppCfgOTBN}, + AppCfgRomCtrl, AppCfgACC}, parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, diff --git a/hw/ip/kmac/rtl/kmac_app.sv b/hw/ip/kmac/rtl/kmac_app.sv index 5c6a8c2246c..ba9c1bc4c44 100644 --- a/hw/ip/kmac/rtl/kmac_app.sv +++ b/hw/ip/kmac/rtl/kmac_app.sv @@ -18,7 +18,7 @@ module kmac_app parameter bit SecIdleAcceptSwMsg = 1'b0, parameter int unsigned NumAppIntf = 4, parameter app_config_t AppCfg[NumAppIntf] = '{AppCfgKeyMgr, AppCfgLcCtrl, - AppCfgRomCtrl, AppCfgOTBN} + AppCfgRomCtrl, AppCfgACC} ) ( input clk_i, input rst_ni, @@ -204,7 +204,7 @@ module kmac_app logic [AppIdxW-1:0] app_id, app_id_d; logic clr_appid, set_appid; - // AppIntf OTBN signals + // AppIntf ACC signals logic set_dynamic_sha_mode; sha3_pkg::sha3_mode_e dynamic_sha3_mode_q; sha3_pkg::keccak_strength_e dynamic_keccak_strength_q; @@ -234,7 +234,7 @@ module kmac_app logic service_rejected_error_set, service_rejected_error_clr; logic err_during_sw_d, err_during_sw_q; - // Digest packer for OTBN app intf + // Digest packer for ACC app intf logic [255:0] digest_word_share_0, digest_word_share_1; logic [255:0] packed_digest_word_share_0, packed_digest_word_share_1; logic [255:0] digest_word_share_valid_0, digest_word_share_valid_1; @@ -247,7 +247,7 @@ module kmac_app logic [255:0] digest_word_mask; logic [1:0] permutation_ctr; logic incr_permutation_ctr, reset_permutation_ctr; - logic otbn_app_intf_done; + logic acc_app_intf_done; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) service_rejected_error <= 1'b 0; @@ -259,7 +259,7 @@ module kmac_app // Application Mux/ Demux // //////////////////////////// - // Set SHA3 mode and Keccak strength if OTBN mode + // Set SHA3 mode and Keccak strength if ACC mode always_ff @(posedge clk_i) begin if (app_i[AppConfigDynamic].valid && set_appid) begin dynamic_sha3_mode_q <= sha3_pkg::sha3_mode_e'(app_i[AppConfigDynamic].data[1:0]); @@ -267,7 +267,7 @@ module kmac_app end end - // Control the permutation index for keccak states and XOFs with OTBN + // Control the permutation index for keccak states and XOFs with ACC always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin permutation_ctr <= 2'h0; @@ -278,7 +278,7 @@ module kmac_app end end - // Control the word index for XOFs with OTBN + // Control the word index for XOFs with ACC assign digest_word_idx_d = digest_word_idx_q; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) digest_word_idx_q <= 3'h0; @@ -290,7 +290,7 @@ module kmac_app // Processing return data. // sends to only selected app intf. // clear digest right after done to not leak info to other interface - // OTBN mode operates different with 256-bit digest being padded out of packer FIFO + // ACC mode operates different with 256-bit digest being padded out of packer FIFO always_comb begin app_rsp_err = error_i | fsm_digest_done_q | sparse_fsm_error_o | service_rejected_error; digest_word_share_valid_0 = (app_rsp_err | !packed_digest_word_valid) ? @@ -302,7 +302,7 @@ module kmac_app app_o[i] = '{ ready: app_data_ready | fsm_data_ready, done: (AppCfg[app_id].Mode == AppConfigDynamic) ? - otbn_app_intf_done : (app_digest_done | fsm_digest_done_q), + acc_app_intf_done : (app_digest_done | fsm_digest_done_q), digest_share0: (AppCfg[app_id].Mode == AppConfigDynamic) ? {128'h0, digest_word_share_valid_0} : app_digest[0], digest_share1: (AppCfg[app_id].Mode == AppConfigDynamic) ? @@ -502,7 +502,7 @@ module kmac_app st_d = StAppWait; end - // Used to control packing into fifo for OTBN return digest + // Used to control packing into fifo for ACC return digest StAppShiftDigest: begin st_d = StAppShiftDigest; if (digest_packer_ready) begin @@ -535,7 +535,7 @@ module kmac_app prim_mubi_pkg::mubi4_test_true_strict(squeezing_i)) begin digest_valid = 1'b 1; - // hold always 1'b0 for non-otbn modes maintaining normal behavior + // hold always 1'b0 for non-acc modes maintaining normal behavior if (app_i[app_id].hold == 1'b0) begin // Send digest to KeyMgr and complete the op st_d = StIdle; @@ -889,7 +889,7 @@ module kmac_app end // Set the final word size for SHAKE 128/256 modes given rate - // SHA3 mode has fixed 256/512 bit sizes for OTBN + // SHA3 mode has fixed 256/512 bit sizes for ACC assign digest_word_mask = (dynamic_keccak_strength_q == sha3_pkg::L128 && digest_word_idx_q == 3'h5) ? { {192{1'b0}}, {64{1'b1}} } : ((dynamic_keccak_strength_q == sha3_pkg::L256 && @@ -980,7 +980,7 @@ module kmac_app || shift_and_pack_digest) && ~clr_appid && (AppCfg[app_id].Mode == AppConfigDynamic); // Assert done for digest when packer has valid word and we are in valid state to push - assign otbn_app_intf_done = packed_digest_word_valid && ~clr_appid && ((st == StAppWait) || + assign acc_app_intf_done = packed_digest_word_valid && ~clr_appid && ((st == StAppWait) || (st == StAppShiftDigest) || (st == StAppManualRun)); assign digest_packer_ready = digest_packer_ready_share_0 & digest_packer_ready_share_1; assign packed_digest_word_valid = packed_digest_word_valid_share_0 && diff --git a/hw/ip/kmac/rtl/kmac_pkg.sv b/hw/ip/kmac/rtl/kmac_pkg.sv index a0c525ba363..430fa2a8b47 100644 --- a/hw/ip/kmac/rtl/kmac_pkg.sv +++ b/hw/ip/kmac/rtl/kmac_pkg.sv @@ -266,8 +266,8 @@ package kmac_pkg; Prefix: NSPrefixW'({EncodedStringRomCtrl, EncodedStringEmpty}) }; - // OTBN - parameter app_config_t AppCfgOTBN = '{ + // ACC + parameter app_config_t AppCfgACC = '{ Mode: AppConfigDynamic, KeccakStrength: sha3_pkg::L256, // Ignored PrefixMode: 1'b0, // No Prefix @@ -482,7 +482,7 @@ package kmac_pkg; // Error due to the counter integrity check failure inside MsgFifo.Fifo ErrMsgFifoIntegrity = 8'h C3, - // Error in the packer that is connected for the app intf to OTBN + // Error in the packer that is connected for the app intf to ACC ErrAppIntfPacker = 8'hC4 } err_code_e; @@ -508,7 +508,7 @@ package kmac_pkg; conv_endian32 = (swap) ? conv_data : v ; endfunction : conv_endian32 - // Function to compute the number of digest words for OTBN request + // Function to compute the number of digest words for ACC request // before starting a manual run function automatic logic [2:0] compute_max_digest ( sha3_pkg::keccak_strength_e keccak_strength_i diff --git a/hw/ip/otbn/doc/developing_otbn.md b/hw/ip/otbn/doc/developing_otbn.md deleted file mode 100644 index ba065958e0d..00000000000 --- a/hw/ip/otbn/doc/developing_otbn.md +++ /dev/null @@ -1,129 +0,0 @@ -# OpenTitan Big Number Accelerator (OTBN) - -This directory contains the implementation of the OpenTitan Big Number -Accelerator (OTBN). OTBN is a coprocessor for asymmetric cryptographic -operations like RSA or Elliptic Curve Cryptography (ECC). - -See [here](../README.md) for documentation on -the current version of OTBN; documentation matching the code in this directory -can be found in the `doc` directory. - -OTBN is under active development. Please ask questions and report issues -through the [GitHub issue tracker](https://github.com/lowRISC/opentitan/issues). - -## Develop OTBN - -### Build OTBN software - -An assembler, linker and disassembler for OTBN can be found in `hw/ip/otbn/util` -(For more details about these tools see the [user guide](../../../../doc/contributing/sw/otbn_sw.md)). - -These tools are wrappers around a RISC-V and binutils toolchain so one must be available. -The toolchain can be installed with the [`util/get-toolchain.py`](../../../../util/get-toolchain.py) script. -Simply call the script from `$REPO_TOP` and make sure to select the correct architecture. - -When the toolchain is installed, the `otbn_as.py` and `otbn_ld.py` can be used to build .elf files for use with simulations. -They work similarly to binutils programs they wrap. - -``` -hw/ip/otbn/util/otbn_as.py -o prog_bin/prog.o prog.s -hw/ip/otbn/util/otbn_ld.py -o prog_bin/prog.elf prog_bin/prog.o -``` - -Will assemble and link `prog.s` resulting in `prog_bin/prog.elf` that can be run -directly on the ISS or the standalone RTL simulation. - -### Work with the ISA - -The instruction set is described in machine readable form in -`data/insns.yml`. This is parsed by Python code in -`util/insn_yaml.py`, which runs various basic checks on the data. The -binutils-based toolchain described above uses this information. Other -users include: - - - `util/yaml_to_doc.py`: Generates a Markdown snippet which is included in - the OTBN specification. - - - `dv/rig/otbn-rig`: A random instruction generator for OTBN. See - dv/rig/README.md for further information. - -### Run the Python simulator -The quickest way to run an OTBN-only program is to use the Python simulator. -First, generate a `.elf.` file either using the usual build process or by -manually running `otbn_as.py` and `otbn_ld.py` as shown above. Then, from `$REPO_TOP`: -```console -$ hw/ip/otbn/dv/otbnsim/standalone.py -t path/to/prog.elf -``` - -### Run the standalone RTL simulation -A standalone environment to run OTBN alone in Verilator is included. Build it -with `fusesoc` as follows: - -```sh -fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ip:otbn_top_sim -``` - -It includes functionality to set the initial Dmem and Imem contents from a .elf -file. The start address is hard coded to 0. Modify the `ImemStartAddr` parameter -in `./dv/verilator/otbn_top_sim.sv` to change this. A .elf (see above for build -instructions) can be loaded and run as follows: - -```sh -./build/lowrisc_ip_otbn_top_sim_0.1/sim-verilator/Votbn_top_sim \ - --load-elf=prog_bin/prog.elf -``` - -The simulation automatically halts on an `ecall` instruction and prints the -final register values. The ISS is run in parallel and final register and memory -state will be cross-checked. - -Tracing functionality is available in the `Votbn_top_sim` binary. To obtain a -full .fst wave trace pass the `-t` flag. To get an instruction level trace pass -the `--otbn-trace-file=trace.log` argument. The instruction trace format is -documented in `hw/ip/otbn/dv/tracer`. - -To run several auto-generated binaries against the Verilated RTL, use -the script at `dv/verilator/run-some.py`. For example, - -```sh -hw/ip/otbn/dv/verilator/run-some.py --size=1500 --count=50 X -``` - -will generate and run 50 binaries, each of which will execute up to -1500 instructions when run. The generated binaries, a Verilated model -and the output from running them can all be found in the directory -called `X`. - -### Run the smoke test - -A smoke test which exercises some functionality of OTBN can be found, together -with its expected outputs (in the form of final register values), in -`./hw/ip/otbn/dv/smoke`. The test can be run using a script. - -```sh -hw/ip/otbn/dv/smoke/run_smoke.sh -``` - -This will build the standalone simulation, build the smoke test binary, run it -and check the results are as expected. - -### Run the ISS on its own - -There are currently two versions of the ISS and they can be found in -`dv/otbnsim`. The easiest to use is `dv/otbnsim/standalone.py`. This -takes an OTBN binary as an ELF file (as produced by the standard -linker script for `otbn_ld.py`) and can dump the resulting DMEM if given -the `--dmem-dump` argument. To see an instruction trace, pass the -`--verbose` flag. - -There is also `dv/otbnsim/otbnsim.py`. This takes flat binary files -with the contents of IMEM and DMEM and, when finished, generates a -cycle count and dumps DMEM contents. This is used to implement the -model inside of simulation, but is probably not very convenient for -command-line use otherwise. - -## Test the ISS - -The ISS has a simple test suite, which runs various instructions and -makes sure they behave as expected. You can find the tests in -`dv/otbnsim/test` and can run them with `make -C dv/otbnsim test`. diff --git a/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson b/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson deleted file mode 100644 index 5ed991ca6b5..00000000000 --- a/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - // Additional build-time options needed to compile C++ sources in - // simulators such as VCS and Xcelium for anything that uses - // otbn_memutil. - // In addition to the build options here the user also must include the - // hw/dv/verilator/memutil_dpi_scrambled_opts.hjson file. - otbn_memutil_core: "lowrisc:dv:otbn_memutil:0" - otbn_memutil_src_dir: "{eval_cmd} echo \"{otbn_memutil_core}\" | tr ':' '_'" - - build_modes: [ - { - name: vcs_otbn_memutil_build_opts - build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{otbn_memutil_src_dir}"] - } - - { - name: xcelium_otbn_memutil_build_opts - build_opts: ["-I{build_dir}/fusesoc-work/src/{otbn_memutil_src_dir}"] - } - - { - name: dsim_otbn_memutil_build_opts - build_opts: ["-c-opts -I{build_dir}/fusesoc-work/src/{otbn_memutil_src_dir}"] - } - ] -} diff --git a/hw/ip/otbn/dv/model/otbn_model.core b/hw/ip/otbn/dv/model/otbn_model.core deleted file mode 100644 index 3cbd27957ca..00000000000 --- a/hw/ip/otbn/dv/model/otbn_model.core +++ /dev/null @@ -1,35 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_model:0.1" -description: "OpenTitan Big Number Accelerator (OTBN)" - -filesets: - files_model: - depend: - - lowrisc:ip:otbn_pkg - - lowrisc:dv_verilator:memutil_dpi - - lowrisc:dv:otbn_memutil - - lowrisc:ip:otbn_tracer - files: - - otbn_model.cc: { file_type: cppSource } - - otbn_model.h: { file_type: cppSource, is_include_file: true } - - otbn_model_dpi.h: { file_type: cppSource, is_include_file: true } - - otbn_model_dpi.svh: { is_include_file: true } - - iss_wrapper.cc: { file_type: cppSource } - - iss_wrapper.h: { file_type: cppSource, is_include_file: true } - - otbn_trace_checker.h: { file_type: cppSource, is_include_file: true } - - otbn_trace_checker.cc: { file_type: cppSource } - - otbn_trace_entry.h: { file_type: cppSource, is_include_file: true } - - otbn_trace_entry.cc: { file_type: cppSource } - - otbn_core_model.sv - - otbn_rf_snooper_if.sv - - otbn_stack_snooper_if.sv - file_type: systemVerilogSource - -targets: - default: - filesets: - - files_model - toplevel: otbn_core_model diff --git a/hw/ip/otbn/dv/model/otbn_model_dpi.h b/hw/ip/otbn/dv/model/otbn_model_dpi.h deleted file mode 100644 index 93a4c93585c..00000000000 --- a/hw/ip/otbn/dv/model/otbn_model_dpi.h +++ /dev/null @@ -1,150 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_MODEL_DPI_H_ -#define OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_MODEL_DPI_H_ - -// The DPI exports for OtbnModel. See also otbn_model_dpi.svh, where -// they are declared for the SystemVerilog side. -// -// These are defined in a separate file from otbn_model.h because otherwise -// something like otbn_top_sim.cc will see both these defines and the -// auto-generated ones that Verilator produces in e.g. Votbn_top_sim__Dpi.h. The -// latter use void* for all the chandle arguments and some versions of GCC treat -// the resulting signatures as incompatible. - -extern "C" { - -// Create an OtbnModel object. Will always succeed. -OtbnModel *otbn_model_init(const char *mem_scope, const char *design_scope); - -// Delete an OtbnModel -void otbn_model_destroy(OtbnModel *model); - -// Take loop warps from an OtbnMemUtil -void otbn_take_loop_warps(OtbnModel *model, OtbnMemUtil *memutil); - -// Returns non-zero if an OtbnMemUtil contains loop warps -int otbn_has_loop_warps(OtbnMemUtil *memutil); - -// Flush URND and RND EDN data from model because of edn_rst_n signal. Returns -// 0 on success; -1 on error. -int otbn_model_edn_flush(OtbnModel *model); - -// Call edn_rnd_step function of OtbnModel. Returns 0 on success; -1 on error. -int otbn_model_edn_rnd_step(OtbnModel *model, - svLogicVecVal *edn_rnd_data /* logic [31:0] */, - unsigned char fips_err); - -// Call edn_urnd_step function of OtbnModel. Returns 0 on success; -1 on error. -int otbn_model_edn_urnd_step(OtbnModel *model, - svLogicVecVal *edn_urnd_data /* logic [31:0] */); - -// Signal RTL is finished processing RND data to Model. Returns 0 on success; -// -1 on error. -int otbn_model_rnd_cdc_done(OtbnModel *model); - -// Signal RTL is finished processing EDN data for URND to Model. Returns 0 on -// success; -1 on error. -int otbn_model_urnd_cdc_done(OtbnModel *model); - -// Signal RTL is finished processing OTP key to the Model. Returns 0 on -// success; -1 on error. -int otbn_model_otp_key_cdc_done(OtbnModel *model); - -// Pass keymgr data to model. Returns 0 on success; -1 on error. -int otbn_model_set_keymgr_value(OtbnModel *model, svLogicVecVal *key0, - svLogicVecVal *key1, unsigned char valid); - -// The main entry point to the OTBN model, exported from here and used in -// otbn_core_model.sv. -// -// This communicates state with otbn_core_model.sv through the model_state -// parameter, which has the following bits: -// -// Bit 0: running True if the model is currently running -// Bit 1: check_due True if the model finished running last cycle -// Bit 2: failed_step Something failed when trying to start/step ISS -// -// The otbn_model_step function should only be called when either the model is -// running (bit 0 of model_state), has a check due (bit 1 of model_state), or -// when start is asserted. At other times, it will return immediately (but -// wastes a DPI call). -// -// If the model is running and start is false, otbn_model_step steps the ISS by -// a single cycle. If something goes wrong, it will set failed_step to true and -// running to false. Otherwise, it writes the new value of otbn.INSN_CNT to -// *insn_cnt. -// -// If nothing goes wrong and the ISS finishes its run, we set running to false, -// write out err_bits and stop_pc and set check_due to ensure otbn_model_check -// runs on the next negedge of the clock. -// -unsigned otbn_model_step(OtbnModel *model, unsigned model_state, - svBitVecVal *cmd /* bit [7:0] */, - svBitVecVal *status /* bit [7:0] */, - svBitVecVal *insn_cnt /* bit [31:0] */, - svBitVecVal *rnd_req /* bit [0:0] */, - svBitVecVal *err_bits /* bit [31:0] */, - svBitVecVal *stop_pc /* bit [31:0] */); - -// This gets run if the otbn_model_step function sets the check_due bit in its -// model_state bitfield (see above). If the model's design_scope is non-empty, -// it should be the scope of an RTL implementation. In that case, we compare -// register and memory contents with that implementation, printing to stderr -// and setting the failed_cmp bit if there are any mismatches. If the model's -// design_scope is the empty string, we grab the contents of DMEM from the ISS -// and inject them into the simulation memory. -// -// Returns 1 on success; 0 on failure. -int otbn_model_check(OtbnModel *model, svBitVecVal *mismatch /* bit [0:0] */); - -// Tell the model to mark all of IMEM as invalid so that any fetch causes an -// integrity error. Returns 0 on success or -1 on failure. -int otbn_model_invalidate_imem(OtbnModel *model); - -// Tell the model to mark all of DMEM as invalid so that any load causes an -// integrity error. Returns 0 on success or -1 on failure. -int otbn_model_invalidate_dmem(OtbnModel *model); - -// Tell the model to set software_errs_fatal bit in ctrl register. Once this bit -// is set, any software error will be elevated to fatal error from recoverable -// error. -int otbn_model_set_software_errs_fatal(OtbnModel *model, unsigned char new_val); - -// Tell the model to not execute checks to see if secure wiping has written -// random data to all registers before wiping them with zeroes. -int otbn_set_no_sec_wipe_chk(OtbnModel *model); - -// Disable stack integrity checks -int otbn_disable_stack_check(OtbnModel *model); - -// Step the CRC calculation for item -// -// state is an inout parameter and should be updated in-place. This is -// a "pure" function: there isn't actually any model state that gets -// updated by calling it. Returns 0 on success or -1 on failure. -int otbn_model_step_crc(OtbnModel *model, svBitVecVal *item /* bit [47:0] */, - svBitVecVal *state /* inout bit [31:0] */); - -// Flush any information in the model. Returns 0 on success; -1 on error. -int otbn_model_reset(OtbnModel *model, svBitVecVal *status /* bit [7:0] */, - svBitVecVal *insn_cnt /* bit [31:0] */, - svBitVecVal *rnd_req /* bit [0:0] */, - svBitVecVal *err_bits /* bit [31:0] */, - svBitVecVal *stop_pc /* bit [31:0] */); - -// React to an error escalation. Returns 0 on success or -1 on failure. -int otbn_model_send_err_escalation(OtbnModel *model, - svBitVecVal *err_val /* bit [31:0] */, - svBit lock_immediately); - -// Send an RMA request value to the model -int otbn_model_set_rma_req(OtbnModel *model, - svBitVecVal *rma_req /* bit [3:0] */); - -// Trigger initial secure wipe. -int otbn_model_initial_secure_wipe(OtbnModel *model); -} - -#endif // OPENTITAN_HW_IP_OTBN_DV_MODEL_OTBN_MODEL_DPI_H_ diff --git a/hw/ip/otbn/dv/rig/rig/__init__.py b/hw/ip/otbn/dv/rig/rig/__init__.py deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/hw/ip/otbn/dv/rig/rig/gens/__init__.py b/hw/ip/otbn/dv/rig/rig/gens/__init__.py deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/hw/ip/otbn/dv/tracer/cpp/otbn_trace_source.cc b/hw/ip/otbn/dv/tracer/cpp/otbn_trace_source.cc deleted file mode 100644 index c8d13287e13..00000000000 --- a/hw/ip/otbn/dv/tracer/cpp/otbn_trace_source.cc +++ /dev/null @@ -1,41 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "otbn_trace_source.h" - -#include -#include -#include - -static std::unique_ptr trace_source; - -OtbnTraceSource &OtbnTraceSource::get() { - if (!trace_source) { - trace_source.reset(new OtbnTraceSource()); - } - return *trace_source; -} - -void OtbnTraceSource::AddListener(OtbnTraceListener *listener) { - listeners_.push_back(listener); -} - -void OtbnTraceSource::RemoveListener(const OtbnTraceListener *listener) { - auto it = std::find(listeners_.begin(), listeners_.end(), listener); - assert(it != listeners_.end()); - listeners_.erase(it); -} - -void OtbnTraceSource::Broadcast(const std::string &trace, - unsigned cycle_count) { - for (OtbnTraceListener *listener : listeners_) { - listener->AcceptTraceString(trace, cycle_count); - } -} - -extern "C" void accept_otbn_trace_string(const char *trace, - unsigned int cycle_count) { - assert(trace != nullptr); - OtbnTraceSource::get().Broadcast(trace, cycle_count); -} diff --git a/hw/ip/otbn/dv/tracer/lint/otbn_tracer_waivers.vlt b/hw/ip/otbn/dv/tracer/lint/otbn_tracer_waivers.vlt deleted file mode 100644 index 051f71555b7..00000000000 --- a/hw/ip/otbn/dv/tracer/lint/otbn_tracer_waivers.vlt +++ /dev/null @@ -1,15 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`verilator_config - -lint_off -rule BLKSEQ -file "*/otbn_tracer.sv" -match "*Blocking assignments (=) in sequential (flop or latch) block*" - -// Flag ISPR (3) has its own trace signals due to special handling -lint_off -rule UNDRIVEN -file "*/otbn_trace_if.sv" -match "*Bits of signal are not driven: 'ispr_*'[3]*" - -lint_off -rule UNUSED -file "*/otbn_trace_if.sv" -match "*Bits of signal are not used: 'dmem_addr_o'*" -lint_off -rule UNUSED -file "*/otbn_trace_if.sv" -match "*Bits of signal are not used: 'insn_dec_shared'*" -lint_off -rule UNUSED -file "*/otbn_trace_if.sv" -match "*Bits of signal are not used: 'insn_dec_bignum'*" -lint_off -rule UNUSED -file "*/otbn_trace_if.sv" -match "*Bits of signal are not used: 'alu_bignum_operation'*" diff --git a/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson b/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson deleted file mode 100644 index ca1bd49bbc0..00000000000 --- a/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - // Additional build-time options needed to compile C++ sources in - // simulators such as VCS and Xcelium for anything that uses - // otbn_tracer. - otbn_tracer_inc_dir: "{build_dir}/fusesoc-work/src/lowrisc_ip_otbn_tracer_0/cpp" - - build_modes: [ - { - name: vcs_otbn_tracer_build_opts - build_opts: ["-CFLAGS -I{otbn_tracer_inc_dir}"] - } - { - name: xcelium_otbn_tracer_build_opts - build_opts: ["-I{otbn_tracer_inc_dir}"] - } - { - name: dsim_otbn_tracer_build_opts - build_opts: ["-c-opts -I{otbn_tracer_inc_dir}"] - } - ] -} diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env.core b/hw/ip/otbn/dv/uvm/env/otbn_env.core deleted file mode 100644 index ddbd3a64515..00000000000 --- a/hw/ip/otbn/dv/uvm/env/otbn_env.core +++ /dev/null @@ -1,86 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Copyright zeroRISC Inc. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_env:0.1" -description: "OTBN DV UVM environment" -filesets: - files_dv: - depend: - - lowrisc:dv:otbn_pqc_env_pkg - - lowrisc:ip:otbn - - lowrisc:dv:ralgen - - lowrisc:dv:cip_lib - - lowrisc:dv:dv_lib - - lowrisc:dv:sram_ctrl_bkdr_util - - lowrisc:dv:otbn_app_agent:0.1 - - lowrisc:dv:tl_agent - - lowrisc:dv:alert_esc_agent - - lowrisc:dv:otbn_model_agent - - lowrisc:dv:key_sideload_agent - files: - - otbn_env_pkg.sv - - otbn_loop_if.sv - - otbn_alu_bignum_if.sv - - otbn_controller_if.sv - - otbn_mac_bignum_if.sv - - otbn_rf_base_if.sv - - otbn_insn_cnt_if.sv - - otbn_rnd_if.sv - - otbn_escalate_if.sv - - otbn_ssctrl_if.sv - - otbn_trace_item.sv: {is_include_file: true} - - otbn_trace_monitor.sv: {is_include_file: true} - - otbn_env_cfg.sv: {is_include_file: true} - - otbn_env_cov.sv: {is_include_file: true} - - otbn_virtual_sequencer.sv: {is_include_file: true} - - otbn_scoreboard.sv: {is_include_file: true} - - otbn_env.sv: {is_include_file: true} - - otbn_test_helpers.cc: {file_type: cppSource} - - seq_lib/otbn_vseq_list.sv: {is_include_file: true} - - seq_lib/otbn_base_vseq.sv: {is_include_file: true} - - seq_lib/otbn_common_vseq.sv: {is_include_file: true} - - seq_lib/otbn_multi_vseq.sv: {is_include_file: true} - - seq_lib/otbn_reset_vseq.sv: {is_include_file: true} - - seq_lib/otbn_sequential_vseq.sv: {is_include_file: true} - - seq_lib/otbn_imem_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_dmem_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_single_vseq.sv: {is_include_file: true} - - seq_lib/otbn_smoke_vseq.sv: {is_include_file: true} - - seq_lib/otbn_stress_all_vseq.sv: {is_include_file: true} - - seq_lib/otbn_escalate_vseq.sv: {is_include_file: true} - - seq_lib/otbn_zero_state_err_urnd_vseq.sv: {is_include_file: true} - - seq_lib/otbn_illegal_mem_acc_vseq.sv: {is_include_file: true} - - seq_lib/otbn_rnd_sec_cm_vseq.sv: {is_include_file: true} - - seq_lib/otbn_sw_errs_fatal_chk_vseq.sv: {is_include_file: true} - - seq_lib/otbn_intg_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_alu_bignum_mod_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_controller_ispr_rdata_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_mac_bignum_acc_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_rf_base_intg_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_rf_bignum_intg_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_pc_ctrl_flow_redun_vseq.sv: {is_include_file: true} - - seq_lib/otbn_ctrl_redun_vseq.sv: {is_include_file: true} - - seq_lib/otbn_sec_wipe_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_urnd_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_sw_no_acc_vseq.sv: {is_include_file: true} - - seq_lib/otbn_mem_gnt_acc_err_vseq.sv: {is_include_file: true} - - seq_lib/otbn_stack_addr_integ_chk_vseq.sv: {is_include_file: true} - - seq_lib/otbn_partial_wipe_vseq.sv: {is_include_file: true} - file_type: systemVerilogSource - -generate: - ral: - generator: ralgen - parameters: - name: otbn - ip_hjson: ../../../data/otbn.hjson - position: prepend - -targets: - default: - filesets: - - files_dv - generate: - - ral diff --git a/hw/ip/otbn/dv/uvm/env/otbn_virtual_sequencer.sv b/hw/ip/otbn/dv/uvm/env/otbn_virtual_sequencer.sv deleted file mode 100644 index 30add775aa4..00000000000 --- a/hw/ip/otbn/dv/uvm/env/otbn_virtual_sequencer.sv +++ /dev/null @@ -1,16 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Copyright zeroRISC Inc. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -class otbn_virtual_sequencer extends cip_base_virtual_sequencer #( - .CFG_T(otbn_env_cfg), - .COV_T(otbn_env_cov) - ); - `uvm_component_utils(otbn_virtual_sequencer) - `uvm_component_new - - key_sideload_sequencer#(keymgr_pkg::otbn_key_req_t) key_sideload_sequencer_h; - otbn_app_sequencer otbn_app_sequencer_h; - -endclass diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_vseq_list.sv b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_vseq_list.sv deleted file mode 100644 index 7b05228f686..00000000000 --- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_vseq_list.sv +++ /dev/null @@ -1,33 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`include "otbn_base_vseq.sv" -`include "otbn_common_vseq.sv" -`include "otbn_multi_vseq.sv" -`include "otbn_reset_vseq.sv" -`include "otbn_sequential_vseq.sv" -`include "otbn_single_vseq.sv" -`include "otbn_smoke_vseq.sv" -`include "otbn_imem_err_vseq.sv" -`include "otbn_dmem_err_vseq.sv" -`include "otbn_stress_all_vseq.sv" -`include "otbn_escalate_vseq.sv" -`include "otbn_zero_state_err_urnd_vseq.sv" -`include "otbn_illegal_mem_acc_vseq.sv" -`include "otbn_sw_errs_fatal_chk_vseq.sv" -`include "otbn_intg_err_vseq.sv" -`include "otbn_alu_bignum_mod_err_vseq.sv" -`include "otbn_controller_ispr_rdata_err_vseq.sv" -`include "otbn_mac_bignum_acc_err_vseq.sv" -`include "otbn_rf_base_intg_err_vseq.sv" -`include "otbn_rf_bignum_intg_err_vseq.sv" -`include "otbn_pc_ctrl_flow_redun_vseq.sv" -`include "otbn_rnd_sec_cm_vseq.sv" -`include "otbn_ctrl_redun_vseq.sv" -`include "otbn_sec_wipe_err_vseq.sv" -`include "otbn_urnd_err_vseq.sv" -`include "otbn_sw_no_acc_vseq.sv" -`include "otbn_mem_gnt_acc_err_vseq.sv" -`include "otbn_stack_addr_integ_chk_vseq.sv" -`include "otbn_partial_wipe_vseq.sv" diff --git a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent.core b/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent.core deleted file mode 100644 index d06930e995f..00000000000 --- a/hw/ip/otbn/dv/uvm/otbn_app_agent/otbn_app_agent.core +++ /dev/null @@ -1,31 +0,0 @@ -CAPI=2: -# Copyright zeroRISC Inc. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:otbn_app_agent:0.1" -description: "otbn_app DV UVM agent" -filesets: - files_dv: - depend: - - lowrisc:dv:dv_utils - - lowrisc:dv:dv_lib - - lowrisc:ip:keymgr_pkg - - lowrisc:ip:kmac_pkg - - lowrisc:dv:kmac_app_agent:0.1 - files: - - otbn_app_agent_pkg.sv - - otbn_app_intf.sv - - otbn_app_item.sv: {is_include_file: true} - - otbn_app_agent_cfg.sv: {is_include_file: true} - - otbn_app_sequencer.sv: {is_include_file: true} - - otbn_app_base_seq.sv: {is_include_file: true} - - otbn_app_agent_cov.sv: {is_include_file: true} - - otbn_app_driver.sv: {is_include_file: true} - - otbn_app_monitor.sv: {is_include_file: true} - - otbn_app_agent.sv: {is_include_file: true} - file_type: systemVerilogSource - -targets: - default: - filesets: - - files_dv diff --git a/hw/ip/otbn/dv/uvm/otbn_base_sim_cfg.hjson b/hw/ip/otbn/dv/uvm/otbn_base_sim_cfg.hjson deleted file mode 100644 index 1482df39743..00000000000 --- a/hw/ip/otbn/dv/uvm/otbn_base_sim_cfg.hjson +++ /dev/null @@ -1,409 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Copyright zeroRISC Inc. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ -// Name of the sim cfg - typically same as the name of the DUT. -name: - otbn - - // Top level dut name (sv module). - dut: otbn - - // Top level testbench name (sv module). - tb: tb - - // Simulator used to sign off this block - tool: xcelium - - otbn_dir: "{proj_root}/hw/ip/otbn" - - // Testplan hjson file. - testplan: "{otbn_dir}/data/otbn_testplan.hjson" - - exports: [ - { REPO_TOP: "{proj_root}" }, - ] - - // Import additional common sim cfg files. - import_cfgs: [ - // Project wide common sim cfg file - "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", - // Config files to get the correct flags for otbn_memutil and otbn_tracer - "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson", - "{otbn_dir}/dv/memutil/otbn_memutil_sim_opts.hjson", - "{otbn_dir}/dv/tracer/otbn_tracer_sim_opts.hjson", - // Common CIP test lists - "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", - "{proj_root}/hw/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson" - ] - - // Add options needed to compile against otbn_memutil, otbn_tracer, and - // memutil_dpi_scrambled. - en_build_modes: ["{tool}_otbn_memutil_build_opts", - "{tool}_otbn_tracer_build_opts", - "{tool}_memutil_dpi_scrambled_build_opts"] - - // Add additional tops for simulation. - sim_tops: ["otbn_bind", "sec_cm_prim_sparse_fsm_flop_bind", "sec_cm_prim_onehot_check_bind", - "sec_cm_prim_count_bind"] - - // Default iterations for all tests - each test entry can override this. - reseed: 50 - - // Default UVM test and seq class name. - uvm_test: otbn_base_test - uvm_test_seq: otbn_base_vseq - - // The default place to find and build ELF binaries. If you have - // some pre-built binaries, you can run the simulation with them by using - // --run-opts to override the otbn_elf_dir plusarg in run_opts. - otbn_elf_dir: "{run_dir}/otbn-binaries" - - - // TODO(lowrisc/opentitan#16689): Enable cdc instrumentation - run_opts: ["+otbn_elf_dir={otbn_elf_dir}", - "+cdc_instrumentation_enabled=0"] - - // The default build mode, used for the tests explicitly listed below does not - // require any pre-build steps. - build_modes: [ - { - name: default - pre_build_cmds: [] - } - ] - - // The value to pass to the --size parameter for gen-binaries.py. This - // controls the number of instructions that are run before ECALL or error. - binary_size: 2000 - - // This runs bazel to locate the RV32 toolchain, needed by gen-binaries.py. - setup_env: "pushd {proj_root}; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd;" - gen_binaries_py: "{setup_env} {otbn_dir}/dv/uvm/gen-binaries.py" - - rnd_args: "--seed {seed} --size {binary_size} --pqc {pqc_enable}" - gen_fixed: "{gen_binaries_py}" - gen_rnd: "{gen_binaries_py} {rnd_args}" - - multi_err_dir: "{otbn_dir}/dv/otbnsim/test/simple/multi" - - run_modes: [ - // Run the random instruction generator and build the one resulting binary - // in {otbn_elf_dir}. If you override the otbn_elf_dir plusarg with - // --run-opts, we'll still build the binary (but will ignore it). - { - name: build_otbn_rig_binary_mode - pre_run_cmds: [ - "{gen_rnd} --count 1 {otbn_elf_dir}" - ] - } - - // Run the random instruction generator in a "safe mode" and build - // resulting binary in {otbn_elf_dir}. Other than the choice of - // RIG config, this the same as build_otbn_rig_binary_mode. - { - name: build_otbn_rig_safe_binary_mode - pre_run_cmds: [ - "{gen_rnd} --count 1 {otbn_elf_dir} --config safe" - ] - } - - // Run the random instruction generator several times and build the - // resulting binaries in {otbn_elf_dir}. - { - name: build_otbn_rig_binaries_mode - pre_run_cmds: [ - "{gen_rnd} --count 10 {otbn_elf_dir}" - ] - } - - // Build the smoke test in {otbn_elf_dir}. - { - name: build_otbn_smoke_binary_mode - pre_run_cmds: [ - "{gen_fixed} --src-dir {smoke_dir} {otbn_elf_dir}" - ] - } - - // Build the multi-error tests in {otbn_elf_dir}. - { - name: build_otbn_multi_err_binaries_mode - pre_run_cmds: [ - "{gen_fixed} --src-dir {multi_err_dir} {otbn_elf_dir}" - ] - } - ] - - // List of test specifications. - tests: [ - { - name: "otbn_smoke" - uvm_test_seq: "otbn_smoke_vseq" - en_run_modes: ["build_otbn_smoke_binary_mode"] - // Run just one smoke test: it's a fixed binary and there's not much - // interaction with the environment so there's probably not much point - // in running it loads of times. - reseed: 1 - } - - { - name: "otbn_single" - uvm_test_seq: "otbn_single_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 100 - } - - // This test runs 10 binaries each time, so we give it a reseed value - // that's much less than for otbn_single: these tests should equally good - // at catching errors within a single run, so the coverage that they give - // is specifically to do with improper clearing of state when starting or - // ending an operation. - { - name: "otbn_multi" - uvm_test_seq: "otbn_multi_vseq" - en_run_modes: ["build_otbn_rig_binaries_mode"] - reseed: 10 - } - - // This test asserts reset somewhere in the middle of an operation. It is - // good for flushing out testbench bugs that are triggered on a reset, but - // it will also catch incorrect initialisation of state and hit some - // FSM/toggle coverage points that need a reset. - { - name: "otbn_reset" - uvm_test_seq: "otbn_reset_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 10 - } - - // This test runs a fixed set of binaries, one after the other. Since this - // is essentially a directed test, there's probably no real benefit to - // running it more than once. - { - name: "otbn_multi_err" - uvm_test_seq: "otbn_sequential_vseq" - en_run_modes: ["build_otbn_multi_err_binaries_mode"] - reseed: 1 - } - - // This test causes a fault in the middle of an execution by triggering an - // IMEM error. We run it several times because (historically) some of the - // bugs it has found have been depended on unfortunate timing coincidences, - // so we want to have a chance of seeing them. - { - name: "otbn_imem_err" - uvm_test_seq: "otbn_imem_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 10 - } - - // This test causes a fault in the middle of an execution by triggering an - // DMEM error. As with the IMEM case, we want a reasonable number of - // reseeds to see awkward timing corners. Also, there's a possibility of an - // otbn_dmem_err test not actually generating an error (if we don't load - // from DMEM after invalidating it), so we bump things up slightly further - // to correct for that. - { - name: "otbn_dmem_err" - uvm_test_seq: "otbn_dmem_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 15 - } - - // This test sets the lc_escalate_en_i and lc_rma_req_i signals somewhere in - // the middle of an operation and makes sure that we see an alert. There's - // not much interesting that can happen here, so a small number of seeds should - // suffice. - { - name: "otbn_escalate" - uvm_test_seq: "otbn_escalate_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 60 - } - - { - name: "otbn_alu_bignum_mod_err" - uvm_test_seq: "otbn_alu_bignum_mod_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - - { - name: "otbn_controller_ispr_rdata_err" - uvm_test_seq: "otbn_controller_ispr_rdata_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - - { - name: "otbn_mac_bignum_acc_err" - uvm_test_seq: "otbn_mac_bignum_acc_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - - { - name: "otbn_rf_bignum_intg_err" - uvm_test_seq: "otbn_rf_bignum_intg_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 10 - } - - { - name: "otbn_rf_base_intg_err" - uvm_test_seq: "otbn_rf_base_intg_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 10 - } - - // This test runs several sequences back-to-back. Unlike otbn_multi, these - // sequences can include imem or dmem error sequences. We shouldn't need - // many seeds here because each test runs several operations. - { - name: "otbn_stress_all" - uvm_test_seq: "otbn_stress_all_vseq" - en_run_modes: ["build_otbn_rig_binaries_mode"] - reseed: 10 - } - - // A combination of otbn_stress_all and otbn_reset. - { - name: "otbn_stress_all_with_rand_reset" - en_run_modes: ["build_otbn_rig_binaries_mode"] - reseed: 10 - } - { - name: "otbn_zero_state_err_urnd" - uvm_test_seq: "otbn_zero_state_err_urnd_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - { - name: "otbn_illegal_mem_acc" - uvm_test_seq: "otbn_illegal_mem_acc_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - { - name: "otbn_sw_errs_fatal_chk" - uvm_test_seq: "otbn_sw_errs_fatal_chk_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 10 - } - { - name: "otbn_pc_ctrl_flow_redun" - uvm_test_seq: "otbn_pc_ctrl_flow_redun_vseq" - // Use a "safe" binary, in the hope that it will run for long - // enough that we can interrupt it with an error. - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - { - name: "otbn_rnd_sec_cm" - uvm_test_seq: "otbn_rnd_sec_cm_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - { - name: "otbn_ctrl_redun" - uvm_test_seq: "otbn_ctrl_redun_vseq" - en_run_modes: ["build_otbn_rig_safe_binary_mode"] - reseed: 12 - } - { - name: "otbn_sec_wipe_err" - uvm_test_seq: "otbn_sec_wipe_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 7 - } - { - name: "otbn_urnd_err" - uvm_test_seq: "otbn_urnd_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 2 - } - { - name: "otbn_sw_no_acc" - uvm_test_seq: "otbn_sw_no_acc_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - { - name: "otbn_mem_gnt_acc_err" - uvm_test_seq: "otbn_mem_gnt_acc_err_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 2 - } - { - name: "otbn_stack_addr_integ_chk" - uvm_test_seq: "otbn_stack_addr_integ_chk_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 5 - } - { - name: "otbn_partial_wipe" - uvm_test_seq: "otbn_partial_wipe_vseq" - en_run_modes: ["build_otbn_rig_binary_mode"] - reseed: 10 - } - ] - - // List of regressions. - regressions: [ - { - name: smoke - tests: ["otbn_smoke"] - } - - { - name: "core" - tests: [ - "otbn_smoke", "otbn_single", "otbn_multi", "otbn_reset", - "otbn_multi_err", "otbn_imem_err", "otbn_dmem_err", - "otbn_stress_all", "otbn_escalate", "otbn_illegal_mem_acc", - "otbn_zero_state_err_urnd", "otbn_sw_errs_fatal_chk", - "otbn_rnd_sec_cm", "otbn_mac_bignum_acc_err", "otbn_rf_base_intg_err", - "otbn_controller_ispr_rdata_err", "otbn_alu_bignum_mod_err" - ] - - } - - { - name: "ci" - tests: [ - # V1 - "otbn_smoke", "otbn_single", "otbn_csr_hw_reset", "otbn_csr_rw", - "otbn_csr_bit_bash", "otbn_csr_aliasing", - "otbn_csr_mem_rw_with_rand_reset", - "otbn_mem_partial_access", - # V1 but known broken - # "otbn_mem_walk", - # V2 - "otbn_reset", "otbn_multi", "otbn_stress_all", - "otbn_zero_state_err_urnd", "otbn_sw_errs_fatal_chk", "otbn_alert_test", - "otbn_intr_test", "otbn_tl_errors", - "otbn_same_csr_outstanding" - # V2 but known broken - # "otbn_multi_err", "otbn_escalate", - # V2S - "otbn_imem_err", "otbn_dmem_err", "otbn_illegal_mem_acc", - "otbn_tl_intg_err", "otbn_sec_cm", "otbn_pc_ctrl_flow_redun", - "otbn_rnd_sec_cm", "otbn_alu_bignum_mod_err", - "otbn_controller_ispr_rdata_err", "otbn_mac_bignum_acc_err", - "otbn_rf_base_intg_err", - "otbn_sec_wipe_err", "otbn_urnd_err", - # V2S but known broken - # "otbn_passthru_mem_tl_intg_err", - # V3 thus not yet active - # "otbn_stress_all_with_rand_reset", - ] - } - ] -} diff --git a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent_pkg.sv b/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent_pkg.sv deleted file mode 100644 index d6eda0c9f12..00000000000 --- a/hw/ip/otbn/dv/uvm/otbn_model_agent/otbn_model_agent_pkg.sv +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -package otbn_model_agent_pkg; - // dep packages - import uvm_pkg::*; - import dv_utils_pkg::*; - import dv_lib_pkg::*; - - import "DPI-C" function bit - otbn_trace_checker_pop_iss_insn(output bit [31:0] insn_addr, output string mnemonic); - - typedef enum { - OtbnModelStatus, - OtbnModelInsn - } otbn_model_item_type_e; - - // macro includes - `include "uvm_macros.svh" - `include "dv_macros.svh" - - typedef otbn_model_item; - typedef otbn_model_agent_cfg; - // driver and sequencer are not used in this agent. Create these dummy components to avoid compile - // error due to the TLM connection between monitor and sequencer in dv_base_*. - // Both TLM fifo/port need to use the same item object (otbn_model_item) - typedef dv_base_sequencer #(otbn_model_item, otbn_model_agent_cfg) otbn_dummy_sequencer; - typedef dv_base_driver #(otbn_model_item, otbn_model_agent_cfg) otbn_dummy_driver; - - // package sources - `include "otbn_model_item.sv" - - `include "otbn_model_agent_cfg.sv" - `include "otbn_model_monitor.sv" - `include "otbn_model_agent.sv" - -endpackage: otbn_model_agent_pkg diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt b/hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt deleted file mode 100644 index f700ad73616..00000000000 --- a/hw/ip/otbn/dv/verilator/otbn_top_sim_waivers.vlt +++ /dev/null @@ -1,28 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -`verilator_config - -lint_off -rule WIDTH -file "*/otbn_top_sim.sv" -match "*'ImemStartAddr' generates 32 bits*" -lint_off -rule WIDTH -file "*/otbn_top_sim.sv" -match "*'stack_wr_ptr_q' generates 4 bits*" - -// Mark some signals in the loop controller as public. These are used -// by the OtbnTopApplyLoopWarp() function in otbn_top_sim.cc -public -module "otbn_loop_controller" -var "insn_addr_i" -public -module "otbn_loop_controller" -var "loop_start_req_i" -public -module "otbn_loop_controller" -var "loop_start_commit_i" -public -module "otbn_loop_controller" -var "loop_iterations_i" -public -module "otbn_loop_controller" -var "current_loop_valid" -public -module "otbn_loop_controller" -var "current_loop" -public -module "otbn_loop_controller" -var "current_loop_finish" -public -module "otbn_loop_controller" -var "loop_stack_rd_idx" -public -module "otbn_loop_controller" -var "prefetch_loop_iterations_o" -public -module "prim_count" -var "max_val" -public -module "prim_count" -var "down_cnt" -public -module "prim_flop" -var "d_i" - -// Mark the "model_handle" variable in the core model as public. We -// use this to pass the information from the ELF file to the ISS on -// the first call to OtbnTopApplyLoopWarp() in otbn_top_sim.cc. -public -module "otbn_core_model" -var "model_handle" diff --git a/hw/ip/otbn/rtl/otbn_reg_pkg.sv b/hw/ip/otbn/rtl/otbn_reg_pkg.sv deleted file mode 100644 index 775780e4991..00000000000 --- a/hw/ip/otbn/rtl/otbn_reg_pkg.sv +++ /dev/null @@ -1,354 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package otbn_reg_pkg; - - // Param list - parameter int NumAlerts = 2; - - // Address widths within the block - parameter int BlockAw = 17; - - // Number of registers for every interface - parameter int NumRegs = 11; - - // Alert indices - typedef enum int { - AlertFatalIdx = 0, - AlertRecovIdx = 1 - } otbn_alert_idx_t; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic q; - } otbn_reg2hw_intr_state_reg_t; - - typedef struct packed { - logic q; - } otbn_reg2hw_intr_enable_reg_t; - - typedef struct packed { - logic q; - logic qe; - } otbn_reg2hw_intr_test_reg_t; - - typedef struct packed { - struct packed { - logic q; - logic qe; - } recov; - struct packed { - logic q; - logic qe; - } fatal; - } otbn_reg2hw_alert_test_reg_t; - - typedef struct packed { - logic [7:0] q; - logic qe; - } otbn_reg2hw_cmd_reg_t; - - typedef struct packed { - logic q; - logic qe; - } otbn_reg2hw_ctrl_reg_t; - - typedef struct packed { - struct packed { - logic q; - logic qe; - } fatal_software; - struct packed { - logic q; - logic qe; - } lifecycle_escalation; - struct packed { - logic q; - logic qe; - } illegal_bus_access; - struct packed { - logic q; - logic qe; - } bad_internal_state; - struct packed { - logic q; - logic qe; - } bus_intg_violation; - struct packed { - logic q; - logic qe; - } reg_intg_violation; - struct packed { - logic q; - logic qe; - } dmem_intg_violation; - struct packed { - logic q; - logic qe; - } imem_intg_violation; - struct packed { - logic q; - logic qe; - } rnd_fips_chk_fail; - struct packed { - logic q; - logic qe; - } rnd_rep_chk_fail; - struct packed { - logic q; - logic qe; - } key_invalid; - struct packed { - logic q; - logic qe; - } loop; - struct packed { - logic q; - logic qe; - } illegal_insn; - struct packed { - logic q; - logic qe; - } call_stack; - struct packed { - logic q; - logic qe; - } bad_insn_addr; - struct packed { - logic q; - logic qe; - } bad_data_addr; - } otbn_reg2hw_err_bits_reg_t; - - typedef struct packed { - logic [31:0] q; - logic qe; - } otbn_reg2hw_insn_cnt_reg_t; - - typedef struct packed { - logic [31:0] q; - logic qe; - } otbn_reg2hw_load_checksum_reg_t; - - typedef struct packed { - logic d; - logic de; - } otbn_hw2reg_intr_state_reg_t; - - typedef struct packed { - logic d; - } otbn_hw2reg_ctrl_reg_t; - - typedef struct packed { - logic [7:0] d; - logic de; - } otbn_hw2reg_status_reg_t; - - typedef struct packed { - struct packed { - logic d; - } fatal_software; - struct packed { - logic d; - } lifecycle_escalation; - struct packed { - logic d; - } illegal_bus_access; - struct packed { - logic d; - } bad_internal_state; - struct packed { - logic d; - } bus_intg_violation; - struct packed { - logic d; - } reg_intg_violation; - struct packed { - logic d; - } dmem_intg_violation; - struct packed { - logic d; - } imem_intg_violation; - struct packed { - logic d; - } rnd_fips_chk_fail; - struct packed { - logic d; - } rnd_rep_chk_fail; - struct packed { - logic d; - } key_invalid; - struct packed { - logic d; - } loop; - struct packed { - logic d; - } illegal_insn; - struct packed { - logic d; - } call_stack; - struct packed { - logic d; - } bad_insn_addr; - struct packed { - logic d; - } bad_data_addr; - } otbn_hw2reg_err_bits_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } fatal_software; - struct packed { - logic d; - logic de; - } lifecycle_escalation; - struct packed { - logic d; - logic de; - } illegal_bus_access; - struct packed { - logic d; - logic de; - } bad_internal_state; - struct packed { - logic d; - logic de; - } bus_intg_violation; - struct packed { - logic d; - logic de; - } reg_intg_violation; - struct packed { - logic d; - logic de; - } dmem_intg_violation; - struct packed { - logic d; - logic de; - } imem_intg_violation; - } otbn_hw2reg_fatal_alert_cause_reg_t; - - typedef struct packed { - logic [31:0] d; - } otbn_hw2reg_insn_cnt_reg_t; - - typedef struct packed { - logic [31:0] d; - } otbn_hw2reg_load_checksum_reg_t; - - // Register -> HW type - typedef struct packed { - otbn_reg2hw_intr_state_reg_t intr_state; // [116:116] - otbn_reg2hw_intr_enable_reg_t intr_enable; // [115:115] - otbn_reg2hw_intr_test_reg_t intr_test; // [114:113] - otbn_reg2hw_alert_test_reg_t alert_test; // [112:109] - otbn_reg2hw_cmd_reg_t cmd; // [108:100] - otbn_reg2hw_ctrl_reg_t ctrl; // [99:98] - otbn_reg2hw_err_bits_reg_t err_bits; // [97:66] - otbn_reg2hw_insn_cnt_reg_t insn_cnt; // [65:33] - otbn_reg2hw_load_checksum_reg_t load_checksum; // [32:0] - } otbn_reg2hw_t; - - // HW -> register type - typedef struct packed { - otbn_hw2reg_intr_state_reg_t intr_state; // [107:106] - otbn_hw2reg_ctrl_reg_t ctrl; // [105:105] - otbn_hw2reg_status_reg_t status; // [104:96] - otbn_hw2reg_err_bits_reg_t err_bits; // [95:80] - otbn_hw2reg_fatal_alert_cause_reg_t fatal_alert_cause; // [79:64] - otbn_hw2reg_insn_cnt_reg_t insn_cnt; // [63:32] - otbn_hw2reg_load_checksum_reg_t load_checksum; // [31:0] - } otbn_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] OTBN_INTR_STATE_OFFSET = 17'h 0; - parameter logic [BlockAw-1:0] OTBN_INTR_ENABLE_OFFSET = 17'h 4; - parameter logic [BlockAw-1:0] OTBN_INTR_TEST_OFFSET = 17'h 8; - parameter logic [BlockAw-1:0] OTBN_ALERT_TEST_OFFSET = 17'h c; - parameter logic [BlockAw-1:0] OTBN_CMD_OFFSET = 17'h 10; - parameter logic [BlockAw-1:0] OTBN_CTRL_OFFSET = 17'h 14; - parameter logic [BlockAw-1:0] OTBN_STATUS_OFFSET = 17'h 18; - parameter logic [BlockAw-1:0] OTBN_ERR_BITS_OFFSET = 17'h 1c; - parameter logic [BlockAw-1:0] OTBN_FATAL_ALERT_CAUSE_OFFSET = 17'h 20; - parameter logic [BlockAw-1:0] OTBN_INSN_CNT_OFFSET = 17'h 24; - parameter logic [BlockAw-1:0] OTBN_LOAD_CHECKSUM_OFFSET = 17'h 28; - - // Reset values for hwext registers and their fields - parameter logic [0:0] OTBN_INTR_TEST_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_INTR_TEST_DONE_RESVAL = 1'h 0; - parameter logic [1:0] OTBN_ALERT_TEST_RESVAL = 2'h 0; - parameter logic [0:0] OTBN_ALERT_TEST_FATAL_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ALERT_TEST_RECOV_RESVAL = 1'h 0; - parameter logic [7:0] OTBN_CMD_RESVAL = 8'h 0; - parameter logic [7:0] OTBN_CMD_CMD_RESVAL = 8'h 0; - parameter logic [0:0] OTBN_CTRL_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_CTRL_SOFTWARE_ERRS_FATAL_RESVAL = 1'h 0; - parameter logic [23:0] OTBN_ERR_BITS_RESVAL = 24'h 0; - parameter logic [0:0] OTBN_ERR_BITS_BAD_DATA_ADDR_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_BAD_INSN_ADDR_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_CALL_STACK_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_ILLEGAL_INSN_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_LOOP_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_KEY_INVALID_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_RND_REP_CHK_FAIL_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_RND_FIPS_CHK_FAIL_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_IMEM_INTG_VIOLATION_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_DMEM_INTG_VIOLATION_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_REG_INTG_VIOLATION_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_BUS_INTG_VIOLATION_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_BAD_INTERNAL_STATE_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_ILLEGAL_BUS_ACCESS_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_LIFECYCLE_ESCALATION_RESVAL = 1'h 0; - parameter logic [0:0] OTBN_ERR_BITS_FATAL_SOFTWARE_RESVAL = 1'h 0; - parameter logic [31:0] OTBN_INSN_CNT_RESVAL = 32'h 0; - parameter logic [31:0] OTBN_INSN_CNT_INSN_CNT_RESVAL = 32'h 0; - parameter logic [31:0] OTBN_LOAD_CHECKSUM_RESVAL = 32'h 0; - parameter logic [31:0] OTBN_LOAD_CHECKSUM_CHECKSUM_RESVAL = 32'h 0; - - // Window parameters - parameter logic [BlockAw-1:0] OTBN_IMEM_OFFSET = 17'h 8000; - parameter int unsigned OTBN_IMEM_SIZE = 'h 8000; - parameter int unsigned OTBN_IMEM_IDX = 0; - parameter logic [BlockAw-1:0] OTBN_DMEM_OFFSET = 17'h 18000; - parameter int unsigned OTBN_DMEM_SIZE = 'h 7c00; - parameter int unsigned OTBN_DMEM_IDX = 1; - - // Register index - typedef enum int { - OTBN_INTR_STATE, - OTBN_INTR_ENABLE, - OTBN_INTR_TEST, - OTBN_ALERT_TEST, - OTBN_CMD, - OTBN_CTRL, - OTBN_STATUS, - OTBN_ERR_BITS, - OTBN_FATAL_ALERT_CAUSE, - OTBN_INSN_CNT, - OTBN_LOAD_CHECKSUM - } otbn_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] OTBN_PERMIT [11] = '{ - 4'b 0001, // index[ 0] OTBN_INTR_STATE - 4'b 0001, // index[ 1] OTBN_INTR_ENABLE - 4'b 0001, // index[ 2] OTBN_INTR_TEST - 4'b 0001, // index[ 3] OTBN_ALERT_TEST - 4'b 0001, // index[ 4] OTBN_CMD - 4'b 0001, // index[ 5] OTBN_CTRL - 4'b 0001, // index[ 6] OTBN_STATUS - 4'b 0111, // index[ 7] OTBN_ERR_BITS - 4'b 0001, // index[ 8] OTBN_FATAL_ALERT_CAUSE - 4'b 1111, // index[ 9] OTBN_INSN_CNT - 4'b 1111 // index[10] OTBN_LOAD_CHECKSUM - }; - -endpackage diff --git a/hw/ip/otbn/util/BUILD b/hw/ip/otbn/util/BUILD deleted file mode 100644 index 81e68c1359c..00000000000 --- a/hw/ip/otbn/util/BUILD +++ /dev/null @@ -1,83 +0,0 @@ -# Copyright lowRISC contributors (OpenTitan project). -# Copyright zeroRISC Inc. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -load("@rules_python//python:defs.bzl", "py_binary") -load("@ot_python_deps//:requirements.bzl", "requirement") - -package(default_visibility = ["//visibility:public"]) - -py_binary( - name = "otbn_as", - srcs = ["otbn_as.py"], - deps = [ - "//hw/ip/otbn/util/shared:bit_ranges", - "//hw/ip/otbn/util/shared:encoding", - "//hw/ip/otbn/util/shared:insn_yaml", - "//hw/ip/otbn/util/shared:operand", - "//hw/ip/otbn/util/shared:toolchain", - ], -) - -py_binary( - name = "otbn_ld", - srcs = ["otbn_ld.py"], - deps = [ - "//hw/ip/otbn/util/shared:mem_layout", - "//hw/ip/otbn/util/shared:toolchain", - requirement("mako"), - ], -) - -py_binary( - name = "otbn_objdump", - srcs = ["otbn_objdump.py"], - deps = [ - "//hw/ip/otbn/util/shared:insn_yaml", - "//hw/ip/otbn/util/shared:toolchain", - ], -) - -py_binary( - name = "check_const_time", - srcs = ["check_const_time.py"], - deps = [ - "//hw/ip/otbn/util/shared:check", - "//hw/ip/otbn/util/shared:control_flow", - "//hw/ip/otbn/util/shared:decode", - "//hw/ip/otbn/util/shared:information_flow_analysis", - requirement("pyelftools"), - ], -) - -py_binary( - name = "get_instruction_count_range", - srcs = ["get_instruction_count_range.py"], - deps = [ - "//hw/ip/otbn/util/shared:decode", - "//hw/ip/otbn/util/shared:instruction_count_range", - ], -) - -py_binary( - name = "gen_instruction_count_header", - srcs = ["gen_instruction_count_header.py"], - deps = [ - "//hw/ip/otbn/util/shared:decode", - "//hw/ip/otbn/util/shared:instruction_count_range", - requirement("mako"), - requirement("pyelftools"), - ], -) - -py_binary( - name = "otbn_sim_test", - srcs = ["otbn_sim_test.py"], - deps = [ - "//hw/ip/otbn/util/shared:check", - "//hw/ip/otbn/util/shared:mem_layout", - "//hw/ip/otbn/util/shared:reg_dump", - requirement("pyelftools"), - ], -) diff --git a/hw/ip/otbn/util/docs/__init__.py b/hw/ip/otbn/util/docs/__init__.py deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv index 4c839ff314c..f9c6313cc77 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_pkg.sv @@ -91,15 +91,15 @@ package otp_ctrl_pkg; parameter int FlashKeyWidth = 128; parameter int SramKeyWidth = 128; parameter int SramNonceWidth = 128; - parameter int OtbnKeyWidth = 128; - parameter int OtbnNonceWidth = 64; + parameter int AccKeyWidth = 128; + parameter int AccNonceWidth = 64; typedef logic [SramKeyWidth-1:0] sram_key_t; typedef logic [SramNonceWidth-1:0] sram_nonce_t; - typedef logic [OtbnKeyWidth-1:0] otbn_key_t; - typedef logic [OtbnNonceWidth-1:0] otbn_nonce_t; + typedef logic [AccKeyWidth-1:0] acc_key_t; + typedef logic [AccNonceWidth-1:0] acc_nonce_t; - localparam int OtbnNonceSel = OtbnNonceWidth / ScrmblBlockWidth; + localparam int AccNonceSel = AccNonceWidth / ScrmblBlockWidth; localparam int FlashNonceSel = FlashKeyWidth / ScrmblBlockWidth; localparam int SramNonceSel = SramNonceWidth / ScrmblBlockWidth; @@ -136,7 +136,7 @@ package otp_ctrl_pkg; typedef struct packed { logic req; // Requests ephemeral scrambling key and nonce. - } otbn_otp_key_req_t; + } acc_otp_key_req_t; typedef struct packed { logic data_ack; // Ack for data key. @@ -173,10 +173,10 @@ package otp_ctrl_pkg; typedef struct packed { logic ack; // Ack for key. - otbn_key_t key; // 128bit ephemeral scrambling key. - otbn_nonce_t nonce; // 256bit nonce. + acc_key_t key; // 128bit ephemeral scrambling key. + acc_nonce_t nonce; // 256bit nonce. logic seed_valid; // Set to 1 if the key seed has been provisioned and is valid. - } otbn_otp_key_rsp_t; + } acc_otp_key_rsp_t; //////////////////////////////// // Power/Reset Ctrl Interface // diff --git a/hw/ip/prim/rtl/prim_ram_1p_scr.sv b/hw/ip/prim/rtl/prim_ram_1p_scr.sv index 16a0732c670..25f7afdd116 100644 --- a/hw/ip/prim/rtl/prim_ram_1p_scr.sv +++ b/hw/ip/prim/rtl/prim_ram_1p_scr.sv @@ -5,7 +5,7 @@ // This is a draft implementation of a low-latency memory scrambling mechanism. // // The module is implemented as a primitive, in the same spirit as similar prim_ram_1p_adv wrappers. -// Hence, it can be conveniently instantiated by comportable IPs (such as OTBN) or in top_earlgrey +// Hence, it can be conveniently instantiated by comportable IPs (such as ACC) or in top_earlgrey // for the main system memory. // // The currently implemented architecture uses a reduced-round PRINCE cipher primitive in CTR mode diff --git a/hw/ip/rom_ctrl/rtl/rom_ctrl.sv b/hw/ip/rom_ctrl/rtl/rom_ctrl.sv index c62ad9c5270..0da24c52d1c 100644 --- a/hw/ip/rom_ctrl/rtl/rom_ctrl.sv +++ b/hw/ip/rom_ctrl/rtl/rom_ctrl.sv @@ -129,7 +129,7 @@ module rom_ctrl // SEC_CM: MEM.DIGEST assign kmac_data_o = '{valid: kmac_rom_vld_outer, - hold: 1'b0, // Tied to 1'b0 outside of OTBN mode + hold: 1'b0, // Tied to 1'b0 outside of ACC mode next: 1'b0, // Not used in ROM mode data: kmac_rom_data, strb: kmac_pkg::MsgStrbW'({NumBytes{1'b1}}), diff --git a/hw/ip/rom_ctrl/util/Makefile b/hw/ip/rom_ctrl/util/Makefile index e804492e936..4736eaca994 100644 --- a/hw/ip/rom_ctrl/util/Makefile +++ b/hw/ip/rom_ctrl/util/Makefile @@ -8,7 +8,7 @@ all: lint # We need a directory to build stuff and use the "rom_ctrl/util" namespace # in the top-level build-out directory. repo-top := ../../../.. -build-dir := $(repo-top)/build-out/otbn/util +build-dir := $(repo-top)/build-out/acc/util lint-build-dir := $(build-dir)/lint $(build-dir) $(lint-build-dir): diff --git a/hw/ip/sram_ctrl/doc/interfaces.md b/hw/ip/sram_ctrl/doc/interfaces.md index 3e9b534ce95..b6af187f865 100644 --- a/hw/ip/sram_ctrl/doc/interfaces.md +++ b/hw/ip/sram_ctrl/doc/interfaces.md @@ -90,7 +90,7 @@ Signal | Direction | Type The interface to the key derivation interface inside the OTP controller follows a simple req / ack protocol, where the SRAM controller first requests an updated ephemeral key by asserting the `sram_otp_key_i.req`. The OTP controller then fetches entropy from CSRNG and derives an ephemeral key using the SRAM_DATA_KEY_SEED and the PRESENT scrambling data path as described in the earlgrey's [OTP controller spec](../../../top_earlgrey/ip_autogen/otp_ctrl/README.md#scrambling-datapath) for example. -Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `otbn_otp_key_o`), which complete the req / ack handshake. +Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `acc_otp_key_o`), which complete the req / ack handshake. The key and nonce are made available to the scrambling primitive in the subsequent cycle. The wave diagram below illustrates this process. diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv index be957637532..b8e57e9f457 100644 --- a/hw/ip/sram_ctrl/rtl/sram_ctrl.sv +++ b/hw/ip/sram_ctrl/rtl/sram_ctrl.sv @@ -333,7 +333,7 @@ module sram_ctrl // case. For one example, see // // https://opentitan.org/book/hw/top_earlgrey/ - // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-otbn-scramblers + // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-acc-scramblers logic key_req, key_ack; assign key_req = reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && diff --git a/hw/ip_templates/clkmgr/doc/theory_of_operation.md.tpl b/hw/ip_templates/clkmgr/doc/theory_of_operation.md.tpl index 9057aac62c1..0a98c52292d 100644 --- a/hw/ip_templates/clkmgr/doc/theory_of_operation.md.tpl +++ b/hw/ip_templates/clkmgr/doc/theory_of_operation.md.tpl @@ -19,7 +19,7 @@ The table shows the group name, the modules that belong to each group, and wheth | Group | Frequencies | Modules | Software | Wait for Interrupt | | ------------- | ------------------------------ | -------------------------------------------------------------- | -------------- | ------------------ | | Power-up | 100~200KHz, 24MHz | Clock Manager, Power Manager, Reset Manager, Pinmux | No | No | -| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Otbn | Yes (1) | Yes (2) | +| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Acc | Yes (1) | Yes (2) | | Infrastructural | 24MHz, ~100MHz | Fabric, Fabric gaskets (iopmp), Memories | No | Yes (3) | | Security | 24MHz, ~100MHz | Alert handler, Entropy, Life cycle, Plic, Sensors | No | No | | Peripheral | 24MHz, 48MHz, 96MHz | I2c, Spi, Uart, Usb, others | Yes | Yes | @@ -177,7 +177,7 @@ Note, the power manager's request to turn off clocks supersedes all other local This means even if a particular clock is turned on by the clock manager (for example a transactional unit that is ongoing or a peripheral that is enabled), the power manager requests will still turn clocks on / off at the root. This makes it software's responsibility to ensure low power entry requests (which can only be initiated by software) do not conflict with any ongoing activities controlled by software. -For example, software should ensure that Aes / Otbn activities have completed before initializing a low power entry process. +For example, software should ensure that Aes / Acc activities have completed before initializing a low power entry process. <%text>### Clock Division diff --git a/hw/ip_templates/clkmgr/dv/README.md.tpl b/hw/ip_templates/clkmgr/dv/README.md.tpl index b98c71d79d3..b40ebe4319e 100644 --- a/hw/ip_templates/clkmgr/dv/README.md.tpl +++ b/hw/ip_templates/clkmgr/dv/README.md.tpl @@ -61,7 +61,7 @@ All common types and methods defined at the package level can be found in Peri${Name.to_camel_case(clk['src_name'])}${sep} % endfor } peri_e; - typedef enum int {TransAes, TransHmac, TransKmac, TransOtbn} trans_e; + typedef enum int {TransAes, TransHmac, TransKmac, TransAcc} trans_e; ``` ${"###"} TL_agent diff --git a/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_manual_excl.el b/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_manual_excl.el index ca5f99828dd..326e1d3c68c 100644 --- a/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_manual_excl.el +++ b/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_manual_excl.el @@ -24,7 +24,7 @@ INSTANCE: tb.dut.u_clk_main_kmac_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "2301929872 1660332954" -INSTANCE: tb.dut.u_clk_main_otbn_trans.u_idle_cnt +INSTANCE: tb.dut.u_clk_main_acc_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "953655365 3155586170" diff --git a/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_unr_excl.el b/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_unr_excl.el index 85e292d7a9f..761e9fac2e7 100644 --- a/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_unr_excl.el +++ b/hw/ip_templates/clkmgr/dv/cov/clkmgr_cov_unr_excl.el @@ -25,7 +25,7 @@ INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3274445021" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3554514034" @@ -47,7 +47,7 @@ Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" CHECKSUM: "2972535896 3554514034" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" diff --git a/hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv.tpl b/hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv.tpl index 567295e564c..40e20043619 100644 --- a/hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv.tpl +++ b/hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv.tpl @@ -70,10 +70,10 @@ class clkmgr_smoke_vseq extends clkmgr_base_vseq; uvm_reg_field value_bit; } trans_descriptor_t; trans_descriptor_t trans_descriptors[NUM_TRANS] = '{ + '{TransAcc, ral.clk_hints.clk_main_acc_hint, ral.clk_hints_status.clk_main_acc_val}, '{TransAes, ral.clk_hints.clk_main_aes_hint, ral.clk_hints_status.clk_main_aes_val}, '{TransHmac, ral.clk_hints.clk_main_hmac_hint, ral.clk_hints_status.clk_main_hmac_val}, - '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val}, - '{TransOtbn, ral.clk_hints.clk_main_otbn_hint, ral.clk_hints_status.clk_main_otbn_val} + '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val} }; idle = 0; // Changes in idle take at least 10 cycles to stick. diff --git a/hw/ip_templates/clkmgr/dv/tb.sv.tpl b/hw/ip_templates/clkmgr/dv/tb.sv.tpl index 5a2e8ef9a53..c5e8876948a 100644 --- a/hw/ip_templates/clkmgr/dv/tb.sv.tpl +++ b/hw/ip_templates/clkmgr/dv/tb.sv.tpl @@ -90,7 +90,7 @@ module tb; % endif % endfor .clk_hints({ - reg2hw.clk_hints.clk_main_otbn_hint.q, + reg2hw.clk_hints.clk_main_acc_hint.q, reg2hw.clk_hints.clk_main_kmac_hint.q, reg2hw.clk_hints.clk_main_hmac_hint.q, reg2hw.clk_hints.clk_main_aes_hint.q}) diff --git a/hw/ip_templates/otp_ctrl/data/otp_ctrl.hjson.tpl b/hw/ip_templates/otp_ctrl/data/otp_ctrl.hjson.tpl index 5520e32d235..c6b4a5e9574 100644 --- a/hw/ip_templates/otp_ctrl/data/otp_ctrl.hjson.tpl +++ b/hw/ip_templates/otp_ctrl/data/otp_ctrl.hjson.tpl @@ -406,14 +406,14 @@ otp_size_as_uint32 = otp_size_as_bytes // 4 package: "otp_ctrl_pkg" desc: "Array with key derivation interfaces for SRAM scrambling devices." } - // Key request from OTBN RAM Scrambler - { struct: "otbn_otp_key" + // Key request from ACC RAM Scrambler + { struct: "acc_otp_key" type: "req_rsp" - name: "otbn_otp_key" + name: "acc_otp_key" act: "rsp" default: "'0" package: "otp_ctrl_pkg" - desc: "Key derivation interface for OTBN scrambling devices." + desc: "Key derivation interface for ACC scrambling devices." } // Hardware config partition { struct: "otp_broadcast" diff --git a/hw/ip_templates/otp_ctrl/data/otp_ctrl_testplan.hjson.tpl b/hw/ip_templates/otp_ctrl/data/otp_ctrl_testplan.hjson.tpl index c65edfb98ff..a5d22c18570 100644 --- a/hw/ip_templates/otp_ctrl/data/otp_ctrl_testplan.hjson.tpl +++ b/hw/ip_templates/otp_ctrl/data/otp_ctrl_testplan.hjson.tpl @@ -40,7 +40,7 @@ - drive pwrmgr's request pin to trigger OTP initialization after reset, check status after OTP initialization - - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `otbn` + - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `acc` - randomly issue LC program request - write random values to random addresses within each OTP partition - read out the random selected write addresses, check if the readout values are expected @@ -143,7 +143,7 @@ { name: interface_key_check desc: ''' - OTP_CTRL will generate keys to `flash`, `sram`, and `otbn` upon their requests. + OTP_CTRL will generate keys to `flash`, `sram`, and `acc` upon their requests. Based on the DAI access sequence, this test will run key requests sequence in parallel, and check if correct keys are generated. ''' @@ -273,8 +273,8 @@ desc: '''Covers whether secret1 partition is locked during all `srams` key request.''' } { - name: otbn_req_cg - desc: '''Covers whether secret1 partition is locked during `otbn` key request.''' + name: acc_req_cg + desc: '''Covers whether secret1 partition is locked during `acc` key request.''' } { name: lc_prog_cg @@ -389,7 +389,7 @@ ''' } { - name: otbn_req_condition_cg + name: acc_req_condition_cg desc: '''Covers the following conditions when `lc_escalation_en` is On: - whether any key requests is in progress - whether DAI interface is busy diff --git a/hw/ip_templates/otp_ctrl/doc/interfaces.md.tpl b/hw/ip_templates/otp_ctrl/doc/interfaces.md.tpl index 1ad88fe126d..80b9c706263 100644 --- a/hw/ip_templates/otp_ctrl/doc/interfaces.md.tpl +++ b/hw/ip_templates/otp_ctrl/doc/interfaces.md.tpl @@ -120,21 +120,21 @@ Otherwise, this signal is tied to a random netlist constant. Since the key manager may run in a different clock domain, key manager is responsible for synchronizing the `otp_keymgr_key_o` signals. -${"###"} Interfaces to SRAM and OTBN Scramblers +${"###"} Interfaces to SRAM and ACC Scramblers -The interfaces to the SRAM and OTBN scrambling devices follow a req / ack protocol, where the scrambling device first requests a new ephemeral key by asserting the request channel (`sram_otp_key_i[*]`, `otbn_otp_key_i`). +The interfaces to the SRAM and ACC scrambling devices follow a req / ack protocol, where the scrambling device first requests a new ephemeral key by asserting the request channel (`sram_otp_key_i[*]`, `acc_otp_key_i`). The OTP controller then fetches entropy from EDN and derives an ephemeral key using the SRAM_DATA_KEY_SEED and the [PRESENT scrambling data path](#scrambling-datapath). -Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `otbn_otp_key_o`), which complete the req / ack handshake. -The wave diagram below illustrates this process for the OTBN scrambling device. +Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `acc_otp_key_o`), which complete the req / ack handshake. +The wave diagram below illustrates this process for the ACC scrambling device. ```wavejson {signal: [ {name: 'clk_i', wave: 'p.......'}, - {name: 'otbn_otp_key_i.req', wave: '01.|..0.'}, - {name: 'otbn_otp_key_o.ack', wave: '0..|.10.'}, - {name: 'otbn_otp_key_o.nonce', wave: '0..|.30.'}, - {name: 'otbn_otp_key_o.key', wave: '0..|.30.'}, - {name: 'otbn_otp_key_o.seed_valid', wave: '0..|.10.'}, + {name: 'acc_otp_key_i.req', wave: '01.|..0.'}, + {name: 'acc_otp_key_o.ack', wave: '0..|.10.'}, + {name: 'acc_otp_key_o.nonce', wave: '0..|.30.'}, + {name: 'acc_otp_key_o.key', wave: '0..|.30.'}, + {name: 'acc_otp_key_o.seed_valid', wave: '0..|.10.'}, ]} ``` @@ -175,7 +175,7 @@ If the key seeds have not yet been provisioned, the keys are derived from all-ze The resulting scrambling key is still ephemeral (i.e., it is derived using entropy from CSRNG) and okay to be used. Note that the req/ack protocol runs on the OTP clock. -It is the task of the scrambling device to perform the synchronization as described in the previous subsection on the [interface to SRAM and OTBN scramblers](#interface-to-sram-and-otbn-scramblers). +It is the task of the scrambling device to perform the synchronization as described in the previous subsection on the [interface to SRAM and ACC scramblers](#interface-to-sram-and-acc-scramblers). % endif ${"###"} Hardware Config Bits diff --git a/hw/ip_templates/otp_ctrl/doc/theory_of_operation.md b/hw/ip_templates/otp_ctrl/doc/theory_of_operation.md index ced9c642c8d..b283427e41e 100644 --- a/hw/ip_templates/otp_ctrl/doc/theory_of_operation.md +++ b/hw/ip_templates/otp_ctrl/doc/theory_of_operation.md @@ -426,7 +426,7 @@ In case of unrecoverable OTP errors, the FSM signals an error to the life cycle ![Key Derivation Interface FSM](otp_ctrl_kdi_fsm.svg) Upon reset release the KDI FSM waits until the OTP controller has initialized and the KDI gets enabled. -Once it is in the idle state, key derivation can be requested via the [flash](interfaces.md#interface-to-flash-scrambler) and [sram](interfaces.md#interface-to-sram-and-otbn-scramblers) interfaces. +Once it is in the idle state, key derivation can be requested via the [flash](interfaces.md#interface-to-flash-scrambler) and [sram](interfaces.md#interface-to-sram-and-acc-scramblers) interfaces. Based on which interface makes the request, the KDI controller will evaluate a variant of the PRESENT digest mechanism as described in more detail below. ### Scrambling Datapath diff --git a/hw/ip_templates/otp_ctrl/dv/README.md.tpl b/hw/ip_templates/otp_ctrl/dv/README.md.tpl index 861d4d3fb20..3f256ff9de3 100644 --- a/hw/ip_templates/otp_ctrl/dv/README.md.tpl +++ b/hw/ip_templates/otp_ctrl/dv/README.md.tpl @@ -64,7 +64,7 @@ fatal_check_alert and fatal_macro_alert. The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in OTP_CTRL device. ${"###"} OTP_CTRL interface -OTP_CTRL design has specific inputs and outputs to communicate with other IPs including LC_CTRL, OTBN, SRAM, FLASH etc. +OTP_CTRL design has specific inputs and outputs to communicate with other IPs including LC_CTRL, ACC, SRAM, FLASH etc. This interface is created to initialize, use simple task to drive, and use assertions to monitor these signals. ${"###"} Memory backdoor interface @@ -107,7 +107,7 @@ It creates the following analysis ports to retrieve the data monitored by corres * tl_d_chan_fifo: tl data channel * alert_fifos: alert handshakes * sram_fifos: sram requests -* otbn_fifo: otbn request +* acc_fifo: acc request * lc_prog_fifo: life cycle programming request * lc_token_fifo: life cycle token request % if enable_flash_key: diff --git a/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv.tpl b/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv.tpl index c4792f648ef..443389793f2 100644 --- a/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv.tpl @@ -40,7 +40,7 @@ module otp_ctrl_cov_bind; .flash_otp_key_i (flash_otp_key_i), % endif .sram_otp_key_i (sram_otp_key_i), - .otbn_otp_key_i (otbn_otp_key_i) + .acc_otp_key_i (acc_otp_key_i) ); bind otp_ctrl cip_lc_tx_cov_if u_lc_creator_seed_sw_rw_en_cov_if ( diff --git a/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv.tpl b/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv.tpl index 2f4ba0d45ce..990502a5f23 100644 --- a/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv.tpl @@ -14,7 +14,7 @@ interface otp_ctrl_cov_if input otp_ctrl_pkg::flash_otp_key_req_t flash_otp_key_i, % endif input otp_ctrl_pkg::sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, - input otp_ctrl_pkg::otbn_otp_key_req_t otbn_otp_key_i + input otp_ctrl_pkg::acc_otp_key_req_t acc_otp_key_i ); import uvm_pkg::*; @@ -28,7 +28,7 @@ interface otp_ctrl_cov_if % endif lc_esc_during_sram_0_req: coverpoint sram_otp_key_i[0].req; lc_esc_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - lc_esc_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_esc_during_acc_req: coverpoint acc_otp_key_i.req; lc_esc_during_otp_idle: coverpoint pwr_otp_o.otp_idle; lc_esc_during_lc_otp_prog_req: coverpoint lc_otp_program_i.req; endgroup @@ -42,7 +42,7 @@ interface otp_ctrl_cov_if flash_data_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; flash_data_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; flash_data_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - flash_data_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + flash_data_req_during_acc_req: coverpoint acc_otp_key_i.req; flash_data_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -54,7 +54,7 @@ interface otp_ctrl_cov_if flash_addr_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; flash_addr_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; flash_addr_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - flash_addr_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + flash_addr_req_during_acc_req: coverpoint acc_otp_key_i.req; flash_addr_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup % endif @@ -69,7 +69,7 @@ interface otp_ctrl_cov_if sram_0_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; % endif sram_0_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - sram_0_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_0_req_during_acc_req: coverpoint acc_otp_key_i.req; sram_0_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -83,22 +83,22 @@ interface otp_ctrl_cov_if sram_1_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; % endif sram_1_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; - sram_1_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_1_req_during_acc_req: coverpoint acc_otp_key_i.req; sram_1_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup - covergroup otbn_req_condition_cg @(otbn_otp_key_i.req); - otbn_req_during_lc_esc: coverpoint lc_escalate_en_i { + covergroup acc_req_condition_cg @(acc_otp_key_i.req); + acc_req_during_lc_esc: coverpoint lc_escalate_en_i { bins lc_esc_on = {lc_ctrl_pkg::On}; bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; } % if enable_flash_key: - otbn_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; - otbn_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + acc_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + acc_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; % endif - otbn_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; - otbn_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - otbn_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + acc_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + acc_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + acc_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup covergroup lc_prog_req_condition_cg @(lc_otp_program_i.req); @@ -112,7 +112,7 @@ interface otp_ctrl_cov_if % endif lc_prog_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; lc_prog_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - lc_prog_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_prog_req_during_acc_req: coverpoint acc_otp_key_i.req; lc_prog_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -123,7 +123,7 @@ interface otp_ctrl_cov_if % endif `DV_FCOV_INSTANTIATE_CG(sram_0_req_condition_cg) `DV_FCOV_INSTANTIATE_CG(sram_1_req_condition_cg) - `DV_FCOV_INSTANTIATE_CG(otbn_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(acc_req_condition_cg) `DV_FCOV_INSTANTIATE_CG(lc_prog_req_condition_cg) endinterface diff --git a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env.sv.tpl index 27fa47c801c..9a466d8bc7a 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env.sv.tpl @@ -19,7 +19,7 @@ class otp_ctrl_env #( `uvm_component_new push_pull_agent#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent[NumSramKeyReqSlots]; - push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent; + push_pull_agent#(.DeviceDataWidth(ACC_DATA_SIZE)) m_acc_pull_agent; % if enable_flash_key: push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_addr_pull_agent; push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_data_pull_agent; @@ -38,11 +38,11 @@ class otp_ctrl_env #( $sformatf("%0s*", sram_agent_name), "cfg", cfg.m_sram_pull_agent_cfg[i]); end - // build otbn-otp pull agent - m_otbn_pull_agent = push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id::create( - "m_otbn_pull_agent", this); - uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set( - this, "m_otbn_pull_agent", "cfg", cfg.m_otbn_pull_agent_cfg); + // build acc-otp pull agent + m_acc_pull_agent = push_pull_agent#(.DeviceDataWidth(ACC_DATA_SIZE))::type_id::create( + "m_acc_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE)))::set( + this, "m_acc_pull_agent", "cfg", cfg.m_acc_pull_agent_cfg); % if enable_flash_key: // build flash-otp pull agent @@ -89,7 +89,7 @@ class otp_ctrl_env #( end end - virtual_sequencer.otbn_pull_sequencer_h = m_otbn_pull_agent.sequencer; + virtual_sequencer.acc_pull_sequencer_h = m_acc_pull_agent.sequencer; % if enable_flash_key: virtual_sequencer.flash_addr_pull_sequencer_h = m_flash_addr_pull_agent.sequencer; virtual_sequencer.flash_data_pull_sequencer_h = m_flash_data_pull_agent.sequencer; @@ -97,7 +97,7 @@ class otp_ctrl_env #( virtual_sequencer.lc_prog_pull_sequencer_h = m_lc_prog_pull_agent.sequencer; if (cfg.en_scb) begin - m_otbn_pull_agent.monitor.analysis_port.connect(scoreboard.otbn_fifo.analysis_export); + m_acc_pull_agent.monitor.analysis_port.connect(scoreboard.acc_fifo.analysis_export); % if enable_flash_key: m_flash_addr_pull_agent.monitor.analysis_port.connect( scoreboard.flash_addr_fifo.analysis_export); diff --git a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv.tpl index 3f24495abc2..5b9e1237b85 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv.tpl @@ -19,7 +19,7 @@ class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block // ext component cfgs rand push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent_cfg[NumSramKeyReqSlots]; - rand push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent_cfg; + rand push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE)) m_acc_pull_agent_cfg; % if enable_flash_key: rand push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_data_pull_agent_cfg; rand push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_addr_pull_agent_cfg; @@ -77,9 +77,9 @@ class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block m_sram_pull_agent_cfg[i].agent_type = PullAgent; end - m_otbn_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id - ::create("m_otbn_pull_agent_cfg"); - m_otbn_pull_agent_cfg.agent_type = PullAgent; + m_acc_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE))::type_id + ::create("m_acc_pull_agent_cfg"); + m_acc_pull_agent_cfg.agent_type = PullAgent; % if enable_flash_key: m_flash_data_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE))::type_id diff --git a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cov.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cov.sv.tpl index e32569b7ebd..f8319962558 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cov.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_cov.sv.tpl @@ -172,7 +172,7 @@ class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); bit_toggle_cg_wrap lc_prog_cg; - bit_toggle_cg_wrap otbn_req_cg; + bit_toggle_cg_wrap acc_req_cg; bit_toggle_cg_wrap status_csr_cg[OtpStatusFieldSize]; // covergroups @@ -417,7 +417,7 @@ class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); super.build_phase(phase); // Create instances from bit_toggle_cg_wrapper. lc_prog_cg = new("lc_prog_cg", "", 0); - otbn_req_cg = new("otbn_req_cg", "", 0); + acc_req_cg = new("acc_req_cg", "", 0); foreach (status_csr_cg[i]) begin otp_status_e index = otp_status_e'(i); status_csr_cg[i]= new(index.name, "status_csr_cg", 0); diff --git a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv.tpl index fc1e6494829..4ee21164060 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv.tpl @@ -65,8 +65,8 @@ package otp_ctrl_env_pkg; // sram rsp data has 1 bit for seed_valid, the rest are for key and nonce parameter uint SRAM_DATA_SIZE = 1 + SramKeyWidth + SramNonceWidth; - // otbn rsp data has 1 bit for seed_valid, the rest are for key and nonce - parameter uint OTBN_DATA_SIZE = 1 + OtbnKeyWidth + OtbnNonceWidth; + // acc rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint ACC_DATA_SIZE = 1 + AccKeyWidth + AccNonceWidth; % if enable_flash_key: // flash rsp data has 1 bit for seed_valid, the rest are for key parameter uint FLASH_DATA_SIZE = 1 + FlashKeyWidth; @@ -75,7 +75,7 @@ package otp_ctrl_env_pkg; parameter uint LC_PROG_DATA_SIZE = LcStateWidth + LcCountWidth; parameter uint NUM_SRAM_EDN_REQ = 12; - parameter uint NUM_OTBN_EDN_REQ = 10; + parameter uint NUM_ACC_EDN_REQ = 10; // This is used to randomize CHECK_TIMEOUT in sequences, set to a low value // so it will certainly cause a check error due to a timeout. diff --git a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_if.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_if.sv.tpl index 9fc10420ce2..f6df8258ccf 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_if.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_if.sv.tpl @@ -81,7 +81,7 @@ interface otp_ctrl_if(input clk_i, input rst_ni); logic lc_prog_err_dly1, lc_prog_no_sta_check; // Connect push_pull interfaces ack signals for assertion checks. - logic otbn_ack, lc_prog_ack; + logic acc_ack, lc_prog_ack; % if enable_flash_key: logic [1:0] flash_acks; % endif @@ -356,7 +356,7 @@ part_data_size = f"(HwCfg1Size - {16 if hw_cfg1_part['zeroizable'] else 8})" `OTP_FATAL_ERR_ASSERT(FlashAcks_A, flash_acks == 0) % endif `OTP_FATAL_ERR_ASSERT(SramAcks_A, sram_acks == 0) - `OTP_FATAL_ERR_ASSERT(OtbnAck_A, otbn_ack == 0) + `OTP_FATAL_ERR_ASSERT(AccAck_A, acc_ack == 0) `undef OTP_ASSERT_WO_LC_ESC `undef OTP_FATAL_ERR_ASSERT diff --git a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv.tpl index c72b9722059..667838e271e 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv.tpl @@ -63,7 +63,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) // TLM agent fifos uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE))) sram_fifos[NumSramKeyReqSlots]; - uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE))) otbn_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(ACC_DATA_SIZE))) acc_fifo; % if enable_flash_key: uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_addr_fifo; uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_data_fifo; @@ -80,7 +80,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) for (int i = 0; i < NumSramKeyReqSlots; i++) begin sram_fifos[i] = new($sformatf("sram_fifos[%0d]", i), this); end - otbn_fifo = new("otbn_fifo", this); + acc_fifo = new("acc_fifo", this); % if enable_flash_key: flash_addr_fifo = new("flash_addr_fifo", this); flash_data_fifo = new("flash_data_fifo", this); @@ -100,7 +100,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) process_lc_esc(); process_lc_prog_req(); process_edn_req(); - check_otbn_rsp(); + check_acc_rsp(); % if enable_flash_key: check_flash_rsps(); % endif @@ -412,32 +412,32 @@ else: end endtask - virtual task check_otbn_rsp(); + virtual task check_acc_rsp(); forever begin - push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE)) rcv_item; + push_pull_item#(.DeviceDataWidth(ACC_DATA_SIZE)) rcv_item; bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; - bit [OtbnKeyWidth-1:0] key, exp_key; - bit [OtbnNonceWidth-1:0] nonce, exp_nonce; + bit [AccKeyWidth-1:0] key, exp_key; + bit [AccNonceWidth-1:0] nonce, exp_nonce; bit seed_valid; bit part_locked; - otbn_fifo.get(rcv_item); + acc_fifo.get(rcv_item); seed_valid = rcv_item.d_data[0]; - nonce = rcv_item.d_data[1+:OtbnNonceWidth]; - key = rcv_item.d_data[OtbnNonceWidth+1+:OtbnKeyWidth]; + nonce = rcv_item.d_data[1+:AccNonceWidth]; + key = rcv_item.d_data[AccNonceWidth+1+:AccKeyWidth]; part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; // seed is valid as long as secret1 is locked - `DV_CHECK_EQ(seed_valid, part_locked, "otbn seed_valid mismatch") + `DV_CHECK_EQ(seed_valid, part_locked, "acc seed_valid mismatch") - // If edn_data_q matches the OTBN requested size, check OTBN outputs - if (edn_data_q.size() == NUM_OTBN_EDN_REQ) begin + // If edn_data_q matches the ACC requested size, check ACC outputs + if (edn_data_q.size() == NUM_ACC_EDN_REQ) begin {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; // check nonce value - `DV_CHECK_EQ(nonce, exp_nonce, "otbn nonce mismatch") + `DV_CHECK_EQ(nonce, exp_nonce, "acc nonce mismatch") // calculate key sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); @@ -455,16 +455,16 @@ else: .second_key(edn_key2), .num_round(2)); exp_key = {exp_key_higher, exp_key_lower}; - `DV_CHECK_EQ(key, exp_key, "otbn key mismatch") + `DV_CHECK_EQ(key, exp_key, "acc key mismatch") - if (cfg.en_cov) cov.otbn_req_cg.sample(part_locked); + if (cfg.en_cov) cov.acc_req_cg.sample(part_locked); - // If during OTBN key request, the LFSR timer expired and trigger an EDN request to acquire - // two EDN keys, then ignore the OTBN output checking, because scb did not know which EDN + // If during ACC key request, the LFSR timer expired and trigger an EDN request to acquire + // two EDN keys, then ignore the ACC output checking, because scb did not know which EDN // keys are used for LFSR. // Thus any edn_data_q size equal to (16+2*N) is exempted from checking. - end else if ((edn_data_q.size() - NUM_OTBN_EDN_REQ) % 2 != 0) begin - `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during OTBN request", + end else if ((edn_data_q.size() - NUM_ACC_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during ACC request", edn_data_q.size())) end edn_data_q.delete(); @@ -541,7 +541,7 @@ else: // seed is valid as long as secret1 is locked `DV_CHECK_EQ(seed_valid, part_locked, $sformatf("sram_%0d seed_valid mismatch", index)) - // If edn_data_q matches the OTBN requested size, check OTBN outputs + // If edn_data_q matches the ACC requested size, check ACC outputs if (edn_data_q.size() == NUM_SRAM_EDN_REQ) begin {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; @@ -1328,7 +1328,7 @@ else: recover_interrupted_op(); super.reset(kind); // flush fifos - otbn_fifo.flush(); + acc_fifo.flush(); % if enable_flash_key: flash_addr_fifo.flush(); flash_data_fifo.flush(); @@ -1368,7 +1368,7 @@ else: // write secret until KDI request is completed. Since the KDI process time could // vary depends on the push-pull-agent, we are going to ignore the checking if // this scenario happens. - cfg.m_otbn_pull_agent_cfg.vif.req || + cfg.m_acc_pull_agent_cfg.vif.req || % if enable_flash_key: cfg.m_flash_data_pull_agent_cfg.vif.req || cfg.m_flash_addr_pull_agent_cfg.vif.req || diff --git a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv.tpl index d7a8b2b9e1a..c580224cfdc 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv.tpl @@ -11,7 +11,7 @@ class otp_ctrl_virtual_sequencer extends cip_base_virtual_sequencer #( `uvm_component_new push_pull_sequencer#(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_pull_sequencer_h[NumSramKeyReqSlots]; - push_pull_sequencer#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_sequencer_h; + push_pull_sequencer#(.DeviceDataWidth(ACC_DATA_SIZE)) acc_pull_sequencer_h; % if enable_flash_key: push_pull_sequencer#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_data_pull_sequencer_h; push_pull_sequencer#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_addr_pull_sequencer_h; diff --git a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv.tpl index c856f5ef243..616fe6034f2 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv.tpl @@ -546,15 +546,15 @@ class otp_ctrl_base_vseq extends cip_base_vseq #( for (int i = 0; i < NumSramKeyReqSlots; i++) req_sram_key(i, blocking); endtask - virtual task req_otbn_key(bit blocking = default_req_blocking); - if (cfg.m_otbn_pull_agent_cfg.vif.req === 1'b1) return; + virtual task req_acc_key(bit blocking = default_req_blocking); + if (cfg.m_acc_pull_agent_cfg.vif.req === 1'b1) return; if (blocking) begin - req_otbn_key_sub(); + req_acc_key_sub(); end else begin fork begin - req_otbn_key_sub(); + req_acc_key_sub(); end join_none; // Add #0 to ensure that this thread starts executing before any subsequent call @@ -562,12 +562,12 @@ class otp_ctrl_base_vseq extends cip_base_vseq #( end endtask - virtual task req_otbn_key_sub(); - push_pull_host_seq#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_seq; + virtual task req_acc_key_sub(); + push_pull_host_seq#(.DeviceDataWidth(ACC_DATA_SIZE)) acc_pull_seq; wait(cfg.under_reset == 0); - `uvm_create_on(otbn_pull_seq, p_sequencer.otbn_pull_sequencer_h); - `DV_CHECK_RANDOMIZE_FATAL(otbn_pull_seq) - `uvm_send(otbn_pull_seq) + `uvm_create_on(acc_pull_seq, p_sequencer.acc_pull_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(acc_pull_seq) + `uvm_send(acc_pull_seq) endtask % if enable_flash_key: diff --git a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv.tpl index 5df5bc10710..47d56f54a8f 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv.tpl @@ -196,7 +196,7 @@ class otp_ctrl_common_vseq extends otp_ctrl_base_vseq; write_sw_digests(); // Access OTP via app interface. - if ($urandom_range(0, 1)) req_otbn_key(0); + if ($urandom_range(0, 1)) req_acc_key(0); % if enable_flash_key: if ($urandom_range(0, 1)) req_flash_addr_key(0); if ($urandom_range(0, 1)) req_flash_data_key(0); diff --git a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv.tpl index 407c2a41109..a43c75e21f7 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv.tpl @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This sequence will randomly issue key otbn, sram, flash key requests during or after partition +// This sequence will randomly issue key acc, sram, flash key requests during or after partition // is locked. // This sequence will check if nonce, seed_valid, and output keys are correct via scb. @@ -22,10 +22,10 @@ class otp_ctrl_parallel_key_req_vseq extends otp_ctrl_parallel_base_vseq; fork begin - // get otbn keys + // get acc keys if ($urandom_range(0, 1)) begin wait_clk_or_reset($urandom_range(0, 500)); - if (!base_vseq_done && !cfg.under_reset) req_otbn_key(); + if (!base_vseq_done && !cfg.under_reset) req_acc_key(); end end % if enable_flash_key: diff --git a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv.tpl index 97cbd06472b..8bca42ae008 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv.tpl @@ -77,7 +77,7 @@ class otp_ctrl_parallel_lc_esc_vseq extends otp_ctrl_dai_lock_vseq; virtual task set_lc_esc_and_check(); // Random issue key requests before lc_esc_en is issued. randcase - 1: req_otbn_key(0); + 1: req_acc_key(0); % if enable_flash_key: 1: req_flash_addr_key(0); 1: req_flash_data_key(0); diff --git a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv.tpl b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv.tpl index 9fc568e0dc7..982b7703d0e 100644 --- a/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv.tpl @@ -133,7 +133,7 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; force_mubi_part_access(); if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs) begin - req_otbn_key(); + req_acc_key(); % if enable_flash_key: req_flash_addr_key(); req_flash_data_key(); @@ -245,7 +245,7 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; end if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs && !cfg.smoke_test) begin - req_otbn_key(); + req_acc_key(); % if enable_flash_key: req_flash_addr_key(); req_flash_data_key(); diff --git a/hw/ip_templates/otp_ctrl/dv/tb.sv.tpl b/hw/ip_templates/otp_ctrl/dv/tb.sv.tpl index 9d22660cf90..b2e7f7e82a9 100644 --- a/hw/ip_templates/otp_ctrl/dv/tb.sv.tpl +++ b/hw/ip_templates/otp_ctrl/dv/tb.sv.tpl @@ -40,8 +40,8 @@ module tb; wire otp_ctrl_pkg::flash_otp_key_req_t flash_req; wire otp_ctrl_pkg::flash_otp_key_rsp_t flash_rsp; % endif - wire otp_ctrl_pkg::otbn_otp_key_req_t otbn_req; - wire otp_ctrl_pkg::otbn_otp_key_rsp_t otbn_rsp; + wire otp_ctrl_pkg::acc_otp_key_req_t acc_req; + wire otp_ctrl_pkg::acc_otp_key_rsp_t acc_rsp; wire otp_ctrl_pkg::sram_otp_key_req_t[NumSramKeyReqSlots-1:0] sram_req; wire otp_ctrl_pkg::sram_otp_key_rsp_t[NumSramKeyReqSlots-1:0] sram_rsp; @@ -63,7 +63,7 @@ module tb; lc_prog_if(.clk(clk), .rst_n(rst_n)); push_pull_if #(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_if[NumSramKeyReqSlots](.clk(clk), .rst_n(rst_n)); - push_pull_if #(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_if(.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(ACC_DATA_SIZE)) acc_if(.clk(clk), .rst_n(rst_n)); % if enable_flash_key: push_pull_if #(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_addr_if(.clk(clk), .rst_n(rst_n)); push_pull_if #(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_data_if(.clk(clk), .rst_n(rst_n)); @@ -87,7 +87,7 @@ module tb; % if enable_flash_key: assign otp_ctrl_if.flash_acks = flash_data_if.ack; % endif - assign otp_ctrl_if.otbn_ack = otbn_if.ack; + assign otp_ctrl_if.acc_ack = acc_if.ack; // This signal probes design's alert request to avoid additional logic for triggering alert and // disable assertions. @@ -150,9 +150,9 @@ module tb; // sram .sram_otp_key_i (sram_req), .sram_otp_key_o (sram_rsp), - // otbn - .otbn_otp_key_i (otbn_req), - .otbn_otp_key_o (otbn_rsp), + // acc + .acc_otp_key_i (acc_req), + .acc_otp_key_o (acc_rsp), .otp_broadcast_o (otp_ctrl_if.otp_broadcast_o), @@ -207,9 +207,9 @@ module tb; $sformatf("*env.m_sram_pull_agent[%0d]*", i), "vif", sram_if[i]); end end - assign otbn_req = otbn_if.req; - assign otbn_if.ack = otbn_rsp.ack; - assign otbn_if.d_data = {otbn_rsp.key, otbn_rsp.nonce, otbn_rsp.seed_valid}; + assign acc_req = acc_if.req; + assign acc_if.ack = acc_rsp.ack; + assign acc_if.d_data = {acc_rsp.key, acc_rsp.nonce, acc_rsp.seed_valid}; % if enable_flash_key: assign flash_req = {flash_data_if.req, flash_addr_if.req}; @@ -266,8 +266,8 @@ module tb; "vif", tl_if); uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_otp_macro_prim_reg_block", "vif", prim_tl_if); - uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set(null, - "*env.m_otbn_pull_agent*", "vif", otbn_if); + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(ACC_DATA_SIZE)))::set(null, + "*env.m_acc_pull_agent*", "vif", acc_if); % if enable_flash_key: uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(FLASH_DATA_SIZE)))::set(null, "*env.m_flash_data_pull_agent*", "vif", flash_data_if); diff --git a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl.sv.tpl b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl.sv.tpl index d8015142b64..debf92ee145 100644 --- a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl.sv.tpl +++ b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl.sv.tpl @@ -83,8 +83,8 @@ module otp_ctrl % endif input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, - input otbn_otp_key_req_t otbn_otp_key_i, - output otbn_otp_key_rsp_t otbn_otp_key_o, + input acc_otp_key_req_t acc_otp_key_i, + output acc_otp_key_rsp_t acc_otp_key_o, // Interface to OTP_MACRO output otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_macro_o, @@ -910,7 +910,7 @@ end // case. For one example, see // // https://opentitan.org/book/hw/top_earlgrey/ - // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-otbn-scramblers + // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-acc-scramblers // Note: as opposed to the OTP arbitration above, we do not perform cycle-wise arbitration, but @@ -1150,8 +1150,8 @@ end % endif .sram_otp_key_i, .sram_otp_key_o, - .otbn_otp_key_i, - .otbn_otp_key_o, + .acc_otp_key_i, + .acc_otp_key_o, .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[KdiIdx] ), .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[KdiIdx] ), .scrmbl_cmd_o ( part_scrmbl_req_bundle[KdiIdx].cmd ), @@ -1570,7 +1570,7 @@ end `ASSERT_KNOWN(FlashOtpKeyRspKnown_A, flash_otp_key_o) % endif `ASSERT_KNOWN(OtpSramKeyKnown_A, sram_otp_key_o) - `ASSERT_KNOWN(OtpOtgnKeyKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(OtpOtgnKeyKnown_A, acc_otp_key_o) `ASSERT_KNOWN(OtpBroadcastKnown_A, otp_broadcast_o) // Alert assertions for sparse FSMs. diff --git a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_kdi.sv.tpl b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_kdi.sv.tpl index f12e542147b..639e34f5fd7 100644 --- a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_kdi.sv.tpl +++ b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_kdi.sv.tpl @@ -4,7 +4,7 @@ // // Scrambling key derivation module for OTP. // -<% otbn_idx = 2 if enable_flash_key else 0 %>\ +<% acc_idx = 2 if enable_flash_key else 0 %>\ `include "prim_assert.sv" @@ -43,8 +43,8 @@ module otp_ctrl_kdi % endif input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, - input otbn_otp_key_req_t otbn_otp_key_i, - output otbn_otp_key_rsp_t otbn_otp_key_o, + input acc_otp_key_req_t acc_otp_key_i, + output acc_otp_key_rsp_t acc_otp_key_o, // Scrambling mutex request output logic scrmbl_mtx_req_o, input scrmbl_mtx_gnt_i, @@ -66,10 +66,10 @@ module otp_ctrl_kdi //////////////////////// % if enable_flash_key: - // 2xFlash, OTBN + SRAM slots + // 2xFlash, ACC + SRAM slots localparam int NumReq = 3 + NumSramKeyReqSlots; % else: - // OTBN + SRAM slots + // ACC + SRAM slots localparam int NumReq = 1 + NumSramKeyReqSlots; % endif // Make sure key sizes in the system are multiples of 64bit and not larger than 256bit. @@ -82,8 +82,8 @@ module otp_ctrl_kdi % endif `ASSERT_INIT(KeyNonceSize3_A, (SramKeyWidth <= 256) && ((SramKeyWidth % 64) == 0)) `ASSERT_INIT(KeyNonceSize4_A, (SramNonceWidth <= 256) && ((SramNonceWidth % 64) == 0)) - `ASSERT_INIT(KeyNonceSize5_A, (OtbnKeyWidth <= 256) && ((OtbnKeyWidth % 64) == 0)) - `ASSERT_INIT(KeyNonceSize6_A, (OtbnNonceWidth <= 256) && ((OtbnNonceWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize5_A, (AccKeyWidth <= 256) && ((AccKeyWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize6_A, (AccNonceWidth <= 256) && ((AccNonceWidth % 64) == 0)) // Make sure EDN interface has compatible width. `ASSERT_INIT(EntropyWidthDividesDigestBlockWidth_A, (ScrmblKeyWidth % EdnDataWidth) == 0) @@ -129,13 +129,13 @@ module otp_ctrl_kdi assign req[0] = flash_otp_key_i.data_req; assign req[1] = flash_otp_key_i.addr_req; % endif - assign req[${otbn_idx}] = otbn_otp_key_i.req; + assign req[${acc_idx}] = acc_otp_key_i.req; % if enable_flash_key: assign flash_otp_key_o.data_ack = gnt[0]; assign flash_otp_key_o.addr_ack = gnt[1]; % endif - assign otbn_otp_key_o.ack = gnt[${otbn_idx}]; + assign acc_otp_key_o.ack = gnt[${acc_idx}]; // anchored seeds % if enable_flash_key: @@ -185,20 +185,20 @@ module otp_ctrl_kdi seed_valid: scrmbl_key_seed_valid_i, seed: flash_addr_key_seed}; // 2x128bit % endif - // OTBN key - assign req_bundles[${otbn_idx}] = '{ingest_entropy: 1'b1, // ingest random data + // ACC key + assign req_bundles[${acc_idx}] = '{ingest_entropy: 1'b1, // ingest random data chained_digest: 1'b0, // revert to netlist IV between blocks digest_sel: SramDataKey, fetch_nonce: 1'b1, // fetch nonce - nonce_size: 2'(OtbnNonceWidth/EdnDataWidth-1), + nonce_size: 2'(AccNonceWidth/EdnDataWidth-1), seed_valid: scrmbl_key_seed_valid_i, seed: {sram_data_key_seed, // reuse same seed sram_data_key_seed}}; // SRAM keys - for (genvar k = ${otbn_idx + 1}; k < NumReq; k++) begin : gen_req_assign - assign req[k] = sram_otp_key_i[k-${otbn_idx + 1}].req; - assign sram_otp_key_o[k-${otbn_idx + 1}].ack = gnt[k]; + for (genvar k = ${acc_idx + 1}; k < NumReq; k++) begin : gen_req_assign + assign req[k] = sram_otp_key_i[k-${acc_idx + 1}].req; + assign sram_otp_key_o[k-${acc_idx + 1}].ack = gnt[k]; assign req_bundles[k] = '{ingest_entropy: 1'b1, // ingest random data chained_digest: 1'b0, // revert to netlist IV between blocks digest_sel: SramDataKey, @@ -306,9 +306,9 @@ module otp_ctrl_kdi .q_o(key_out_q) ); - assign otbn_otp_key_o.key = key_out_q; - assign otbn_otp_key_o.nonce = nonce_out_q[OtbnNonceSel-1:0]; - assign otbn_otp_key_o.seed_valid = seed_valid_q; + assign acc_otp_key_o.key = key_out_q; + assign acc_otp_key_o.nonce = nonce_out_q[AccNonceSel-1:0]; + assign acc_otp_key_o.seed_valid = seed_valid_q; % if enable_flash_key: assign flash_otp_key_o.key = key_out_q; @@ -621,7 +621,7 @@ module otp_ctrl_kdi `ASSERT_KNOWN(FlashOtpKeyRspKnown_A, flash_otp_key_o) % endif `ASSERT_KNOWN(SramOtpKeyRspKnown_A, sram_otp_key_o) - `ASSERT_KNOWN(OtbnOtpKeyRspKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(AccOtpKeyRspKnown_A, acc_otp_key_o) `ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) `ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) `ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) diff --git a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv.tpl b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv.tpl index 15f456da922..77c17bd8e1d 100644 --- a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv.tpl +++ b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv.tpl @@ -98,12 +98,12 @@ package otp_ctrl_top_specific_pkg; // Get maximum nonce width % if enable_flash_key: localparam int NumNonceChunks = - (OtbnNonceWidth > FlashKeyWidth) ? - ((OtbnNonceWidth > SramNonceWidth) ? OtbnNonceSel : SramNonceSel) : + (AccNonceWidth > FlashKeyWidth) ? + ((AccNonceWidth > SramNonceWidth) ? AccNonceSel : SramNonceSel) : ((FlashKeyWidth > SramNonceWidth) ? FlashNonceSel : SramNonceSel); % else: localparam int NumNonceChunks = - (OtbnNonceWidth > SramNonceWidth) ? OtbnNonceSel : SramNonceSel; + (AccNonceWidth > SramNonceWidth) ? AccNonceSel : SramNonceSel; % endif /////////////////////////////////////////// diff --git a/hw/top_darjeeling/data/autogen/defs.bzl b/hw/top_darjeeling/data/autogen/defs.bzl index bd6df6d8a41..281ca8c7a86 100644 --- a/hw/top_darjeeling/data/autogen/defs.bzl +++ b/hw/top_darjeeling/data/autogen/defs.bzl @@ -8,6 +8,7 @@ # -o hw/top_darjeeling/ load("//hw/top_darjeeling/ip_autogen/ac_range_check:defs.bzl", "AC_RANGE_CHECK") +load("//hw/ip/acc:defs.bzl", "ACC") load("//hw/ip/aes:defs.bzl", "AES") load("//hw/top_darjeeling/ip_autogen/alert_handler:defs.bzl", "ALERT_HANDLER") load("//hw/ip/aon_timer:defs.bzl", "AON_TIMER") @@ -24,7 +25,6 @@ load("//hw/ip/keymgr_dpe:defs.bzl", "KEYMGR_DPE") load("//hw/ip/kmac:defs.bzl", "KMAC") load("//hw/ip/lc_ctrl:defs.bzl", "LC_CTRL") load("//hw/ip/mbx:defs.bzl", "MBX") -load("//hw/ip/otbn:defs.bzl", "OTBN") load("//hw/top_darjeeling/ip_autogen/otp_ctrl:defs.bzl", "OTP_CTRL") load("//hw/ip/otp_macro:defs.bzl", "OTP_MACRO") load("//hw/top_darjeeling/ip_autogen/pinmux:defs.bzl", "PINMUX") @@ -45,6 +45,7 @@ load("//hw/ip/uart:defs.bzl", "UART") DARJEELING_IPS = [ AC_RANGE_CHECK, + ACC, AES, ALERT_HANDLER, AON_TIMER, @@ -61,7 +62,6 @@ DARJEELING_IPS = [ KMAC, LC_CTRL, MBX, - OTBN, OTP_CTRL, OTP_MACRO, PINMUX, @@ -107,13 +107,13 @@ DARJEELING_ALERTS = [ "sram_ctrl_ret_aon_fatal_error", "rv_dm_fatal_fault", "rv_plic_fatal_fault", + "acc_fatal", + "acc_recov", "aes_recov_ctrl_update_err", "aes_fatal_fault", "hmac_fatal_fault", "kmac_recov_operation_err", "kmac_fatal_fault_err", - "otbn_fatal", - "otbn_recov", "keymgr_dpe_recov_operation_err", "keymgr_dpe_fatal_fault_err", "csrng_recov_alert", diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 829bedd20ee..1e71c9d429c 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -86,10 +86,10 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } { @@ -392,7 +392,7 @@ rv_plic aes hmac - otbn + acc keymgr_dpe csrng entropy_src @@ -1299,9 +1299,9 @@ index: -1 } { - name: otbn_otp_key - desc: Key derivation interface for OTBN scrambling devices. - struct: otbn_otp_key + name: acc_otp_key + desc: Key derivation interface for ACC scrambling devices. + struct: acc_otp_key package: otp_ctrl_pkg type: req_rsp act: rsp @@ -1309,7 +1309,7 @@ default: "'0" inst_name: otp_ctrl end_idx: -1 - top_signame: otp_ctrl_otbn_otp_key + top_signame: otp_ctrl_acc_otp_key index: -1 } { @@ -2100,7 +2100,7 @@ width: 2 default: lc_ctrl_pkg::On inst_name: lc_ctrl - top_signame: otbn_lc_rma_ack + top_signame: acc_lc_rma_ack index: -1 } { @@ -4786,12 +4786,29 @@ ] } { - name: aes - type: aes + name: acc + type: acc + param_decl: + { + AccPQCEn: "0" + } clock_srcs: { - clk_i: main - clk_edn_i: main + clk_i: + { + clock: main + group: trans + } + clk_edn_i: + { + clock: main + group: secure + } + clk_otp_i: + { + clock: io + group: secure + } } clock_group: trans reset_connections: @@ -4806,95 +4823,127 @@ name: lc domain: "0" } - } - param_decl: - { - SecMasking: "1" - SecSBoxImpl: aes_pkg::SBoxImplDom + rst_otp_ni: + { + name: lc_io + domain: "0" + } } clock_connections: { - clk_i: clkmgr_aon_clocks.clk_main_aes - clk_edn_i: clkmgr_aon_clocks.clk_main_aes + clk_i: clkmgr_aon_clocks.clk_main_acc + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + clk_otp_i: clkmgr_aon_clocks.clk_io_secure } memory: {} param_list: [ { - name: AES192Enable - desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192). - type: bit - default: 1'b1 - local: "false" - expose: "false" - name_top: AesAES192Enable - } - { - name: SecMasking - desc: - ''' - Disable (0) or enable (1) first-order masking of the AES cipher core. - Masking requires the use of a masked S-Box, see SecSBoxImpl parameter. - ''' + name: Stub + desc: Stub out the core of Acc logic type: bit - default: "1" + default: "0" local: "false" expose: "true" - name_top: SecAesMasking + name_top: AccStub } { - name: SecSBoxImpl - desc: Selection of the S-Box implementation. See aes_pkg.sv. - type: aes_pkg::sbox_impl_e - default: aes_pkg::SBoxImplDom + name: RegFile + desc: Selection of the register file implementation. See acc_pkg.sv. + type: acc_pkg::regfile_e + default: acc_pkg::RegFileFF local: "false" expose: "true" - name_top: SecAesSBoxImpl + name_top: AccRegFile } { - name: SecStartTriggerDelay + name: SecMuteUrnd desc: ''' - Manual start trigger delay, useful for SCA measurements. - A value of e.g. 40 allows the processor to go into sleep before AES starts operation. + If enabled (1), URND is advanced only when data is needed. + Disabled (0) by default. + Useful for SCA measurements only. ''' - type: int unsigned + type: bit default: "0" local: "false" expose: "true" - name_top: SecAesStartTriggerDelay + name_top: SecAccMuteUrnd } { - name: SecAllowForcingMasks + name: SecSkipUrndReseedAtStart desc: ''' - Forbid (0) or allow (1) forcing the masking PRNG output to a constant value via FORCE_MASKS bit in the Auxiliary Control Register. - Useful for SCA measurements. - Meaningful only if masking is enabled. + If enabled (1), URND reseed is skipped at the start of an operation. + Disabled (0) by default. + Useful for SCA measurements only. ''' type: bit - default: 1'b0 + default: "0" local: "false" expose: "true" - name_top: SecAesAllowForcingMasks + name_top: SecAccSkipUrndReseedAtStart } { - name: SecSkipPRNGReseeding - desc: - ''' - Perform (0) or skip (1) PRNG reseeding requests, useful for SCA measurements only. - The current SCA setup doesn't provide sufficient resources to implement the infrastructure required for PRNG reseeding (CSRNG, EDN). - To enable SCA resistance evaluations, we need to skip reseeding requests on the SCA platform. - ''' + name: AccPQCEn + desc: If enabled (1), vector ISA extension for PQC is enabled. type: bit - default: 1'b0 + default: "0" local: "false" expose: "true" - name_top: SecAesSkipPRNGReseeding + name_top: AccAccPQCEn } ] inter_signal_list: [ + { + name: acc_otp_key + struct: acc_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: acc + top_signame: otp_ctrl_acc_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn0_edn + index: 5 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: kmac_app + index: 4 + } { name: idle struct: mubi4 @@ -4902,11 +4951,67 @@ type: uni act: req width: 1 - inst_name: aes + inst_name: acc default: "" top_signame: clkmgr_aon_idle index: 0 } + { + name: ram_cfg_imem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: acc + default: "" + external: true + top_signame: acc_imem_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_dmem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: acc + default: "" + external: true + top_signame: acc_dmem_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_imem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: acc + default: "" + external: true + top_signame: acc_imem_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_dmem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: acc + default: "" + external: true + top_signame: acc_dmem_ram_1p_cfg_rsp + conn_type: false + index: -1 + } { name: lc_escalate_en struct: lc_tx @@ -4915,32 +5020,46 @@ act: rcv width: 1 default: lc_ctrl_pkg::Off - inst_name: aes + inst_name: acc top_signame: lc_ctrl_lc_escalate_en index: -1 } { - name: edn - struct: edn - package: edn_pkg - type: req_rsp + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni act: req width: 1 - inst_name: aes - default: "" - top_signame: edn0_edn - index: 4 + default: lc_ctrl_pkg::Off + inst_name: acc + end_idx: -1 + top_type: broadcast + top_signame: acc_lc_rma_ack + index: -1 } { name: keymgr_key - struct: hw_key_req + struct: acc_key_req package: keymgr_pkg type: uni act: rcv width: 1 - inst_name: aes + inst_name: acc default: "" - top_signame: keymgr_dpe_aes_key + top_signame: keymgr_dpe_acc_key index: -1 } { @@ -4950,10 +5069,10 @@ type: req_rsp act: rsp width: 1 - inst_name: aes + inst_name: acc default: "" end_idx: -1 - top_signame: aes_tl + top_signame: acc_tl index: -1 } ] @@ -4961,7 +5080,7 @@ { null: { - hart: 0x21100000 + hart: 0x22100000 } } generate_dif: true @@ -4971,11 +5090,12 @@ ] } { - name: hmac - type: hmac + name: aes + type: aes clock_srcs: { clk_i: main + clk_edn_i: main } clock_group: trans reset_connections: @@ -4985,33 +5105,217 @@ name: lc domain: "0" } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + param_decl: + { + SecMasking: "1" + SecSBoxImpl: aes_pkg::SBoxImplDom } clock_connections: { - clk_i: clkmgr_aon_clocks.clk_main_hmac + clk_i: clkmgr_aon_clocks.clk_main_aes + clk_edn_i: clkmgr_aon_clocks.clk_main_aes } - param_decl: {} memory: {} - param_list: [] - inter_signal_list: + param_list: [ { - name: idle - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: req - width: 1 - inst_name: hmac - default: "" - top_signame: clkmgr_aon_idle - index: 1 - } - { - name: tl - struct: tl - package: tlul_pkg - type: req_rsp + name: AES192Enable + desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192). + type: bit + default: 1'b1 + local: "false" + expose: "false" + name_top: AesAES192Enable + } + { + name: SecMasking + desc: + ''' + Disable (0) or enable (1) first-order masking of the AES cipher core. + Masking requires the use of a masked S-Box, see SecSBoxImpl parameter. + ''' + type: bit + default: "1" + local: "false" + expose: "true" + name_top: SecAesMasking + } + { + name: SecSBoxImpl + desc: Selection of the S-Box implementation. See aes_pkg.sv. + type: aes_pkg::sbox_impl_e + default: aes_pkg::SBoxImplDom + local: "false" + expose: "true" + name_top: SecAesSBoxImpl + } + { + name: SecStartTriggerDelay + desc: + ''' + Manual start trigger delay, useful for SCA measurements. + A value of e.g. 40 allows the processor to go into sleep before AES starts operation. + ''' + type: int unsigned + default: "0" + local: "false" + expose: "true" + name_top: SecAesStartTriggerDelay + } + { + name: SecAllowForcingMasks + desc: + ''' + Forbid (0) or allow (1) forcing the masking PRNG output to a constant value via FORCE_MASKS bit in the Auxiliary Control Register. + Useful for SCA measurements. + Meaningful only if masking is enabled. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecAesAllowForcingMasks + } + { + name: SecSkipPRNGReseeding + desc: + ''' + Perform (0) or skip (1) PRNG reseeding requests, useful for SCA measurements only. + The current SCA setup doesn't provide sufficient resources to implement the infrastructure required for PRNG reseeding (CSRNG, EDN). + To enable SCA resistance evaluations, we need to skip reseeding requests on the SCA platform. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecAesSkipPRNGReseeding + } + ] + inter_signal_list: + [ + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: aes + default: "" + top_signame: clkmgr_aon_idle + index: 1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aes + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: aes + default: "" + top_signame: edn0_edn + index: 4 + } + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: aes + default: "" + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aes + default: "" + end_idx: -1 + top_signame: aes_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21100000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: hmac + type: hmac + clock_srcs: + { + clk_i: main + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_hmac + } + param_decl: {} + memory: {} + param_list: [] + inter_signal_list: + [ + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: hmac + default: "" + top_signame: clkmgr_aon_idle + index: 2 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp act: rsp width: 1 inst_name: hmac @@ -5047,7 +5351,7 @@ kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgRomCtrl, - kmac_pkg::AppCfgOTBN} + kmac_pkg::AppCfgACC} ''' } clock_srcs: @@ -5154,7 +5458,7 @@ kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgRomCtrl, - kmac_pkg::AppCfgOTBN} + kmac_pkg::AppCfgACC} ''' local: "false" expose: "true" @@ -5216,341 +5520,37 @@ struct: mubi4 package: prim_mubi_pkg type: uni - act: req - width: 1 - inst_name: kmac - default: "" - top_signame: clkmgr_aon_idle - index: 2 - } - { - name: en_masking - struct: logic - type: uni - act: req - width: 1 - inst_name: kmac - default: "" - package: "" - end_idx: -1 - top_type: broadcast - top_signame: kmac_en_masking - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: kmac - top_signame: lc_ctrl_lc_escalate_en - index: -1 - } - { - name: tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: kmac - default: "" - end_idx: -1 - top_signame: kmac_tl - index: -1 - } - ] - base_addrs: - { - null: - { - hart: 0x21120000 - } - } - generate_dif: true - domain: - [ - "0" - ] - } - { - name: otbn - type: otbn - param_decl: - { - OtbnPQCEn: "0" - } - clock_srcs: - { - clk_i: - { - clock: main - group: trans - } - clk_edn_i: - { - clock: main - group: secure - } - clk_otp_i: - { - clock: io - group: secure - } - } - clock_group: trans - reset_connections: - { - rst_ni: - { - name: lc - domain: "0" - } - rst_edn_ni: - { - name: lc - domain: "0" - } - rst_otp_ni: - { - name: lc_io - domain: "0" - } - } - clock_connections: - { - clk_i: clkmgr_aon_clocks.clk_main_otbn - clk_edn_i: clkmgr_aon_clocks.clk_main_secure - clk_otp_i: clkmgr_aon_clocks.clk_io_secure - } - memory: {} - param_list: - [ - { - name: Stub - desc: Stub out the core of Otbn logic - type: bit - default: "0" - local: "false" - expose: "true" - name_top: OtbnStub - } - { - name: RegFile - desc: Selection of the register file implementation. See otbn_pkg.sv. - type: otbn_pkg::regfile_e - default: otbn_pkg::RegFileFF - local: "false" - expose: "true" - name_top: OtbnRegFile - } - { - name: SecMuteUrnd - desc: - ''' - If enabled (1), URND is advanced only when data is needed. - Disabled (0) by default. - Useful for SCA measurements only. - ''' - type: bit - default: "0" - local: "false" - expose: "true" - name_top: SecOtbnMuteUrnd - } - { - name: SecSkipUrndReseedAtStart - desc: - ''' - If enabled (1), URND reseed is skipped at the start of an operation. - Disabled (0) by default. - Useful for SCA measurements only. - ''' - type: bit - default: "0" - local: "false" - expose: "true" - name_top: SecOtbnSkipUrndReseedAtStart - } - { - name: OtbnPQCEn - desc: If enabled (1), vector ISA extension for PQC is enabled. - type: bit - default: "0" - local: "false" - expose: "true" - name_top: OtbnOtbnPQCEn - } - ] - inter_signal_list: - [ - { - name: otbn_otp_key - struct: otbn_otp_key - package: otp_ctrl_pkg - type: req_rsp - act: req - width: 1 - default: "'0" - inst_name: otbn - top_signame: otp_ctrl_otbn_otp_key - index: -1 - } - { - name: edn_rnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn1_edn - index: 0 - } - { - name: edn_urnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn0_edn - index: 5 - } - { - name: kmac_data - struct: app - package: kmac_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: kmac_app - index: 4 - } - { - name: idle - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: clkmgr_aon_idle - index: 3 - } - { - name: ram_cfg_imem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_imem_ram_1p_cfg - conn_type: false - index: -1 - } - { - name: ram_cfg_dmem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_dmem_ram_1p_cfg - conn_type: false - index: -1 - } - { - name: ram_cfg_rsp_imem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_imem_ram_1p_cfg_rsp - conn_type: false - index: -1 - } - { - name: ram_cfg_rsp_dmem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_dmem_ram_1p_cfg_rsp - conn_type: false - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_escalate_en - index: -1 - } - { - name: lc_rma_req - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv + act: req width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_flash_rma_req - index: -1 + inst_name: kmac + default: "" + top_signame: clkmgr_aon_idle + index: 3 } { - name: lc_rma_ack - struct: lc_tx - package: lc_ctrl_pkg + name: en_masking + struct: logic type: uni act: req width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn + inst_name: kmac + default: "" + package: "" end_idx: -1 top_type: broadcast - top_signame: otbn_lc_rma_ack + top_signame: kmac_en_masking index: -1 } { - name: keymgr_key - struct: otbn_key_req - package: keymgr_pkg + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg type: uni act: rcv width: 1 - inst_name: otbn - default: "" - top_signame: keymgr_dpe_otbn_key + default: lc_ctrl_pkg::Off + inst_name: kmac + top_signame: lc_ctrl_lc_escalate_en index: -1 } { @@ -5560,10 +5560,10 @@ type: req_rsp act: rsp width: 1 - inst_name: otbn + inst_name: kmac default: "" end_idx: -1 - top_signame: otbn_tl + top_signame: kmac_tl index: -1 } ] @@ -5571,7 +5571,7 @@ { null: { - hart: 0x22100000 + hart: 0x21120000 } } generate_dif: true @@ -5664,8 +5664,8 @@ index: -1 } { - name: otbn_key - struct: otbn_key_req + name: acc_key + struct: acc_key_req package: keymgr_pkg type: uni act: req @@ -5674,7 +5674,7 @@ default: "" end_idx: -1 top_type: broadcast - top_signame: keymgr_dpe_otbn_key + top_signame: keymgr_dpe_acc_key index: -1 } { @@ -11084,9 +11084,9 @@ ] lc_ctrl.lc_flash_rma_req: [ - otbn.lc_rma_req + acc.lc_rma_req ] - otbn.lc_rma_ack: + acc.lc_rma_ack: [ lc_ctrl.lc_flash_rma_ack ] @@ -11097,16 +11097,16 @@ kmac.entropy alert_handler.edn aes.edn - otbn.edn_urnd + acc.edn_urnd rv_core_ibex.edn ] edn1.edn: [ - otbn.edn_rnd + acc.edn_rnd ] - otp_ctrl.otbn_otp_key: + otp_ctrl.acc_otp_key: [ - otbn.otbn_otp_key + acc.acc_otp_key ] otp_ctrl.otp_keymgr_key: [ @@ -11120,9 +11120,9 @@ [ kmac.keymgr_key ] - keymgr_dpe.otbn_key: + keymgr_dpe.acc_key: [ - otbn.keymgr_key + acc.keymgr_key ] kmac.app: [ @@ -11130,7 +11130,7 @@ lc_ctrl.kmac_data rom_ctrl0.kmac_data rom_ctrl1.kmac_data - otbn.kmac_data + acc.kmac_data ] kmac.en_masking: [ @@ -11138,10 +11138,10 @@ ] clkmgr_aon.idle: [ + acc.idle aes.idle hmac.idle kmac.idle - otbn.idle ] otp_ctrl.otp_lc_data: [ @@ -11205,7 +11205,7 @@ [ aes.lc_escalate_en kmac.lc_escalate_en - otbn.lc_escalate_en + acc.lc_escalate_en otp_ctrl.lc_escalate_en sram_ctrl_main.lc_escalate_en sram_ctrl_ret_aon.lc_escalate_en @@ -11382,9 +11382,9 @@ [ main.tl_rv_plic ] - otbn.tl: + acc.tl: [ - main.tl_otbn + main.tl_acc ] keymgr_dpe.tl: [ @@ -11692,10 +11692,10 @@ sram_ctrl_main.cfg_rsp: sram_ctrl_main_ram_1p_cfg_rsp sram_ctrl_mbox.cfg: sram_ctrl_mbox_ram_1p_cfg sram_ctrl_mbox.cfg_rsp: sram_ctrl_mbox_ram_1p_cfg_rsp - otbn.ram_cfg_imem: otbn_imem_ram_1p_cfg - otbn.ram_cfg_rsp_imem: otbn_imem_ram_1p_cfg_rsp - otbn.ram_cfg_dmem: otbn_dmem_ram_1p_cfg - otbn.ram_cfg_rsp_dmem: otbn_dmem_ram_1p_cfg_rsp + acc.ram_cfg_imem: acc_imem_ram_1p_cfg + acc.ram_cfg_rsp_imem: acc_imem_ram_1p_cfg_rsp + acc.ram_cfg_dmem: acc_dmem_ram_1p_cfg + acc.ram_cfg_rsp_dmem: acc_dmem_ram_1p_cfg_rsp rv_core_ibex.ram_cfg_icache_tag: rv_core_ibex_icache_tag_ram_1p_cfg rv_core_ibex.ram_cfg_rsp_icache_tag: rv_core_ibex_icache_tag_ram_1p_cfg_rsp rv_core_ibex.ram_cfg_icache_data: rv_core_ibex_icache_data_ram_1p_cfg @@ -11842,7 +11842,7 @@ edn1 hmac rv_plic - otbn + acc keymgr_dpe kmac sram_ctrl_main.regs @@ -11880,7 +11880,7 @@ edn1 hmac rv_plic - otbn + acc keymgr_dpe kmac sram_ctrl_main.regs @@ -11907,7 +11907,7 @@ sram_ctrl_mbox.ram aes hmac - otbn + acc keymgr_dpe kmac soc_proxy.ctn @@ -12369,13 +12369,13 @@ pipeline: true } { - name: otbn + name: acc type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: false rsp_fifo_pass: false - inst_type: otbn + inst_type: acc addr_range: [ { @@ -13301,7 +13301,7 @@ index: -1 } { - name: tl_otbn + name: tl_acc struct: tl package: tlul_pkg type: req_rsp @@ -13309,7 +13309,7 @@ inst_name: main width: 1 default: "" - top_signame: otbn_tl + top_signame: acc_tl index: -1 } { @@ -17728,6 +17728,28 @@ lpg_name: secure_lc_0 lpg_idx: 13 } + { + name: acc_fatal + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: acc + desc: acc fatal alert + lpg_name: acc_trans_lc_0 + lpg_idx: 14 + } + { + name: acc_recov + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: acc + desc: acc recov alert + lpg_name: acc_trans_lc_0 + lpg_idx: 14 + } { name: aes_recov_ctrl_update_err width: 1 @@ -17737,7 +17759,7 @@ module_name: aes desc: aes recov_ctrl_update_err alert lpg_name: aes_trans_lc_0 - lpg_idx: 14 + lpg_idx: 15 } { name: aes_fatal_fault @@ -17748,7 +17770,7 @@ module_name: aes desc: aes fatal_fault alert lpg_name: aes_trans_lc_0 - lpg_idx: 14 + lpg_idx: 15 } { name: hmac_fatal_fault @@ -17759,7 +17781,7 @@ module_name: hmac desc: hmac fatal_fault alert lpg_name: hmac_trans_lc_0 - lpg_idx: 15 + lpg_idx: 16 } { name: kmac_recov_operation_err @@ -17770,7 +17792,7 @@ module_name: kmac desc: kmac recov_operation_err alert lpg_name: kmac_trans_lc_0 - lpg_idx: 16 + lpg_idx: 17 } { name: kmac_fatal_fault_err @@ -17781,28 +17803,6 @@ module_name: kmac desc: kmac fatal_fault_err alert lpg_name: kmac_trans_lc_0 - lpg_idx: 16 - } - { - name: otbn_fatal - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: otbn - desc: otbn fatal alert - lpg_name: otbn_trans_lc_0 - lpg_idx: 17 - } - { - name: otbn_recov - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: otbn - desc: otbn recov alert - lpg_name: otbn_trans_lc_0 lpg_idx: 17 } { @@ -18844,6 +18844,18 @@ plic: rv_plic outgoing: false } + { + name: acc_done + width: 1 + type: interrupt + module_name: acc + desc: acc done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } { name: hmac_hmac_done width: 1 @@ -18916,18 +18928,6 @@ plic: rv_plic outgoing: false } - { - name: otbn_done - width: 1 - type: interrupt - module_name: otbn - desc: otbn done interrupt - intr_type: IntrType.Event - default_val: false - incoming: false - plic: rv_plic - outgoing: false - } { name: keymgr_dpe_op_done width: 1 @@ -19525,10 +19525,10 @@ sram_ctrl_ret_aon rv_dm rv_plic + acc aes hmac kmac - otbn keymgr_dpe csrng entropy_src @@ -19734,47 +19734,47 @@ alert_handler[24]: fatal_fault ] } - module_aes: + module_acc: { tx_expr: alert_tx[26:25] rx_expr: alert_rx[26:25] async_expr: alert_handler_reg_pkg::AsyncOn[26:25] comments: [ - alert_handler[25]: recov_ctrl_update_err - alert_handler[26]: fatal_fault + alert_handler[25]: fatal + alert_handler[26]: recov ] } - module_hmac: + module_aes: { - tx_expr: alert_tx[27:27] - rx_expr: alert_rx[27:27] - async_expr: alert_handler_reg_pkg::AsyncOn[27:27] + tx_expr: alert_tx[28:27] + rx_expr: alert_rx[28:27] + async_expr: alert_handler_reg_pkg::AsyncOn[28:27] comments: [ - alert_handler[27]: fatal_fault + alert_handler[27]: recov_ctrl_update_err + alert_handler[28]: fatal_fault ] } - module_kmac: + module_hmac: { - tx_expr: alert_tx[29:28] - rx_expr: alert_rx[29:28] - async_expr: alert_handler_reg_pkg::AsyncOn[29:28] + tx_expr: alert_tx[29:29] + rx_expr: alert_rx[29:29] + async_expr: alert_handler_reg_pkg::AsyncOn[29:29] comments: [ - alert_handler[28]: recov_operation_err - alert_handler[29]: fatal_fault_err + alert_handler[29]: fatal_fault ] } - module_otbn: + module_kmac: { tx_expr: alert_tx[31:30] rx_expr: alert_rx[31:30] async_expr: alert_handler_reg_pkg::AsyncOn[31:30] comments: [ - alert_handler[30]: fatal - alert_handler[31]: recov + alert_handler[30]: recov_operation_err + alert_handler[31]: fatal_fault_err ] } module_keymgr_dpe: @@ -20051,9 +20051,9 @@ spi_host0 pwrmgr_aon aon_timer_aon + acc hmac kmac - otbn keymgr_dpe csrng entropy_src @@ -20402,7 +20402,7 @@ } } { - name: aes_trans_lc_0 + name: acc_trans_lc_0 clock_group: { name: trans @@ -20411,13 +20411,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_aes + clock_connection: clkmgr_aon_clocks.clk_main_acc unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -20427,7 +20427,7 @@ } } { - name: hmac_trans_lc_0 + name: aes_trans_lc_0 clock_group: { name: trans @@ -20436,13 +20436,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_hmac + clock_connection: clkmgr_aon_clocks.clk_main_aes unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -20452,7 +20452,7 @@ } } { - name: kmac_trans_lc_0 + name: hmac_trans_lc_0 clock_group: { name: trans @@ -20461,13 +20461,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_kmac + clock_connection: clkmgr_aon_clocks.clk_main_hmac unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -20477,7 +20477,7 @@ } } { - name: otbn_trans_lc_0 + name: kmac_trans_lc_0 clock_group: { name: trans @@ -20486,13 +20486,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_otbn + clock_connection: clkmgr_aon_clocks.clk_main_kmac unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -21080,9 +21080,9 @@ index: -1 } { - name: otbn_otp_key - desc: Key derivation interface for OTBN scrambling devices. - struct: otbn_otp_key + name: acc_otp_key + desc: Key derivation interface for ACC scrambling devices. + struct: acc_otp_key package: otp_ctrl_pkg type: req_rsp act: rsp @@ -21090,7 +21090,7 @@ default: "'0" inst_name: otp_ctrl end_idx: -1 - top_signame: otp_ctrl_otbn_otp_key + top_signame: otp_ctrl_acc_otp_key index: -1 } { @@ -21626,7 +21626,7 @@ width: 2 default: lc_ctrl_pkg::On inst_name: lc_ctrl - top_signame: otbn_lc_rma_ack + top_signame: acc_lc_rma_ack index: -1 } { @@ -23305,85 +23305,264 @@ type: req_rsp act: req width: 1 - inst_name: rv_dm + inst_name: rv_dm + default: "" + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: mem_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_mem_tl_d + index: -1 + } + { + name: dbg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_dbg_tl_d + index: -1 + } + { + name: irq + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_irq + index: -1 + } + { + name: irq_id + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + index: -1 + } + { + name: msip + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_msip + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_plic + default: "" + end_idx: -1 + top_signame: rv_plic_tl + index: -1 + } + { + name: acc_otp_key + struct: acc_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: acc + top_signame: otp_ctrl_acc_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn0_edn + index: 5 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: kmac_app + index: 4 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: acc + default: "" + top_signame: clkmgr_aon_idle + index: 0 + } + { + name: ram_cfg_imem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: acc default: "" - top_signame: main_tl_rv_dm__sba + external: true + top_signame: acc_imem_ram_1p_cfg + conn_type: false index: -1 } { - name: regs_tl_d - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp + name: ram_cfg_dmem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv width: 1 - inst_name: rv_dm + inst_name: acc default: "" - end_idx: -1 - top_signame: rv_dm_regs_tl_d + external: true + top_signame: acc_dmem_ram_1p_cfg + conn_type: false index: -1 } { - name: mem_tl_d - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp + name: ram_cfg_rsp_imem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req width: 1 - inst_name: rv_dm + inst_name: acc default: "" - end_idx: -1 - top_signame: rv_dm_mem_tl_d + external: true + top_signame: acc_imem_ram_1p_cfg_rsp + conn_type: false index: -1 } { - name: dbg_tl_d - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp + name: ram_cfg_rsp_dmem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req width: 1 - inst_name: rv_dm + inst_name: acc default: "" - end_idx: -1 - top_signame: rv_dm_dbg_tl_d + external: true + top_signame: acc_dmem_ram_1p_cfg_rsp + conn_type: false index: -1 } { - name: irq - struct: logic + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg type: uni - act: req + act: rcv width: 1 - inst_name: rv_plic - default: "" - package: "" - end_idx: -1 - top_type: broadcast - top_signame: rv_plic_irq + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_escalate_en index: -1 } { - name: irq_id - struct: logic + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg type: uni - act: req + act: rcv width: 1 - inst_name: rv_plic + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_flash_rma_req index: -1 } { - name: msip - struct: logic + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg type: uni act: req width: 1 - inst_name: rv_plic - default: "" - package: "" + default: lc_ctrl_pkg::Off + inst_name: acc end_idx: -1 top_type: broadcast - top_signame: rv_plic_msip + top_signame: acc_lc_rma_ack + index: -1 + } + { + name: keymgr_key + struct: acc_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: acc + default: "" + top_signame: keymgr_dpe_acc_key index: -1 } { @@ -23393,10 +23572,10 @@ type: req_rsp act: rsp width: 1 - inst_name: rv_plic + inst_name: acc default: "" end_idx: -1 - top_signame: rv_plic_tl + top_signame: acc_tl index: -1 } { @@ -23409,7 +23588,7 @@ inst_name: aes default: "" top_signame: clkmgr_aon_idle - index: 0 + index: 1 } { name: lc_escalate_en @@ -23470,7 +23649,7 @@ inst_name: hmac default: "" top_signame: clkmgr_aon_idle - index: 1 + index: 2 } { name: tl @@ -23543,7 +23722,7 @@ inst_name: kmac default: "" top_signame: clkmgr_aon_idle - index: 2 + index: 3 } { name: en_masking @@ -23584,185 +23763,6 @@ top_signame: kmac_tl index: -1 } - { - name: otbn_otp_key - struct: otbn_otp_key - package: otp_ctrl_pkg - type: req_rsp - act: req - width: 1 - default: "'0" - inst_name: otbn - top_signame: otp_ctrl_otbn_otp_key - index: -1 - } - { - name: edn_rnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn1_edn - index: 0 - } - { - name: edn_urnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn0_edn - index: 5 - } - { - name: kmac_data - struct: app - package: kmac_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: kmac_app - index: 4 - } - { - name: idle - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: clkmgr_aon_idle - index: 3 - } - { - name: ram_cfg_imem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_imem_ram_1p_cfg - conn_type: false - index: -1 - } - { - name: ram_cfg_dmem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_dmem_ram_1p_cfg - conn_type: false - index: -1 - } - { - name: ram_cfg_rsp_imem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_imem_ram_1p_cfg_rsp - conn_type: false - index: -1 - } - { - name: ram_cfg_rsp_dmem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - external: true - top_signame: otbn_dmem_ram_1p_cfg_rsp - conn_type: false - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_escalate_en - index: -1 - } - { - name: lc_rma_req - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_flash_rma_req - index: -1 - } - { - name: lc_rma_ack - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: req - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - end_idx: -1 - top_type: broadcast - top_signame: otbn_lc_rma_ack - index: -1 - } - { - name: keymgr_key - struct: otbn_key_req - package: keymgr_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - top_signame: keymgr_dpe_otbn_key - index: -1 - } - { - name: tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: otbn - default: "" - end_idx: -1 - top_signame: otbn_tl - index: -1 - } { name: edn struct: edn @@ -23804,8 +23804,8 @@ index: -1 } { - name: otbn_key - struct: otbn_key_req + name: acc_key + struct: acc_key_req package: keymgr_pkg type: uni act: req @@ -23814,7 +23814,7 @@ default: "" end_idx: -1 top_type: broadcast - top_signame: keymgr_dpe_otbn_key + top_signame: keymgr_dpe_acc_key index: -1 } { @@ -27244,7 +27244,7 @@ index: -1 } { - name: tl_otbn + name: tl_acc struct: tl package: tlul_pkg type: req_rsp @@ -27252,7 +27252,7 @@ inst_name: main width: 1 default: "" - top_signame: otbn_tl + top_signame: acc_tl index: -1 } { @@ -28175,50 +28175,50 @@ { package: prim_ram_1p_pkg struct: ram_1p_cfg - signame: otbn_imem_ram_1p_cfg_i + signame: acc_imem_ram_1p_cfg_i width: 1 type: uni default: "" direction: in conn_type: false index: -1 - netname: otbn_imem_ram_1p_cfg + netname: acc_imem_ram_1p_cfg } { package: prim_ram_1p_pkg struct: ram_1p_cfg_rsp - signame: otbn_imem_ram_1p_cfg_rsp_o + signame: acc_imem_ram_1p_cfg_rsp_o width: 1 type: uni default: "" direction: out conn_type: false index: -1 - netname: otbn_imem_ram_1p_cfg_rsp + netname: acc_imem_ram_1p_cfg_rsp } { package: prim_ram_1p_pkg struct: ram_1p_cfg - signame: otbn_dmem_ram_1p_cfg_i + signame: acc_dmem_ram_1p_cfg_i width: 1 type: uni default: "" direction: in conn_type: false index: -1 - netname: otbn_dmem_ram_1p_cfg + netname: acc_dmem_ram_1p_cfg } { package: prim_ram_1p_pkg struct: ram_1p_cfg_rsp - signame: otbn_dmem_ram_1p_cfg_rsp_o + signame: acc_dmem_ram_1p_cfg_rsp_o width: 1 type: uni default: "" direction: out conn_type: false index: -1 - netname: otbn_dmem_ram_1p_cfg_rsp + netname: acc_dmem_ram_1p_cfg_rsp } { package: prim_ram_1p_pkg @@ -29691,7 +29691,7 @@ { package: lc_ctrl_pkg struct: lc_tx - signame: otbn_lc_rma_ack + signame: acc_lc_rma_ack width: 1 type: uni end_idx: -1 @@ -29745,8 +29745,8 @@ } { package: otp_ctrl_pkg - struct: otbn_otp_key_req - signame: otp_ctrl_otbn_otp_key_req + struct: acc_otp_key_req + signame: otp_ctrl_acc_otp_key_req width: 1 type: req_rsp end_idx: -1 @@ -29756,8 +29756,8 @@ } { package: otp_ctrl_pkg - struct: otbn_otp_key_rsp - signame: otp_ctrl_otbn_otp_key_rsp + struct: acc_otp_key_rsp + signame: otp_ctrl_acc_otp_key_rsp width: 1 type: req_rsp end_idx: -1 @@ -29800,14 +29800,14 @@ } { package: keymgr_pkg - struct: otbn_key_req - signame: keymgr_dpe_otbn_key + struct: acc_key_req + signame: keymgr_dpe_acc_key width: 1 type: uni end_idx: -1 act: req suffix: "" - default: keymgr_pkg::OTBN_KEY_REQ_DEFAULT + default: keymgr_pkg::ACC_KEY_REQ_DEFAULT } { package: kmac_pkg @@ -30734,7 +30734,7 @@ { package: tlul_pkg struct: tl_h2d - signame: otbn_tl_req + signame: acc_tl_req width: 1 type: req_rsp end_idx: -1 @@ -30745,7 +30745,7 @@ { package: tlul_pkg struct: tl_d2h - signame: otbn_tl_rsp + signame: acc_tl_rsp width: 1 type: req_rsp end_idx: -1 diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson index ab31985032e..01bcdce37ab 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.secrets.testing.gen.hjson @@ -47,7 +47,7 @@ randcount: 40 randtype: data name_top: RndCnstOtpCtrlLfsrSeed - default: 0xa1c8ef1830 + default: 0x3065f53e38 randwidth: 40 } { @@ -57,7 +57,7 @@ randcount: 40 randtype: perm name_top: RndCnstOtpCtrlLfsrPerm - default: 0x3569628c371948e0086c13e45c241428c1938452de9d16951181e67dd809 + default: 0x2575209c7852a49cf4c72166467cd4153899848635205c36016cb44c89a randwidth: 240 } { @@ -67,7 +67,7 @@ randcount: 256 randtype: data name_top: RndCnstOtpCtrlScrmblKeyInit - default: 0xd6780626a12b5904a9b37439f8177d19d04d3fad040ed02909a9ea4b5429b9e6 + default: 0x2cc1ed9bec346650d956b1fdcfcdaa8510f4abd3bbe952c4c216b6840c8c08a6 randwidth: 256 } { @@ -2988,7 +2988,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivInvalid - default: 0xd20b07721f7ff507ad2b9fb9cc7ff06 + default: 0xf7ae497edb550d6780626a12b5904a9 randwidth: 128 } { @@ -2998,7 +2998,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivTestUnlocked - default: 0xe4c72c47d9e15fa8ff9f82833e32c151 + default: 0xb37439f8177d19d04d3fad040ed02909 randwidth: 128 } { @@ -3008,7 +3008,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivDev - default: 0xd2fd2987e3062f6119c7560acbbe9f6f + default: 0xa9ea4b5429b9e60d20b07721f7ff507a randwidth: 128 } { @@ -3018,7 +3018,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivProduction - default: 0xffc2171a49199bb53d8e0daa8f0578db + default: 0xd2b9fb9cc7ff06e4c72c47d9e15fa8ff randwidth: 128 } { @@ -3028,7 +3028,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivRma - default: 0xaa5f022791480b4e709e0f80976e0966 + default: 0x9f82833e32c151d2fd2987e3062f6119 randwidth: 128 } { @@ -3038,7 +3038,7 @@ randcount: 1024 randtype: data name_top: RndCnstLcCtrlInvalidTokens - default: 0x1357e13758a3e2211e20faa36d00779eb2cff38b90adf94a0675da263541c78aa9dc0c623c09ee7fd16a6687d3a1b4e21456518ea00db8f75489d932535fcb7684ed330ad9aa219ea28bfb6fda16a61bbeacddc922169858a90a977c043eb407a7042544ef79b15f8dbe9946ed90adafccedc18c38ae4473e404d38a4d2302a + default: 0xc7560acbbe9f6fffc2171a49199bb53d8e0daa8f0578dbaa5f022791480b4e709e0f80976e096601357e13758a3e2211e20faa36d00779eb2cff38b90adf94a0675da263541c78aa9dc0c623c09ee7fd16a6687d3a1b4e21456518ea00db8f75489d932535fcb7684ed330ad9aa219ea28bfb6fda16a61bbeacddc922169858a randwidth: 1024 } ] @@ -3063,7 +3063,7 @@ randcount: 32 randtype: data name_top: RndCnstAlertHandlerLfsrSeed - default: 0x295c50f4 + default: 0x90a977c0 randwidth: 32 } { @@ -3073,7 +3073,7 @@ randcount: 32 randtype: perm name_top: RndCnstAlertHandlerLfsrPerm - default: 0xca09b9e222b820ced83f7979e4e9c3952a6534eb + default: 0x28174b98f0c5999e6c95d44616c8534abce7ffa8 randwidth: 160 } ] @@ -3114,7 +3114,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetAonSramKey - default: 0xd6c33dcd8c46c8180da77f58394513f2 + default: 0xa8a0911970ac4838b2c251c9b9a2dbe2 randwidth: 128 } { @@ -3124,7 +3124,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetAonSramNonce - default: 0xabb1b3744276549afd120e862d3419d9 + default: 0x29a87db11e1e16111c07365cb738535a randwidth: 128 } { @@ -3134,7 +3134,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlRetAonLfsrSeed - default: 0xccfb691a3e5d0916 + default: 0x96aad6c33dcd8c46 randwidth: 64 } { @@ -3144,11 +3144,56 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlRetAonLfsrPerm - default: 0xde14097a1d4c397d0af43ca4a7bb1597bdaa5bd7822ab7b44d54b87df2291d0a0dc1a199bf4ec73224ecc41be8f660c + default: 0x2bbc20e236efa36794225ad207f7008939c9eb9c6e1d992dd183050973fc6be34b87dde657341dd6ca8444e59fa431b2 randwidth: 384 } ] } + { + name: acc + type: acc + base_addrs: + { + null: + { + hart: 0x22100000 + } + } + memory: {} + param_list: + [ + { + name: RndCnstUrndPrngSeed + desc: Default seed of the PRNG used for URND. + type: acc_pkg::urnd_prng_seed_t + randcount: 256 + randtype: data + name_top: RndCnstAccUrndPrngSeed + default: 0xcd45c60d144177e89f75139f749de9b374a3636a66f969aea3e98fc6f4892beb + randwidth: 256 + } + { + name: RndCnstAccKey + desc: Compile-time random reset value for IMem/DMem scrambling key. + type: otp_ctrl_pkg::acc_key_t + randcount: 128 + randtype: data + name_top: RndCnstAccAccKey + default: 0x458d5b4bd644e79a35d690bbb852739d + randwidth: 128 + } + { + name: RndCnstAccNonce + desc: Compile-time random reset value for IMem/DMem scrambling nonce. + type: otp_ctrl_pkg::acc_nonce_t + randcount: 64 + randtype: data + name_top: RndCnstAccAccNonce + default: 0xc155fec8b9a9ca90 + randwidth: 64 + } + ] + } { name: aes type: aes @@ -3169,7 +3214,7 @@ randcount: 64 randtype: data name_top: RndCnstAesClearingLfsrSeed - default: 0xb852739dc155fec8 + default: 0xafaa4655965a49d1 randwidth: 64 } { @@ -3179,7 +3224,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingLfsrPerm - default: 0xb43a6878187c6372714364fbccb31f29de2010615c1e636f6633b90b5522eacf67fdb0083d7c1ad125a5551fab932aae + default: 0xbd8d049a41be7f3f680fb06da47563e1370a860165e9d59e43130934bdacfeb66e3aa4424948b5dfc9f96c0c883d7c1a randwidth: 384 } { @@ -3189,7 +3234,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingSharePerm - default: 0xe67dc05448a1a0af54e3245e8c3fdb3d731d4c7bc521865027e19aeacc7682606bcfcc0248ba5f3a591cab5b6eed6374 + default: 0xd23336895fdb16ac70def229e54b005d1c9309ce180d6b4fcc774a799384d508493466a8f6e967f0b920981eab7fe4bb randwidth: 384 } { @@ -3199,7 +3244,7 @@ randcount: 288 randtype: data name_top: RndCnstAesMaskingLfsrSeed - default: 0xb80b1581ba47b081edad7956485909768ef3dba808cbc6d57fe7489f41549870395c90d9 + default: 0xcbc6d57fe7489f41549870395c90d9abf4e0f5ed5ba097b3ba3ccf06d21e513960c35528 randwidth: 288 } { @@ -3209,7 +3254,7 @@ randcount: 160 randtype: perm name_top: RndCnstAesMaskingLfsrPerm - default: 0x842e70641d6b4c9d696c09038062541c1b5231460b4f1f858f203a0a22137a3b253f872b2753245f0267379f7e639c2f953d3565689b1a3249734507365e6a087d42342a7983238b764a18989916217f936117404b304e6677780c4829929a71158c81108e0e9012593874055d0f6e1944049e1456338d4d72573e8a967b41886d91016f26947500110d898243505c587c475a2c2d8628556039511e063c975b + default: 0x8061271d536b0b52815b200744953b7e9994658d2b453a9f03258e0a70139a3e6277876a1b14545e0f2e08913690712472027a313f8f3d416c63062f4637681e1c3c35648a3278607693424f342a4a4c664919238c5f5718848573391621929d7417404b304e797b4d557f0c48296e699c510415968b10980e8812593856055d1f330928677d1a9783226d9b016f269e7500110d898243505c587c475a2c2d86 randwidth: 1280 } ] @@ -3234,7 +3279,7 @@ randcount: 288 randtype: data name_top: RndCnstKmacLfsrSeed - default: 0xd09377df413b2b191272161213b80315a177c7516ecd4b002af6b49253ad7151c8e8f1a5 + default: 0x315a177c7516ecd4b002af6b49253ad7151c8e8f1a51fd184abfa40d2cd2d16f3d54d9d randwidth: 288 } { @@ -3244,7 +3289,7 @@ randcount: 800 randtype: perm name_top: RndCnstKmacLfsrPerm - default: 0xbe81cbd13e35b1e8c41583e5ca8284870362f98735253bf17d9aae9b01932ea9f6d4d8200dca924b89aeb3fc6e946ff28263228adafec52a2b884ea90f27c0e583ac5b40c010734b1275ac32df811ec2c5432829a50ee8c251e3b3e52c4a3b6981b882198371887705454408cddd6c7179820470a074ac44758b66a55b5c6ec7faac75c71a452967cec2b25a2aa983499e9ac241f89a334136b94f23e36a54b000dafc30d93223e27205715fb63e7f7e9c44722d47e433faf501c7a0d21586dba3d8fc428a413d21b5ec94486d6161757459a41354588db9e6107c3a33dd450db30bd968bc9378828346838a0bd634c71ecabaa1949e8b2311f47bca54b08441e93263197244518164ac8b56c22e3d46b2e199496df91a6d5027116a016c9a2389ecc39d855c49a68545ac2a6e083a9d2e60afe905e8b04c248931175743be217320c43e18564d50b4a682ede600a1a6dc16f71b2eccc80d728884ba3920c3d035a1c8b355362ae3199df4a85005adb3b8a3ab80849dcf9755e8dd7f7d85cbc865941021546a6a97cc085e421349deed895c358a7438da399de63a46f05270add47b3259c407d16d107ce1e4346c374f23de490d41d09872519148f55a66e69324863a2da342c6a509737d00809ed0654eb3852267040495ca49ad596aa35c872e64e530db31532ad952961e005c22ba21a23a992043f2fd6a2a41ab1313700774245f3c5a7105b6ae9773eea56a2348e1fc9f960aac059a1419ca5768288792a272d92844624e6781e43d66a756048b8e40b745ce28864a2d79ba9ea3d151a14f345d95a869738142c690418e6cacd4ab751d4e82bab5581a089c25bf74dd22ddeb6ae2c908e1932ee97f0b612733a80e83a3a1d6be462244fd73391195d9a44cc8c5b074b28965d456c28ca8f2765e11a2444c8adeeb91f76869e7a598301d0b95385a58b03ce500a4747b16242dc22101820337d55f9296d46d66136d23c264841912bddeb4609ae5f10dee6bc47088c3852411b4c7c764a7934d31e31d0c54ba02d04c0ed00154a3cf9446b5a289536806b8a823ae2a16163958820b2a608186ac13cb0d2f006b4011894b6e089f1f914c66f8f863229a1d28a24239e70696d3b19d7009666b63088cb0110cc149a55c02163e9dc7843e6404207ac7be6c81d90c44c4a0b956c0c69419b9439557c80dbbc2737a14c7009032f8b65b714d5093d4502a812ced43f505796651ce9626ebc978570a6afaf707729f0214c3671c6a196f121c7491377e6d5b589e9104e2f13d87f11520e65f9235ba4079e9c676f3585bc9217bb2d8e119fdbf57a42ef79ec9fa366e536e1c3654bda6f768e781944338619f5d576d888fe628d630a8d9759c21c51bb24851062bbbc0ae801ffbee9d4d8b48487f + default: 0x3f2076c6cd702cf984c7be6258f0f53f9b42f9d7070945ce6d8a1b6602d3056b34a8ecb1176c41a7bfd40292396a08f2287e67d0a7a1358e97cb0a880f1160d880480397e9b8a2d82628300414384a3ebfa95a65ecc48328369311c3b1b89a3d9e2a425dc0d6206e432b63b9f193aae311023679aa82da631c58f829314b044760cb47f026a4b104d6b77ddd2a2eb8ad573724ec6cd64a57469ac109298280d9ab6877310f78c0387237c7194ad4b0271cd20ed1b4b162aac53449d496460a92201ef10d2184f9c2a245d2b0c23344f3fe24b6cba4606d7ae1e990599f93f4708d9c5b307c3a89a94745120bd9eafdc424cd80a1e45c9992f51960cc81ecab68ad0908b231153ab1f82962033c845fec3261ac53c453486066eb62d6df805c31acb86c92b962c094b098f45aa9e04b8a4138a2dc3ea2574ef1267fc7daa151714b9071eae9a6cd4752744561b6b4d50b4a661dae9a8a1a7a02716a02eccca460f8d04bbbe8fc4d0397e03739596f60b1995ebb45005ab03b8a3ac80849ee79816485585c745cc006594d021546a5f5bac185e421349e996889cb5a2ee38d5ba5def3a46f05273a11476925cc507d16d107f2214346c374f23de4c0d41d09872519146955a68e6c324863a2de341fb8689737d00815f60654e91c52266800495c7a9b5596ae35c872e651530db31532ae98d54a837061905c22bb21d23ac92043f2fd6a2a41ab2317720774245f3c5af1060eaf9773eea96c21373ce48b16085c059ad41c365a6830ea0aa67b59295c624e6f81e43d66a786048b8300b925d628864a397992df33d1519a4f345d95a969a381429a10418ef4add4abf51d4e9e00aeb156068226596fdd3748b77d1ab8be7738670bc9fe8cd849d8ea03a119d475b8d21725332316c1d2ce2597515a3832b08c6578468911322e7bae87dda1a85e9660c07429f4e16962c0f394029291e9c890b8088406080cdf557e4d5b51b5984db68f099e10644af77ad9826ca7c437baaf51c2230e149046d71f1d929e5034c782d03152ec6b51303b400552923e511ae6fa254da01ae6a14eb8a85858e562082caa82061ab44f2c74bc01ae0046252db92271fe45319be3e18c8a68a4a28c08e79c2a5b4ec675c02599adcc3232c14433052695704858fa771e10f9901081ec6ae5b3076431131282e55b071a6a4419b9439557c80dbcc2737a144d809032fcb75b714d5093d4502a812ced83f505796651ce9626ebc978570a6afaf70b729f0214c3671c6a196f121c7491377e6d5b589e9104e2f13d87f15520e65f9235ba4079e9c676f7585bc9217bb2d8e119fdc057a42f1e9ec9fa366e536e1c4654bda6f768e781944338619f5d576d888fe628d630a8d9759c21c61bb24851062bbbc0ae801ffbee9d randwidth: 8000 } { @@ -3269,51 +3314,6 @@ } ] } - { - name: otbn - type: otbn - base_addrs: - { - null: - { - hart: 0x22100000 - } - } - memory: {} - param_list: - [ - { - name: RndCnstUrndPrngSeed - desc: Default seed of the PRNG used for URND. - type: otbn_pkg::urnd_prng_seed_t - randcount: 256 - randtype: data - name_top: RndCnstOtbnUrndPrngSeed - default: 0xf463ef2fdff5f6dddc13ecc2583d51fedb1b6197dcbb40dec2a9fe69fab1eb9e - randwidth: 256 - } - { - name: RndCnstOtbnKey - desc: Compile-time random reset value for IMem/DMem scrambling key. - type: otp_ctrl_pkg::otbn_key_t - randcount: 128 - randtype: data - name_top: RndCnstOtbnOtbnKey - default: 0xe13c367895adefd6dbb19e7a24526b82 - randwidth: 128 - } - { - name: RndCnstOtbnNonce - desc: Compile-time random reset value for IMem/DMem scrambling nonce. - type: otp_ctrl_pkg::otbn_nonce_t - randcount: 64 - randtype: data - name_top: RndCnstOtbnOtbnNonce - default: 0x5bb435ed63d9513e - randwidth: 64 - } - ] - } { name: keymgr_dpe type: keymgr_dpe @@ -3334,7 +3334,7 @@ randcount: 64 randtype: data name_top: RndCnstKeymgrDpeLfsrSeed - default: 0x488f3ffa7700ec4c + default: 0xf463ef2fdff5f6dd randwidth: 64 } { @@ -3344,7 +3344,7 @@ randcount: 64 randtype: perm name_top: RndCnstKeymgrDpeLfsrPerm - default: 0x8df69cd71b07313bf8070a19f1492984a5ee7449fd9a0e903858ada8603fcc8574df65897986f23eb0e52fe091e4ded2 + default: 0x87eb6290a74b0f14c2cdb5cc7154858c123f66800e7d1a479b8bfd832e49af4d5e37a9ec6aaf10ba5606d943d6c3b137 randwidth: 384 } { @@ -3354,7 +3354,7 @@ randcount: 32 randtype: perm name_top: RndCnstKeymgrDpeRandPerm - default: 0xb70fadc45465678f050f9100557f374c1c36f4cb + default: 0xe5e9e327784327ab15ebe924dfbb3038a2155460 randwidth: 160 } { @@ -3364,7 +3364,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeRevisionSeed - default: 0x7b416b49b114f994a969864a57c3482ab3bdcbd9fe825728f7ba40a22c9719c5 + default: 0xbc99a2c9ff8d13e6e3c95b9f3b64c45930f2e8ff6a1d7485e74bb8805c552e9e randwidth: 256 } { @@ -3374,7 +3374,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeSoftOutputSeed - default: 0xd7c160f492d0e8757631ebf752a1e5604e2d6171f5dba9ec4249052dcc7a4d58 + default: 0x2301f1821969975992ad61b349807084ebb1b47b416b49b114f994a969864a randwidth: 256 } { @@ -3384,7 +3384,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeHardOutputSeed - default: 0x4d57ac27843ea2a0163efeda5b24d93f97d62d99c960542f4a1f2595192e9a96 + default: 0x57c3482ab3bdcbd9fe825728f7ba40a22c9719c5d7c160f492d0e8757631ebf7 randwidth: 256 } { @@ -3394,7 +3394,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeAesSeed - default: 0x9a885419a9d57e36519fa42d20efa348cb77f5089a8381b62d9717b3647e5ce0 + default: 0x52a1e5604e2d6171f5dba9ec4249052dcc7a4d584d57ac27843ea2a0163efeda randwidth: 256 } { @@ -3404,17 +3404,17 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeKmacSeed - default: 0x796ca68aa29523d3f94f27c74acae76b3e145326741f804e3c3a3451469c6118 + default: 0x5b24d93f97d62d99c960542f4a1f2595192e9a969a885419a9d57e36519fa42d randwidth: 256 } { - name: RndCnstOtbnSeed - desc: Compile-time random bits for generation seed when otbn destination selected + name: RndCnstAccSeed + desc: Compile-time random bits for generation seed when acc destination selected type: keymgr_pkg::seed_t randcount: 256 randtype: data - name_top: RndCnstKeymgrDpeOtbnSeed - default: 0xfa23bc32e428ad2be2584fe8d5491fa8e7f19aaa4133ad0d2704702ae2ff9d98 + name_top: RndCnstKeymgrDpeAccSeed + default: 0x20efa348cb77f5089a8381b62d9717b3647e5ce0796ca68aa29523d3f94f27c7 randwidth: 256 } { @@ -3424,7 +3424,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrDpeNoneSeed - default: 0x49fcb59874cddc9cbc645d9e02a96b9980911844d3c74de85e05164b829d484b + default: 0x4acae76b3e145326741f804e3c3a3451469c6118fa23bc32e428ad2be2584fe8 randwidth: 256 } ] @@ -3449,7 +3449,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivNonProduction - default: 0xd447c9d7611999ca523b11575a82d625ea331f0dd07b9876a95d48469d8be58d526100d826ebf4137728e993b979b05b + default: 0xd5491fa8e7f19aaa4133ad0d2704702ae2ff9d9849fcb59874cddc9cbc645d9e02a96b9980911844d3c74de85e05164b randwidth: 384 } { @@ -3459,7 +3459,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivProduction - default: 0xddc26ccb34aab93413f8b7dc7cc8c4bfdb394d03e99a0dae61eaf3b64effa6de29a9812ffd69dd7a95a3e3c99e381a97 + default: 0x829d484bd447c9d7611999ca523b11575a82d625ea331f0dd07b9876a95d48469d8be58d526100d826ebf4137728e993 randwidth: 384 } ] @@ -3499,7 +3499,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramKey - default: 0x68c85f002483aafa2a1b591a4617b8f7 + default: 0xb979b05bddc26ccb34aab93413f8b7dc randwidth: 128 } { @@ -3509,7 +3509,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramNonce - default: 0xe2806138001d6ec345718e6e7248d8d8 + default: 0x7cc8c4bfdb394d03e99a0dae61eaf3b6 randwidth: 128 } { @@ -3519,7 +3519,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlMainLfsrSeed - default: 0x5f141c915c06870e + default: 0x4effa6de29a9812f randwidth: 64 } { @@ -3529,7 +3529,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlMainLfsrPerm - default: 0x1db66b08cfe8d13f76590967b339b77953df7790c1d57a63bd4108aa1b8660e80b27ce3003ee9c49aec5911c6d8b228d + default: 0xf343ec70c754559884c6d4e123da41423cd20c22ef7cd9a4e9b1f0d98b8546b5b52aa809017e7eec63a7cb8a257b76bf randwidth: 384 } ] @@ -3569,7 +3569,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMboxSramKey - default: 0xdeaeb4eea0ba96ff2b3eb56debdbc1b3 + default: 0x61cdb1a7ca1990bff0b4c0f1a0cc87ef randwidth: 128 } { @@ -3579,7 +3579,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMboxSramNonce - default: 0xb6ed4daf88e9ea4f8051d088092fb879 + default: 0xc382b123a4e4bd1153024473bbd5fa0e randwidth: 128 } { @@ -3589,7 +3589,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlMboxLfsrSeed - default: 0xffd7e8265faf402c + default: 0x188ebef945f9d57d randwidth: 64 } { @@ -3599,7 +3599,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlMboxLfsrPerm - default: 0x112d94a4693327d966cbe2cde270f0ac5bad1f7d686ea5d166c0957b1300213fd0ed671a63ad1f7413a284af0f839be3 + default: 0x342d7e8793192674af0cec5fa631ec79c215f44997170d37520ca2e1b3ca97ff36433b80ed6afa45891a4c6a01b4b76a randwidth: 384 } ] @@ -3639,7 +3639,7 @@ randcount: 64 randtype: data name_top: RndCnstRomCtrl0ScrNonce - default: 0xa553e45bab60fd5 + default: 0xac8feb4f2302c232 randwidth: 64 } { @@ -3649,7 +3649,7 @@ randcount: 128 randtype: data name_top: RndCnstRomCtrl0ScrKey - default: 0x30ae84156d37cc68063276f9e85faee1 + default: 0xc482d07b560a3d678fb9a9dc420a1339 randwidth: 128 } ] @@ -3689,7 +3689,7 @@ randcount: 64 randtype: data name_top: RndCnstRomCtrl1ScrNonce - default: 0x29ae80f5b440dc77 + default: 0xb243bb28853b19b5 randwidth: 64 } { @@ -3699,7 +3699,7 @@ randcount: 128 randtype: data name_top: RndCnstRomCtrl1ScrKey - default: 0x9649127ec56c7b0e9645bf231b5b37b8 + default: 0xc399d4da9b067ed9be1d5753ffd02f20 randwidth: 128 } ] @@ -3724,7 +3724,7 @@ randcount: 32 randtype: data name_top: RndCnstRvCoreIbexLfsrSeed - default: 0xc5559aee + default: 0xf4e52516 randwidth: 32 } { @@ -3734,7 +3734,7 @@ randcount: 32 randtype: perm name_top: RndCnstRvCoreIbexLfsrPerm - default: 0x3ac764379b5401824b549f991766e9119f5e97e1 + default: 0x74a8bedc9c896dadcd8368a06c20ea0d5e0ffb29 randwidth: 160 } { @@ -3744,7 +3744,7 @@ randcount: 128 randtype: data name_top: RndCnstRvCoreIbexIbexKeyDefault - default: 0x8afd1f07532671eb83c820e1f1eaa3a1 + default: 0x49127ec56c7b0e9645bf231b5b37b8c5 randwidth: 128 } { @@ -3754,7 +3754,7 @@ randcount: 64 randtype: data name_top: RndCnstRvCoreIbexIbexNonceDefault - default: 0x8ad34d471b199cfd + default: 0x559aee0d0e2f2dab randwidth: 64 } ] diff --git a/hw/top_darjeeling/data/chip_conn_testplan.hjson b/hw/top_darjeeling/data/chip_conn_testplan.hjson index 457f8f746d4..5d1970db770 100644 --- a/hw/top_darjeeling/data/chip_conn_testplan.hjson +++ b/hw/top_darjeeling/data/chip_conn_testplan.hjson @@ -156,8 +156,8 @@ name: ast_dft_ram_1p_cfg desc: '''Verify ast model's single port configuration bits are connected to the single port RAMs in the following blocks: - - otbn_imem - - otbn_dmem + - acc_imem + - acc_dmem - rv_core_ibex_tag0 - rv_core_ibex_tag1 - rv_core_ibex_data0 @@ -167,8 +167,8 @@ - rom ''' stage: V2 - tests: ["ast_dft_otbn_imem_ram_1p_cfg", - "ast_dft_otbn_dmem_ram_1p_cfg", + tests: ["ast_dft_acc_imem_ram_1p_cfg", + "ast_dft_acc_dmem_ram_1p_cfg", "ast_dft_rv_core_ibex_tag0_ram_1p_cfg", "ast_dft_rv_core_ibex_tag1_ram_1p_cfg", "ast_dft_rv_core_ibex_data0_ram_1p_cfg", @@ -310,7 +310,7 @@ - index 0 to aes's `idle_o` - index 1 to hmac's `idle_o` - index 2 to kmac's `idle_o` - - index 3 to otbn's `idle_o` + - index 3 to acc's `idle_o` ''' stage: V2 tests: ["clkmgr_idle0", "clkmgr_idle1", "clkmgr_idle2", "clkmgr_idle3"] @@ -479,7 +479,7 @@ input: - alert_handler clk_i - lc_ctrl clk_i - - otbn clk_otp_i + - acc clk_otp_i - otp_ctrl clk_i - pwrmgr clk_lc_i - rv_core_ibex clk_esc_i @@ -489,7 +489,7 @@ stage: V2 tests: ["clkmgr_secure_clk_alert_handler_clk", "clkmgr_secure_clk_lc_ctrl_clk", - "clkmgr_secure_clk_otbn_otp_clk", + "clkmgr_secure_clk_acc_otp_clk", "clkmgr_secure_clk_otp_ctrl_clk", "clkmgr_secure_clk_rv_core_ibex_clk", "clkmgr_secure_clk_rv_core_ibex_otp_clk", @@ -506,7 +506,7 @@ - keymgr clk_i - keymgr clk_edn_i - lc_ctrl clk_kmac_i - - otbn clk_edn_i + - acc clk_edn_i - otp_ctrl clk_edn_i - rv_plic clk_i ''' @@ -518,7 +518,7 @@ "clkmgr_secure_clk_keymgr_clk", "clkmgr_secure_clk_keymgr_edn_clk", "clkmgr_secure_clk_lc_ctrl_kmac_clk", - "clkmgr_secure_clk_otbn_edn_clk", + "clkmgr_secure_clk_acc_edn_clk", "clkmgr_secure_clk_otp_ctrl_edn_clk", "clkmgr_secure_clk_rv_plic_clk"] tags: ["conn"] @@ -583,10 +583,10 @@ tags: ["conn"] } { - name: clk_main_otbn - desc: '''Verify clkmgr's clk_main_otbn is connected to otbn's clk_i.''' + name: clk_main_acc + desc: '''Verify clkmgr's clk_main_acc is connected to acc's clk_i.''' stage: V2 - tests: ["clkmgr_trans_otbn"] + tests: ["clkmgr_trans_acc"] tags: ["conn"] } @@ -639,7 +639,7 @@ - flash_ctrl - aes - kmac - - otbn + - acc ''' stage: V2 tests: ["lc_escalate_en_otp", @@ -649,7 +649,7 @@ "lc_escalate_en_flash", "lc_escalate_en_aes", "lc_escalate_en_kmac", - "lc_escalate_en_otbn"] + "lc_escalate_en_acc"] tags: ["conn"] } { @@ -697,13 +697,13 @@ tags: ["conn"] } { - name: lc_flash_otbn_rma + name: lc_flash_acc_rma desc: "Verify lc_ctrl's RMA request connections." stage: V2 tests: ["lc_rma_seed_flash_ctrl", "lc_rma_req_flash_ctrl", - "flash_ctrl_rma_ack_otbn", - "otbn_rma_ack_lc"] + "flash_ctrl_rma_ack_acc", + "acc_rma_ack_lc"] tags: ["conn"] } { @@ -823,7 +823,7 @@ desc: '''Verify rstmgr's rst_lc_io_n[1] is connected to the following: - alert_handler's rst_ni - lc_ctrl's rst_ni - - otbn's rst_otp_ni + - acc's rst_otp_ni - otp_ctrl's rst_ni - pwrmgr's rst_lc_ni - rv_core_ibex's rst_esc_ni @@ -833,7 +833,7 @@ stage: V2 tests: ["rstmgr_lc_io_d0_alert_handler_rst_ni", "rstmgr_lc_io_d0_lc_ctrl_rst_ni", - "rstmgr_lc_io_d0_otbn_rst_otp_ni", + "rstmgr_lc_io_d0_acc_rst_otp_ni", "rstmgr_lc_io_d0_otp_ctrl_rst_ni", "rstmgr_lc_io_d0_rv_core_ibex_rst_esc_ni", "rstmgr_lc_io_d0_rv_core_ibex_rst_otp_ni", @@ -984,8 +984,8 @@ - keymgr's rst_ni - kmac's rst_edn_ni - kmac's rst_ni - - otbn's rst_edn_ni - - otbn's rst_ni + - acc's rst_edn_ni + - acc's rst_ni - lc_ctrl's rst_kmac_ni - otp_ctrl's rst_edn_ni - rv_core_ibex's rst_edn_ni @@ -1007,8 +1007,8 @@ "rstmgr_sys_d0_keymgr_rst_ni", "rstmgr_sys_d0_kmac_rst_edn_ni", "rstmgr_sys_d0_kmac_rst_ni", - "rstmgr_sys_d0_otbn_rst_edn_ni", - "rstmgr_sys_d0_otbn_rst_ni", + "rstmgr_sys_d0_acc_rst_edn_ni", + "rstmgr_sys_d0_acc_rst_ni", "rstmgr_sys_d0_lc_ctrl_rst_kmac_ni", "rstmgr_sys_d0_otp_ctrl_rst_edn_ni", "rstmgr_sys_d0_rv_core_ibex_rst_edn_ni", diff --git a/hw/top_darjeeling/data/chip_testplan.hjson b/hw/top_darjeeling/data/chip_testplan.hjson index bf6b5f52b0d..4f47974290d 100644 --- a/hw/top_darjeeling/data/chip_testplan.hjson +++ b/hw/top_darjeeling/data/chip_testplan.hjson @@ -438,7 +438,7 @@ Verify accessibility of all the memories in the chip over JTAG. This test will target the following memories in the chip: - sram_main, sram_ret, otbn i|dmem, ROM + sram_main, sram_ret, acc i|dmem, ROM - Shuffle the list of memories first to remove the effect of ordering. - Write a location in a randomly chosen set of addresses within each memory via JTAG @@ -714,7 +714,7 @@ tests: ["chip_sw_aes_idle", "chip_sw_hmac_enc_idle", "chip_sw_kmac_idle", - "chip_sw_otbn_randomness"] + "chip_sw_acc_randomness"] } { name: chip_sw_clkmgr_off_trans @@ -731,7 +731,7 @@ tests: ["chip_sw_clkmgr_off_aes_trans", "chip_sw_clkmgr_off_hmac_trans", "chip_sw_clkmgr_off_kmac_trans", - "chip_sw_clkmgr_off_otbn_trans"] + "chip_sw_clkmgr_off_acc_trans"] } { name: chip_sw_clkmgr_off_peri @@ -756,7 +756,7 @@ ''' stage: V2 tests: ["chip_sw_clkmgr_jitter", - "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_acc_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", "chip_sw_keymgr_dpe_key_derivation_jitter_en", @@ -779,14 +779,14 @@ Test the following functionalities with reduced clock: - - AES, HMAC, KMAC and OTBN operations + - AES, HMAC, KMAC and ACC operations - Keymgr key derivation - Scramble-enabled access from the main SRAM - Csrng edn concurrency ''' stage: V2 tests: ["chip_sw_clkmgr_jitter_reduced_freq", - "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq", + "chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq", "chip_sw_aes_enc_jitter_en_reduced_freq", "chip_sw_hmac_enc_jitter_en_reduced_freq", "chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq", @@ -1526,7 +1526,7 @@ /////////////////////////////////////////////////////// // Security Peripherals // - // AES, HMAC, KMAC, CSRNG, ENTROPY_SRC, KEYMGR, OTBN // + // AES, HMAC, KMAC, CSRNG, ENTROPY_SRC, KEYMGR, ACC // /////////////////////////////////////////////////////// // AES (pre-verified IP) integration tests: @@ -1783,7 +1783,7 @@ - Have each EDN instance issue an instantiate, reseed and generate command to CSRNG. - On each command done, verify the reception of edn cmd req done interrupt. - - Run OTBN randomness test to test the output from EDN0 and EDN1. + - Run ACC randomness test to test the output from EDN0 and EDN1. - Check the data returned to EDN via connectivity assertion checks. ''' stage: V2 @@ -1911,16 +1911,16 @@ tests: ["chip_sw_keymgr_sideload_aes"] } { - name: chip_sw_keymgr_sideload_otbn - desc: '''Verify the keymgr sideload interface to OTBN. + name: chip_sw_keymgr_sideload_acc + desc: '''Verify the keymgr sideload interface to ACC. - Load OTBN binary image, the rest is similar to `chip_keymgr_sideload_kmac`, except - sideloading to otbn. + Load ACC binary image, the rest is similar to `chip_keymgr_sideload_kmac`, except + sideloading to acc. Clear the sideload key once done. ''' stage: V2 - tests: ["chip_sw_keymgr_sideload_otbn"] + tests: ["chip_sw_keymgr_sideload_acc"] } { name: chip_sw_keymgr_sideload_kmac_error @@ -1940,73 +1940,73 @@ tests: [] } - // OTBN (pre-verified IP) integration tests: + // ACC (pre-verified IP) integration tests: { - name: chip_sw_otbn_op - desc: '''Verify an OTBN operation. + name: chip_sw_acc_op + desc: '''Verify an ACC operation. - - SW test directs the OTBN engine to perform an ECDSA operation. - - SW validates the reception of the otbn done interrupt once the operation is complete. + - SW test directs the ACC engine to perform an ECDSA operation. + - SW validates the reception of the acc done interrupt once the operation is complete. - SW verifies the correctness of the result with the expected value which is pre-computed using a reference model. ''' stage: V2 - tests: ["chip_sw_otbn_ecdsa_op_irq", - "chip_sw_otbn_ecdsa_op_irq_jitter_en"] + tests: ["chip_sw_acc_ecdsa_op_irq", + "chip_sw_acc_ecdsa_op_irq_jitter_en"] } { - name: chip_sw_otbn_rnd_entropy - desc: '''Verify OTBN can fetch RND numbers from the entropy src. + name: chip_sw_acc_rnd_entropy + desc: '''Verify ACC can fetch RND numbers from the entropy src. - SW initializes the entropy subsystem to generate randomness. - - SW loads an OTBN app that executes instructions to read the RND bits. - - The OTBN app ensures that the values when read consecutively do not match, and it's + - SW loads an ACC app that executes instructions to read the RND bits. + - The ACC app ensures that the values when read consecutively do not match, and it's not all 0s or all 1s, as a basic measure to ensure that the entropy subsystem is returning some data. ''' stage: V2 - tests: ["chip_sw_otbn_randomness"] + tests: ["chip_sw_acc_randomness"] } { - name: chip_sw_otbn_urnd_entropy - desc: '''Verify OTBN can fetch URND numbers from the entropy src. + name: chip_sw_acc_urnd_entropy + desc: '''Verify ACC can fetch URND numbers from the entropy src. - - Similar to chip_otbn_rnd_entropy, but verifies the URND bits. + - Similar to chip_acc_rnd_entropy, but verifies the URND bits. ''' stage: V2 - tests: ["chip_sw_otbn_randomness"] + tests: ["chip_sw_acc_randomness"] } { - name: chip_sw_otbn_idle - desc: '''Verify the OTBN idle signal to clkmgr. + name: chip_sw_acc_idle + desc: '''Verify the ACC idle signal to clkmgr. - - Write the OTBN clk hint to 0 within clkmgr to indicate OTBN clk can be gated - and verify that the OTBN clk hint status within clkmgr reads 0 (OTBN is disabled). - - Write the OTBN clk hint to 1 within clkmgr to indicate OTBN clk can be enabled. - Verify that the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled). - - Start an OTBN operation, write the OTBN clk hint to 0 within clkmgr and verify that - the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled) before the - OTBN operation is complete. - - After the OTBN operation is complete, verify that the OTBN clk hint status within - clkmgr now reads 0 again (OTBN is disabled). - - Write the OTBN clk hint to 1, read and check the OTBN output for correctness. + - Write the ACC clk hint to 0 within clkmgr to indicate ACC clk can be gated + and verify that the ACC clk hint status within clkmgr reads 0 (ACC is disabled). + - Write the ACC clk hint to 1 within clkmgr to indicate ACC clk can be enabled. + Verify that the ACC clk hint status within clkmgr reads 1 (ACC is enabled). + - Start an ACC operation, write the ACC clk hint to 0 within clkmgr and verify that + the ACC clk hint status within clkmgr reads 1 (ACC is enabled) before the + ACC operation is complete. + - After the ACC operation is complete, verify that the ACC clk hint status within + clkmgr now reads 0 again (ACC is disabled). + - Write the ACC clk hint to 1, read and check the ACC output for correctness. ''' stage: V2 - tests: ["chip_sw_otbn_randomness"] + tests: ["chip_sw_acc_randomness"] } { - name: chip_sw_otbn_mem_scramble - desc: '''Verify the OTBN can receive keys from the OTP to scramble the OTBN imem and dmem. + name: chip_sw_acc_mem_scramble + desc: '''Verify the ACC can receive keys from the OTP to scramble the ACC imem and dmem. - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already done by the test_rom startup code). - Extract random address offsets from RV_CORE_IBEX_RND_DATA. - - Wait for OTBN to be idle. - - Write random address offsets in OTBN imem and dmem. + - Wait for ACC to be idle. + - Write random address offsets in ACC imem and dmem. - Read back the written address offsets and compare against expected values. All values must match, no integrity errors must be triggered. - - Have OTBN fetch new keys and nonces from the OTP_CTRL. - - Wait for OTBN to be idle. + - Have ACC fetch new keys and nonces from the OTP_CTRL. + - Wait for ACC to be idle. - Read back the written address offsets. Most reads should trigger integrity errors. It is possible that after re-scrambling the integrity bits are still valid. But this is expected to happen rarely. If the number of observed integrity errors is below a @@ -2015,7 +2015,7 @@ (unique, non-zero data). ''' stage: V2 - tests: ["chip_sw_otbn_mem_scramble"] + tests: ["chip_sw_acc_mem_scramble"] } ///////////////////////////////////////////////////// @@ -2170,20 +2170,20 @@ desc: '''Verify the proliferation of keys to security peripherals. - Verify the correctness of keys provided to SRAM ctrl (main & ret), flash ctrl, keymgr, - (note that keymgr does not have handshake), OTBN and the CPU instruction cache. + (note that keymgr does not have handshake), ACC and the CPU instruction cache. - Ensure that the test requests a new key and verifies the previously written data to an address now returns a garbage value. X-ref'ed with the following IP tests that consume these signals: - chip_sw_sram_scrambled_access - chip_sw_keymgr_key_derivation - - chip_sw_otbn_mem_scramble + - chip_sw_acc_mem_scramble ''' stage: V2 tests: [// Verifies both, main and retention SRAM scrambling. "chip_sw_sram_ctrl_scrambled_access", "chip_sw_keymgr_dpe_key_derivation", - "chip_sw_otbn_mem_scramble", + "chip_sw_acc_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] } { @@ -2191,12 +2191,12 @@ desc: '''Verify the entropy interface from OTP ctrl to EDN. This is X-ref'ed with the chip_otp_ctrl_keys test, which needs to handshake with the EDN - to receive some entropy bits before the keys for SRAM ctrl and OTBN are computed. + to receive some entropy bits before the keys for SRAM ctrl and ACC are computed. ''' stage: V2 tests: ["chip_sw_sram_ctrl_scrambled_access", "chip_sw_keymgr_dpe_key_derivation", - "chip_sw_otbn_mem_scramble", + "chip_sw_acc_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] } { @@ -2401,7 +2401,7 @@ ''' stage: V2 tests: ["chip_sw_clkmgr_jitter", - "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_acc_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", "chip_sw_keymgr_dpe_key_derivation_jitter_en", @@ -2667,7 +2667,7 @@ "chip_sw_gpio_smoketest", "chip_sw_hmac_smoketest", "chip_sw_kmac_smoketest", - "chip_sw_otbn_smoketest", + "chip_sw_acc_smoketest", "chip_sw_otp_ctrl_smoketest", "chip_sw_pwrmgr_smoketest", "chip_sw_rv_plic_smoketest", @@ -2827,7 +2827,7 @@ RAW_UNLOCK mode of operation. - Switch TAP interface to rv_dm and configure the ROM_EXEC_EN OTP to enable ROM execution. - - If running with the production ROM, enable signature verification via OTBN to + - If running with the production ROM, enable signature verification via ACC to improve simulation time. - Perform POR to apply OTP changes. - With rv_dm TAP still selected, switch to external clock via clkmgr using extclk @@ -2856,11 +2856,11 @@ Blocks / functionality to run simultaneously in this test: - - Staggered activation of OTBN, aes, KMAC/HMAC. + - Staggered activation of ACC, aes, KMAC/HMAC. - KMAC / aes would need to take turns being fed data - KMAC activation should be a combination of otp background, key manager background and software - - for OTBN, any signature verification / signing event is sufficient + - for ACC, any signature verification / signing event is sufficient - Entropy complex ongoing - reseed / update operation ongoing - Flash scramble ongoing (ideally both instruction and data, but data should be sufficient diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson index 8935493e045..551f5a61ee5 100644 --- a/hw/top_darjeeling/data/top_darjeeling.hjson +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -227,7 +227,7 @@ "rv_plic", "aes", "hmac", - "otbn", + "acc", "keymgr_dpe" "csrng", "entropy_src", @@ -674,6 +674,31 @@ attr: "ipgen", targets: ["rv_core_ibex"] }, + { name: "acc", + type: "acc", + param_decl: { + AccPQCEn: "0" + } + clock_srcs: { + clk_i: { + clock: "main", + group: "trans" + }, + clk_edn_i: { + clock: "main", + group: "secure" + }, + clk_otp_i: { + clock: "io", + group: "secure" + }, + }, + clock_group: "trans", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc", rst_otp_ni: "lc_io"}, + base_addr: { + hart: "0x22100000", + }, + }, { name: "aes", type: "aes", clock_srcs: {clk_i: "main", clk_edn_i: "main"}, @@ -701,7 +726,7 @@ param_decl: { EnMasking: "1", NumAppIntf: 5, - AppCfg: "'{kmac_pkg::AppCfgKeyMgr,\n kmac_pkg::AppCfgLcCtrl,\n kmac_pkg::AppCfgRomCtrl,\n kmac_pkg::AppCfgRomCtrl,\n kmac_pkg::AppCfgOTBN}" + AppCfg: "'{kmac_pkg::AppCfgKeyMgr,\n kmac_pkg::AppCfgLcCtrl,\n kmac_pkg::AppCfgRomCtrl,\n kmac_pkg::AppCfgRomCtrl,\n kmac_pkg::AppCfgACC}" } clock_srcs: {clk_i: "main", clk_edn_i: "main"} clock_group: "trans" @@ -710,31 +735,6 @@ hart: "0x21120000", } }, - { name: "otbn", - type: "otbn", - param_decl: { - OtbnPQCEn: "0" - } - clock_srcs: { - clk_i: { - clock: "main", - group: "trans" - }, - clk_edn_i: { - clock: "main", - group: "secure" - }, - clk_otp_i: { - clock: "io", - group: "secure" - }, - }, - clock_group: "trans", - reset_connections: {rst_ni: "lc", rst_edn_ni: "lc", rst_otp_ni: "lc_io"}, - base_addr: { - hart: "0x22100000", - }, - }, { name: "keymgr_dpe", type: "keymgr_dpe", clock_srcs: {clk_i: "main", clk_edn_i: "main"}, @@ -1216,26 +1216,26 @@ 'spi_host0.lsio_trigger' : ['soc_proxy.spi_host_lsio_trigger'], 'uart0.lsio_trigger' : ['soc_proxy.uart_lsio_trigger'], - // LC RMA req/ack interface: LC -> OTBN + // LC RMA req/ack interface: LC -> ACC // Note: this RoT configuration has no embedded flash, hence - // the RMA request is just routed to OTBN directly. - 'lc_ctrl.lc_flash_rma_req' : ['otbn.lc_rma_req'], - 'otbn.lc_rma_ack' : ['lc_ctrl.lc_flash_rma_ack'], + // the RMA request is just routed to ACC directly. + 'lc_ctrl.lc_flash_rma_req' : ['acc.lc_rma_req'], + 'acc.lc_rma_ack' : ['lc_ctrl.lc_flash_rma_ack'], // Edn connections 'edn0.edn' : ['keymgr_dpe.edn', 'otp_ctrl.edn', 'kmac.entropy', - 'alert_handler.edn', 'aes.edn', 'otbn.edn_urnd', + 'alert_handler.edn', 'aes.edn', 'acc.edn_urnd', 'rv_core_ibex.edn'], - 'edn1.edn' : ['otbn.edn_rnd'], + 'edn1.edn' : ['acc.edn_rnd'], - // OTBN OTP scramble key - 'otp_ctrl.otbn_otp_key' : ['otbn.otbn_otp_key'], + // ACC OTP scramble key + 'otp_ctrl.acc_otp_key' : ['acc.acc_otp_key'], // KeyMgr Sideload & KDF function 'otp_ctrl.otp_keymgr_key' : ['keymgr_dpe.otp_key'], 'keymgr_dpe.aes_key' : ['aes.keymgr_key'], 'keymgr_dpe.kmac_key' : ['kmac.keymgr_key'], - 'keymgr_dpe.otbn_key' : ['otbn.keymgr_key'], + 'keymgr_dpe.acc_key' : ['acc.keymgr_key'], // KMAC Application Interface // Note that arbitration is fixed priority top to bottom. @@ -1243,7 +1243,7 @@ 'lc_ctrl.kmac_data', // LC needs to be at index 1 'rom_ctrl0.kmac_data', // ROM needs to be at index 2 or 3 'rom_ctrl1.kmac_data', // ROM needs to be at index 2 or 3 - 'otbn.kmac_data'], // OTBN needs to be at index 4 + 'acc.kmac_data'], // ACC needs to be at index 4 'kmac.en_masking' : ['keymgr_dpe.kmac_en_masking'] // The idle connection is automatically connected through topgen. @@ -1284,7 +1284,7 @@ 'lc_ctrl.lc_keymgr_en' : ['keymgr_dpe.lc_keymgr_en'], 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en', 'kmac.lc_escalate_en', - 'otbn.lc_escalate_en', + 'acc.lc_escalate_en', 'otp_ctrl.lc_escalate_en', 'sram_ctrl_main.lc_escalate_en', 'sram_ctrl_ret_aon.lc_escalate_en', @@ -1392,10 +1392,10 @@ 'sram_ctrl_main.cfg_rsp' : 'sram_ctrl_main_ram_1p_cfg_rsp', 'sram_ctrl_mbox.cfg' : 'sram_ctrl_mbox_ram_1p_cfg', 'sram_ctrl_mbox.cfg_rsp' : 'sram_ctrl_mbox_ram_1p_cfg_rsp', - 'otbn.ram_cfg_imem' : 'otbn_imem_ram_1p_cfg', - 'otbn.ram_cfg_rsp_imem' : 'otbn_imem_ram_1p_cfg_rsp', - 'otbn.ram_cfg_dmem' : 'otbn_dmem_ram_1p_cfg', - 'otbn.ram_cfg_rsp_dmem' : 'otbn_dmem_ram_1p_cfg_rsp', + 'acc.ram_cfg_imem' : 'acc_imem_ram_1p_cfg', + 'acc.ram_cfg_rsp_imem' : 'acc_imem_ram_1p_cfg_rsp', + 'acc.ram_cfg_dmem' : 'acc_dmem_ram_1p_cfg', + 'acc.ram_cfg_rsp_dmem' : 'acc_dmem_ram_1p_cfg_rsp', 'rv_core_ibex.ram_cfg_icache_tag' : 'rv_core_ibex_icache_tag_ram_1p_cfg', 'rv_core_ibex.ram_cfg_rsp_icache_tag' : 'rv_core_ibex_icache_tag_ram_1p_cfg_rsp', 'rv_core_ibex.ram_cfg_icache_data' : 'rv_core_ibex_icache_data_ram_1p_cfg', diff --git a/hw/top_darjeeling/data/xbar_main.hjson b/hw/top_darjeeling/data/xbar_main.hjson index ba00a1c0c15..f4db3cd0d3d 100644 --- a/hw/top_darjeeling/data/xbar_main.hjson +++ b/hw/top_darjeeling/data/xbar_main.hjson @@ -165,7 +165,7 @@ req_fifo_pass: false, rsp_fifo_pass: false, }, - { name: "otbn", + { name: "acc", type: "device", clock: "clk_main_i" reset: "rst_main_ni" @@ -375,7 +375,7 @@ "rom_ctrl0.rom", "rom_ctrl0.regs", "rom_ctrl1.rom", "rom_ctrl1.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "peri", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", - "rv_plic", "otbn", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", + "rv_plic", "acc", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", "rv_core_ibex.cfg", "sram_ctrl_mbox.ram", "sram_ctrl_mbox.regs", "soc_proxy.ctn", "soc_proxy.core", "dma", "mbx0.core", "mbx1.core", "mbx2.core", "mbx3.core", "mbx4.core", "mbx5.core", "mbx6.core", @@ -385,7 +385,7 @@ "rom_ctrl0.rom", "rom_ctrl0.regs", "rom_ctrl1.rom", "rom_ctrl1.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "peri", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", - "rv_plic", "otbn", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", + "rv_plic", "acc", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", "rv_core_ibex.cfg", "sram_ctrl_mbox.ram", "sram_ctrl_mbox.regs", "soc_proxy.ctn", "soc_proxy.core", "dma", "mbx0.core", "mbx1.core", "mbx2.core", "mbx3.core", "mbx4.core", "mbx5.core", "mbx6.core", @@ -395,7 +395,7 @@ // but without ROM0/1 and RV_DM. dma.host: [ "sram_ctrl_main.ram", "sram_ctrl_mbox.ram", - "aes", "hmac", "otbn", "keymgr_dpe", "kmac", + "aes", "hmac", "acc", "keymgr_dpe", "kmac", "soc_proxy.ctn", "peri" ], mbx0.sram: [ diff --git a/hw/top_darjeeling/doc/datasheet.md b/hw/top_darjeeling/doc/datasheet.md index afb88288c64..fba35586fd9 100644 --- a/hw/top_darjeeling/doc/datasheet.md +++ b/hw/top_darjeeling/doc/datasheet.md @@ -65,7 +65,7 @@ The following table provides a more detailed summary of the supported features:
  • AES-128/192/256 with ECB/CBC/CFB/OFB/CTR modes
  • HMAC / SHA2-256, 384, 512
  • KMAC / SHA3-224, 256, 384, 512, [c]SHAKE-128, 256
    • -
  • Programmable big number accelerator for RSA and ECC (OTBN)
    • +
  • Programmable big number accelerator for RSA and ECC (ACC)
  • NIST-compliant cryptographically secure random number generator (CSRNG)
  • Entropy source, with FIPS- and CC-compliant health checks, which can be bypassed depending on the properties of the connected digital noise source
  • Key manager with DICE & DPE support
    • @@ -121,7 +121,7 @@ The following table provides a more detailed summary of the supported features:
    • Boot ROM code implementing secure boot, including owner-approved second signing, and chip configuration
    • Bare metal top-level tests
      • -
    • OpenTitan Crypto Library with OTBN accelerated standard algorithms for
      • +
    • OpenTitan Crypto Library with ACC accelerated standard algorithms for
      • RSA 2K, 3K, 4K
      • ECC with NIST P256/P384, Brainpool P256r1 or X25519/Ed25519
        • diff --git a/hw/top_darjeeling/doc/memory_map.md b/hw/top_darjeeling/doc/memory_map.md index c41184b383a..99828b630c8 100644 --- a/hw/top_darjeeling/doc/memory_map.md +++ b/hw/top_darjeeling/doc/memory_map.md @@ -35,10 +35,10 @@ The main address space, shared between the CPU and DM | rv_dm | regs | `0x21200000` | `0x10` | `0x4` | regs device on rv_dm | | rv_dm | mem | `0x40000` | `0x1000` | `0x400` | mem device on rv_dm | | rv_plic | default | `0x28000000` | `0x8000000` | `0x2000000` | rv_plic | +| acc | default | `0x22100000` | `0x20000` | `0x8000` | acc | | aes | default | `0x21100000` | `0x100` | `0x40` | aes | | hmac | default | `0x21110000` | `0x2000` | `0x800` | hmac | | kmac | default | `0x21120000` | `0x1000` | `0x400` | kmac | -| otbn | default | `0x22100000` | `0x20000` | `0x8000` | otbn | | keymgr_dpe | default | `0x21140000` | `0x100` | `0x40` | keymgr_dpe | | csrng | default | `0x21150000` | `0x80` | `0x20` | csrng | | entropy_src | default | `0x21160000` | `0x100` | `0x40` | entropy_src | diff --git a/hw/top_darjeeling/dv/autogen/tb__alert_handler_connect.sv b/hw/top_darjeeling/dv/autogen/tb__alert_handler_connect.sv index e42deaf899e..be867555df7 100644 --- a/hw/top_darjeeling/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_darjeeling/dv/autogen/tb__alert_handler_connect.sv @@ -29,13 +29,13 @@ assign alert_if[21].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[0]; assign alert_if[22].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; assign alert_if[23].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0]; assign alert_if[24].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; -assign alert_if[25].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; -assign alert_if[26].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; -assign alert_if[27].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; -assign alert_if[28].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; -assign alert_if[29].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; -assign alert_if[30].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[31].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[25].alert_tx = `CHIP_HIER.u_acc.alert_tx_o[0]; +assign alert_if[26].alert_tx = `CHIP_HIER.u_acc.alert_tx_o[1]; +assign alert_if[27].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[28].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[29].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[30].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[31].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; assign alert_if[32].alert_tx = `CHIP_HIER.u_keymgr_dpe.alert_tx_o[0]; assign alert_if[33].alert_tx = `CHIP_HIER.u_keymgr_dpe.alert_tx_o[1]; assign alert_if[34].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; diff --git a/hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv index b7ed9c70256..a9bfdc95b3d 100644 --- a/hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv @@ -62,7 +62,7 @@ tl_if csrng_tl_if(clk_main, rst_n); tl_if edn0_tl_if(clk_main, rst_n); tl_if edn1_tl_if(clk_main, rst_n); tl_if rv_plic_tl_if(clk_main, rst_n); -tl_if otbn_tl_if(clk_main, rst_n); +tl_if acc_tl_if(clk_main, rst_n); tl_if keymgr_dpe_tl_if(clk_main, rst_n); tl_if rv_core_ibex__cfg_tl_if(clk_main, rst_n); tl_if sram_ctrl_main__regs_tl_if(clk_main, rst_n); @@ -164,7 +164,7 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(edn0, edn0, tl) `DRIVE_CHIP_TL_DEVICE_IF(edn1, edn1, tl) `DRIVE_CHIP_TL_DEVICE_IF(rv_plic, rv_plic, tl) - `DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl) + `DRIVE_CHIP_TL_DEVICE_IF(acc, acc, tl) `DRIVE_CHIP_TL_DEVICE_IF(keymgr_dpe, keymgr_dpe, tl) `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex__cfg, rv_core_ibex, cfg_tl_d) `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__regs, sram_ctrl_main, regs_tl) diff --git a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv index b1f0a2cc4ff..64a8380a700 100644 --- a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv @@ -55,7 +55,7 @@ tl_device_t xbar_devices[$] = '{ '{"rv_plic", '{ '{32'h28000000, 32'h2fffffff} }}, - '{"otbn", '{ + '{"acc", '{ '{32'h22100000, 32'h2211ffff} }}, '{"keymgr_dpe", '{ @@ -255,7 +255,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr_dpe", "kmac", "sram_ctrl_main__regs", @@ -310,7 +310,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr_dpe", "kmac", "sram_ctrl_main__regs", @@ -336,7 +336,7 @@ tl_host_t xbar_hosts[$] = '{ "sram_ctrl_mbox__ram", "aes", "hmac", - "otbn", + "acc", "keymgr_dpe", "kmac", "soc_proxy__ctn", diff --git a/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg index 133f672ba3e..3c2e7a2d90e 100644 --- a/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg @@ -84,10 +84,10 @@ -node tb.dut*.u_edn1 tl_*i.a_address[31:30] -node tb.dut*.u_rv_plic tl_*i.a_address[28:28] -node tb.dut*.u_rv_plic tl_*i.a_address[31:30] --node tb.dut*.u_otbn tl_*i.a_address[19:17] --node tb.dut*.u_otbn tl_*i.a_address[24:21] --node tb.dut*.u_otbn tl_*i.a_address[28:26] --node tb.dut*.u_otbn tl_*i.a_address[31:30] +-node tb.dut*.u_acc tl_*i.a_address[19:17] +-node tb.dut*.u_acc tl_*i.a_address[24:21] +-node tb.dut*.u_acc tl_*i.a_address[28:26] +-node tb.dut*.u_acc tl_*i.a_address[31:30] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[17:8] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[19:19] -node tb.dut*.u_keymgr_dpe tl_*i.a_address[23:21] diff --git a/hw/top_darjeeling/dv/chip_rom_tests.hjson b/hw/top_darjeeling/dv/chip_rom_tests.hjson index befe9feadbc..fd64927771f 100644 --- a/hw/top_darjeeling/dv/chip_rom_tests.hjson +++ b/hw/top_darjeeling/dv/chip_rom_tests.hjson @@ -753,11 +753,11 @@ run_timeout_mins: 120 } { - name: rom_e2e_sigverify_mod_exp_test_unlocked0_otbn + name: rom_e2e_sigverify_mod_exp_test_unlocked0_acc uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_test_unlocked0_otbn:4", + "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_test_unlocked0_acc:4", ] en_run_modes: ["sw_test_mode_rom_with_fake_keys"] run_opts: [ @@ -781,11 +781,11 @@ run_timeout_mins: 480 } { - name: rom_e2e_sigverify_mod_exp_dev_otbn + name: rom_e2e_sigverify_mod_exp_dev_acc uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_otbn:4", + "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_dev_acc:4", ] en_run_modes: ["sw_test_mode_rom_with_fake_keys"] run_opts: [ @@ -809,11 +809,11 @@ run_timeout_mins: 120 } { - name: rom_e2e_sigverify_mod_exp_prod_otbn + name: rom_e2e_sigverify_mod_exp_prod_acc uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_otbn:4", + "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_acc:4", ] en_run_modes: ["sw_test_mode_rom_with_fake_keys"] run_opts: [ @@ -837,11 +837,11 @@ run_timeout_mins: 120 } { - name: rom_e2e_sigverify_mod_exp_prod_end_otbn + name: rom_e2e_sigverify_mod_exp_prod_end_acc uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_otbn:4", + "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_prod_end_acc:4", ] en_run_modes: ["sw_test_mode_rom_with_fake_keys"] run_opts: [ @@ -865,11 +865,11 @@ run_timeout_mins: 120 } { - name: rom_e2e_sigverify_mod_exp_rma_otbn + name: rom_e2e_sigverify_mod_exp_rma_acc uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp:6:ot_flash_binary:signed:fake_rsa_prod_key_0", - "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4", + "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_acc:4", ] en_run_modes: ["sw_test_mode_rom_with_fake_keys"] run_opts: [ @@ -933,7 +933,7 @@ uvm_test_seq: chip_sw_base_vseq sw_images: [ "//sw/device/silicon_creator/rom/e2e/presigned_images:rom_e2e_self_hash:6:signed:ot_flash_binary" - "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4", + "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_acc:4", ] en_run_modes: ["sw_test_mode_rom_with_real_keys"] run_opts: [ @@ -950,7 +950,7 @@ // uvm_test_seq: chip_sw_base_vseq // sw_images: [ // "//sw/device/silicon_creator/rom/e2e/presigned_images:rom_e2e_self_hash:1:signed:ot_flash_binary" - // "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn:4", + // "//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_acc:4", // ] // // We purposely use the `sw_test_mode_common` run mode here instead of the // // run modes that add either ROM image to the list of sw_images to @@ -1055,15 +1055,15 @@ { name: rom_e2e_sigverify_mod_exp tests: [ - "rom_e2e_sigverify_mod_exp_test_unlocked0_otbn", + "rom_e2e_sigverify_mod_exp_test_unlocked0_acc", "rom_e2e_sigverify_mod_exp_test_unlocked0_sw", - "rom_e2e_sigverify_mod_exp_dev_otbn", + "rom_e2e_sigverify_mod_exp_dev_acc", "rom_e2e_sigverify_mod_exp_dev_sw", - "rom_e2e_sigverify_mod_exp_prod_otbn", + "rom_e2e_sigverify_mod_exp_prod_acc", "rom_e2e_sigverify_mod_exp_prod_sw", - "rom_e2e_sigverify_mod_exp_prod_end_otbn", + "rom_e2e_sigverify_mod_exp_prod_end_acc", "rom_e2e_sigverify_mod_exp_prod_end_sw", - "rom_e2e_sigverify_mod_exp_rma_otbn", + "rom_e2e_sigverify_mod_exp_rma_acc", "rom_e2e_sigverify_mod_exp_rma_sw", ] } diff --git a/hw/top_darjeeling/dv/chip_sim_cfg.hjson b/hw/top_darjeeling/dv/chip_sim_cfg.hjson index c8b7ca2e5f9..668507bc589 100644 --- a/hw/top_darjeeling/dv/chip_sim_cfg.hjson +++ b/hw/top_darjeeling/dv/chip_sim_cfg.hjson @@ -55,10 +55,10 @@ // "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", // xbar tests "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson", - // Config files to get the correct flags for otbn_memutil and otbn_tracer + // Config files to get the correct flags for acc_memutil and acc_tracer "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson", - "{proj_root}/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson", - "{proj_root}/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson", + "{proj_root}/hw/ip/acc/dv/memutil/acc_memutil_sim_opts.hjson", + "{proj_root}/hw/ip/acc/dv/tracer/acc_tracer_sim_opts.hjson", // "{proj_root}/hw/{top_chip}/data/chip_cfg.hjson", "{top_dv_path}/chip_smoketests.hjson", "{top_dv_path}/chip_rom_tests.hjson", @@ -228,10 +228,10 @@ } ] - // Add options needed to compile against otbn_memutil, otbn_tracer, + // Add options needed to compile against acc_memutil, acc_tracer, // memutil_dpi_scrambled, and AES C model - en_build_modes: ["{tool}_otbn_memutil_build_opts", - "{tool}_otbn_tracer_build_opts", + en_build_modes: ["{tool}_acc_memutil_build_opts", + "{tool}_acc_tracer_build_opts", "{tool}_memutil_dpi_scrambled_build_opts", "{tool}_aes_model_build_opts"] @@ -401,7 +401,7 @@ // to know what type of image is it: // - 0 for Boot ROM, // - 1 for SW test (loaded in flash), - // - 2 for OTBN test, and + // - 2 for ACC test, and // - 3 for OTP. // This allows an arbitrary number of SW images to be supplied to the TB. // @@ -940,32 +940,32 @@ run_opts: ["+sw_test_timeout_ns=18_000_000"] } { - name: chip_sw_otbn_randomness + name: chip_sw_acc_randomness uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_randomness_test:6:new_rules"] + sw_images: ["//sw/device/tests:acc_randomness_test:6:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=18_000_000","+rng_srate_value=30"] } { - name: chip_sw_otbn_ecdsa_op_irq + name: chip_sw_acc_ecdsa_op_irq uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:6:new_rules"] + sw_images: ["//sw/device/tests:acc_ecdsa_op_irq_test:6:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=28_000_000", "+rng_srate_value=30"] run_timeout_mins: 300 } { - name: chip_sw_otbn_ecdsa_op_irq_jitter_en + name: chip_sw_acc_ecdsa_op_irq_jitter_en uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:6:new_rules"] + sw_images: ["//sw/device/tests:acc_ecdsa_op_irq_test:6:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=33_000_000", "+rng_srate_value=30", "+en_jitter=1"] run_timeout_mins: 300 } { - name: chip_sw_otbn_mem_scramble + name: chip_sw_acc_mem_scramble uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_mem_scramble_test:6:new_rules"] + sw_images: ["//sw/device/tests:acc_mem_scramble_test:6:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=15_000_000", "+en_scb_tl_err_chk=0", "+bypass_alert_ready_to_end_check=1"] @@ -1210,9 +1210,9 @@ // run_opts: ["+sw_test_timeout_ns=20_000_000"] // } // { - // name: chip_sw_keymgr_sideload_otbn + // name: chip_sw_keymgr_sideload_acc // uvm_test_seq: chip_sw_base_vseq - // sw_images: ["//sw/device/tests:keymgr_sideload_otbn_test:6:new_rules"] + // sw_images: ["//sw/device/tests:keymgr_sideload_acc_test:6:new_rules"] // en_run_modes: ["sw_test_mode_test_rom"] // run_opts: ["+sw_test_timeout_ns=20_000_000"] // run_timeout_mins: 180 @@ -1368,9 +1368,9 @@ en_run_modes: ["sw_test_mode_test_rom"] } { - name: chip_sw_clkmgr_off_otbn_trans + name: chip_sw_clkmgr_off_acc_trans uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:clkmgr_off_otbn_trans_test:6:new_rules"] + sw_images: ["//sw/device/tests:clkmgr_off_acc_trans_test:6:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] } { @@ -1511,9 +1511,9 @@ run_opts: ["+cal_sys_clk_70mhz=1"] } { - name: chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq + name: chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:6:new_rules"] + sw_images: ["//sw/device/tests:acc_ecdsa_op_irq_test:6:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=33_000_000", "+rng_srate_value=30", "+en_jitter=1", "+cal_sys_clk_70mhz=1"] run_timeout_mins: 1000 @@ -1623,7 +1623,7 @@ "chip_sw_gpio_smoketest" "chip_sw_hmac_smoketest", "chip_sw_kmac_smoketest", - "chip_sw_otbn_smoketest", + "chip_sw_acc_smoketest", "chip_sw_otp_ctrl_smoketest", "chip_sw_rstmgr_smoketest", "chip_sw_rv_plic_smoketest", @@ -1639,7 +1639,7 @@ { name: jitter tests: ["chip_sw_clkmgr_jitter", - "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_acc_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", "chip_sw_keymgr_key_derivation_jitter_en", @@ -1649,7 +1649,7 @@ { name: jitter_reduced_freq tests: ["chip_sw_clkmgr_jitter_reduced_freq", - "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq", + "chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq", "chip_sw_aes_enc_jitter_en_reduced_freq", "chip_sw_hmac_enc_jitter_en_reduced_freq", "chip_sw_keymgr_key_derivation_jitter_en_reduced_freq", diff --git a/hw/top_darjeeling/dv/chip_smoketests.hjson b/hw/top_darjeeling/dv/chip_smoketests.hjson index 6b7cba1dbd9..995079d2a22 100644 --- a/hw/top_darjeeling/dv/chip_smoketests.hjson +++ b/hw/top_darjeeling/dv/chip_smoketests.hjson @@ -64,9 +64,9 @@ run_opts: ["+use_mbx_if=1"] } { - name: chip_sw_otbn_smoketest + name: chip_sw_acc_smoketest uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_smoketest:6:new_rules"] + sw_images: ["//sw/device/tests:acc_smoketest:6:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] } { @@ -131,7 +131,7 @@ "chip_sw_hmac_smoketest", "chip_sw_kmac_smoketest", "chip_sw_mbx_smoketest", - "chip_sw_otbn_smoketest", + "chip_sw_acc_smoketest", "chip_sw_otp_ctrl_smoketest", "chip_sw_rv_plic_smoketest", "chip_sw_pwrmgr_smoketest", diff --git a/hw/top_darjeeling/dv/cov/chip_cover_reg_top.cfg b/hw/top_darjeeling/dv/cov/chip_cover_reg_top.cfg index 04b2de01490..14376fdcb86 100644 --- a/hw/top_darjeeling/dv/cov/chip_cover_reg_top.cfg +++ b/hw/top_darjeeling/dv/cov/chip_cover_reg_top.cfg @@ -27,7 +27,7 @@ +node tb.dut.top_darjeeling.u_aes *tl_* +node tb.dut.top_darjeeling.u_hmac *tl_* +node tb.dut.top_darjeeling.u_kmac *tl_* -+node tb.dut.top_darjeeling.u_otbn *tl_* ++node tb.dut.top_darjeeling.u_acc *tl_* +node tb.dut.top_darjeeling.u_keymgr_dpe *tl_* +node tb.dut.top_darjeeling.u_csrng *tl_* +node tb.dut.top_darjeeling.u_edn0 *tl_* diff --git a/hw/top_darjeeling/dv/cov/conn_ast_mem_cfg.el b/hw/top_darjeeling/dv/cov/conn_ast_mem_cfg.el index 681d113842a..cd1e5c2360f 100644 --- a/hw/top_darjeeling/dv/cov/conn_ast_mem_cfg.el +++ b/hw/top_darjeeling/dv/cov/conn_ast_mem_cfg.el @@ -9,7 +9,7 @@ // ExclMode: default //================================================== CHECKSUM: "1723488990 3787458315" -INSTANCE: tb.dut.top_darjeeling.u_otbn +INSTANCE: tb.dut.top_darjeeling.u_acc ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv" Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en" ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv" diff --git a/hw/top_darjeeling/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_darjeeling/dv/env/autogen/chip_env_pkg__params.sv index c3a1aa31657..14dfb72a65a 100644 --- a/hw/top_darjeeling/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_darjeeling/dv/env/autogen/chip_env_pkg__params.sv @@ -31,13 +31,13 @@ parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "sram_ctrl_ret_aon_fatal_error", "rv_dm_fatal_fault", "rv_plic_fatal_fault", + "acc_fatal", + "acc_recov", "aes_recov_ctrl_update_err", "aes_fatal_fault", "hmac_fatal_fault", "kmac_recov_operation_err", "kmac_fatal_fault_err", - "otbn_fatal", - "otbn_recov", "keymgr_dpe_recov_operation_err", "keymgr_dpe_fatal_fault_err", "csrng_recov_alert", diff --git a/hw/top_darjeeling/dv/env/chip_env.sv b/hw/top_darjeeling/dv/env/chip_env.sv index 7d088d65567..6e607da09fe 100644 --- a/hw/top_darjeeling/dv/env/chip_env.sv +++ b/hw/top_darjeeling/dv/env/chip_env.sv @@ -53,8 +53,8 @@ class chip_env extends cip_base_env #( is_invalid |= mem inside {[RamMbox0:RamMbox15]} && (int'(mem - RamMbox0) > cfg.num_ram_mbox_tiles - 1); - is_invalid |= mem inside {[OtbnDmem0:OtbnDmem15]} && (int'(mem - OtbnDmem0) > - cfg.num_otbn_dmem_tiles - 1); + is_invalid |= mem inside {[AccDmem0:AccDmem15]} && (int'(mem - AccDmem0) > + cfg.num_acc_dmem_tiles - 1); is_invalid |= mem inside {[RamCtn0:RamCtn15]} && (int'(mem - RamCtn0) > cfg.num_ram_ctn_tiles - 1); diff --git a/hw/top_darjeeling/dv/env/chip_env_cfg.sv b/hw/top_darjeeling/dv/env/chip_env_cfg.sv index 901fb877dfc..2c0b9493944 100644 --- a/hw/top_darjeeling/dv/env/chip_env_cfg.sv +++ b/hw/top_darjeeling/dv/env/chip_env_cfg.sv @@ -80,7 +80,7 @@ class chip_env_cfg #(type RAL_T = chip_ral_pkg::chip_reg_block) extends cip_base uint num_ram_ret_tiles; uint num_ram_mbox_tiles; uint num_ram_ctn_tiles; - uint num_otbn_dmem_tiles; + uint num_acc_dmem_tiles; // ext component cfgs rand uart_agent_cfg m_uart_agent_cfgs[NUM_UARTS]; @@ -225,7 +225,7 @@ class chip_env_cfg #(type RAL_T = chip_ral_pkg::chip_reg_block) extends cip_base `DV_CHECK_LE_FATAL(num_ram_ret_tiles, 16) `DV_CHECK_LE_FATAL(num_ram_mbox_tiles, 16) `DV_CHECK_LE_FATAL(num_ram_ctn_tiles, 16) - `DV_CHECK_LE_FATAL(num_otbn_dmem_tiles, 16) + `DV_CHECK_LE_FATAL(num_acc_dmem_tiles, 16) if (use_jtag_dmi == 1) begin jtag_dmi_ral = create_jtag_dmi_reg_block(m_jtag_riscv_agent_cfg.m_jtag_agent_cfg); @@ -263,7 +263,7 @@ class chip_env_cfg #(type RAL_T = chip_ral_pkg::chip_reg_block) extends cip_base num_ram_ret_tiles = 1; num_ram_mbox_tiles = 1; num_ram_ctn_tiles = 1; - num_otbn_dmem_tiles = 1; + num_acc_dmem_tiles = 1; endfunction // Disable functional coverage of comportable IP-specific specialized registers. diff --git a/hw/top_darjeeling/dv/env/chip_env_pkg.sv b/hw/top_darjeeling/dv/env/chip_env_pkg.sv index c47b2cce9d1..bb527a2ca42 100644 --- a/hw/top_darjeeling/dv/env/chip_env_pkg.sv +++ b/hw/top_darjeeling/dv/env/chip_env_pkg.sv @@ -89,8 +89,8 @@ package chip_env_pkg; ICacheWay1Tag, ICacheWay0Data, ICacheWay1Data, - OtbnDmem[16], - OtbnImem, + AccDmem[16], + AccImem, Otp, RamMain[16], RamRet[16], @@ -102,13 +102,13 @@ package chip_env_pkg; SpiDeviceIngressMem } chip_mem_e; - // On OpenTitan, we deal with 4 types of SW - ROM, the main test, the OTBN test and the OTP image. + // On OpenTitan, we deal with 4 types of SW - ROM, the main test, the ACC test and the OTP image. // This basically puts these SW types into 'slots' that the external regression tool can set. typedef enum { SwTypeRom = 0, // Ibex SW - first stage boot ROM. SwTypeTestSlotA = 1, // Ibex SW - test SW in (flash) slot A. SwTypeTestSlotB = 2, // Ibex SW - test SW in (flash) slot B. - SwTypeOtbn = 3, // Otbn SW + SwTypeAcc = 3, // Acc SW SwTypeOtp = 4, // Customized OTP image SwTypeDebug = 5, // Debug SW - injected into SRAM. SwTypeCtn = 6, // Ibex SW - test SW in CTN SRAM. diff --git a/hw/top_darjeeling/dv/env/chip_if.sv b/hw/top_darjeeling/dv/env/chip_if.sv index df75342ed14..fe527d59d43 100644 --- a/hw/top_darjeeling/dv/env/chip_if.sv +++ b/hw/top_darjeeling/dv/env/chip_if.sv @@ -54,7 +54,7 @@ interface chip_if; `define KMAC_HIER `TOP_HIER.u_kmac `define KEYMGR_DPE_HIER `TOP_HIER.u_keymgr_dpe `define LC_CTRL_HIER `TOP_HIER.u_lc_ctrl -`define OTBN_HIER `TOP_HIER.u_otbn +`define ACC_HIER `TOP_HIER.u_acc `define OTP_CTRL_HIER `TOP_HIER.u_otp_ctrl `define OTP_MACRO_HIER `TOP_HIER.u_otp_macro `define PINMUX_HIER `TOP_HIER.u_pinmux_aon @@ -572,14 +572,14 @@ interface chip_if; wire aes_clk_is_enabled = 0; wire hmac_clk_is_enabled = 0; wire kmac_clk_is_enabled = 0; - wire otbn_clk_is_enabled = 0; + wire acc_clk_is_enabled = 0; wire io_clk_is_enabled = 0; `else wire aes_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_aes_val.d; wire hmac_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_hmac_val.d; wire kmac_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_kmac_val.d; - wire otbn_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_otbn_val.d; + wire acc_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_acc_val.d; // TODO: Not used in DV simulation. // wire io_clk_is_enabled = `CLKMGR_HIER.u_reg.reg2hw.clk_enables.clk_io_peri_en.q; @@ -816,7 +816,7 @@ interface chip_if; PeripheralKeymgrDpe: path = {path, ".", `DV_STRINGIFY(`KEYMGR_DPE_HIER)}; PeripheralKmac: path = {path, ".", `DV_STRINGIFY(`KMAC_HIER)}; PeripheralLcCtrl: path = {path, ".", `DV_STRINGIFY(`LC_CTRL_HIER)}; - PeripheralOtbn: path = {path, ".", `DV_STRINGIFY(`OTBN_HIER)}; + PeripheralAcc: path = {path, ".", `DV_STRINGIFY(`ACC_HIER)}; PeripheralOtpCtrl: path = {path, ".", `DV_STRINGIFY(`OTP_CTRL_HIER)}; PeripheralPinmuxAon: path = {path, ".", `DV_STRINGIFY(`PINMUX_HIER)}; PeripheralPwrmgrAon: path = {path, ".", `DV_STRINGIFY(`PWRMGR_HIER)}; @@ -952,11 +952,11 @@ interface chip_if; `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_kmac_fsm_state, kmac_fsm_state, 6) - // Signal probe function for `state_q` OTBN_START_STOP_CONTROL - wire [6:0] otbn_fsm_state; - assign otbn_fsm_state = `OTBN_HIER.u_otbn_core.u_otbn_start_stop_control.u_state_regs.state_o; - `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_otbn_fsm_state, - otbn_fsm_state, 7) + // Signal probe function for `state_q` ACC_START_STOP_CONTROL + wire [6:0] acc_fsm_state; + assign acc_fsm_state = `ACC_HIER.u_acc_core.u_acc_start_stop_control.u_state_regs.state_o; + `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_acc_fsm_state, + acc_fsm_state, 7) // Signal probe function for `state_q` of EDN_0_MAIN_SM wire [8:0] edn_0_fsm_state; @@ -1023,7 +1023,7 @@ interface chip_if; `undef KMAC_HIER `undef KEYMGR_DPE_HIER `undef LC_CTRL_HIER -`undef OTBN_HIER +`undef ACC_HIER `undef OTP_CTRL_HIER `undef OTP_MACRO_HIER `undef PINMUX_HIER diff --git a/hw/top_darjeeling/dv/env/seq_lib/chip_base_vseq.sv b/hw/top_darjeeling/dv/env/seq_lib/chip_base_vseq.sv index c3bdf0328db..2e05f37a6fa 100644 --- a/hw/top_darjeeling/dv/env/seq_lib/chip_base_vseq.sv +++ b/hw/top_darjeeling/dv/env/seq_lib/chip_base_vseq.sv @@ -175,11 +175,11 @@ class chip_base_vseq #( initialize_otp_sig_verify(); initialize_otp_creator_sw_cfg_ast_cfg(); // Initialize selected memories to all 0. This is required for some chip-level tests such as - // otbn_mem_scramble that may intentionally read memories before writing them. Reading these + // acc_mem_scramble that may intentionally read memories before writing them. Reading these // memories still triggers ECC integrity errors that need to be handled by the test. - cfg.mem_bkdr_util_h[OtbnImem].clear_mem(); - for (int ram_idx = 0; ram_idx < cfg.num_otbn_dmem_tiles; ram_idx++) begin - cfg.mem_bkdr_util_h[chip_mem_e'(OtbnDmem0 + ram_idx)].clear_mem(); + cfg.mem_bkdr_util_h[AccImem].clear_mem(); + for (int ram_idx = 0; ram_idx < cfg.num_acc_dmem_tiles; ram_idx++) begin + cfg.mem_bkdr_util_h[chip_mem_e'(AccDmem0 + ram_idx)].clear_mem(); end // Early cpu init if (early_cpu_init) cpu_init(); @@ -315,9 +315,9 @@ class chip_base_vseq #( end endtask : alert_ping_en_shorten - // Initialize the OTP creator SW cfg region to use otbn for signature verification. + // Initialize the OTP creator SW cfg region to use acc for signature verification. virtual function void initialize_otp_sig_verify(); - // Use otbn mod_exp implementation for signature + // Use acc mod_exp implementation for signature // verification. See the definition of `hardened_bool_t` in // sw/lib/sw/device/base/hardened.h. cfg.mem_bkdr_util_h[Otp].write32(otp_ctrl_reg_pkg::CreatorSwCfgSigverifyRsaModExpIbexEnOffset, diff --git a/hw/top_darjeeling/dv/env/seq_lib/chip_jtag_mem_vseq.sv b/hw/top_darjeeling/dv/env/seq_lib/chip_jtag_mem_vseq.sv index 8d2826828e6..ad23ce23948 100644 --- a/hw/top_darjeeling/dv/env/seq_lib/chip_jtag_mem_vseq.sv +++ b/hw/top_darjeeling/dv/env/seq_lib/chip_jtag_mem_vseq.sv @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 // This test write and read back test through jtag interface for -// following memories : otbn.imem, otbn.dmem, sram_ctrl_main_ram.ram, sram_ctrl_ret_aon_ram.ram +// following memories : acc.imem, acc.dmem, sram_ctrl_main_ram.ram, sram_ctrl_ret_aon_ram.ram // Also preload random data to rom_ctrl_rom.rom and check read data integrity // through jtag interface class chip_jtag_mem_vseq extends chip_common_vseq; diff --git a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv index 8232486e3da..d752167be33 100644 --- a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv +++ b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv @@ -28,7 +28,7 @@ class chip_sw_all_escalation_resets_vseq extends chip_sw_base_vseq; // TODO TopDarjeelingAlertIdLcCtrlFatalProgError: done in sw/device/tests/sim_dv/lc_ctrl_program_error.c? '{"*lc_ctrl*state_regs*", TopDarjeelingAlertIdLcCtrlFatalStateError}, '{"*lc_ctrl*prim_reg_we_check*", TopDarjeelingAlertIdLcCtrlFatalBusIntegError}, - '{"*otbn*prim_reg_we_check*", TopDarjeelingAlertIdOtbnFatal}, + '{"*acc*prim_reg_we_check*", TopDarjeelingAlertIdAccFatal}, // TopDarjeelingAlertIdOtpCtrlFatalMacroError: done in chip_sw_otp_ctrl_escalation_vseq '{"*otp_ctrl.u_otp.*u_state_regs", TopDarjeelingAlertIdOtpCtrlFatalPrimOtpAlert}, '{"*otp_ctrl*u_otp_ctrl_dai*", TopDarjeelingAlertIdOtpCtrlFatalCheckError}, diff --git a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_keymgr_dpe_key_derivation_vseq.sv b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_keymgr_dpe_key_derivation_vseq.sv index 66f24a6b39f..6ee03d458be 100644 --- a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_keymgr_dpe_key_derivation_vseq.sv +++ b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_keymgr_dpe_key_derivation_vseq.sv @@ -15,8 +15,8 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; typedef bit [TL_DW-1:0] tl_data_t; typedef bit [keymgr_pkg::KeyWidth-1:0] key_t; typedef key_t [keymgr_pkg::Shares-1:0] key_shares_t; - typedef bit [keymgr_pkg::OtbnKeyWidth-1:0] otbn_key_t; - typedef otbn_key_t [keymgr_pkg::Shares-1:0] otbn_key_shares_t; + typedef bit [keymgr_pkg::AccKeyWidth-1:0] acc_key_t; + typedef acc_key_t [keymgr_pkg::Shares-1:0] acc_key_shares_t; typedef tl_data_t [keymgr_dpe_reg_pkg::NumSaltReg-1:0] salt_t; typedef tl_data_t [keymgr_dpe_reg_pkg::NumSwBindingReg-1:0] sw_binding_t; @@ -96,12 +96,12 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; // Verify that the outputs generated from the boot stage 0 key match the expectation. // Note that the values for version and salt must match those passed in SW. (Ideally, we would // backdoor-load them into SW to remove the redundancy, but that's no immediate priority.) - `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated OTBN output from boot stage 0") + `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated ACC output from boot stage 0") check_generated_output(.key_shares(stage_0_key), // These values must match those passed in SW. (Ideally, we would // backdoor-load them into SW to remove the redundancy, but that's no // immediate priority.) - .dest(keymgr_pkg::Otbn), + .dest(keymgr_pkg::Acc), .version('d0), .salt({32'h49379059, 32'hff523992, 32'h75666880, 32'hc0e44716, 32'h999612df, 32'h80f1a9de, 32'h481eae40, 32'h45e2c7f0})); @@ -175,9 +175,9 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; .version('d2), .salt({32'h72d5886b, 32'h4e359e52, 32'h0d7ff336, 32'h267773cf, 32'h00c7d10c, 32'h6dea4fb9, 32'h77fa328a, 32'h15779805})); - `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated OTBN output from boot stage 1") + `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated ACC output from boot stage 1") check_generated_output(.key_shares(stage_1_key), - .dest(keymgr_pkg::Otbn), + .dest(keymgr_pkg::Acc), .version('d3), .salt({32'h564712d4, 32'h7ab745f5, 32'h5fa8faa9, 32'h77fce728, 32'hffa3fd3c, 32'h876930f2, 32'h593b54d4, 32'ha75e231b})); @@ -224,9 +224,9 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; .version('d2), .salt({32'hb31031a3, 32'h59fe6e8e, 32'h4171de6b, 32'ha3f3d397, 32'h7bb7800b, 32'h8f8f8cda, 32'hb697609d, 32'h122eb3b7})); - `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated OTBN output from boot stage 2") + `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated ACC output from boot stage 2") check_generated_output(.key_shares(stage_2_key), - .dest(keymgr_pkg::Otbn), + .dest(keymgr_pkg::Acc), .version('d3), .salt({32'h3f184f9b, 32'hd4af6765, 32'h8abeb221, 32'haae3ca52, 32'h29f7114f, 32'hf5bf3e01, 32'h6a961bc2, 32'hec932d64})); @@ -269,9 +269,9 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; .version(32'h10), .salt({32'h30059d96, 32'h97436d9c, 32'hf539a20a, 32'h6838564e, 32'h74ad4bb7, 32'h78000277, 32'h423025af, 32'h732e53a9})); - `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated OTBN output from boot stage 3") + `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated ACC output from boot stage 3") check_generated_output(.key_shares(stage_3_key), - .dest(keymgr_pkg::Otbn), + .dest(keymgr_pkg::Acc), .version(32'h20), .salt({32'h2cd82d66, 32'h24275e98, 32'he0344ab2, 32'hc048d59e, 32'h139694c3, 32'h0043f9b4, 32'h413a2212, 32'hc2dcfbc8})); @@ -298,9 +298,9 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; .version(32'd42), .salt({32'h2488d617, 32'h99227306, 32'hcd789bc0, 32'h9787039b, 32'h9869544a, 32'hb28b9fc7, 32'h69ab6f9d, 32'hfb11f188})); - `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated OTBN output from boot stage 2") + `DV_WAIT(cfg.sw_logger_vif.printed_log == "KeymgrDpe generated ACC output from boot stage 2") check_generated_output(.key_shares(stage_2_key), - .dest(keymgr_pkg::Otbn), + .dest(keymgr_pkg::Acc), .version(32'd7), .salt({32'hfa94162c, 32'hd039a40f, 32'hc2b81d98, 32'h999ce18d, 32'hbf8fb838, 32'h589544ce, 32'hee7790c4, 32'h0de6bdcf})); @@ -470,8 +470,8 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; gen_data.OutputSeed = top_darjeeling_rnd_cnst_pkg::RndCnstKeymgrDpeHardOutputSeed; end - keymgr_pkg::Otbn: begin // HW -> OTBN - gen_data.HwDestSeed = top_darjeeling_rnd_cnst_pkg::RndCnstKeymgrDpeOtbnSeed; + keymgr_pkg::Acc: begin // HW -> ACC + gen_data.HwDestSeed = top_darjeeling_rnd_cnst_pkg::RndCnstKeymgrDpeAccSeed; gen_data.OutputSeed = top_darjeeling_rnd_cnst_pkg::RndCnstKeymgrDpeHardOutputSeed; end @@ -490,11 +490,11 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; act_digest) endfunction - // Same as `check_kmac_digest` but for OTBN, which uses wider values. - virtual function void check_kmac_otbn_digest(key_t kmac_key, + // Same as `check_kmac_digest` but for ACC, which uses wider values. + virtual function void check_kmac_acc_digest(key_t kmac_key, bit [7:0] data_arr[], - otbn_key_t act_digest); - `DV_CHECK_EQ(keymgr_pkg::OtbnKeyWidth'(get_kmac_digest(kmac_key, data_arr)), + acc_key_t act_digest); + `DV_CHECK_EQ(keymgr_pkg::AccKeyWidth'(get_kmac_digest(kmac_key, data_arr)), act_digest) endfunction @@ -537,10 +537,10 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; salt_t salt); bit [7:0] data_arr[]; {<< byte {data_arr}} = get_gen_data(.key_version(version), .salt(salt), .dest(dest)); - if (dest == keymgr_pkg::Otbn) begin - // Outputs generated for OTBN have a different width. - otbn_key_shares_t output_shares = get_output_otbn(); - check_kmac_otbn_digest(get_unmasked_key(key_shares), + if (dest == keymgr_pkg::Acc) begin + // Outputs generated for ACC have a different width. + acc_key_shares_t output_shares = get_output_acc(); + check_kmac_acc_digest(get_unmasked_key(key_shares), data_arr, output_shares[1] ^ output_shares[0]); end else begin @@ -556,7 +556,7 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; keymgr_pkg::None: return get_sw_output(); keymgr_pkg::Aes: return get_hw_output("tb.dut.top_darjeeling.u_keymgr_dpe.aes_key_o"); keymgr_pkg::Kmac: return get_hw_output("tb.dut.top_darjeeling.u_keymgr_dpe.kmac_key_o"); - keymgr_pkg::Otbn: `dv_fatal("Illegal use of this function; use `get_output_otbn` instead!") + keymgr_pkg::Acc: `dv_fatal("Illegal use of this function; use `get_output_acc` instead!") default: `dv_fatal("Illegal destination (DV bug)!") endcase endfunction @@ -583,14 +583,14 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; return hw_key.key; endfunction - virtual function otbn_key_shares_t get_output_otbn(); - string path = "tb.dut.top_darjeeling.u_keymgr_dpe.otbn_key_o"; - keymgr_pkg::otbn_key_req_t otbn_key; - `DV_CHECK_FATAL(uvm_hdl_read(path, otbn_key)) - `DV_CHECK_EQ(otbn_key.valid, 1, "Expected OTBN output key to be valid") - `uvm_info(`gfn, $sformatf("HW Output at %s:\n%s", path, otbn_key_shares_str(otbn_key.key)), + virtual function acc_key_shares_t get_output_acc(); + string path = "tb.dut.top_darjeeling.u_keymgr_dpe.acc_key_o"; + keymgr_pkg::acc_key_req_t acc_key; + `DV_CHECK_FATAL(uvm_hdl_read(path, acc_key)) + `DV_CHECK_EQ(acc_key.valid, 1, "Expected ACC output key to be valid") + `uvm_info(`gfn, $sformatf("HW Output at %s:\n%s", path, acc_key_shares_str(acc_key.key)), UVM_LOW) - return otbn_key.key; + return acc_key.key; endfunction // Format a key. @@ -603,8 +603,8 @@ class chip_sw_keymgr_dpe_key_derivation_vseq extends chip_sw_base_vseq; return $sformatf("%s%s%s", key_str(key_shares[0]), separator, key_str(key_shares[1])); endfunction - // Format two shares of an OTBN key. - virtual function string otbn_key_shares_str(otbn_key_shares_t shares, string separator = "\n"); + // Format two shares of an ACC key. + virtual function string acc_key_shares_str(acc_key_shares_t shares, string separator = "\n"); return $sformatf("384'h%096h%s384'h%096h", shares[0], separator, shares[1]); endfunction diff --git a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_lc_raw_unlock_vseq.sv b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_lc_raw_unlock_vseq.sv index 3dde545e2e8..f7ac5b3f1ba 100644 --- a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_lc_raw_unlock_vseq.sv +++ b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_lc_raw_unlock_vseq.sv @@ -81,7 +81,7 @@ class chip_sw_lc_raw_unlock_vseq extends chip_sw_base_vseq; jtag_otp_program32(otp_ctrl_reg_pkg::CreatorSwCfgRomExecEnOffset, 1); if (rom_prod_mode) begin - // Use otbn mod_exp implementation for signature verification. See the + // Use acc mod_exp implementation for signature verification. See the // definition of `hardened_bool_t` in sw/lib/sw/device/base/hardened.h. jtag_otp_program32(otp_ctrl_reg_pkg::CreatorSwCfgSigverifyRsaModExpIbexEnOffset, 32'h1d4); end diff --git a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_power_virus_vseq.sv b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_power_virus_vseq.sv index 202c6531c06..77552b5f41a 100644 --- a/hw/top_darjeeling/dv/env/seq_lib/chip_sw_power_virus_vseq.sv +++ b/hw/top_darjeeling/dv/env/seq_lib/chip_sw_power_virus_vseq.sv @@ -117,7 +117,7 @@ class chip_sw_power_virus_vseq extends chip_sw_base_vseq; logic [5:0] aes_ctrl_fsm_state; logic [2:0] hmac_fsm_state; logic [5:0] kmac_fsm_state; - logic [6:0] otbn_fsm_state; + logic [6:0] acc_fsm_state; logic [8:0] edn_0_fsm_state; logic [8:0] edn_1_fsm_state; @@ -132,7 +132,7 @@ class chip_sw_power_virus_vseq extends chip_sw_base_vseq; `_DV_PROBE_AND_CHECK_IDLE(aes_ctrl_fsm_state, aes_pkg::CTRL_IDLE) `_DV_PROBE_AND_CHECK_IDLE(hmac_fsm_state, 3'b000) `_DV_PROBE_AND_CHECK_IDLE(kmac_fsm_state, 6'b011000) - `_DV_PROBE_AND_CHECK_IDLE(otbn_fsm_state, otbn_pkg::OtbnStartStopStateInitial) + `_DV_PROBE_AND_CHECK_IDLE(acc_fsm_state, acc_pkg::AccStartStopStateInitial) `_DV_PROBE_AND_CHECK_IDLE(edn_0_fsm_state, edn_pkg::Idle) `_DV_PROBE_AND_CHECK_IDLE(edn_1_fsm_state, edn_pkg::Idle) endtask diff --git a/hw/top_darjeeling/dv/tb/chip_hier_macros.svh b/hw/top_darjeeling/dv/tb/chip_hier_macros.svh index df861a9dfe9..7dff4eb469f 100644 --- a/hw/top_darjeeling/dv/tb/chip_hier_macros.svh +++ b/hw/top_darjeeling/dv/tb/chip_hier_macros.svh @@ -26,7 +26,7 @@ `define SPI_DEVICE_HIER `CHIP_HIER.u_spi_device `define UART_HIER `CHIP_HIER.u_uart `define PWRMGR_HIER `CHIP_HIER.u_pwrmgr_aon -`define OTBN_HIER `CHIP_HIER.u_otbn +`define ACC_HIER `CHIP_HIER.u_acc // The path to the actual memory array in rom_ctrl. This is a bit of a hack to allow a long path // without overflowing 100 characters or including any whitespace (which breaks a DV_STRINGIFY call @@ -56,5 +56,5 @@ `define SPI_DEVICE_EGRESS_HIER `SPI_DEVICE_HIER.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.`MEM_ARRAY_SUB `define SPI_DEVICE_INGRESS_HIER `SPI_DEVICE_HIER.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.`MEM_ARRAY_SUB `define OTP_MEM_HIER `OTP_MACRO_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB -`define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB -`define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ACC_IMEM_HIER `ACC_HIER.u_imem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ACC_DMEM_HIER `ACC_HIER.u_dmem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB diff --git a/hw/top_darjeeling/dv/tb/tb.sv b/hw/top_darjeeling/dv/tb/tb.sv index 74afc3b1195..42b4f6d94f6 100644 --- a/hw/top_darjeeling/dv/tb/tb.sv +++ b/hw/top_darjeeling/dv/tb/tb.sv @@ -443,21 +443,21 @@ module tb; m_mem_bkdr_util[Rom1] = rom1; `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[Rom1], `ROM1_MEM_HIER) - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for OTBN IMEM", UVM_MEDIUM) - m_mem_bkdr_util[OtbnImem] = new(.name ("mem_bkdr_util[OtbnImem]"), - .path (`DV_STRINGIFY(`OTBN_IMEM_HIER)), - .depth ($size(`OTBN_IMEM_HIER)), - .n_bits($bits(`OTBN_IMEM_HIER)), + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for ACC IMEM", UVM_MEDIUM) + m_mem_bkdr_util[AccImem] = new(.name ("mem_bkdr_util[AccImem]"), + .path (`DV_STRINGIFY(`ACC_IMEM_HIER)), + .depth ($size(`ACC_IMEM_HIER)), + .n_bits($bits(`ACC_IMEM_HIER)), .err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32)); - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[OtbnImem], `OTBN_IMEM_HIER) + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[AccImem], `ACC_IMEM_HIER) - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for OTBN DMEM", UVM_MEDIUM) - m_mem_bkdr_util[OtbnDmem0] = new(.name ("mem_bkdr_util[OtbnDmem0]"), - .path (`DV_STRINGIFY(`OTBN_DMEM_HIER)), - .depth ($size(`OTBN_DMEM_HIER)), - .n_bits($bits(`OTBN_DMEM_HIER)), + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for ACC DMEM", UVM_MEDIUM) + m_mem_bkdr_util[AccDmem0] = new(.name ("mem_bkdr_util[AccDmem0]"), + .path (`DV_STRINGIFY(`ACC_DMEM_HIER)), + .depth ($size(`ACC_DMEM_HIER)), + .n_bits($bits(`ACC_DMEM_HIER)), .err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32)); - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[OtbnDmem0], `OTBN_DMEM_HIER) + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[AccDmem0], `ACC_DMEM_HIER) `uvm_info("tb.sv", "Creating mem_bkdr_util instance for SPI_DEVICE EGRESS MEM", UVM_MEDIUM) m_mem_bkdr_util[SpiDeviceEgressMem] = @@ -482,7 +482,7 @@ module tb; mem inside {[RamRet1:RamRet15]} || mem inside {[RamMbox1:RamMbox15]} || mem inside {[RamCtn1:RamCtn15]} || - mem inside {[OtbnDmem1:OtbnDmem15]}) begin + mem inside {[AccDmem1:AccDmem15]}) begin mem = mem.next(); continue; end diff --git a/hw/top_darjeeling/dv/top_darjeeling_sim_cfgs.hjson b/hw/top_darjeeling/dv/top_darjeeling_sim_cfgs.hjson index fa85f67728c..864a9234edb 100644 --- a/hw/top_darjeeling/dv/top_darjeeling_sim_cfgs.hjson +++ b/hw/top_darjeeling/dv/top_darjeeling_sim_cfgs.hjson @@ -35,7 +35,7 @@ "{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_dmi_volatile_unlock_disabled_sim_cfg.hjson", "{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_dmi_volatile_unlock_enabled_sim_cfg.hjson", "{proj_root}/hw/ip/mbx/dv/mbx_sim_cfg.hjson", - "{proj_root}/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson", + "{proj_root}/hw/ip/acc/dv/uvm/acc_sim_cfg.hjson", "{proj_root}/hw/ip/prim/dv/prim_alert/prim_alert_sim_cfg.hjson", "{proj_root}/hw/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson", "{proj_root}/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson", diff --git a/hw/top_darjeeling/dv/verilator/verilator_sim_cfg.hjson b/hw/top_darjeeling/dv/verilator/verilator_sim_cfg.hjson index b00315a9717..506a3ef3b9e 100644 --- a/hw/top_darjeeling/dv/verilator/verilator_sim_cfg.hjson +++ b/hw/top_darjeeling/dv/verilator/verilator_sim_cfg.hjson @@ -57,7 +57,7 @@ // needed as a run time switch to Verilator. '''{eval_cmd} \ opts=; \ - types=(rom flash otbn otp); \ + types=(rom flash acc otp); \ exts=(scr.39.vmem elf elf vmem); \ images=`echo {sw_images}`; \ for image in $images; do \ @@ -81,7 +81,7 @@ // to know what type of image is it: // - 0 for Boot ROM, // - 1 for SW test (loaded in flash), - // - 2 for OTBN test, + // - 2 for ACC test, // - 3 for OTP. // This allows an arbitrary number of SW images to be supplied to the TB. // @@ -136,8 +136,8 @@ sw_images: ["//sw/device/tests:crt_test:1"] } { - name: otbn_smoketest_rtl - sw_images: ["//sw/device/tests:otbn_smoketest:1"] + name: acc_smoketest_rtl + sw_images: ["//sw/device/tests:acc_smoketest:1"] } { name: otp_ctrl_smoketest diff --git a/hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv b/hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv index 42de5881a36..e8ab90475a9 100644 --- a/hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv +++ b/hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv @@ -20,9 +20,9 @@ CONNECTION, AST_DFT_SPI_DEVICE_RAM_2P_CFG, u_ast.u_ast_dft, "{10'h0, dpram_rml_o}", top_darjeeling.u_spi_device.u_memory_2p.u_mem, cfg_i # Single port RAMs. -# To otbn. -CONNECTION, AST_DFT_OTBN_IMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_darjeeling.u_otbn.u_imem.u_prim_ram_1p_adv.u_mem, cfg_i -CONNECTION, AST_DFT_OTBN_DMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_darjeeling.u_otbn.u_dmem.u_prim_ram_1p_adv.u_mem, cfg_i +# To acc. +CONNECTION, AST_DFT_ACC_IMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_darjeeling.u_acc.u_imem.u_prim_ram_1p_adv.u_mem, cfg_i +CONNECTION, AST_DFT_ACC_DMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_darjeeling.u_acc.u_dmem.u_prim_ram_1p_adv.u_mem, cfg_i # To rv_core_ibex. CONNECTION, AST_DFT_RV_CORE_IBEX_TAG0_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_darjeeling.u_rv_core_ibex.u_core.gen_rams.gen_rams_inner[0].gen_scramble_rams.tag_bank.u_prim_ram_1p_adv.u_mem, cfg_i diff --git a/hw/top_darjeeling/formal/conn_csvs/clkmgr_idle.csv b/hw/top_darjeeling/formal/conn_csvs/clkmgr_idle.csv index 2ac31143363..c8a1b138eb1 100644 --- a/hw/top_darjeeling/formal/conn_csvs/clkmgr_idle.csv +++ b/hw/top_darjeeling/formal/conn_csvs/clkmgr_idle.csv @@ -11,4 +11,4 @@ CONNECTION, CLKMGR_IDLE0, top_darjeeling.u_aes, idle_o, top_darjeeling.u_clkmgr_aon, idle_i[0] CONNECTION, CLKMGR_IDLE1, top_darjeeling.u_hmac, idle_o, top_darjeeling.u_clkmgr_aon, idle_i[1] CONNECTION, CLKMGR_IDLE2, top_darjeeling.u_kmac, idle_o, top_darjeeling.u_clkmgr_aon, idle_i[2] -CONNECTION, CLKMGR_IDLE3, top_darjeeling.u_otbn, idle_o, top_darjeeling.u_clkmgr_aon, idle_i[3] +CONNECTION, CLKMGR_IDLE3, top_darjeeling.u_acc, idle_o, top_darjeeling.u_clkmgr_aon, idle_i[3] diff --git a/hw/top_darjeeling/formal/conn_csvs/clkmgr_secure.csv b/hw/top_darjeeling/formal/conn_csvs/clkmgr_secure.csv index 8cba373ecff..164fc43a8e8 100644 --- a/hw/top_darjeeling/formal/conn_csvs/clkmgr_secure.csv +++ b/hw/top_darjeeling/formal/conn_csvs/clkmgr_secure.csv @@ -22,8 +22,8 @@ CONNECTION, CLKMGR_SECURE_CLK_KEYMGR_EDN_CLK, top_darjeeling.u_clkmgr_aon, clock CONNECTION, CLKMGR_SECURE_CLK_LC_CTRL, top_darjeeling.u_clkmgr_aon, clocks_o.clk_io_secure, top_darjeeling.u_lc_ctrl, clk_i CONNECTION, CLKMGR_SECURE_KMAC_CLK_LC_CTRL, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_secure, top_darjeeling.u_lc_ctrl, clk_kmac_i -CONNECTION, CLKMGR_SECURE_CLK_OTBN_EDN_CLK, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_secure, top_darjeeling.u_otbn, clk_edn_i -CONNECTION, CLKMGR_SECURE_CLK_OTBN_OTP_CLK, top_darjeeling.u_clkmgr_aon, clocks_o.clk_io_secure, top_darjeeling.u_otbn, clk_otp_i +CONNECTION, CLKMGR_SECURE_CLK_ACC_EDN_CLK, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_secure, top_darjeeling.u_acc, clk_edn_i +CONNECTION, CLKMGR_SECURE_CLK_ACC_OTP_CLK, top_darjeeling.u_clkmgr_aon, clocks_o.clk_io_secure, top_darjeeling.u_acc, clk_otp_i CONNECTION, CLKMGR_SECURE_CLK_OTP_CTRL_CLK, top_darjeeling.u_clkmgr_aon, clocks_o.clk_io_secure, top_darjeeling.u_otp_ctrl, clk_i CONNECTION, CLKMGR_SECURE_CLK_OTP_CTRL_EDN_CLK, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_secure, top_darjeeling.u_otp_ctrl, clk_edn_i diff --git a/hw/top_darjeeling/formal/conn_csvs/clkmgr_trans.csv b/hw/top_darjeeling/formal/conn_csvs/clkmgr_trans.csv index cc145ee6c92..2523ad6795d 100644 --- a/hw/top_darjeeling/formal/conn_csvs/clkmgr_trans.csv +++ b/hw/top_darjeeling/formal/conn_csvs/clkmgr_trans.csv @@ -13,4 +13,4 @@ CONNECTION,CLKMGR_TRANS_AES_EDN, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main CONNECTION,CLKMGR_TRANS_HMAC, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_hmac, top_darjeeling.u_hmac,clk_i CONNECTION,CLKMGR_TRANS_KMAC, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_kmac, top_darjeeling.u_kmac,clk_i CONNECTION,CLKMGR_TRANS_KMAC_EDN, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_kmac, top_darjeeling.u_kmac,clk_edn_i -CONNECTION,CLKMGR_TRANS_OTBN, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_otbn, top_darjeeling.u_otbn,clk_i +CONNECTION,CLKMGR_TRANS_ACC, top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_acc, top_darjeeling.u_acc,clk_i diff --git a/hw/top_darjeeling/formal/conn_csvs/lc_ctrl_broadcast.csv b/hw/top_darjeeling/formal/conn_csvs/lc_ctrl_broadcast.csv index 677c1ed401b..e0136732fde 100644 --- a/hw/top_darjeeling/formal/conn_csvs/lc_ctrl_broadcast.csv +++ b/hw/top_darjeeling/formal/conn_csvs/lc_ctrl_broadcast.csv @@ -15,7 +15,7 @@ CONNECTION, LC_ESCALATE_EN_SRAM_RET, top_darjeeling.u_lc_ctrl, lc_escalate_en_o CONNECTION, LC_ESCALATE_EN_FLASH, top_darjeeling.u_lc_ctrl, lc_escalate_en_o, top_darjeeling.u_flash_ctrl, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_AES, top_darjeeling.u_lc_ctrl, lc_escalate_en_o, top_darjeeling.u_aes, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_KMAC, top_darjeeling.u_lc_ctrl, lc_escalate_en_o, top_darjeeling.u_kmac, lc_escalate_en_i -CONNECTION, LC_ESCALATE_EN_OTBN, top_darjeeling.u_lc_ctrl, lc_escalate_en_o, top_darjeeling.u_otbn, lc_escalate_en_i +CONNECTION, LC_ESCALATE_EN_ACC, top_darjeeling.u_lc_ctrl, lc_escalate_en_o, top_darjeeling.u_acc, lc_escalate_en_i # Verify that lc_ctrl's keymanager enable signal and diversification value are correctly connected to the keymgr. CONNECTION, LC_KEYMGR_EN_KEYMGR, top_darjeeling.u_lc_ctrl, lc_keymgr_en_o, top_darjeeling.u_keymgr, lc_keymgr_en_i @@ -44,8 +44,8 @@ CONNECTION, LC_DFT_EN_AST, top_darjeeling.u_lc_ctrl, lc_dft_en_o, u_ast, # Verify lc_ctrl's RMA request connections. CONNECTION, LC_RMA_SEED_FLASH_CTRL, top_darjeeling.u_lc_ctrl, lc_flash_rma_seed_o, top_darjeeling.u_flash_ctrl, rma_seed_i CONNECTION, LC_RMA_REQ_FLASH_CTRL, top_darjeeling.u_lc_ctrl, lc_flash_rma_req_o, top_darjeeling.u_flash_ctrl, rma_req_i -CONNECTION, FLASH_CTRL_RMA_ACK_OTBN, top_darjeeling.u_flash_ctrl, rma_ack_o, top_darjeeling.u_otbn, lc_rma_req_i -CONNECTION, OTBN_RMA_ACK_LC, top_darjeeling.u_otbn, lc_rma_ack_o, top_darjeeling.u_lc_ctrl, lc_flash_rma_ack_i +CONNECTION, FLASH_CTRL_RMA_ACK_ACC, top_darjeeling.u_flash_ctrl, rma_ack_o, top_darjeeling.u_acc, lc_rma_req_i +CONNECTION, ACC_RMA_ACK_LC, top_darjeeling.u_acc, lc_rma_ack_o, top_darjeeling.u_lc_ctrl, lc_flash_rma_ack_i # Verify lc_ctrl's clock bypass request connections. CONNECTION, LC_CLK_BYP_REQ_CLKMGR, top_darjeeling.u_lc_ctrl, lc_clk_byp_req_o, top_darjeeling.u_clkmgr_aon, lc_clk_byp_req_i diff --git a/hw/top_darjeeling/formal/conn_csvs/rstmgr_resets_o.csv b/hw/top_darjeeling/formal/conn_csvs/rstmgr_resets_o.csv index 2eb3f068c80..1c55005eef8 100644 --- a/hw/top_darjeeling/formal/conn_csvs/rstmgr_resets_o.csv +++ b/hw/top_darjeeling/formal/conn_csvs/rstmgr_resets_o.csv @@ -60,9 +60,9 @@ CONNECTION, RSTMGR_LC_D0_HMAC_RST_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_ CONNECTION, RSTMGR_LC_D0_KMAC_RST_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_kmac, rst_ni CONNECTION, RSTMGR_LC_SHADOWED_D0_KMAC_RST_SHADOWED_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_shadowed_n[1], top_darjeeling.u_kmac, rst_shadowed_ni CONNECTION, RSTMGR_LC_D0_KMAC_RST_EDN_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_kmac, rst_edn_ni -CONNECTION, RSTMGR_LC_D0_OTBN_RST_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_otbn, rst_ni -CONNECTION, RSTMGR_LC_D0_OTBN_RST_EDN_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_otbn, rst_edn_ni -CONNECTION, RSTMGR_LC_IO_D0_OTBN_RST_OTP_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_io_n[1], top_darjeeling.u_otbn, rst_otp_ni +CONNECTION, RSTMGR_LC_D0_ACC_RST_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_acc, rst_ni +CONNECTION, RSTMGR_LC_D0_ACC_RST_EDN_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_acc, rst_edn_ni +CONNECTION, RSTMGR_LC_IO_D0_ACC_RST_OTP_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_io_n[1], top_darjeeling.u_acc, rst_otp_ni CONNECTION, RSTMGR_LC_D0_KEYMGR_RST_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_keymgr, rst_ni CONNECTION, RSTMGR_LC_SHADOWED_D0_KEYMGR_RST_SHADOWED_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_shadowed_n[1], top_darjeeling.u_keymgr, rst_shadowed_ni CONNECTION, RSTMGR_LC_D0_KEYMGR_RST_EDN_NI, top_darjeeling.u_rstmgr_aon, resets_o.rst_lc_n[1], top_darjeeling.u_keymgr, rst_edn_ni diff --git a/hw/top_darjeeling/formal/top_darjeeling_fpv_sec_cm_cfgs.hjson b/hw/top_darjeeling/formal/top_darjeeling_fpv_sec_cm_cfgs.hjson index 895928c0057..24954e4d694 100644 --- a/hw/top_darjeeling/formal/top_darjeeling_fpv_sec_cm_cfgs.hjson +++ b/hw/top_darjeeling/formal/top_darjeeling_fpv_sec_cm_cfgs.hjson @@ -125,11 +125,11 @@ task: "FpvSecCm" } { - name: otbn_sec_cm - dut: otbn - fusesoc_core: lowrisc:dv:top_darjeeling_otbn_sva + name: acc_sec_cm + dut: acc + fusesoc_core: lowrisc:dv:top_darjeeling_acc_sva import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"] - rel_path: "hw/ip/otbn/{sub_flow}/{tool}" + rel_path: "hw/ip/acc/{sub_flow}/{tool}" stopats: ["*u_state_regs.state_o"] task: "FpvSecCm" } @@ -165,7 +165,7 @@ dut: rv_core_ibex fusesoc_core: lowrisc:darjeeling_dv:rv_core_ibex_sva import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"] - rel_path: "hw/ip/otbn/{sub_flow}/{tool}" + rel_path: "hw/ip/acc/{sub_flow}/{tool}" stopats: ["*if_stage_i.pc_mismatch_alert_o", "*icache_i.ecc_error_o", "*gen_regfile_ecc.rf_ecc_err_a", diff --git a/hw/top_darjeeling/ip/ast/data/ast_cdc_abstract.sgdc b/hw/top_darjeeling/ip/ast/data/ast_cdc_abstract.sgdc index 8e22579c831..e7211cd69cd 100644 --- a/hw/top_darjeeling/ip/ast/data/ast_cdc_abstract.sgdc +++ b/hw/top_darjeeling/ip/ast/data/ast_cdc_abstract.sgdc @@ -327,7 +327,7 @@ abstract_port -ports "sns_clks_i[clk_io_secure]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_io_infra]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_infra]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_io_infra]" -ignore -comment "hanging path" -abstract_port -ports "sns_clks_i[clk_main_otbn]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_acc]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_kmac]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_hmac]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_aes]" -ignore -comment "hanging path" diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson index e6929cb6d20..9b784434e08 100644 --- a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -64,7 +64,7 @@ edn1 hmac rv_plic - otbn + acc keymgr_dpe kmac sram_ctrl_main.regs @@ -102,7 +102,7 @@ edn1 hmac rv_plic - otbn + acc keymgr_dpe kmac sram_ctrl_main.regs @@ -129,7 +129,7 @@ sram_ctrl_mbox.ram aes hmac - otbn + acc keymgr_dpe kmac soc_proxy.ctn @@ -591,13 +591,13 @@ pipeline: true } { - name: otbn + name: acc type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: false rsp_fifo_pass: false - inst_type: otbn + inst_type: acc addr_range: [ { @@ -1523,7 +1523,7 @@ index: -1 } { - name: tl_otbn + name: tl_acc struct: tl package: tlul_pkg type: req_rsp @@ -1531,7 +1531,7 @@ inst_name: main width: 1 default: "" - top_signame: otbn_tl + top_signame: acc_tl index: -1 } { diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.hjson index 9b86222dfc4..d660a27fab8 100644 --- a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.hjson @@ -201,7 +201,7 @@ } { struct: "tl" type: "req_rsp" - name: "tl_otbn" + name: "tl_acc" act: "req" package: "tlul_pkg" } diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 413eea27a87..06bc40e67ba 100644 --- a/hw/top_darjeeling/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -50,7 +50,7 @@ initial force dut.rst_fixed_ni = rst_n; `CONNECT_TL_DEVICE_IF(edn0, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(edn1, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(acc, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(keymgr_dpe, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rv_core_ibex__cfg, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(sram_ctrl_main__regs, dut, clk_main_i, rst_n) diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg index 90d3a39c48b..82c717a2b49 100644 --- a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -82,10 +82,10 @@ -node tb.dut tl_edn1_o.a_address[31:30] -node tb.dut tl_rv_plic_o.a_address[28:28] -node tb.dut tl_rv_plic_o.a_address[31:30] --node tb.dut tl_otbn_o.a_address[19:17] --node tb.dut tl_otbn_o.a_address[24:21] --node tb.dut tl_otbn_o.a_address[28:26] --node tb.dut tl_otbn_o.a_address[31:30] +-node tb.dut tl_acc_o.a_address[19:17] +-node tb.dut tl_acc_o.a_address[24:21] +-node tb.dut tl_acc_o.a_address[28:26] +-node tb.dut tl_acc_o.a_address[31:30] -node tb.dut tl_keymgr_dpe_o.a_address[17:8] -node tb.dut tl_keymgr_dpe_o.a_address[19:19] -node tb.dut tl_keymgr_dpe_o.a_address[23:21] diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index 2ea01d20756..d84f410c49e 100644 --- a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -58,7 +58,7 @@ tl_device_t xbar_devices[$] = '{ '{"rv_plic", '{ '{32'h28000000, 32'h2fffffff} }}, - '{"otbn", '{ + '{"acc", '{ '{32'h22100000, 32'h2211ffff} }}, '{"keymgr_dpe", '{ @@ -138,7 +138,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr_dpe", "kmac", "sram_ctrl_main__regs", @@ -175,7 +175,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr_dpe", "kmac", "sram_ctrl_main__regs", @@ -201,7 +201,7 @@ tl_host_t xbar_hosts[$] = '{ "sram_ctrl_mbox__ram", "aes", "hmac", - "otbn", + "acc", "keymgr_dpe", "kmac", "soc_proxy__ctn", diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.sv index 2aab1c8ef27..02f4fa4f874 100644 --- a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -194,11 +194,11 @@ module xbar_main_bind; .h2d (tl_rv_plic_o), .d2h (tl_rv_plic_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_otbn ( + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_acc ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .h2d (tl_otbn_o), - .d2h (tl_otbn_i) + .h2d (tl_acc_o), + .d2h (tl_acc_i) ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_keymgr_dpe ( .clk_i (clk_main_i), diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index dddde170ec5..6d28157545a 100644 --- a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -25,7 +25,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_SPACE_EDN0 = 32'h 21170000; localparam logic [31:0] ADDR_SPACE_EDN1 = 32'h 21180000; localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 28000000; - localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 22100000; + localparam logic [31:0] ADDR_SPACE_ACC = 32'h 22100000; localparam logic [31:0] ADDR_SPACE_KEYMGR_DPE = 32'h 21140000; localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX__CFG = 32'h 211f0000; localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__REGS = 32'h 211c0000; @@ -63,7 +63,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_EDN0 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff; - localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0001ffff; + localparam logic [31:0] ADDR_MASK_ACC = 32'h 0001ffff; localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000000ff; localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG = 32'h 000007ff; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f; @@ -103,7 +103,7 @@ package tl_main_pkg; TlEdn0 = 14, TlEdn1 = 15, TlRvPlic = 16, - TlOtbn = 17, + TlAcc = 17, TlKeymgrDpe = 18, TlRvCoreIbexCfg = 19, TlSramCtrlMainRegs = 20, diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv index e65f61b641c..a62967b193f 100644 --- a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -52,7 +52,7 @@ // -> sm1_67 // -> rv_plic // -> sm1_68 -// -> otbn +// -> acc // -> sm1_69 // -> keymgr_dpe // -> sm1_70 @@ -125,7 +125,7 @@ // -> sm1_67 // -> rv_plic // -> sm1_68 -// -> otbn +// -> acc // -> sm1_69 // -> keymgr_dpe // -> sm1_70 @@ -175,7 +175,7 @@ // -> sm1_66 // -> hmac // -> sm1_68 -// -> otbn +// -> acc // -> sm1_69 // -> keymgr_dpe // -> sm1_70 @@ -297,8 +297,8 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_edn1_i, output tlul_pkg::tl_h2d_t tl_rv_plic_o, input tlul_pkg::tl_d2h_t tl_rv_plic_i, - output tlul_pkg::tl_h2d_t tl_otbn_o, - input tlul_pkg::tl_d2h_t tl_otbn_i, + output tlul_pkg::tl_h2d_t tl_acc_o, + input tlul_pkg::tl_d2h_t tl_acc_i, output tlul_pkg::tl_h2d_t tl_keymgr_dpe_o, input tlul_pkg::tl_d2h_t tl_keymgr_dpe_i, output tlul_pkg::tl_h2d_t tl_rv_core_ibex__cfg_o, @@ -1076,8 +1076,8 @@ module xbar_main ( assign tl_rv_plic_o = tl_sm1_67_ds_h2d; assign tl_sm1_67_ds_d2h = tl_rv_plic_i; - assign tl_otbn_o = tl_sm1_68_ds_h2d; - assign tl_sm1_68_ds_d2h = tl_otbn_i; + assign tl_acc_o = tl_sm1_68_ds_h2d; + assign tl_sm1_68_ds_d2h = tl_acc_i; assign tl_keymgr_dpe_o = tl_sm1_69_ds_h2d; assign tl_sm1_69_ds_d2h = tl_keymgr_dpe_i; @@ -1258,7 +1258,7 @@ end dev_sel_s1n_55 = 6'd14; end else if ((tl_s1n_55_us_h2d.a_address & - ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + ~(ADDR_MASK_ACC)) == ADDR_SPACE_ACC) begin dev_sel_s1n_55 = 6'd15; end else if ((tl_s1n_55_us_h2d.a_address & @@ -1403,7 +1403,7 @@ end dev_sel_s1n_87 = 6'd14; end else if ((tl_s1n_87_us_h2d.a_address & - ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + ~(ADDR_MASK_ACC)) == ADDR_SPACE_ACC) begin dev_sel_s1n_87 = 6'd15; end else if ((tl_s1n_87_us_h2d.a_address & @@ -1504,7 +1504,7 @@ end dev_sel_s1n_88 = 4'd3; end else if ((tl_s1n_88_us_h2d.a_address & - ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + ~(ADDR_MASK_ACC)) == ADDR_SPACE_ACC) begin dev_sel_s1n_88 = 4'd4; end else if ((tl_s1n_88_us_h2d.a_address & diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson index 0f20bad3647..fede49e99b9 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson +++ b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson @@ -119,7 +119,7 @@ 5'd17, 5'd17, 5'd16, - 5'd16, + 5'd15, 5'd15, 5'd14, 5'd14, diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson index 6495089baaf..d0d8797052f 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson @@ -123,7 +123,7 @@ 5'd14 5'd14 5'd15 - 5'd16 + 5'd15 5'd16 5'd17 5'd17 diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv index 3505d898735..accc7b3e77e 100644 --- a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -59,7 +59,7 @@ package alert_handler_reg_pkg; 5'd17, 5'd17, 5'd16, - 5'd16, + 5'd15, 5'd15, 5'd14, 5'd14, diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson index 6e8f6a1c11a..9329b9fa54e 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson @@ -81,6 +81,9 @@ { name: "CLKMGR.ENABLE.IO", desc: "Gating of IO peripheral clock." } + { name: "CLKMGR.HINT.ACC", + desc: "Gating of ACC transactional clock." + } { name: "CLKMGR.HINT.AES", desc: "Gating of AES transactional clock." } @@ -90,9 +93,6 @@ { name: "CLKMGR.HINT.KMAC", desc: "Gating of KMAC transactional clock." } - { name: "CLKMGR.HINT.OTBN", - desc: "Gating of OTBN transactional clock." - } { name: "CLKMGR.MEAS_CTRL.REGWEN", desc: '''Control modification of all clock frequency and timeout measurements. @@ -276,6 +276,15 @@ fields: [ { bits: "0", + name: "CLK_MAIN_ACC_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_ACC can be disabled. + 1 CLK_MAIN_ACC is enabled. + ''' + } + { + bits: "1", name: "CLK_MAIN_AES_HINT", resval: 1, desc: ''' @@ -284,7 +293,7 @@ ''' } { - bits: "1", + bits: "2", name: "CLK_MAIN_HMAC_HINT", resval: 1, desc: ''' @@ -293,7 +302,7 @@ ''' } { - bits: "2", + bits: "3", name: "CLK_MAIN_KMAC_HINT", resval: 1, desc: ''' @@ -301,15 +310,6 @@ 1 CLK_MAIN_KMAC is enabled. ''' } - { - bits: "3", - name: "CLK_MAIN_OTBN_HINT", - resval: 1, - desc: ''' - 0 CLK_MAIN_OTBN can be disabled. - 1 CLK_MAIN_OTBN is enabled. - ''' - } ] // the CLK_HINT register cannot be written. // During top level randomized tests, it is possible to disable the clocks to transactional blocks @@ -328,6 +328,15 @@ fields: [ { bits: "0", + name: "CLK_MAIN_ACC_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_ACC is disabled. + 1 CLK_MAIN_ACC is enabled. + ''' + } + { + bits: "1", name: "CLK_MAIN_AES_VAL", resval: 1, desc: ''' @@ -336,7 +345,7 @@ ''' } { - bits: "1", + bits: "2", name: "CLK_MAIN_HMAC_VAL", resval: 1, desc: ''' @@ -345,7 +354,7 @@ ''' } { - bits: "2", + bits: "3", name: "CLK_MAIN_KMAC_VAL", resval: 1, desc: ''' @@ -353,15 +362,6 @@ 1 CLK_MAIN_KMAC is enabled. ''' } - { - bits: "3", - name: "CLK_MAIN_OTBN_VAL", - resval: 1, - desc: ''' - 0 CLK_MAIN_OTBN is disabled. - 1 CLK_MAIN_OTBN is enabled. - ''' - } ] // the CLK_HINT_STATUS register is read-only and cannot be checked. // This register's value depends on the IDLE inputs, so cannot be predicted. diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson index 3a97d8112cc..abb1760f950 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson @@ -117,6 +117,11 @@ } hint_clks: { + clk_main_acc: + { + src_name: main + endpoint_ip: acc + } clk_main_aes: { src_name: main @@ -132,19 +137,14 @@ src_name: main endpoint_ip: kmac } - clk_main_otbn: - { - src_name: main - endpoint_ip: otbn - } } } hint_names: { + clk_main_acc: HintMainAcc clk_main_aes: HintMainAes clk_main_hmac: HintMainHmac clk_main_kmac: HintMainKmac - clk_main_otbn: HintMainOtbn } parent_child_clks: { diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md b/hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md index 6d7b882cca9..1934b2eecae 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md @@ -109,16 +109,16 @@ feedback in this case. ### Fields ```wavejson -{"reg": [{"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +{"reg": [{"name": "CLK_MAIN_ACC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} ``` | Bits | Type | Reset | Name | Description | |:------:|:------:|:-------:|:-------------------|:-------------------------------------------------------------| | 31:4 | | | | Reserved | -| 3 | rw | 0x1 | CLK_MAIN_OTBN_HINT | 0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled. | -| 2 | rw | 0x1 | CLK_MAIN_KMAC_HINT | 0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled. | -| 1 | rw | 0x1 | CLK_MAIN_HMAC_HINT | 0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled. | -| 0 | rw | 0x1 | CLK_MAIN_AES_HINT | 0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled. | +| 3 | rw | 0x1 | CLK_MAIN_KMAC_HINT | 0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled. | +| 2 | rw | 0x1 | CLK_MAIN_HMAC_HINT | 0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled. | +| 1 | rw | 0x1 | CLK_MAIN_AES_HINT | 0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled. | +| 0 | rw | 0x1 | CLK_MAIN_ACC_HINT | 0 CLK_MAIN_ACC can be disabled. 1 CLK_MAIN_ACC is enabled. | ## CLK_HINTS_STATUS Since the final state of [`CLK_HINTS`](#clk_hints) is not always determined by software, @@ -131,16 +131,16 @@ this register provides read feedback for the current clock state. ### Fields ```wavejson -{"reg": [{"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +{"reg": [{"name": "CLK_MAIN_ACC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} ``` | Bits | Type | Reset | Name | Description | |:------:|:------:|:-------:|:------------------|:---------------------------------------------------------| | 31:4 | | | | Reserved | -| 3 | ro | 0x1 | CLK_MAIN_OTBN_VAL | 0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled. | -| 2 | ro | 0x1 | CLK_MAIN_KMAC_VAL | 0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled. | -| 1 | ro | 0x1 | CLK_MAIN_HMAC_VAL | 0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled. | -| 0 | ro | 0x1 | CLK_MAIN_AES_VAL | 0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled. | +| 3 | ro | 0x1 | CLK_MAIN_KMAC_VAL | 0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled. | +| 2 | ro | 0x1 | CLK_MAIN_HMAC_VAL | 0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled. | +| 1 | ro | 0x1 | CLK_MAIN_AES_VAL | 0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled. | +| 0 | ro | 0x1 | CLK_MAIN_ACC_VAL | 0 CLK_MAIN_ACC is disabled. 1 CLK_MAIN_ACC is enabled. | ## MEASURE_CTRL_REGWEN Measurement control write enable diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/clkmgr/doc/theory_of_operation.md index 65235548bb9..649088f343e 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/doc/theory_of_operation.md +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/theory_of_operation.md @@ -19,7 +19,7 @@ The table shows the group name, the modules that belong to each group, and wheth | Group | Frequencies | Modules | Software | Wait for Interrupt | | ------------- | ------------------------------ | -------------------------------------------------------------- | -------------- | ------------------ | | Power-up | 100~200KHz, 24MHz | Clock Manager, Power Manager, Reset Manager, Pinmux | No | No | -| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Otbn | Yes (1) | Yes (2) | +| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Acc | Yes (1) | Yes (2) | | Infrastructural | 24MHz, ~100MHz | Fabric, Fabric gaskets (iopmp), Memories | No | Yes (3) | | Security | 24MHz, ~100MHz | Alert handler, Entropy, Life cycle, Plic, Sensors | No | No | | Peripheral | 24MHz, 48MHz, 96MHz | I2c, Spi, Uart, Usb, others | Yes | Yes | @@ -175,7 +175,7 @@ Note, the power manager's request to turn off clocks supersedes all other local This means even if a particular clock is turned on by the clock manager (for example a transactional unit that is ongoing or a peripheral that is enabled), the power manager requests will still turn clocks on / off at the root. This makes it software's responsibility to ensure low power entry requests (which can only be initiated by software) do not conflict with any ongoing activities controlled by software. -For example, software should ensure that Aes / Otbn activities have completed before initializing a low power entry process. +For example, software should ensure that Aes / Acc activities have completed before initializing a low power entry process. ### Clock Division diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md b/hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md index 8cbac45f145..d2c78b1e77c 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md @@ -54,7 +54,7 @@ All common types and methods defined at the package level can be found in typedef enum int { PeriIo } peri_e; - typedef enum int {TransAes, TransHmac, TransKmac, TransOtbn} trans_e; + typedef enum int {TransAes, TransHmac, TransKmac, TransAcc} trans_e; ``` ### TL_agent diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el index ca5f99828dd..326e1d3c68c 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el @@ -24,7 +24,7 @@ INSTANCE: tb.dut.u_clk_main_kmac_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "2301929872 1660332954" -INSTANCE: tb.dut.u_clk_main_otbn_trans.u_idle_cnt +INSTANCE: tb.dut.u_clk_main_acc_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "953655365 3155586170" diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el index 85e292d7a9f..761e9fac2e7 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el @@ -25,7 +25,7 @@ INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3274445021" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3554514034" @@ -47,7 +47,7 @@ Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" CHECKSUM: "2972535896 3554514034" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv index ea526c34cb5..094c99e3de4 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv @@ -61,16 +61,16 @@ package clkmgr_env_pkg; } clk_enables_t; typedef enum int { + TransAcc, TransAes, TransHmac, - TransKmac, - TransOtbn + TransKmac } trans_e; typedef struct packed { - logic otbn; logic kmac; logic hmac; logic aes; + logic acc; } clk_hints_t; typedef struct { diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv index c87bca193ac..1275c526a1b 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv @@ -52,19 +52,19 @@ interface clkmgr_if ( clk_hints_t clk_hints_csr; always_comb clk_hints_csr = '{ - otbn: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_otbn_hint.q, kmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_kmac_hint.q, hmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_hmac_hint.q, - aes: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_aes_hint.q + aes: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_aes_hint.q, + acc: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_acc_hint.q }; clk_hints_t clk_hints_status_csr; always_comb clk_hints_status_csr = '{ - otbn: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_otbn_val_qs, kmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_kmac_val_qs, hmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_hmac_val_qs, - aes: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_aes_val_qs + aes: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_aes_val_qs, + acc: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_acc_val_qs }; prim_mubi_pkg::mubi4_t jitter_enable_csr; always_comb begin diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv index 32a3dc315e9..bbc5d6377b9 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv @@ -67,10 +67,10 @@ class clkmgr_smoke_vseq extends clkmgr_base_vseq; uvm_reg_field value_bit; } trans_descriptor_t; trans_descriptor_t trans_descriptors[NUM_TRANS] = '{ + '{TransAcc, ral.clk_hints.clk_main_acc_hint, ral.clk_hints_status.clk_main_acc_val}, '{TransAes, ral.clk_hints.clk_main_aes_hint, ral.clk_hints_status.clk_main_aes_val}, '{TransHmac, ral.clk_hints.clk_main_hmac_hint, ral.clk_hints_status.clk_main_hmac_val}, - '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val}, - '{TransOtbn, ral.clk_hints.clk_main_otbn_hint, ral.clk_hints_status.clk_main_otbn_val} + '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val} }; idle = 0; // Changes in idle take at least 10 cycles to stick. diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv index 25b4291c852..a8bb10ba113 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv @@ -37,6 +37,16 @@ module clkmgr_bind; ); // Assertions for transactional clocks. + bind clkmgr clkmgr_trans_sva_if clkmgr_acc_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_acc_hint.q), + .idle(idle_i[HintMainAcc] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_acc_val.d), + .trans_clk(clocks_o.clk_main_acc) + ); + bind clkmgr clkmgr_trans_sva_if clkmgr_aes_trans_sva_if ( .clk(clk_main_i), .rst_n(rst_main_ni), @@ -67,16 +77,6 @@ module clkmgr_bind; .trans_clk(clocks_o.clk_main_kmac) ); - bind clkmgr clkmgr_trans_sva_if clkmgr_otbn_trans_sva_if ( - .clk(clk_main_i), - .rst_n(rst_main_ni), - .hint(reg2hw.clk_hints.clk_main_otbn_hint.q), - .idle(idle_i[HintMainOtbn] == prim_mubi_pkg::MuBi4True), - .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), - .status(hw2reg.clk_hints_status.clk_main_otbn_val.d), - .trans_clk(clocks_o.clk_main_otbn) - ); - // AON clock gating enables. bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_infra ( @@ -156,6 +156,15 @@ module clkmgr_bind; ); // Hint controlled gating enables. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_acc ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_acc_trans.sw_hint_synced || !u_clk_main_acc_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_acc == prim_mubi_pkg::MuBi4True) + ); + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_aes ( .clk(clk_main_i), .rst_n(rst_main_ni), @@ -183,14 +192,5 @@ module clkmgr_bind; .cg_en(cg_en_o.main_kmac == prim_mubi_pkg::MuBi4True) ); - bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_otbn ( - .clk(clk_main_i), - .rst_n(rst_main_ni), - .ip_clk_en(clk_main_en), - .sw_clk_en(u_clk_main_otbn_trans.sw_hint_synced || !u_clk_main_otbn_trans.idle_valid), - .scanmode(prim_mubi_pkg::MuBi4False), - .cg_en(cg_en_o.main_otbn == prim_mubi_pkg::MuBi4True) - ); - `endif endmodule : clkmgr_bind diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv index 60d58bc4153..707336e7ced 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv @@ -77,7 +77,7 @@ module tb; .clk_enables({ reg2hw.clk_enables.q}), .clk_hints({ - reg2hw.clk_hints.clk_main_otbn_hint.q, + reg2hw.clk_hints.clk_main_acc_hint.q, reg2hw.clk_hints.clk_main_kmac_hint.q, reg2hw.clk_hints.clk_main_hmac_hint.q, reg2hw.clk_hints.clk_main_aes_hint.q}) diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv index 453211765f7..05a5f512988 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv @@ -488,6 +488,28 @@ logic [3:0] idle_cnt_err; + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_acc_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainAcc]), + .sw_hint_i(reg2hw.clk_hints.clk_main_acc_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_acc), + .clk_o(clocks_o.clk_main_acc), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_acc_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainAcc]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainAccCountCheck_A, + u_clk_main_acc_trans.u_idle_cnt, + alert_tx_o[1]) + clkmgr_trans #( .FpgaBufGlobal(1'b0) // This clock is used primarily locally. ) u_clk_main_aes_trans ( @@ -553,36 +575,14 @@ ClkMainKmacCountCheck_A, u_clk_main_kmac_trans.u_idle_cnt, alert_tx_o[1]) - - clkmgr_trans #( - .FpgaBufGlobal(1'b0) // This clock is used primarily locally. - ) u_clk_main_otbn_trans ( - .clk_i(clk_main), - .clk_gated_i(clk_main_root), - .rst_ni(rst_main_ni), - .en_i(clk_main_en), - .idle_i(idle_i[HintMainOtbn]), - .sw_hint_i(reg2hw.clk_hints.clk_main_otbn_hint.q), - .scanmode_i, - .alert_cg_en_o(cg_en_o.main_otbn), - .clk_o(clocks_o.clk_main_otbn), - .clk_reg_i(clk_i), - .rst_reg_ni(rst_ni), - .reg_en_o(hw2reg.clk_hints_status.clk_main_otbn_val.d), - .reg_cnt_err_o(idle_cnt_err[HintMainOtbn]) - ); - `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( - ClkMainOtbnCountCheck_A, - u_clk_main_otbn_trans.u_idle_cnt, - alert_tx_o[1]) assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1; assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err; // state readback + assign hw2reg.clk_hints_status.clk_main_acc_val.de = 1'b1; assign hw2reg.clk_hints_status.clk_main_aes_val.de = 1'b1; assign hw2reg.clk_hints_status.clk_main_hmac_val.de = 1'b1; assign hw2reg.clk_hints_status.clk_main_kmac_val.de = 1'b1; - assign hw2reg.clk_hints_status.clk_main_otbn_val.de = 1'b1; // SEC_CM: JITTER.CONFIG.MUBI assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q); diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv index d1d4b29bab7..90e34e43db1 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv @@ -5,10 +5,10 @@ package clkmgr_pkg; typedef enum int { - HintMainAes = 0, - HintMainHmac = 1, - HintMainKmac = 2, - HintMainOtbn = 3 + HintMainAcc = 0, + HintMainAes = 1, + HintMainHmac = 2, + HintMainKmac = 3 } hint_names_e; // clocks generated and broadcast @@ -18,10 +18,10 @@ package clkmgr_pkg; logic clk_main_powerup; logic clk_aon_infra; logic clk_aon_timers; + logic clk_main_acc; logic clk_main_aes; logic clk_main_hmac; logic clk_main_kmac; - logic clk_main_otbn; logic clk_io_infra; logic clk_main_infra; logic clk_io_secure; @@ -37,10 +37,10 @@ package clkmgr_pkg; prim_mubi_pkg::mubi4_t main_powerup; prim_mubi_pkg::mubi4_t aon_infra; prim_mubi_pkg::mubi4_t aon_timers; + prim_mubi_pkg::mubi4_t main_acc; prim_mubi_pkg::mubi4_t main_aes; prim_mubi_pkg::mubi4_t main_hmac; prim_mubi_pkg::mubi4_t main_kmac; - prim_mubi_pkg::mubi4_t main_otbn; prim_mubi_pkg::mubi4_t io_infra; prim_mubi_pkg::mubi4_t main_infra; prim_mubi_pkg::mubi4_t io_secure; diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv index 2b6fdf4b722..fbaa54e75db 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv @@ -48,9 +48,6 @@ package clkmgr_reg_pkg; } clkmgr_reg2hw_clk_enables_reg_t; typedef struct packed { - struct packed { - logic q; - } clk_main_otbn_hint; struct packed { logic q; } clk_main_kmac_hint; @@ -60,6 +57,9 @@ package clkmgr_reg_pkg; struct packed { logic q; } clk_main_aes_hint; + struct packed { + logic q; + } clk_main_acc_hint; } clkmgr_reg2hw_clk_hints_reg_t; typedef struct packed { @@ -105,10 +105,6 @@ package clkmgr_reg_pkg; } clkmgr_reg2hw_fatal_err_code_reg_t; typedef struct packed { - struct packed { - logic d; - logic de; - } clk_main_otbn_val; struct packed { logic d; logic de; @@ -121,6 +117,10 @@ package clkmgr_reg_pkg; logic d; logic de; } clk_main_aes_val; + struct packed { + logic d; + logic de; + } clk_main_acc_val; } clkmgr_hw2reg_clk_hints_status_reg_t; typedef struct packed { diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv index ed23427ec60..29487f33fad 100644 --- a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv @@ -142,18 +142,18 @@ module clkmgr_reg_top ( logic clk_enables_qs; logic clk_enables_wd; logic clk_hints_we; + logic clk_hints_clk_main_acc_hint_qs; + logic clk_hints_clk_main_acc_hint_wd; logic clk_hints_clk_main_aes_hint_qs; logic clk_hints_clk_main_aes_hint_wd; logic clk_hints_clk_main_hmac_hint_qs; logic clk_hints_clk_main_hmac_hint_wd; logic clk_hints_clk_main_kmac_hint_qs; logic clk_hints_clk_main_kmac_hint_wd; - logic clk_hints_clk_main_otbn_hint_qs; - logic clk_hints_clk_main_otbn_hint_wd; + logic clk_hints_status_clk_main_acc_val_qs; logic clk_hints_status_clk_main_aes_val_qs; logic clk_hints_status_clk_main_hmac_val_qs; logic clk_hints_status_clk_main_kmac_val_qs; - logic clk_hints_status_clk_main_otbn_val_qs; logic measure_ctrl_regwen_we; logic measure_ctrl_regwen_qs; logic measure_ctrl_regwen_wd; @@ -494,19 +494,19 @@ module clkmgr_reg_top ( // R[clk_hints]: V(False) - // F[clk_main_aes_hint]: 0:0 + // F[clk_main_acc_hint]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_aes_hint ( + ) u_clk_hints_clk_main_acc_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_aes_hint_wd), + .wd (clk_hints_clk_main_acc_hint_wd), // from internal hardware .de (1'b0), @@ -514,26 +514,26 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_aes_hint.q), + .q (reg2hw.clk_hints.clk_main_acc_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_aes_hint_qs) + .qs (clk_hints_clk_main_acc_hint_qs) ); - // F[clk_main_hmac_hint]: 1:1 + // F[clk_main_aes_hint]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_hmac_hint ( + ) u_clk_hints_clk_main_aes_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_hmac_hint_wd), + .wd (clk_hints_clk_main_aes_hint_wd), // from internal hardware .de (1'b0), @@ -541,26 +541,26 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_hmac_hint.q), + .q (reg2hw.clk_hints.clk_main_aes_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_hmac_hint_qs) + .qs (clk_hints_clk_main_aes_hint_qs) ); - // F[clk_main_kmac_hint]: 2:2 + // F[clk_main_hmac_hint]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_kmac_hint ( + ) u_clk_hints_clk_main_hmac_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_kmac_hint_wd), + .wd (clk_hints_clk_main_hmac_hint_wd), // from internal hardware .de (1'b0), @@ -568,26 +568,26 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_kmac_hint.q), + .q (reg2hw.clk_hints.clk_main_hmac_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_kmac_hint_qs) + .qs (clk_hints_clk_main_hmac_hint_qs) ); - // F[clk_main_otbn_hint]: 3:3 + // F[clk_main_kmac_hint]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_otbn_hint ( + ) u_clk_hints_clk_main_kmac_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_otbn_hint_wd), + .wd (clk_hints_clk_main_kmac_hint_wd), // from internal hardware .de (1'b0), @@ -595,22 +595,22 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_otbn_hint.q), + .q (reg2hw.clk_hints.clk_main_kmac_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_otbn_hint_qs) + .qs (clk_hints_clk_main_kmac_hint_qs) ); // R[clk_hints_status]: V(False) - // F[clk_main_aes_val]: 0:0 + // F[clk_main_acc_val]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_aes_val ( + ) u_clk_hints_status_clk_main_acc_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -619,8 +619,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_aes_val.de), - .d (hw2reg.clk_hints_status.clk_main_aes_val.d), + .de (hw2reg.clk_hints_status.clk_main_acc_val.de), + .d (hw2reg.clk_hints_status.clk_main_acc_val.d), // to internal hardware .qe (), @@ -628,16 +628,16 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_aes_val_qs) + .qs (clk_hints_status_clk_main_acc_val_qs) ); - // F[clk_main_hmac_val]: 1:1 + // F[clk_main_aes_val]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_hmac_val ( + ) u_clk_hints_status_clk_main_aes_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -646,8 +646,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_hmac_val.de), - .d (hw2reg.clk_hints_status.clk_main_hmac_val.d), + .de (hw2reg.clk_hints_status.clk_main_aes_val.de), + .d (hw2reg.clk_hints_status.clk_main_aes_val.d), // to internal hardware .qe (), @@ -655,16 +655,16 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_hmac_val_qs) + .qs (clk_hints_status_clk_main_aes_val_qs) ); - // F[clk_main_kmac_val]: 2:2 + // F[clk_main_hmac_val]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_kmac_val ( + ) u_clk_hints_status_clk_main_hmac_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -673,8 +673,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_kmac_val.de), - .d (hw2reg.clk_hints_status.clk_main_kmac_val.d), + .de (hw2reg.clk_hints_status.clk_main_hmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_hmac_val.d), // to internal hardware .qe (), @@ -682,16 +682,16 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_kmac_val_qs) + .qs (clk_hints_status_clk_main_hmac_val_qs) ); - // F[clk_main_otbn_val]: 3:3 + // F[clk_main_kmac_val]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_otbn_val ( + ) u_clk_hints_status_clk_main_kmac_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -700,8 +700,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_otbn_val.de), - .d (hw2reg.clk_hints_status.clk_main_otbn_val.d), + .de (hw2reg.clk_hints_status.clk_main_kmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_kmac_val.d), // to internal hardware .qe (), @@ -709,7 +709,7 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_otbn_val_qs) + .qs (clk_hints_status_clk_main_kmac_val_qs) ); @@ -1331,13 +1331,13 @@ module clkmgr_reg_top ( assign clk_enables_wd = reg_wdata[0]; assign clk_hints_we = addr_hit[4] & reg_we & !reg_error; - assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0]; + assign clk_hints_clk_main_acc_hint_wd = reg_wdata[0]; - assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1]; + assign clk_hints_clk_main_aes_hint_wd = reg_wdata[1]; - assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2]; + assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[2]; - assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3]; + assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[3]; assign measure_ctrl_regwen_we = addr_hit[6] & reg_we & !reg_error; assign measure_ctrl_regwen_wd = reg_wdata[0]; @@ -1404,17 +1404,17 @@ module clkmgr_reg_top ( end addr_hit[4]: begin - reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs; - reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs; - reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs; - reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs; + reg_rdata_next[0] = clk_hints_clk_main_acc_hint_qs; + reg_rdata_next[1] = clk_hints_clk_main_aes_hint_qs; + reg_rdata_next[2] = clk_hints_clk_main_hmac_hint_qs; + reg_rdata_next[3] = clk_hints_clk_main_kmac_hint_qs; end addr_hit[5]: begin - reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs; - reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs; - reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs; - reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs; + reg_rdata_next[0] = clk_hints_status_clk_main_acc_val_qs; + reg_rdata_next[1] = clk_hints_status_clk_main_aes_val_qs; + reg_rdata_next[2] = clk_hints_status_clk_main_hmac_val_qs; + reg_rdata_next[3] = clk_hints_status_clk_main_kmac_val_qs; end addr_hit[6]: begin diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl.hjson b/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl.hjson index 1d52c2b9405..3f33363791b 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl.hjson +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl.hjson @@ -2041,14 +2041,14 @@ package: "otp_ctrl_pkg" desc: "Array with key derivation interfaces for SRAM scrambling devices." } - // Key request from OTBN RAM Scrambler - { struct: "otbn_otp_key" + // Key request from ACC RAM Scrambler + { struct: "acc_otp_key" type: "req_rsp" - name: "otbn_otp_key" + name: "acc_otp_key" act: "rsp" default: "'0" package: "otp_ctrl_pkg" - desc: "Key derivation interface for OTBN scrambling devices." + desc: "Key derivation interface for ACC scrambling devices." } // Hardware config partition { struct: "otp_broadcast" diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson b/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson index fa243c7b4ec..420c715d586 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson @@ -40,7 +40,7 @@ - drive pwrmgr's request pin to trigger OTP initialization after reset, check status after OTP initialization - - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `otbn` + - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `acc` - randomly issue LC program request - write random values to random addresses within each OTP partition - read out the random selected write addresses, check if the readout values are expected @@ -143,7 +143,7 @@ { name: interface_key_check desc: ''' - OTP_CTRL will generate keys to `flash`, `sram`, and `otbn` upon their requests. + OTP_CTRL will generate keys to `flash`, `sram`, and `acc` upon their requests. Based on the DAI access sequence, this test will run key requests sequence in parallel, and check if correct keys are generated. ''' @@ -266,8 +266,8 @@ desc: '''Covers whether secret1 partition is locked during all `srams` key request.''' } { - name: otbn_req_cg - desc: '''Covers whether secret1 partition is locked during `otbn` key request.''' + name: acc_req_cg + desc: '''Covers whether secret1 partition is locked during `acc` key request.''' } { name: lc_prog_cg @@ -364,7 +364,7 @@ ''' } { - name: otbn_req_condition_cg + name: acc_req_condition_cg desc: '''Covers the following conditions when `lc_escalation_en` is On: - whether any key requests is in progress - whether DAI interface is busy diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/interfaces.md b/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/interfaces.md index 185ff3b1562..5a6fb15e726 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/interfaces.md +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/interfaces.md @@ -39,7 +39,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | lc_check_byp_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Life cycle partition check bypass signal. This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. | | otp_keymgr_key | otp_ctrl_pkg::otp_keymgr_key | uni | req | 1 | Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. | | sram_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | rsp | 4 | Array with key derivation interfaces for SRAM scrambling devices. | -| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | rsp | 1 | Key derivation interface for OTBN scrambling devices. | +| acc_otp_key | otp_ctrl_pkg::acc_otp_key | req_rsp | rsp | 1 | Key derivation interface for ACC scrambling devices. | | otp_broadcast | otp_ctrl_part_pkg::otp_broadcast | uni | req | 1 | Output of the HW partitions with breakout data types. | | otp_macro | otp_ctrl_macro_pkg::otp_ctrl_macro | req_rsp | req | 1 | Data interface for the OTP macro. | | core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | @@ -213,21 +213,21 @@ Otherwise, this signal is tied to a random netlist constant. Since the key manager may run in a different clock domain, key manager is responsible for synchronizing the `otp_keymgr_key_o` signals. -### Interfaces to SRAM and OTBN Scramblers +### Interfaces to SRAM and ACC Scramblers -The interfaces to the SRAM and OTBN scrambling devices follow a req / ack protocol, where the scrambling device first requests a new ephemeral key by asserting the request channel (`sram_otp_key_i[*]`, `otbn_otp_key_i`). +The interfaces to the SRAM and ACC scrambling devices follow a req / ack protocol, where the scrambling device first requests a new ephemeral key by asserting the request channel (`sram_otp_key_i[*]`, `acc_otp_key_i`). The OTP controller then fetches entropy from EDN and derives an ephemeral key using the SRAM_DATA_KEY_SEED and the [PRESENT scrambling data path](#scrambling-datapath). -Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `otbn_otp_key_o`), which complete the req / ack handshake. -The wave diagram below illustrates this process for the OTBN scrambling device. +Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `acc_otp_key_o`), which complete the req / ack handshake. +The wave diagram below illustrates this process for the ACC scrambling device. ```wavejson {signal: [ {name: 'clk_i', wave: 'p.......'}, - {name: 'otbn_otp_key_i.req', wave: '01.|..0.'}, - {name: 'otbn_otp_key_o.ack', wave: '0..|.10.'}, - {name: 'otbn_otp_key_o.nonce', wave: '0..|.30.'}, - {name: 'otbn_otp_key_o.key', wave: '0..|.30.'}, - {name: 'otbn_otp_key_o.seed_valid', wave: '0..|.10.'}, + {name: 'acc_otp_key_i.req', wave: '01.|..0.'}, + {name: 'acc_otp_key_o.ack', wave: '0..|.10.'}, + {name: 'acc_otp_key_o.nonce', wave: '0..|.30.'}, + {name: 'acc_otp_key_o.key', wave: '0..|.30.'}, + {name: 'acc_otp_key_o.seed_valid', wave: '0..|.10.'}, ]} ``` diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/theory_of_operation.md index ced9c642c8d..b283427e41e 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/theory_of_operation.md +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/doc/theory_of_operation.md @@ -426,7 +426,7 @@ In case of unrecoverable OTP errors, the FSM signals an error to the life cycle ![Key Derivation Interface FSM](otp_ctrl_kdi_fsm.svg) Upon reset release the KDI FSM waits until the OTP controller has initialized and the KDI gets enabled. -Once it is in the idle state, key derivation can be requested via the [flash](interfaces.md#interface-to-flash-scrambler) and [sram](interfaces.md#interface-to-sram-and-otbn-scramblers) interfaces. +Once it is in the idle state, key derivation can be requested via the [flash](interfaces.md#interface-to-flash-scrambler) and [sram](interfaces.md#interface-to-sram-and-acc-scramblers) interfaces. Based on which interface makes the request, the KDI controller will evaluate a variant of the PRESENT digest mechanism as described in more detail below. ### Scrambling Datapath diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/README.md b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/README.md index ce4b8ccf700..390734441bb 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/README.md +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/README.md @@ -64,7 +64,7 @@ fatal_check_alert and fatal_macro_alert. The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in OTP_CTRL device. ### OTP_CTRL interface -OTP_CTRL design has specific inputs and outputs to communicate with other IPs including LC_CTRL, OTBN, SRAM, FLASH etc. +OTP_CTRL design has specific inputs and outputs to communicate with other IPs including LC_CTRL, ACC, SRAM, FLASH etc. This interface is created to initialize, use simple task to drive, and use assertions to monitor these signals. ### Memory backdoor interface @@ -107,7 +107,7 @@ It creates the following analysis ports to retrieve the data monitored by corres * tl_d_chan_fifo: tl data channel * alert_fifos: alert handshakes * sram_fifos: sram requests -* otbn_fifo: otbn request +* acc_fifo: acc request * lc_prog_fifo: life cycle programming request * lc_token_fifo: life cycle token request * edn_fifo: edn response to OTP_CTRL diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv index 8c19c58c398..b2cfcd6ff7a 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv @@ -32,7 +32,7 @@ module otp_ctrl_cov_bind; .lc_otp_program_i (lc_otp_program_i), .lc_escalate_en_i (lc_escalate_en_i), .sram_otp_key_i (sram_otp_key_i), - .otbn_otp_key_i (otbn_otp_key_i) + .acc_otp_key_i (acc_otp_key_i) ); bind otp_ctrl cip_lc_tx_cov_if u_lc_creator_seed_sw_rw_en_cov_if ( diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv index 344adf6845b..81c3dea5792 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv @@ -11,7 +11,7 @@ interface otp_ctrl_cov_if input otp_ctrl_pkg::lc_otp_program_req_t lc_otp_program_i, input bit [3:0] lc_escalate_en_i, input otp_ctrl_pkg::sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, - input otp_ctrl_pkg::otbn_otp_key_req_t otbn_otp_key_i + input otp_ctrl_pkg::acc_otp_key_req_t acc_otp_key_i ); import uvm_pkg::*; @@ -21,7 +21,7 @@ interface otp_ctrl_cov_if covergroup lc_esc_en_condition_cg @(lc_escalate_en_i == lc_ctrl_pkg::On); lc_esc_during_sram_0_req: coverpoint sram_otp_key_i[0].req; lc_esc_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - lc_esc_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_esc_during_acc_req: coverpoint acc_otp_key_i.req; lc_esc_during_otp_idle: coverpoint pwr_otp_o.otp_idle; lc_esc_during_lc_otp_prog_req: coverpoint lc_otp_program_i.req; endgroup @@ -33,7 +33,7 @@ interface otp_ctrl_cov_if bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; } sram_0_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - sram_0_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_0_req_during_acc_req: coverpoint acc_otp_key_i.req; sram_0_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -43,18 +43,18 @@ interface otp_ctrl_cov_if bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; } sram_1_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; - sram_1_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_1_req_during_acc_req: coverpoint acc_otp_key_i.req; sram_1_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup - covergroup otbn_req_condition_cg @(otbn_otp_key_i.req); - otbn_req_during_lc_esc: coverpoint lc_escalate_en_i { + covergroup acc_req_condition_cg @(acc_otp_key_i.req); + acc_req_during_lc_esc: coverpoint lc_escalate_en_i { bins lc_esc_on = {lc_ctrl_pkg::On}; bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; } - otbn_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; - otbn_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - otbn_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + acc_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + acc_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + acc_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup covergroup lc_prog_req_condition_cg @(lc_otp_program_i.req); @@ -64,14 +64,14 @@ interface otp_ctrl_cov_if } lc_prog_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; lc_prog_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - lc_prog_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_prog_req_during_acc_req: coverpoint acc_otp_key_i.req; lc_prog_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup `DV_FCOV_INSTANTIATE_CG(lc_esc_en_condition_cg) `DV_FCOV_INSTANTIATE_CG(sram_0_req_condition_cg) `DV_FCOV_INSTANTIATE_CG(sram_1_req_condition_cg) - `DV_FCOV_INSTANTIATE_CG(otbn_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(acc_req_condition_cg) `DV_FCOV_INSTANTIATE_CG(lc_prog_req_condition_cg) endinterface diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv index da818238122..269577a8ec7 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv @@ -19,7 +19,7 @@ class otp_ctrl_env #( `uvm_component_new push_pull_agent#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent[NumSramKeyReqSlots]; - push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent; + push_pull_agent#(.DeviceDataWidth(ACC_DATA_SIZE)) m_acc_pull_agent; push_pull_agent#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) m_lc_prog_pull_agent; function void build_phase(uvm_phase phase); @@ -34,11 +34,11 @@ class otp_ctrl_env #( $sformatf("%0s*", sram_agent_name), "cfg", cfg.m_sram_pull_agent_cfg[i]); end - // build otbn-otp pull agent - m_otbn_pull_agent = push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id::create( - "m_otbn_pull_agent", this); - uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set( - this, "m_otbn_pull_agent", "cfg", cfg.m_otbn_pull_agent_cfg); + // build acc-otp pull agent + m_acc_pull_agent = push_pull_agent#(.DeviceDataWidth(ACC_DATA_SIZE))::type_id::create( + "m_acc_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE)))::set( + this, "m_acc_pull_agent", "cfg", cfg.m_acc_pull_agent_cfg); // build lc-otp program pull agent m_lc_prog_pull_agent = push_pull_agent#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1)) @@ -73,11 +73,11 @@ class otp_ctrl_env #( end end - virtual_sequencer.otbn_pull_sequencer_h = m_otbn_pull_agent.sequencer; + virtual_sequencer.acc_pull_sequencer_h = m_acc_pull_agent.sequencer; virtual_sequencer.lc_prog_pull_sequencer_h = m_lc_prog_pull_agent.sequencer; if (cfg.en_scb) begin - m_otbn_pull_agent.monitor.analysis_port.connect(scoreboard.otbn_fifo.analysis_export); + m_acc_pull_agent.monitor.analysis_port.connect(scoreboard.acc_fifo.analysis_export); m_lc_prog_pull_agent.monitor.analysis_port.connect(scoreboard.lc_prog_fifo.analysis_export); end diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv index cb4335d2809..fe9bc59277b 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv @@ -19,7 +19,7 @@ class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block // ext component cfgs rand push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent_cfg[NumSramKeyReqSlots]; - rand push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent_cfg; + rand push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE)) m_acc_pull_agent_cfg; rand push_pull_agent_cfg#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) m_lc_prog_pull_agent_cfg; @@ -73,9 +73,9 @@ class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block m_sram_pull_agent_cfg[i].agent_type = PullAgent; end - m_otbn_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id - ::create("m_otbn_pull_agent_cfg"); - m_otbn_pull_agent_cfg.agent_type = PullAgent; + m_acc_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE))::type_id + ::create("m_acc_pull_agent_cfg"); + m_acc_pull_agent_cfg.agent_type = PullAgent; m_lc_prog_pull_agent_cfg = push_pull_agent_cfg#(.HostDataWidth(LC_PROG_DATA_SIZE), diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv index 2d5fa5b6bdd..23b2b94ac6d 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv @@ -182,7 +182,7 @@ class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); bit_toggle_cg_wrap lc_prog_cg; - bit_toggle_cg_wrap otbn_req_cg; + bit_toggle_cg_wrap acc_req_cg; bit_toggle_cg_wrap status_csr_cg[OtpStatusFieldSize]; // covergroups @@ -493,7 +493,7 @@ class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); super.build_phase(phase); // Create instances from bit_toggle_cg_wrapper. lc_prog_cg = new("lc_prog_cg", "", 0); - otbn_req_cg = new("otbn_req_cg", "", 0); + acc_req_cg = new("acc_req_cg", "", 0); foreach (status_csr_cg[i]) begin otp_status_e index = otp_status_e'(i); status_csr_cg[i]= new(index.name, "status_csr_cg", 0); diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv index 3719d622d89..48c1450c7b8 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv @@ -58,13 +58,13 @@ package otp_ctrl_env_pkg; // sram rsp data has 1 bit for seed_valid, the rest are for key and nonce parameter uint SRAM_DATA_SIZE = 1 + SramKeyWidth + SramNonceWidth; - // otbn rsp data has 1 bit for seed_valid, the rest are for key and nonce - parameter uint OTBN_DATA_SIZE = 1 + OtbnKeyWidth + OtbnNonceWidth; + // acc rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint ACC_DATA_SIZE = 1 + AccKeyWidth + AccNonceWidth; // lc program data has lc_state data and lc_cnt data parameter uint LC_PROG_DATA_SIZE = LcStateWidth + LcCountWidth; parameter uint NUM_SRAM_EDN_REQ = 12; - parameter uint NUM_OTBN_EDN_REQ = 10; + parameter uint NUM_ACC_EDN_REQ = 10; // This is used to randomize CHECK_TIMEOUT in sequences, set to a low value // so it will certainly cause a check error due to a timeout. diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv index cd6f70bb4f6..c7a0c0b9db6 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv @@ -69,7 +69,7 @@ interface otp_ctrl_if(input clk_i, input rst_ni); logic lc_prog_err_dly1, lc_prog_no_sta_check; // Connect push_pull interfaces ack signals for assertion checks. - logic otbn_ack, lc_prog_ack; + logic acc_ack, lc_prog_ack; logic [NumSramKeyReqSlots-1:0] sram_acks; // Variables for internal interface logic. @@ -455,7 +455,7 @@ interface otp_ctrl_if(input clk_i, input rst_ni); `OTP_FATAL_ERR_ASSERT(LcProgAck_A, lc_prog_ack == 0) `OTP_FATAL_ERR_ASSERT(SramAcks_A, sram_acks == 0) - `OTP_FATAL_ERR_ASSERT(OtbnAck_A, otbn_ack == 0) + `OTP_FATAL_ERR_ASSERT(AccAck_A, acc_ack == 0) `undef OTP_ASSERT_WO_LC_ESC `undef OTP_FATAL_ERR_ASSERT diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv index cc1bea3bf73..5153ff9f417 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv @@ -46,7 +46,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) // TLM agent fifos uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE))) sram_fifos[NumSramKeyReqSlots]; - uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE))) otbn_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(ACC_DATA_SIZE))) acc_fifo; uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE))) lc_prog_fifo; @@ -59,7 +59,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) for (int i = 0; i < NumSramKeyReqSlots; i++) begin sram_fifos[i] = new($sformatf("sram_fifos[%0d]", i), this); end - otbn_fifo = new("otbn_fifo", this); + acc_fifo = new("acc_fifo", this); lc_prog_fifo = new("lc_prog_fifo", this); endfunction @@ -75,7 +75,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) process_lc_esc(); process_lc_prog_req(); process_edn_req(); - check_otbn_rsp(); + check_acc_rsp(); check_sram_rsps(); recover_lc_prog_req(); join_none @@ -424,32 +424,32 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) end endtask - virtual task check_otbn_rsp(); + virtual task check_acc_rsp(); forever begin - push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE)) rcv_item; + push_pull_item#(.DeviceDataWidth(ACC_DATA_SIZE)) rcv_item; bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; - bit [OtbnKeyWidth-1:0] key, exp_key; - bit [OtbnNonceWidth-1:0] nonce, exp_nonce; + bit [AccKeyWidth-1:0] key, exp_key; + bit [AccNonceWidth-1:0] nonce, exp_nonce; bit seed_valid; bit part_locked; - otbn_fifo.get(rcv_item); + acc_fifo.get(rcv_item); seed_valid = rcv_item.d_data[0]; - nonce = rcv_item.d_data[1+:OtbnNonceWidth]; - key = rcv_item.d_data[OtbnNonceWidth+1+:OtbnKeyWidth]; + nonce = rcv_item.d_data[1+:AccNonceWidth]; + key = rcv_item.d_data[AccNonceWidth+1+:AccKeyWidth]; part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; // seed is valid as long as secret1 is locked - `DV_CHECK_EQ(seed_valid, part_locked, "otbn seed_valid mismatch") + `DV_CHECK_EQ(seed_valid, part_locked, "acc seed_valid mismatch") - // If edn_data_q matches the OTBN requested size, check OTBN outputs - if (edn_data_q.size() == NUM_OTBN_EDN_REQ) begin + // If edn_data_q matches the ACC requested size, check ACC outputs + if (edn_data_q.size() == NUM_ACC_EDN_REQ) begin {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; // check nonce value - `DV_CHECK_EQ(nonce, exp_nonce, "otbn nonce mismatch") + `DV_CHECK_EQ(nonce, exp_nonce, "acc nonce mismatch") // calculate key sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); @@ -467,16 +467,16 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) .second_key(edn_key2), .num_round(2)); exp_key = {exp_key_higher, exp_key_lower}; - `DV_CHECK_EQ(key, exp_key, "otbn key mismatch") + `DV_CHECK_EQ(key, exp_key, "acc key mismatch") - if (cfg.en_cov) cov.otbn_req_cg.sample(part_locked); + if (cfg.en_cov) cov.acc_req_cg.sample(part_locked); - // If during OTBN key request, the LFSR timer expired and trigger an EDN request to acquire - // two EDN keys, then ignore the OTBN output checking, because scb did not know which EDN + // If during ACC key request, the LFSR timer expired and trigger an EDN request to acquire + // two EDN keys, then ignore the ACC output checking, because scb did not know which EDN // keys are used for LFSR. // Thus any edn_data_q size equal to (16+2*N) is exempted from checking. - end else if ((edn_data_q.size() - NUM_OTBN_EDN_REQ) % 2 != 0) begin - `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during OTBN request", + end else if ((edn_data_q.size() - NUM_ACC_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during ACC request", edn_data_q.size())) end edn_data_q.delete(); @@ -505,7 +505,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) // seed is valid as long as secret1 is locked `DV_CHECK_EQ(seed_valid, part_locked, $sformatf("sram_%0d seed_valid mismatch", index)) - // If edn_data_q matches the OTBN requested size, check OTBN outputs + // If edn_data_q matches the ACC requested size, check ACC outputs if (edn_data_q.size() == NUM_SRAM_EDN_REQ) begin {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; @@ -1530,7 +1530,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) recover_interrupted_op(); super.reset(kind); // flush fifos - otbn_fifo.flush(); + acc_fifo.flush(); lc_prog_fifo.flush(); for (int i = 0; i < NumSramKeyReqSlots; i++) begin sram_fifos[i].flush(); @@ -1566,7 +1566,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) // write secret until KDI request is completed. Since the KDI process time could // vary depends on the push-pull-agent, we are going to ignore the checking if // this scenario happens. - cfg.m_otbn_pull_agent_cfg.vif.req || + cfg.m_acc_pull_agent_cfg.vif.req || cfg.m_sram_pull_agent_cfg[0].vif.req || cfg.m_sram_pull_agent_cfg[1].vif.req || cfg.m_sram_pull_agent_cfg[2].vif.req || diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv index 399df4a830c..327894ba88b 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv @@ -11,7 +11,7 @@ class otp_ctrl_virtual_sequencer extends cip_base_virtual_sequencer #( `uvm_component_new push_pull_sequencer#(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_pull_sequencer_h[NumSramKeyReqSlots]; - push_pull_sequencer#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_sequencer_h; + push_pull_sequencer#(.DeviceDataWidth(ACC_DATA_SIZE)) acc_pull_sequencer_h; push_pull_sequencer#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) lc_prog_pull_sequencer_h; endclass diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv index 889052acbb7..6145712cb37 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv @@ -750,15 +750,15 @@ class otp_ctrl_base_vseq extends cip_base_vseq #( for (int i = 0; i < NumSramKeyReqSlots; i++) req_sram_key(i, blocking); endtask - virtual task req_otbn_key(bit blocking = default_req_blocking); - if (cfg.m_otbn_pull_agent_cfg.vif.req === 1'b1) return; + virtual task req_acc_key(bit blocking = default_req_blocking); + if (cfg.m_acc_pull_agent_cfg.vif.req === 1'b1) return; if (blocking) begin - req_otbn_key_sub(); + req_acc_key_sub(); end else begin fork begin - req_otbn_key_sub(); + req_acc_key_sub(); end join_none; // Add #0 to ensure that this thread starts executing before any subsequent call @@ -766,12 +766,12 @@ class otp_ctrl_base_vseq extends cip_base_vseq #( end endtask - virtual task req_otbn_key_sub(); - push_pull_host_seq#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_seq; + virtual task req_acc_key_sub(); + push_pull_host_seq#(.DeviceDataWidth(ACC_DATA_SIZE)) acc_pull_seq; wait(cfg.under_reset == 0); - `uvm_create_on(otbn_pull_seq, p_sequencer.otbn_pull_sequencer_h); - `DV_CHECK_RANDOMIZE_FATAL(otbn_pull_seq) - `uvm_send(otbn_pull_seq) + `uvm_create_on(acc_pull_seq, p_sequencer.acc_pull_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(acc_pull_seq) + `uvm_send(acc_pull_seq) endtask virtual task req_lc_transition(bit check_intr = 0, diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv index 3cd651a57ae..41d662db67a 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv @@ -192,7 +192,7 @@ class otp_ctrl_common_vseq extends otp_ctrl_base_vseq; write_sw_digests(); // Access OTP via app interface. - if ($urandom_range(0, 1)) req_otbn_key(0); + if ($urandom_range(0, 1)) req_acc_key(0); if ($urandom_range(0, 1)) req_all_sram_keys(0); cfg.clk_rst_vif.wait_clks($urandom_range(10, 20)); diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv index 83a4515b9ad..69a231866e6 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This sequence will randomly issue key otbn, sram, flash key requests during or after partition +// This sequence will randomly issue key acc, sram, flash key requests during or after partition // is locked. // This sequence will check if nonce, seed_valid, and output keys are correct via scb. @@ -22,10 +22,10 @@ class otp_ctrl_parallel_key_req_vseq extends otp_ctrl_parallel_base_vseq; fork begin - // get otbn keys + // get acc keys if ($urandom_range(0, 1)) begin wait_clk_or_reset($urandom_range(0, 500)); - if (!base_vseq_done && !cfg.under_reset) req_otbn_key(); + if (!base_vseq_done && !cfg.under_reset) req_acc_key(); end end begin diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv index 5d77c545a44..be776b0ef6b 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv @@ -77,7 +77,7 @@ class otp_ctrl_parallel_lc_esc_vseq extends otp_ctrl_dai_lock_vseq; virtual task set_lc_esc_and_check(); // Random issue key requests before lc_esc_en is issued. randcase - 1: req_otbn_key(0); + 1: req_acc_key(0); 1: req_all_sram_keys(0); 1: req_lc_transition(0, 0); endcase diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv index 726bf11a4c6..3012a8d0571 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv @@ -164,7 +164,7 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; force_mubi_part_access(); if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs) begin - req_otbn_key(); + req_acc_key(); req_all_sram_keys(); end if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin @@ -272,7 +272,7 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; end if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs && !cfg.smoke_test) begin - req_otbn_key(); + req_acc_key(); req_all_sram_keys(); end diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/tb.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/tb.sv index 560f400af04..2a1fd0f6ec7 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/tb.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/dv/tb.sv @@ -36,8 +36,8 @@ module tb; wire otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_ctrl_macro_req; wire otp_ctrl_macro_pkg::otp_ctrl_macro_rsp_t otp_ctrl_macro_rsp; - wire otp_ctrl_pkg::otbn_otp_key_req_t otbn_req; - wire otp_ctrl_pkg::otbn_otp_key_rsp_t otbn_rsp; + wire otp_ctrl_pkg::acc_otp_key_req_t acc_req; + wire otp_ctrl_pkg::acc_otp_key_rsp_t acc_rsp; wire otp_ctrl_pkg::sram_otp_key_req_t[NumSramKeyReqSlots-1:0] sram_req; wire otp_ctrl_pkg::sram_otp_key_rsp_t[NumSramKeyReqSlots-1:0] sram_rsp; @@ -59,7 +59,7 @@ module tb; lc_prog_if(.clk(clk), .rst_n(rst_n)); push_pull_if #(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_if[NumSramKeyReqSlots](.clk(clk), .rst_n(rst_n)); - push_pull_if #(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_if(.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(ACC_DATA_SIZE)) acc_if(.clk(clk), .rst_n(rst_n)); tl_if tl_if(.clk(clk), .rst_n(rst_n)); tl_if prim_tl_if(.clk(clk), .rst_n(rst_n)); @@ -76,7 +76,7 @@ module tb; // Assign to otp_ctrl_if for assertion checks. assign otp_ctrl_if.lc_prog_ack = lc_prog_if.ack; - assign otp_ctrl_if.otbn_ack = otbn_if.ack; + assign otp_ctrl_if.acc_ack = acc_if.ack; // This signal probes design's alert request to avoid additional logic for triggering alert and // disable assertions. @@ -133,9 +133,9 @@ module tb; // sram .sram_otp_key_i (sram_req), .sram_otp_key_o (sram_rsp), - // otbn - .otbn_otp_key_i (otbn_req), - .otbn_otp_key_o (otbn_rsp), + // acc + .acc_otp_key_i (acc_req), + .acc_otp_key_o (acc_rsp), .otp_broadcast_o (otp_ctrl_if.otp_broadcast_o), @@ -190,9 +190,9 @@ module tb; $sformatf("*env.m_sram_pull_agent[%0d]*", i), "vif", sram_if[i]); end end - assign otbn_req = otbn_if.req; - assign otbn_if.ack = otbn_rsp.ack; - assign otbn_if.d_data = {otbn_rsp.key, otbn_rsp.nonce, otbn_rsp.seed_valid}; + assign acc_req = acc_if.req; + assign acc_if.ack = acc_rsp.ack; + assign acc_if.d_data = {acc_rsp.key, acc_rsp.nonce, acc_rsp.seed_valid}; assign interrupts[OtpOperationDone] = intr_otp_operation_done; @@ -242,8 +242,8 @@ module tb; "vif", tl_if); uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_otp_macro_prim_reg_block", "vif", prim_tl_if); - uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set(null, - "*env.m_otbn_pull_agent*", "vif", otbn_if); + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(ACC_DATA_SIZE)))::set(null, + "*env.m_acc_pull_agent*", "vif", acc_if); uvm_config_db#(virtual push_pull_if#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1))):: set(null, "*env.m_lc_prog_pull_agent*", "vif", lc_prog_if); diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv index 6917804ce27..6224def9d38 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv @@ -77,8 +77,8 @@ module otp_ctrl // Scrambling key requests input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, - input otbn_otp_key_req_t otbn_otp_key_i, - output otbn_otp_key_rsp_t otbn_otp_key_o, + input acc_otp_key_req_t acc_otp_key_i, + output acc_otp_key_rsp_t acc_otp_key_o, // Interface to OTP_MACRO output otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_macro_o, @@ -904,7 +904,7 @@ end // case. For one example, see // // https://opentitan.org/book/hw/top_earlgrey/ - // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-otbn-scramblers + // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-acc-scramblers // Note: as opposed to the OTP arbitration above, we do not perform cycle-wise arbitration, but @@ -1133,8 +1133,8 @@ end .edn_data_i ( edn_data ), .sram_otp_key_i, .sram_otp_key_o, - .otbn_otp_key_i, - .otbn_otp_key_o, + .acc_otp_key_i, + .acc_otp_key_o, .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[KdiIdx] ), .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[KdiIdx] ), .scrmbl_cmd_o ( part_scrmbl_req_bundle[KdiIdx].cmd ), @@ -1540,7 +1540,7 @@ end `ASSERT_KNOWN(OtpLcDataKnown_A, otp_lc_data_o) `ASSERT_KNOWN(OtpKeymgrKeyKnown_A, otp_keymgr_key_o) `ASSERT_KNOWN(OtpSramKeyKnown_A, sram_otp_key_o) - `ASSERT_KNOWN(OtpOtgnKeyKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(OtpOtgnKeyKnown_A, acc_otp_key_o) `ASSERT_KNOWN(OtpBroadcastKnown_A, otp_broadcast_o) // Alert assertions for sparse FSMs. diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv index adf391e7dc4..25eb342a781 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv @@ -34,8 +34,8 @@ module otp_ctrl_kdi // Scrambling key requests input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, - input otbn_otp_key_req_t otbn_otp_key_i, - output otbn_otp_key_rsp_t otbn_otp_key_o, + input acc_otp_key_req_t acc_otp_key_i, + output acc_otp_key_rsp_t acc_otp_key_o, // Scrambling mutex request output logic scrmbl_mtx_req_o, input scrmbl_mtx_gnt_i, @@ -56,14 +56,14 @@ module otp_ctrl_kdi // Integration Checks // //////////////////////// - // OTBN + SRAM slots + // ACC + SRAM slots localparam int NumReq = 1 + NumSramKeyReqSlots; // Make sure key sizes in the system are multiples of 64bit and not larger than 256bit. `ASSERT_INIT(KeyNonceSize1_A, (SramKeySeedWidth <= 256) && ((SramKeySeedWidth % 64) == 0)) `ASSERT_INIT(KeyNonceSize3_A, (SramKeyWidth <= 256) && ((SramKeyWidth % 64) == 0)) `ASSERT_INIT(KeyNonceSize4_A, (SramNonceWidth <= 256) && ((SramNonceWidth % 64) == 0)) - `ASSERT_INIT(KeyNonceSize5_A, (OtbnKeyWidth <= 256) && ((OtbnKeyWidth % 64) == 0)) - `ASSERT_INIT(KeyNonceSize6_A, (OtbnNonceWidth <= 256) && ((OtbnNonceWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize5_A, (AccKeyWidth <= 256) && ((AccKeyWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize6_A, (AccNonceWidth <= 256) && ((AccNonceWidth % 64) == 0)) // Make sure EDN interface has compatible width. `ASSERT_INIT(EntropyWidthDividesDigestBlockWidth_A, (ScrmblKeyWidth % EdnDataWidth) == 0) @@ -105,9 +105,9 @@ module otp_ctrl_kdi logic [NumReq-1:0] req, gnt; req_bundle_t req_bundles [NumReq]; - assign req[0] = otbn_otp_key_i.req; + assign req[0] = acc_otp_key_i.req; - assign otbn_otp_key_o.ack = gnt[0]; + assign acc_otp_key_o.ack = gnt[0]; // anchored seeds logic [SramKeySeedWidth-1:0] sram_data_key_seed; @@ -120,12 +120,12 @@ module otp_ctrl_kdi .out_o(sram_data_key_seed) ); - // OTBN key + // ACC key assign req_bundles[0] = '{ingest_entropy: 1'b1, // ingest random data chained_digest: 1'b0, // revert to netlist IV between blocks digest_sel: SramDataKey, fetch_nonce: 1'b1, // fetch nonce - nonce_size: 2'(OtbnNonceWidth/EdnDataWidth-1), + nonce_size: 2'(AccNonceWidth/EdnDataWidth-1), seed_valid: scrmbl_key_seed_valid_i, seed: {sram_data_key_seed, // reuse same seed sram_data_key_seed}}; @@ -241,9 +241,9 @@ module otp_ctrl_kdi .q_o(key_out_q) ); - assign otbn_otp_key_o.key = key_out_q; - assign otbn_otp_key_o.nonce = nonce_out_q[OtbnNonceSel-1:0]; - assign otbn_otp_key_o.seed_valid = seed_valid_q; + assign acc_otp_key_o.key = key_out_q; + assign acc_otp_key_o.nonce = nonce_out_q[AccNonceSel-1:0]; + assign acc_otp_key_o.seed_valid = seed_valid_q; for (genvar k = 0; k < NumSramKeyReqSlots; k++) begin : gen_out_assign assign sram_otp_key_o[k].key = key_out_q; @@ -547,7 +547,7 @@ module otp_ctrl_kdi `ASSERT_KNOWN(FsmErrKnown_A, fsm_err_o) `ASSERT_KNOWN(EdnReqKnown_A, edn_req_o) `ASSERT_KNOWN(SramOtpKeyRspKnown_A, sram_otp_key_o) - `ASSERT_KNOWN(OtbnOtpKeyRspKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(AccOtpKeyRspKnown_A, acc_otp_key_o) `ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) `ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) `ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv index 221422ea8b3..7146627b3d7 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv @@ -97,7 +97,7 @@ package otp_ctrl_top_specific_pkg; // Get maximum nonce width localparam int NumNonceChunks = - (OtbnNonceWidth > SramNonceWidth) ? OtbnNonceSel : SramNonceSel; + (AccNonceWidth > SramNonceWidth) ? AccNonceSel : SramNonceSel; /////////////////////////////////////////// // Defaults for random netlist constants // diff --git a/hw/top_darjeeling/lint/top_darjeeling.waiver b/hw/top_darjeeling/lint/top_darjeeling.waiver index 31769a2acdd..3e9eeaeb0de 100644 --- a/hw/top_darjeeling/lint/top_darjeeling.waiver +++ b/hw/top_darjeeling/lint/top_darjeeling.waiver @@ -36,11 +36,11 @@ waive -rules {CLOCK_USE} -location {pinmux.sv} -regexp {'dio_wkup_mux\[(42|43)\ # Since these functions / parameters / signals live in different scopes, this is acceptable, and we can waive them. waive -rules SAME_NAME_TYPE -location {aes_sbox_canright_pkg.sv keccak_2share.sv} -regexp {'theta' is used as a (reg|function) here, and as a (function|reg) at} \ -comment {This is acceptable, since these are used in different hierarchies.} -waive -rules SAME_NAME_TYPE -location {keccak_round.sv otbn_pkg.sv} -regexp {'L' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ +waive -rules SAME_NAME_TYPE -location {keccak_round.sv acc_pkg.sv} -regexp {'L' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ -comment {This is acceptable, since these are used in different hierarchies.} waive -rules SAME_NAME_TYPE -location {spi_device.sv rstmgr_pkg.sv} -regexp {'spi_device' is used as a (module|reg) here, and as a (reg|module) at } \ -comment {This is acceptable, since these are used in different hierarchies.} -waive -rules SAME_NAME_TYPE -location {tlul_socket_m1.sv otbn_pkg.sv} -regexp {'M' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ +waive -rules SAME_NAME_TYPE -location {tlul_socket_m1.sv acc_pkg.sv} -regexp {'M' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ -comment {This is acceptable, since these are used in different hierarchies.} waive -rules SAME_NAME_TYPE -location {prim_trivium.sv prim_xoshiro256pp.sv} -regexp {'state_update' is used as a (reg|function) here, and as a (function|reg) at} \ -comment {This is acceptable, since these are used in different hierarchies.} diff --git a/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson b/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson index e0ee0343120..9f456072d0e 100644 --- a/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson +++ b/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson @@ -123,11 +123,11 @@ additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" rel_path: "hw/ip/keymgr_dpe/lint/{tool}" }, - { name: otbn - fusesoc_core: lowrisc:ip:otbn + { name: acc + fusesoc_core: lowrisc:ip:acc import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" - rel_path: "hw/ip/otbn/lint/{tool}" + rel_path: "hw/ip/acc/lint/{tool}" }, { name: otp_ctrl fusesoc_core: lowrisc:darjeeling_ip:otp_ctrl diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv index 6ce3902c4de..baf3782a375 100644 --- a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv @@ -1663,10 +1663,10 @@ module chip_darjeeling_asic #( .sram_ctrl_main_ram_1p_cfg_rsp_o ( ), .sram_ctrl_mbox_ram_1p_cfg_i ( ram_1p_cfg ), .sram_ctrl_mbox_ram_1p_cfg_rsp_o ( ), - .otbn_imem_ram_1p_cfg_i ( ram_1p_cfg ), - .otbn_imem_ram_1p_cfg_rsp_o ( ), - .otbn_dmem_ram_1p_cfg_i ( ram_1p_cfg ), - .otbn_dmem_ram_1p_cfg_rsp_o ( ), + .acc_imem_ram_1p_cfg_i ( ram_1p_cfg ), + .acc_imem_ram_1p_cfg_rsp_o ( ), + .acc_dmem_ram_1p_cfg_i ( ram_1p_cfg ), + .acc_dmem_ram_1p_cfg_rsp_o ( ), .rv_core_ibex_icache_tag_ram_1p_cfg_i ( ram_1p_cfg ), .rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o ( ), .rv_core_ibex_icache_data_ram_1p_cfg_i ( ram_1p_cfg ), diff --git a/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_rnd_cnst_pkg.sv b/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_rnd_cnst_pkg.sv index c7dc10d79ff..787e18c0693 100644 --- a/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_rnd_cnst_pkg.sv +++ b/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_rnd_cnst_pkg.sv @@ -19,17 +19,17 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter otp_ctrl_top_specific_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = { - 40'hA1_C8EF1830 + 40'h30_65F53E38 }; // Compile-time random permutation for LFSR output parameter otp_ctrl_top_specific_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = { - 240'h3569_628C3719_48E0086C_13E45C24_1428C193_8452DE9D_16951181_E67DD809 + 240'h0257_5209C785_2A49CF4C_72166467_CD415389_98486352_05C36016_CB44C89A }; // Compile-time random permutation for scrambling key/nonce register reset value parameter otp_ctrl_top_specific_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = { - 256'hD6780626_A12B5904_A9B37439_F8177D19_D04D3FAD_040ED029_09A9EA4B_5429B9E6 + 256'h2CC1ED9B_EC346650_D956B1FD_CFCDAA85_10F4ABD3_BBE952C4_C216B684_0C8C08A6 }; // Compile-time scrambling key @@ -246,35 +246,35 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Diversification value used for all invalid life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = { - 128'h0D20B077_21F7FF50_7AD2B9FB_9CC7FF06 + 128'h0F7AE497_EDB550D6_780626A1_2B5904A9 }; // Diversification value used for the TEST_UNLOCKED* life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestUnlocked = { - 128'hE4C72C47_D9E15FA8_FF9F8283_3E32C151 + 128'hB37439F8_177D19D0_4D3FAD04_0ED02909 }; // Diversification value used for the DEV life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivDev = { - 128'hD2FD2987_E3062F61_19C7560A_CBBE9F6F + 128'hA9EA4B54_29B9E60D_20B07721_F7FF507A }; // Diversification value used for the PROD/PROD_END life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = { - 128'hFFC2171A_49199BB5_3D8E0DAA_8F0578DB + 128'hD2B9FB9C_C7FF06E4_C72C47D9_E15FA8FF }; // Diversification value used for the RMA life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivRma = { - 128'hAA5F0227_91480B4E_709E0F80_976E0966 + 128'h9F82833E_32C151D2_FD2987E3_062F6119 }; // Compile-time random bits used for invalid tokens in the token mux parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = { - 256'h01357E13_758A3E22_11E20FAA_36D00779_EB2CFF38_B90ADF94_A0675DA2_63541C78, - 256'hAA9DC0C6_23C09EE7_FD16A668_7D3A1B4E_21456518_EA00DB8F_75489D93_2535FCB7, - 256'h684ED330_AD9AA219_EA28BFB6_FDA16A61_BBEACDDC_92216985_8A90A977_C043EB40, - 256'h7A704254_4EF79B15_F8DBE994_6ED90ADA_FCCEDC18_C38AE447_3E404D38_A4D2302A + 256'hC7560ACB_BE9F6FFF_C2171A49_199BB53D_8E0DAA8F_0578DBAA_5F022791_480B4E70, + 256'h9E0F8097_6E096601_357E1375_8A3E2211_E20FAA36_D00779EB_2CFF38B9_0ADF94A0, + 256'h675DA263_541C78AA_9DC0C623_C09EE7FD_16A6687D_3A1B4E21_456518EA_00DB8F75, + 256'h489D9325_35FCB768_4ED330AD_9AA219EA_28BFB6FD_A16A61BB_EACDDC92_2169858A }; //////////////////////////////////////////// @@ -282,12 +282,12 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter alert_handler_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = { - 32'h295C50F4 + 32'h90A977C0 }; // Compile-time random permutation for LFSR output parameter alert_handler_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = { - 160'hCA09B9E2_22B820CE_D83F7979_E4E9C395_2A6534EB + 160'h28174B98_F0C5999E_6C95D446_16C8534A_BCE7FFA8 }; //////////////////////////////////////////// @@ -295,23 +295,41 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetAonSramKey = { - 128'hD6C33DCD_8C46C818_0DA77F58_394513F2 + 128'hA8A09119_70AC4838_B2C251C9_B9A2DBE2 }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetAonSramNonce = { - 128'hABB1B374_4276549A_FD120E86_2D3419D9 + 128'h29A87DB1_1E1E1611_1C07365C_B738535A }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetAonLfsrSeed = { - 64'hCCFB691A_3E5D0916 + 64'h96AAD6C3_3DCD8C46 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetAonLfsrPerm = { - 128'h0DE14097_A1D4C397_D0AF43CA_4A7BB159, - 256'h7BDAA5BD_7822AB7B_44D54B87_DF2291D0_A0DC1A19_9BF4EC73_224ECC41_BE8F660C + 128'h2BBC20E2_36EFA367_94225AD2_07F70089, + 256'h39C9EB9C_6E1D992D_D1830509_73FC6BE3_4B87DDE6_57341DD6_CA8444E5_9FA431B2 + }; + + //////////////////////////////////////////// + // acc + //////////////////////////////////////////// + // Default seed of the PRNG used for URND. + parameter acc_pkg::urnd_prng_seed_t RndCnstAccUrndPrngSeed = { + 256'hCD45C60D_144177E8_9F75139F_749DE9B3_74A3636A_66F969AE_A3E98FC6_F4892BEB + }; + + // Compile-time random reset value for IMem/DMem scrambling key. + parameter otp_ctrl_pkg::acc_key_t RndCnstAccAccKey = { + 128'h458D5B4B_D644E79A_35D690BB_B852739D + }; + + // Compile-time random reset value for IMem/DMem scrambling nonce. + parameter otp_ctrl_pkg::acc_nonce_t RndCnstAccAccNonce = { + 64'hC155FEC8_B9A9CA90 }; //////////////////////////////////////////// @@ -319,34 +337,34 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for register clearing. parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = { - 64'hB852739D_C155FEC8 + 64'hAFAA4655_965A49D1 }; // Permutation applied to the LFSR of the PRNG used for clearing. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = { - 128'hB43A6878_187C6372_714364FB_CCB31F29, - 256'hDE201061_5C1E636F_6633B90B_5522EACF_67FDB008_3D7C1AD1_25A5551F_AB932AAE + 128'hBD8D049A_41BE7F3F_680FB06D_A47563E1, + 256'h370A8601_65E9D59E_43130934_BDACFEB6_6E3AA442_4948B5DF_C9F96C0C_883D7C1A }; // Permutation applied to the clearing PRNG output for clearing the second share of registers. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = { - 128'hE67DC054_48A1A0AF_54E3245E_8C3FDB3D, - 256'h731D4C7B_C5218650_27E19AEA_CC768260_6BCFCC02_48BA5F3A_591CAB5B_6EED6374 + 128'hD2333689_5FDB16AC_70DEF229_E54B005D, + 256'h1C9309CE_180D6B4F_CC774A79_9384D508_493466A8_F6E967F0_B920981E_AB7FE4BB }; // Default seed of the PRNG used for masking. parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = { - 32'hB80B1581, - 256'hBA47B081_EDAD7956_48590976_8EF3DBA8_08CBC6D5_7FE7489F_41549870_395C90D9 + 32'hCBC6D57F, + 256'hE7489F41_54987039_5C90D9AB_F4E0F5ED_5BA097B3_BA3CCF06_D21E5139_60C35528 }; // Permutation applied to the output of the PRNG used for masking. parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = { - 256'h842E7064_1D6B4C9D_696C0903_8062541C_1B523146_0B4F1F85_8F203A0A_22137A3B, - 256'h253F872B_2753245F_0267379F_7E639C2F_953D3565_689B1A32_49734507_365E6A08, - 256'h7D42342A_7983238B_764A1898_9916217F_93611740_4B304E66_77780C48_29929A71, - 256'h158C8110_8E0E9012_59387405_5D0F6E19_44049E14_56338D4D_72573E8A_967B4188, - 256'h6D91016F_26947500_110D8982_43505C58_7C475A2C_2D862855_6039511E_063C975B + 256'h8061271D_536B0B52_815B2007_44953B7E_9994658D_2B453A9F_03258E0A_70139A3E, + 256'h6277876A_1B14545E_0F2E0891_36907124_72027A31_3F8F3D41_6C63062F_4637681E, + 256'h1C3C3564_8A327860_7693424F_342A4A4C_66491923_8C5F5718_84857339_1621929D, + 256'h7417404B_304E797B_4D557F0C_48296E69_9C510415_968B1098_0E881259_3856055D, + 256'h1F330928_677D1A97_83226D9B_016F269E_7500110D_89824350_5C587C47_5A2C2D86 }; //////////////////////////////////////////// @@ -354,44 +372,44 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random data for PRNG default seed parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = { - 32'hD09377DF, - 256'h413B2B19_12721612_13B80315_A177C751_6ECD4B00_2AF6B492_53AD7151_C8E8F1A5 + 32'h0315A177, + 256'hC7516ECD_4B002AF6_B49253AD_7151C8E8_F1A51FD1_84ABFA40_D2CD2D16_F3D54D9D }; // Compile-time random permutation for PRNG output parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = { - 64'hBE81CBD1_3E35B1E8, - 256'hC41583E5_CA828487_0362F987_35253BF1_7D9AAE9B_01932EA9_F6D4D820_0DCA924B, - 256'h89AEB3FC_6E946FF2_8263228A_DAFEC52A_2B884EA9_0F27C0E5_83AC5B40_C010734B, - 256'h1275AC32_DF811EC2_C5432829_A50EE8C2_51E3B3E5_2C4A3B69_81B88219_83718877, - 256'h05454408_CDDD6C71_79820470_A074AC44_758B66A5_5B5C6EC7_FAAC75C7_1A452967, - 256'hCEC2B25A_2AA98349_9E9AC241_F89A3341_36B94F23_E36A54B0_00DAFC30_D93223E2, - 256'h7205715F_B63E7F7E_9C44722D_47E433FA_F501C7A0_D21586DB_A3D8FC42_8A413D21, - 256'hB5EC9448_6D616175_7459A413_54588DB9_E6107C3A_33DD450D_B30BD968_BC937882, - 256'h8346838A_0BD634C7_1ECABAA1_949E8B23_11F47BCA_54B08441_E9326319_72445181, - 256'h64AC8B56_C22E3D46_B2E19949_6DF91A6D_5027116A_016C9A23_89ECC39D_855C49A6, - 256'h8545AC2A_6E083A9D_2E60AFE9_05E8B04C_24893117_5743BE21_7320C43E_18564D50, - 256'hB4A682ED_E600A1A6_DC16F71B_2ECCC80D_728884BA_3920C3D0_35A1C8B3_55362AE3, - 256'h199DF4A8_5005ADB3_B8A3AB80_849DCF97_55E8DD7F_7D85CBC8_65941021_546A6A97, - 256'hCC085E42_1349DEED_895C358A_7438DA39_9DE63A46_F05270AD_D47B3259_C407D16D, - 256'h107CE1E4_346C374F_23DE490D_41D09872_519148F5_5A66E693_24863A2D_A342C6A5, - 256'h09737D00_809ED065_4EB38522_67040495_CA49AD59_6AA35C87_2E64E530_DB31532A, - 256'hD952961E_005C22BA_21A23A99_2043F2FD_6A2A41AB_13137007_74245F3C_5A7105B6, - 256'hAE9773EE_A56A2348_E1FC9F96_0AAC059A_1419CA57_68288792_A272D928_44624E67, - 256'h81E43D66_A756048B_8E40B745_CE28864A_2D79BA9E_A3D151A1_4F345D95_A8697381, - 256'h42C69041_8E6CACD4_AB751D4E_82BAB558_1A089C25_BF74DD22_DDEB6AE2_C908E193, - 256'h2EE97F0B_612733A8_0E83A3A1_D6BE4622_44FD7339_1195D9A4_4CC8C5B0_74B28965, - 256'hD456C28C_A8F2765E_11A2444C_8ADEEB91_F76869E7_A598301D_0B95385A_58B03CE5, - 256'h00A4747B_16242DC2_21018203_37D55F92_96D46D66_136D23C2_64841912_BDDEB460, - 256'h9AE5F10D_EE6BC470_88C38524_11B4C7C7_64A7934D_31E31D0C_54BA02D0_4C0ED001, - 256'h54A3CF94_46B5A289_536806B8_A823AE2A_16163958_820B2A60_8186AC13_CB0D2F00, - 256'h6B401189_4B6E089F_1F914C66_F8F86322_9A1D28A2_4239E706_96D3B19D_7009666B, - 256'h63088CB0_110CC149_A55C0216_3E9DC784_3E640420_7AC7BE6C_81D90C44_C4A0B956, - 256'hC0C69419_B9439557_C80DBBC2_737A14C7_009032F8_B65B714D_5093D450_2A812CED, - 256'h43F50579_6651CE96_26EBC978_570A6AFA_F707729F_0214C367_1C6A196F_121C7491, - 256'h377E6D5B_589E9104_E2F13D87_F11520E6_5F9235BA_4079E9C6_76F3585B_C9217BB2, - 256'hD8E119FD_BF57A42E_F79EC9FA_366E536E_1C3654BD_A6F768E7_81944338_619F5D57, - 256'h6D888FE6_28D630A8_D9759C21_C51BB248_51062BBB_C0AE801F_FBEE9D4D_8B48487F + 64'h3F2076C6_CD702CF9, + 256'h84C7BE62_58F0F53F_9B42F9D7_070945CE_6D8A1B66_02D3056B_34A8ECB1_176C41A7, + 256'hBFD40292_396A08F2_287E67D0_A7A1358E_97CB0A88_0F1160D8_80480397_E9B8A2D8, + 256'h26283004_14384A3E_BFA95A65_ECC48328_369311C3_B1B89A3D_9E2A425D_C0D6206E, + 256'h432B63B9_F193AAE3_11023679_AA82DA63_1C58F829_314B0447_60CB47F0_26A4B104, + 256'hD6B77DDD_2A2EB8AD_573724EC_6CD64A57_469AC109_298280D9_AB687731_0F78C038, + 256'h7237C719_4AD4B027_1CD20ED1_B4B162AA_C53449D4_96460A92_201EF10D_2184F9C2, + 256'hA245D2B0_C23344F3_FE24B6CB_A4606D7A_E1E99059_9F93F470_8D9C5B30_7C3A89A9, + 256'h4745120B_D9EAFDC4_24CD80A1_E45C9992_F51960CC_81ECAB68_AD0908B2_31153AB1, + 256'hF8296203_3C845FEC_3261AC53_C4534860_66EB62D6_DF805C31_ACB86C92_B962C094, + 256'hB098F45A_A9E04B8A_4138A2DC_3EA2574E_F1267FC7_DAA15171_4B9071EA_E9A6CD47, + 256'h52744561_B6B4D50B_4A661DAE_9A8A1A7A_02716A02_ECCCA460_F8D04BBB_E8FC4D03, + 256'h97E03739_596F60B1_995EBB45_005AB03B_8A3AC808_49EE7981_6485585C_745CC006, + 256'h594D0215_46A5F5BA_C185E421_349E9968_89CB5A2E_E38D5BA5_DEF3A46F_05273A11, + 256'h476925CC_507D16D1_07F22143_46C374F2_3DE4C0D4_1D098725_19146955_A68E6C32, + 256'h4863A2DE_341FB868_9737D008_15F60654_E91C5226_6800495C_7A9B5596_AE35C872, + 256'hE651530D_B31532AE_98D54A83_7061905C_22BB21D2_3AC92043_F2FD6A2A_41AB2317, + 256'h72077424_5F3C5AF1_060EAF97_73EEA96C_21373CE4_8B16085C_059AD41C_365A6830, + 256'hEA0AA67B_59295C62_4E6F81E4_3D66A786_048B8300_B925D628_864A3979_92DF33D1, + 256'h519A4F34_5D95A969_A381429A_10418EF4_ADD4ABF5_1D4E9E00_AEB15606_8226596F, + 256'hDD3748B7_7D1AB8BE_7738670B_C9FE8CD8_49D8EA03_A119D475_B8D21725_332316C1, + 256'hD2CE2597_515A3832_B08C6578_46891132_2E7BAE87_DDA1A85E_9660C074_29F4E169, + 256'h62C0F394_029291E9_C890B808_8406080C_DF557E4D_5B51B598_4DB68F09_9E10644A, + 256'hF77AD982_6CA7C437_BAAF51C2_230E1490_46D71F1D_929E5034_C782D031_52EC6B51, + 256'h303B4005_52923E51_1AE6FA25_4DA01AE6_A14EB8A8_5858E562_082CAA82_061AB44F, + 256'h2C74BC01_AE004625_2DB92271_FE45319B_E3E18C8A_68A4A28C_08E79C2A_5B4EC675, + 256'hC02599AD_CC3232C1_44330526_95704858_FA771E10_F9901081_EC6AE5B3_07643113, + 256'h1282E55B_071A6A44_19B94395_57C80DBC_C2737A14_4D809032_FCB75B71_4D5093D4, + 256'h502A812C_ED83F505_796651CE_9626EBC9_78570A6A_FAF70B72_9F0214C3_671C6A19, + 256'h6F121C74_91377E6D_5B589E91_04E2F13D_87F15520_E65F9235_BA4079E9_C676F758, + 256'h5BC9217B_B2D8E119_FDC057A4_2F1E9EC9_FA366E53_6E1C4654_BDA6F768_E7819443, + 256'h38619F5D_576D888F_E628D630_A8D9759C_21C61BB2_4851062B_BBC0AE80_1FFBEE9D }; // Compile-time random data for PRNG buffer default seed @@ -408,76 +426,58 @@ package top_darjeeling_rnd_cnst_pkg; 256'h52B8EFC2_6E1DBE98_1AD2E2A9_2BEC3819_CC364D88_A57F854E_B5B47919_710F0700 }; - //////////////////////////////////////////// - // otbn - //////////////////////////////////////////// - // Default seed of the PRNG used for URND. - parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = { - 256'hF463EF2F_DFF5F6DD_DC13ECC2_583D51FE_DB1B6197_DCBB40DE_C2A9FE69_FAB1EB9E - }; - - // Compile-time random reset value for IMem/DMem scrambling key. - parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = { - 128'hE13C3678_95ADEFD6_DBB19E7A_24526B82 - }; - - // Compile-time random reset value for IMem/DMem scrambling nonce. - parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = { - 64'h5BB435ED_63D9513E - }; - //////////////////////////////////////////// // keymgr_dpe //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrDpeLfsrSeed = { - 64'h488F3FFA_7700EC4C + 64'hF463EF2F_DFF5F6DD }; // Compile-time random permutation for LFSR output parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrDpeLfsrPerm = { - 128'h8DF69CD7_1B07313B_F8070A19_F1492984, - 256'hA5EE7449_FD9A0E90_3858ADA8_603FCC85_74DF6589_7986F23E_B0E52FE0_91E4DED2 + 128'h87EB6290_A74B0F14_C2CDB5CC_7154858C, + 256'h123F6680_0E7D1A47_9B8BFD83_2E49AF4D_5E37A9EC_6AAF10BA_5606D943_D6C3B137 }; // Compile-time random permutation for entropy used in share overriding parameter keymgr_pkg::rand_perm_t RndCnstKeymgrDpeRandPerm = { - 160'hB70FADC4_5465678F_050F9100_557F374C_1C36F4CB + 160'hE5E9E327_784327AB_15EBE924_DFBB3038_A2155460 }; // Compile-time random bits for revision seed parameter keymgr_pkg::seed_t RndCnstKeymgrDpeRevisionSeed = { - 256'h7B416B49_B114F994_A969864A_57C3482A_B3BDCBD9_FE825728_F7BA40A2_2C9719C5 + 256'hBC99A2C9_FF8D13E6_E3C95B9F_3B64C459_30F2E8FF_6A1D7485_E74BB880_5C552E9E }; // Compile-time random bits for software generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrDpeSoftOutputSeed = { - 256'hD7C160F4_92D0E875_7631EBF7_52A1E560_4E2D6171_F5DBA9EC_4249052D_CC7A4D58 + 256'h002301F1_82196997_5992AD61_B3498070_84EBB1B4_7B416B49_B114F994_A969864A }; // Compile-time random bits for hardware generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrDpeHardOutputSeed = { - 256'h4D57AC27_843EA2A0_163EFEDA_5B24D93F_97D62D99_C960542F_4A1F2595_192E9A96 + 256'h57C3482A_B3BDCBD9_FE825728_F7BA40A2_2C9719C5_D7C160F4_92D0E875_7631EBF7 }; // Compile-time random bits for generation seed when aes destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrDpeAesSeed = { - 256'h9A885419_A9D57E36_519FA42D_20EFA348_CB77F508_9A8381B6_2D9717B3_647E5CE0 + 256'h52A1E560_4E2D6171_F5DBA9EC_4249052D_CC7A4D58_4D57AC27_843EA2A0_163EFEDA }; // Compile-time random bits for generation seed when kmac destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrDpeKmacSeed = { - 256'h796CA68A_A29523D3_F94F27C7_4ACAE76B_3E145326_741F804E_3C3A3451_469C6118 + 256'h5B24D93F_97D62D99_C960542F_4A1F2595_192E9A96_9A885419_A9D57E36_519FA42D }; - // Compile-time random bits for generation seed when otbn destination selected - parameter keymgr_pkg::seed_t RndCnstKeymgrDpeOtbnSeed = { - 256'hFA23BC32_E428AD2B_E2584FE8_D5491FA8_E7F19AAA_4133AD0D_2704702A_E2FF9D98 + // Compile-time random bits for generation seed when acc destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeAccSeed = { + 256'h20EFA348_CB77F508_9A8381B6_2D9717B3_647E5CE0_796CA68A_A29523D3_F94F27C7 }; // Compile-time random bits for generation seed when no destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrDpeNoneSeed = { - 256'h49FCB598_74CDDC9C_BC645D9E_02A96B99_80911844_D3C74DE8_5E05164B_829D484B + 256'h4ACAE76B_3E145326_741F804E_3C3A3451_469C6118_FA23BC32_E428AD2B_E2584FE8 }; //////////////////////////////////////////// @@ -485,14 +485,14 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = { - 128'hD447C9D7_611999CA_523B1157_5A82D625, - 256'hEA331F0D_D07B9876_A95D4846_9D8BE58D_526100D8_26EBF413_7728E993_B979B05B + 128'hD5491FA8_E7F19AAA_4133AD0D_2704702A, + 256'hE2FF9D98_49FCB598_74CDDC9C_BC645D9E_02A96B99_80911844_D3C74DE8_5E05164B }; // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = { - 128'hDDC26CCB_34AAB934_13F8B7DC_7CC8C4BF, - 256'hDB394D03_E99A0DAE_61EAF3B6_4EFFA6DE_29A9812F_FD69DD7A_95A3E3C9_9E381A97 + 128'h829D484B_D447C9D7_611999CA_523B1157, + 256'h5A82D625_EA331F0D_D07B9876_A95D4846_9D8BE58D_526100D8_26EBF413_7728E993 }; //////////////////////////////////////////// @@ -500,23 +500,23 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = { - 128'h68C85F00_2483AAFA_2A1B591A_4617B8F7 + 128'hB979B05B_DDC26CCB_34AAB934_13F8B7DC }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = { - 128'hE2806138_001D6EC3_45718E6E_7248D8D8 + 128'h7CC8C4BF_DB394D03_E99A0DAE_61EAF3B6 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = { - 64'h5F141C91_5C06870E + 64'h4EFFA6DE_29A9812F }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = { - 128'h1DB66B08_CFE8D13F_76590967_B339B779, - 256'h53DF7790_C1D57A63_BD4108AA_1B8660E8_0B27CE30_03EE9C49_AEC5911C_6D8B228D + 128'hF343EC70_C7545598_84C6D4E1_23DA4142, + 256'h3CD20C22_EF7CD9A4_E9B1F0D9_8B8546B5_B52AA809_017E7EEC_63A7CB8A_257B76BF }; //////////////////////////////////////////// @@ -524,23 +524,23 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMboxSramKey = { - 128'hDEAEB4EE_A0BA96FF_2B3EB56D_EBDBC1B3 + 128'h61CDB1A7_CA1990BF_F0B4C0F1_A0CC87EF }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMboxSramNonce = { - 128'hB6ED4DAF_88E9EA4F_8051D088_092FB879 + 128'hC382B123_A4E4BD11_53024473_BBD5FA0E }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMboxLfsrSeed = { - 64'hFFD7E826_5FAF402C + 64'h188EBEF9_45F9D57D }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMboxLfsrPerm = { - 128'h112D94A4_693327D9_66CBE2CD_E270F0AC, - 256'h5BAD1F7D_686EA5D1_66C0957B_1300213F_D0ED671A_63AD1F74_13A284AF_0F839BE3 + 128'h342D7E87_93192674_AF0CEC5F_A631EC79, + 256'hC215F449_97170D37_520CA2E1_B3CA97FF_36433B80_ED6AFA45_891A4C6A_01B4B76A }; //////////////////////////////////////////// @@ -548,12 +548,12 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Fixed nonce used for address / data scrambling parameter bit [63:0] RndCnstRomCtrl0ScrNonce = { - 64'h0A553E45_BAB60FD5 + 64'hAC8FEB4F_2302C232 }; // Randomised constant used as a scrambling key for ROM data parameter bit [127:0] RndCnstRomCtrl0ScrKey = { - 128'h30AE8415_6D37CC68_063276F9_E85FAEE1 + 128'hC482D07B_560A3D67_8FB9A9DC_420A1339 }; //////////////////////////////////////////// @@ -561,12 +561,12 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Fixed nonce used for address / data scrambling parameter bit [63:0] RndCnstRomCtrl1ScrNonce = { - 64'h29AE80F5_B440DC77 + 64'hB243BB28_853B19B5 }; // Randomised constant used as a scrambling key for ROM data parameter bit [127:0] RndCnstRomCtrl1ScrKey = { - 128'h9649127E_C56C7B0E_9645BF23_1B5B37B8 + 128'hC399D4DA_9B067ED9_BE1D5753_FFD02F20 }; //////////////////////////////////////////// @@ -574,22 +574,22 @@ package top_darjeeling_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for random instructions. parameter ibex_pkg::lfsr_seed_t RndCnstRvCoreIbexLfsrSeed = { - 32'hC5559AEE + 32'hF4E52516 }; // Permutation applied to the LFSR of the PRNG used for random instructions. parameter ibex_pkg::lfsr_perm_t RndCnstRvCoreIbexLfsrPerm = { - 160'h3AC76437_9B540182_4B549F99_1766E911_9F5E97E1 + 160'h74A8BEDC_9C896DAD_CD8368A0_6C20EA0D_5E0FFB29 }; // Default icache scrambling key parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexIbexKeyDefault = { - 128'h8AFD1F07_532671EB_83C820E1_F1EAA3A1 + 128'h49127EC5_6C7B0E96_45BF231B_5B37B8C5 }; // Default icache scrambling nonce parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexIbexNonceDefault = { - 64'h8AD34D47_1B199CFD + 64'h559AEE0D_0E2F2DAB }; endpackage : top_darjeeling_rnd_cnst_pkg diff --git a/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_testing_rnd_cnst_pkg.core b/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_testing_rnd_cnst_pkg.core index 701ebc3d1b5..396114fddcd 100644 --- a/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_testing_rnd_cnst_pkg.core +++ b/hw/top_darjeeling/rtl/autogen/testing/top_darjeeling_testing_rnd_cnst_pkg.core @@ -14,11 +14,11 @@ filesets: - lowrisc:darjeeling_ip:alert_handler_pkg - lowrisc:darjeeling_ip:otp_ctrl_top_specific_pkg - lowrisc:ibex:ibex_pkg + - lowrisc:ip:acc_pkg - lowrisc:ip:aes - lowrisc:ip:csrng_pkg - lowrisc:ip:kmac_pkg - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:otbn_pkg - lowrisc:ip:otp_ctrl_pkg - lowrisc:ip:sram_ctrl_pkg files: diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index 59e69f1c961..59f180238a3 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -58,6 +58,12 @@ module top_darjeeling #( parameter bit SecRvDmVolatileRawUnlockEn = top_pkg::SecVolatileRawUnlockEn, parameter logic [tlul_pkg::RsvdWidth-1:0] RvDmTlulHostUserRsvdBits = '0, // parameters for rv_plic + // parameters for acc + parameter bit AccStub = 0, + parameter acc_pkg::regfile_e AccRegFile = acc_pkg::RegFileFF, + parameter bit SecAccMuteUrnd = 0, + parameter bit SecAccSkipUrndReseedAtStart = 0, + parameter bit AccAccPQCEn = 0, // parameters for aes parameter bit SecAesMasking = 1, parameter aes_pkg::sbox_impl_e SecAesSBoxImpl = aes_pkg::SBoxImplDom, @@ -76,13 +82,7 @@ module top_darjeeling #( kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgRomCtrl, - kmac_pkg::AppCfgOTBN}, - // parameters for otbn - parameter bit OtbnStub = 0, - parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF, - parameter bit SecOtbnMuteUrnd = 0, - parameter bit SecOtbnSkipUrndReseedAtStart = 0, - parameter bit OtbnOtbnPQCEn = 0, + kmac_pkg::AppCfgACC}, // parameters for keymgr_dpe parameter bit KeymgrDpeKmacEnMasking = 1, // parameters for csrng @@ -195,10 +195,10 @@ module top_darjeeling #( output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_ram_1p_cfg_rsp_o, input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMboxNumRamInst-1:0] sram_ctrl_mbox_ram_1p_cfg_i, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlMboxNumRamInst-1:0] sram_ctrl_mbox_ram_1p_cfg_rsp_o, - input prim_ram_1p_pkg::ram_1p_cfg_t otbn_imem_ram_1p_cfg_i, - output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_imem_ram_1p_cfg_rsp_o, - input prim_ram_1p_pkg::ram_1p_cfg_t otbn_dmem_ram_1p_cfg_i, - output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_dmem_ram_1p_cfg_rsp_o, + input prim_ram_1p_pkg::ram_1p_cfg_t acc_imem_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t acc_imem_ram_1p_cfg_rsp_o, + input prim_ram_1p_pkg::ram_1p_cfg_t acc_dmem_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t acc_dmem_ram_1p_cfg_rsp_o, input prim_ram_1p_pkg::ram_1p_cfg_t rv_core_ibex_icache_tag_ram_1p_cfg_i, output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [RvCoreIbexICacheNWays-1:0] rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o, input prim_ram_1p_pkg::ram_1p_cfg_t rv_core_ibex_icache_data_ram_1p_cfg_i, @@ -392,10 +392,10 @@ module top_darjeeling #( // sram_ctrl_ret_aon // rv_dm // rv_plic + // acc // aes // hmac // kmac - // otbn // keymgr_dpe // csrng // entropy_src @@ -469,13 +469,13 @@ module top_darjeeling #( logic intr_pwrmgr_aon_wakeup; logic intr_aon_timer_aon_wkup_timer_expired; logic intr_aon_timer_aon_wdog_timer_bark; + logic intr_acc_done; logic intr_hmac_hmac_done; logic intr_hmac_fifo_empty; logic intr_hmac_hmac_err; logic intr_kmac_kmac_done; logic intr_kmac_fifo_empty; logic intr_kmac_kmac_err; - logic intr_otbn_done; logic intr_keymgr_dpe_op_done; logic intr_csrng_cs_cmd_req_done; logic intr_csrng_cs_entropy_req; @@ -563,17 +563,17 @@ module top_darjeeling #( logic spi_host0_lsio_trigger; logic uart0_lsio_trigger; lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_flash_rma_req; - lc_ctrl_pkg::lc_tx_t otbn_lc_rma_ack; + lc_ctrl_pkg::lc_tx_t acc_lc_rma_ack; edn_pkg::edn_req_t [7:0] edn0_edn_req; edn_pkg::edn_rsp_t [7:0] edn0_edn_rsp; edn_pkg::edn_req_t [7:0] edn1_edn_req; edn_pkg::edn_rsp_t [7:0] edn1_edn_rsp; - otp_ctrl_pkg::otbn_otp_key_req_t otp_ctrl_otbn_otp_key_req; - otp_ctrl_pkg::otbn_otp_key_rsp_t otp_ctrl_otbn_otp_key_rsp; + otp_ctrl_pkg::acc_otp_key_req_t otp_ctrl_acc_otp_key_req; + otp_ctrl_pkg::acc_otp_key_rsp_t otp_ctrl_acc_otp_key_rsp; otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key; keymgr_pkg::hw_key_req_t keymgr_dpe_aes_key; keymgr_pkg::hw_key_req_t keymgr_dpe_kmac_key; - keymgr_pkg::otbn_key_req_t keymgr_dpe_otbn_key; + keymgr_pkg::acc_key_req_t keymgr_dpe_acc_key; kmac_pkg::app_req_t [KmacNumAppIntf-1:0] kmac_app_req; kmac_pkg::app_rsp_t [KmacNumAppIntf-1:0] kmac_app_rsp; logic kmac_en_masking; @@ -656,8 +656,8 @@ module top_darjeeling #( tlul_pkg::tl_d2h_t edn1_tl_rsp; tlul_pkg::tl_h2d_t rv_plic_tl_req; tlul_pkg::tl_d2h_t rv_plic_tl_rsp; - tlul_pkg::tl_h2d_t otbn_tl_req; - tlul_pkg::tl_d2h_t otbn_tl_rsp; + tlul_pkg::tl_h2d_t acc_tl_req; + tlul_pkg::tl_d2h_t acc_tl_rsp; tlul_pkg::tl_h2d_t keymgr_dpe_tl_req; tlul_pkg::tl_d2h_t keymgr_dpe_tl_rsp; tlul_pkg::tl_h2d_t rv_core_ibex_cfg_tl_d_req; @@ -919,17 +919,17 @@ module top_darjeeling #( // secure_lc_0 assign lpg_cg_en[13] = clkmgr_aon_cg_en.main_secure; assign lpg_rst_en[13] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // aes_trans_lc_0 - assign lpg_cg_en[14] = clkmgr_aon_cg_en.main_aes; + // acc_trans_lc_0 + assign lpg_cg_en[14] = clkmgr_aon_cg_en.main_acc; assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // hmac_trans_lc_0 - assign lpg_cg_en[15] = clkmgr_aon_cg_en.main_hmac; + // aes_trans_lc_0 + assign lpg_cg_en[15] = clkmgr_aon_cg_en.main_aes; assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // kmac_trans_lc_0 - assign lpg_cg_en[16] = clkmgr_aon_cg_en.main_kmac; + // hmac_trans_lc_0 + assign lpg_cg_en[16] = clkmgr_aon_cg_en.main_hmac; assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // otbn_trans_lc_0 - assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_otbn; + // kmac_trans_lc_0 + assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_kmac; assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; @@ -1216,8 +1216,8 @@ module top_darjeeling #( .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key), .sram_otp_key_i(otp_ctrl_sram_otp_key_req), .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp), - .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req), - .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp), + .acc_otp_key_i(otp_ctrl_acc_otp_key_req), + .acc_otp_key_o(otp_ctrl_acc_otp_key_rsp), .otp_broadcast_o(otp_ctrl_otp_broadcast), .otp_macro_o(otp_ctrl_otp_macro_req), .otp_macro_i(otp_ctrl_otp_macro_rsp), @@ -1321,7 +1321,7 @@ module top_darjeeling #( .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_ack), .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack), .lc_flash_rma_req_o(lc_ctrl_lc_flash_rma_req), - .lc_flash_rma_ack_i(otbn_lc_rma_ack), + .lc_flash_rma_ack_i(acc_lc_rma_ack), .lc_flash_rma_seed_o(), .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en), .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en), @@ -1769,9 +1769,58 @@ module top_darjeeling #( .clk_i (clkmgr_aon_clocks.clk_main_secure), .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); - aes #( + acc #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25]), .AlertSkewCycles(top_pkg::AlertSkewCycles), + .Stub(AccStub), + .RegFile(AccRegFile), + .RndCnstUrndPrngSeed(RndCnstAccUrndPrngSeed), + .SecMuteUrnd(SecAccMuteUrnd), + .SecSkipUrndReseedAtStart(SecAccSkipUrndReseedAtStart), + .RndCnstAccKey(RndCnstAccAccKey), + .RndCnstAccNonce(RndCnstAccAccNonce), + .AccPQCEn(AccAccPQCEn) + ) u_acc ( + + // Interrupt + .intr_done_o (intr_acc_done), + // alert_handler[25]: fatal + // alert_handler[26]: recov + .alert_tx_o ( alert_tx[26:25] ), + .alert_rx_i ( alert_rx[26:25] ), + + // Inter-module signals + .acc_otp_key_o(otp_ctrl_acc_otp_key_req), + .acc_otp_key_i(otp_ctrl_acc_otp_key_rsp), + .edn_rnd_o(edn1_edn_req[0]), + .edn_rnd_i(edn1_edn_rsp[0]), + .edn_urnd_o(edn0_edn_req[5]), + .edn_urnd_i(edn0_edn_rsp[5]), + .kmac_data_o(kmac_app_req[4]), + .kmac_data_i(kmac_app_rsp[4]), + .idle_o(clkmgr_aon_idle[0]), + .ram_cfg_imem_i(acc_imem_ram_1p_cfg_i), + .ram_cfg_dmem_i(acc_dmem_ram_1p_cfg_i), + .ram_cfg_rsp_imem_o(acc_imem_ram_1p_cfg_rsp_o), + .ram_cfg_rsp_dmem_o(acc_dmem_ram_1p_cfg_rsp_o), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_rma_req_i(lc_ctrl_lc_flash_rma_req), + .lc_rma_ack_o(acc_lc_rma_ack), + .keymgr_key_i(keymgr_dpe_acc_key), + .tl_i(acc_tl_req), + .tl_o(acc_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_acc), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .clk_otp_i (clkmgr_aon_clocks.clk_io_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]) + ); + aes #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:27]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), .AES192Enable(1'b1), .SecMasking(SecAesMasking), .SecSBoxImpl(SecAesSBoxImpl), @@ -1784,13 +1833,13 @@ module top_darjeeling #( .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm) ) u_aes ( - // alert_handler[25]: recov_ctrl_update_err - // alert_handler[26]: fatal_fault - .alert_tx_o ( alert_tx[26:25] ), - .alert_rx_i ( alert_rx[26:25] ), + // alert_handler[27]: recov_ctrl_update_err + // alert_handler[28]: fatal_fault + .alert_tx_o ( alert_tx[28:27] ), + .alert_rx_i ( alert_rx[28:27] ), // Inter-module signals - .idle_o(clkmgr_aon_idle[0]), + .idle_o(clkmgr_aon_idle[1]), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .edn_o(edn0_edn_req[4]), .edn_i(edn0_edn_rsp[4]), @@ -1806,7 +1855,7 @@ module top_darjeeling #( .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); hmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29]), .AlertSkewCycles(top_pkg::AlertSkewCycles) ) u_hmac ( @@ -1814,12 +1863,12 @@ module top_darjeeling #( .intr_hmac_done_o (intr_hmac_hmac_done), .intr_fifo_empty_o (intr_hmac_fifo_empty), .intr_hmac_err_o (intr_hmac_hmac_err), - // alert_handler[27]: fatal_fault - .alert_tx_o ( alert_tx[27:27] ), - .alert_rx_i ( alert_rx[27:27] ), + // alert_handler[29]: fatal_fault + .alert_tx_o ( alert_tx[29:29] ), + .alert_rx_i ( alert_rx[29:29] ), // Inter-module signals - .idle_o(clkmgr_aon_idle[1]), + .idle_o(clkmgr_aon_idle[2]), .tl_i(hmac_tl_req), .tl_o(hmac_tl_rsp), @@ -1828,7 +1877,7 @@ module top_darjeeling #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); kmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:30]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .EnMasking(KmacEnMasking), .SwKeyMasked(KmacSwKeyMasked), @@ -1846,10 +1895,10 @@ module top_darjeeling #( .intr_kmac_done_o (intr_kmac_kmac_done), .intr_fifo_empty_o (intr_kmac_fifo_empty), .intr_kmac_err_o (intr_kmac_kmac_err), - // alert_handler[28]: recov_operation_err - // alert_handler[29]: fatal_fault_err - .alert_tx_o ( alert_tx[29:28] ), - .alert_rx_i ( alert_rx[29:28] ), + // alert_handler[30]: recov_operation_err + // alert_handler[31]: fatal_fault_err + .alert_tx_o ( alert_tx[31:30] ), + .alert_rx_i ( alert_rx[31:30] ), // Inter-module signals .keymgr_key_i(keymgr_dpe_kmac_key), @@ -1857,7 +1906,7 @@ module top_darjeeling #( .app_o(kmac_app_rsp), .entropy_o(edn0_edn_req[2]), .entropy_i(edn0_edn_rsp[2]), - .idle_o(clkmgr_aon_idle[2]), + .idle_o(clkmgr_aon_idle[3]), .en_masking_o(kmac_en_masking), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .tl_i(kmac_tl_req), @@ -1870,55 +1919,6 @@ module top_darjeeling #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); - otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:30]), - .AlertSkewCycles(top_pkg::AlertSkewCycles), - .Stub(OtbnStub), - .RegFile(OtbnRegFile), - .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed), - .SecMuteUrnd(SecOtbnMuteUrnd), - .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart), - .RndCnstOtbnKey(RndCnstOtbnOtbnKey), - .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce), - .OtbnPQCEn(OtbnOtbnPQCEn) - ) u_otbn ( - - // Interrupt - .intr_done_o (intr_otbn_done), - // alert_handler[30]: fatal - // alert_handler[31]: recov - .alert_tx_o ( alert_tx[31:30] ), - .alert_rx_i ( alert_rx[31:30] ), - - // Inter-module signals - .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), - .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp), - .edn_rnd_o(edn1_edn_req[0]), - .edn_rnd_i(edn1_edn_rsp[0]), - .edn_urnd_o(edn0_edn_req[5]), - .edn_urnd_i(edn0_edn_rsp[5]), - .kmac_data_o(kmac_app_req[4]), - .kmac_data_i(kmac_app_rsp[4]), - .idle_o(clkmgr_aon_idle[3]), - .ram_cfg_imem_i(otbn_imem_ram_1p_cfg_i), - .ram_cfg_dmem_i(otbn_dmem_ram_1p_cfg_i), - .ram_cfg_rsp_imem_o(otbn_imem_ram_1p_cfg_rsp_o), - .ram_cfg_rsp_dmem_o(otbn_dmem_ram_1p_cfg_rsp_o), - .lc_escalate_en_i(lc_ctrl_lc_escalate_en), - .lc_rma_req_i(lc_ctrl_lc_flash_rma_req), - .lc_rma_ack_o(otbn_lc_rma_ack), - .keymgr_key_i(keymgr_dpe_otbn_key), - .tl_i(otbn_tl_req), - .tl_o(otbn_tl_rsp), - - // Clock and reset connections - .clk_i (clkmgr_aon_clocks.clk_main_otbn), - .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), - .clk_otp_i (clkmgr_aon_clocks.clk_io_secure), - .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), - .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), - .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]) - ); keymgr_dpe #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]), .AlertSkewCycles(top_pkg::AlertSkewCycles), @@ -1931,7 +1931,7 @@ module top_darjeeling #( .RndCnstHardOutputSeed(RndCnstKeymgrDpeHardOutputSeed), .RndCnstAesSeed(RndCnstKeymgrDpeAesSeed), .RndCnstKmacSeed(RndCnstKeymgrDpeKmacSeed), - .RndCnstOtbnSeed(RndCnstKeymgrDpeOtbnSeed), + .RndCnstAccSeed(RndCnstKeymgrDpeAccSeed), .RndCnstNoneSeed(RndCnstKeymgrDpeNoneSeed) ) u_keymgr_dpe ( @@ -1947,7 +1947,7 @@ module top_darjeeling #( .edn_i(edn0_edn_rsp[0]), .aes_key_o(keymgr_dpe_aes_key), .kmac_key_o(keymgr_dpe_kmac_key), - .otbn_key_o(keymgr_dpe_otbn_key), + .acc_key_o(keymgr_dpe_acc_key), .kmac_data_o(kmac_app_req[0]), .kmac_data_i(kmac_app_rsp[0]), .otp_key_i(otp_ctrl_otp_keymgr_key), @@ -2876,13 +2876,13 @@ module top_darjeeling #( intr_csrng_cs_entropy_req, // IDs [86 +: 1] intr_csrng_cs_cmd_req_done, // IDs [85 +: 1] intr_keymgr_dpe_op_done, // IDs [84 +: 1] - intr_otbn_done, // IDs [83 +: 1] - intr_kmac_kmac_err, // IDs [82 +: 1] - intr_kmac_fifo_empty, // IDs [81 +: 1] - intr_kmac_kmac_done, // IDs [80 +: 1] - intr_hmac_hmac_err, // IDs [79 +: 1] - intr_hmac_fifo_empty, // IDs [78 +: 1] - intr_hmac_hmac_done, // IDs [77 +: 1] + intr_kmac_kmac_err, // IDs [83 +: 1] + intr_kmac_fifo_empty, // IDs [82 +: 1] + intr_kmac_kmac_done, // IDs [81 +: 1] + intr_hmac_hmac_err, // IDs [80 +: 1] + intr_hmac_fifo_empty, // IDs [79 +: 1] + intr_hmac_hmac_done, // IDs [78 +: 1] + intr_acc_done, // IDs [77 +: 1] intr_aon_timer_aon_wdog_timer_bark, // IDs [76 +: 1] intr_aon_timer_aon_wkup_timer_expired, // IDs [75 +: 1] intr_pwrmgr_aon_wakeup, // IDs [74 +: 1] @@ -3062,9 +3062,9 @@ module top_darjeeling #( .tl_rv_plic_o(rv_plic_tl_req), .tl_rv_plic_i(rv_plic_tl_rsp), - // port: tl_otbn - .tl_otbn_o(otbn_tl_req), - .tl_otbn_i(otbn_tl_rsp), + // port: tl_acc + .tl_acc_o(acc_tl_req), + .tl_acc_i(acc_tl_rsp), // port: tl_keymgr_dpe .tl_keymgr_dpe_o(keymgr_dpe_tl_req), diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv index ab893c83b1f..2d9d90f2148 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv @@ -219,6 +219,16 @@ package top_darjeeling_pkg; */ parameter int unsigned TOP_DARJEELING_RV_PLIC_SIZE_BYTES = 32'h8000000; + /** + * Peripheral base address for acc in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ACC_BASE_ADDR = 32'h22100000; + + /** + * Peripheral size in bytes for acc in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ACC_SIZE_BYTES = 32'h20000; + /** * Peripheral base address for aes in top darjeeling. */ @@ -249,16 +259,6 @@ package top_darjeeling_pkg; */ parameter int unsigned TOP_DARJEELING_KMAC_SIZE_BYTES = 32'h1000; - /** - * Peripheral base address for otbn in top darjeeling. - */ - parameter int unsigned TOP_DARJEELING_OTBN_BASE_ADDR = 32'h22100000; - - /** - * Peripheral size in bytes for otbn in top darjeeling. - */ - parameter int unsigned TOP_DARJEELING_OTBN_SIZE_BYTES = 32'h20000; - /** * Peripheral base address for keymgr_dpe in top darjeeling. */ @@ -569,10 +569,10 @@ package top_darjeeling_pkg; TopDarjeelingAlertPeripheralSramCtrlRetAon = 14, TopDarjeelingAlertPeripheralRvDm = 15, TopDarjeelingAlertPeripheralRvPlic = 16, - TopDarjeelingAlertPeripheralAes = 17, - TopDarjeelingAlertPeripheralHmac = 18, - TopDarjeelingAlertPeripheralKmac = 19, - TopDarjeelingAlertPeripheralOtbn = 20, + TopDarjeelingAlertPeripheralAcc = 17, + TopDarjeelingAlertPeripheralAes = 18, + TopDarjeelingAlertPeripheralHmac = 19, + TopDarjeelingAlertPeripheralKmac = 20, TopDarjeelingAlertPeripheralKeymgrDpe = 21, TopDarjeelingAlertPeripheralCsrng = 22, TopDarjeelingAlertPeripheralEntropySrc = 23, @@ -627,13 +627,13 @@ package top_darjeeling_pkg; TopDarjeelingAlertIdSramCtrlRetAonFatalError = 22, TopDarjeelingAlertIdRvDmFatalFault = 23, TopDarjeelingAlertIdRvPlicFatalFault = 24, - TopDarjeelingAlertIdAesRecovCtrlUpdateErr = 25, - TopDarjeelingAlertIdAesFatalFault = 26, - TopDarjeelingAlertIdHmacFatalFault = 27, - TopDarjeelingAlertIdKmacRecovOperationErr = 28, - TopDarjeelingAlertIdKmacFatalFaultErr = 29, - TopDarjeelingAlertIdOtbnFatal = 30, - TopDarjeelingAlertIdOtbnRecov = 31, + TopDarjeelingAlertIdAccFatal = 25, + TopDarjeelingAlertIdAccRecov = 26, + TopDarjeelingAlertIdAesRecovCtrlUpdateErr = 27, + TopDarjeelingAlertIdAesFatalFault = 28, + TopDarjeelingAlertIdHmacFatalFault = 29, + TopDarjeelingAlertIdKmacRecovOperationErr = 30, + TopDarjeelingAlertIdKmacFatalFaultErr = 31, TopDarjeelingAlertIdKeymgrDpeRecovOperationErr = 32, TopDarjeelingAlertIdKeymgrDpeFatalFaultErr = 33, TopDarjeelingAlertIdCsrngRecovAlert = 34, @@ -761,13 +761,13 @@ package top_darjeeling_pkg; TopDarjeelingPlicIrqIdPwrmgrAonWakeup = 74, TopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired = 75, TopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark = 76, - TopDarjeelingPlicIrqIdHmacHmacDone = 77, - TopDarjeelingPlicIrqIdHmacFifoEmpty = 78, - TopDarjeelingPlicIrqIdHmacHmacErr = 79, - TopDarjeelingPlicIrqIdKmacKmacDone = 80, - TopDarjeelingPlicIrqIdKmacFifoEmpty = 81, - TopDarjeelingPlicIrqIdKmacKmacErr = 82, - TopDarjeelingPlicIrqIdOtbnDone = 83, + TopDarjeelingPlicIrqIdAccDone = 77, + TopDarjeelingPlicIrqIdHmacHmacDone = 78, + TopDarjeelingPlicIrqIdHmacFifoEmpty = 79, + TopDarjeelingPlicIrqIdHmacHmacErr = 80, + TopDarjeelingPlicIrqIdKmacKmacDone = 81, + TopDarjeelingPlicIrqIdKmacFifoEmpty = 82, + TopDarjeelingPlicIrqIdKmacKmacErr = 83, TopDarjeelingPlicIrqIdKeymgrDpeOpDone = 84, TopDarjeelingPlicIrqIdCsrngCsCmdReqDone = 85, TopDarjeelingPlicIrqIdCsrngCsEntropyReq = 86, @@ -1034,6 +1034,7 @@ package top_darjeeling_pkg; // List of peripheral instantiated in this chip. typedef enum { + PeripheralAcc, PeripheralAes, PeripheralAlertHandler, PeripheralAonTimerAon, @@ -1060,7 +1061,6 @@ package top_darjeeling_pkg; PeripheralMbxJtag, PeripheralMbxPcie0, PeripheralMbxPcie1, - PeripheralOtbn, PeripheralOtpCtrl, PeripheralOtpMacro, PeripheralPinmuxAon, diff --git a/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv b/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv index d7b067a2871..f91e7989b0d 100644 --- a/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv +++ b/hw/top_darjeeling/rtl/chip_darjeeling_verilator.sv @@ -858,10 +858,10 @@ module chip_darjeeling_verilator #( .sram_ctrl_main_ram_1p_cfg_rsp_o ( ), .sram_ctrl_mbox_ram_1p_cfg_i ( '0 ), .sram_ctrl_mbox_ram_1p_cfg_rsp_o ( ), - .otbn_imem_ram_1p_cfg_i ( '0 ), - .otbn_imem_ram_1p_cfg_rsp_o ( ), - .otbn_dmem_ram_1p_cfg_i ( '0 ), - .otbn_dmem_ram_1p_cfg_rsp_o ( ), + .acc_imem_ram_1p_cfg_i ( '0 ), + .acc_imem_ram_1p_cfg_rsp_o ( ), + .acc_dmem_ram_1p_cfg_i ( '0 ), + .acc_dmem_ram_1p_cfg_rsp_o ( ), .rv_core_ibex_icache_tag_ram_1p_cfg_i ( '0 ), .rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o ( ), .rv_core_ibex_icache_data_ram_1p_cfg_i ( '0 ), diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs index 031289b89de..7e10ab7325a 100644 --- a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs @@ -315,6 +315,20 @@ pub const RV_PLIC_BASE_ADDR: usize = 0x28000000; /// `RV_PLIC_BASE_ADDR + RV_PLIC_SIZE_BYTES`. pub const RV_PLIC_SIZE_BYTES: usize = 0x8000000; +/// Peripheral base address for acc in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ACC_BASE_ADDR: usize = 0x22100000; + +/// Peripheral size for acc in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ACC_BASE_ADDR and +/// `ACC_BASE_ADDR + ACC_SIZE_BYTES`. +pub const ACC_SIZE_BYTES: usize = 0x20000; + /// Peripheral base address for aes in top darjeeling. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped @@ -357,20 +371,6 @@ pub const KMAC_BASE_ADDR: usize = 0x21120000; /// `KMAC_BASE_ADDR + KMAC_SIZE_BYTES`. pub const KMAC_SIZE_BYTES: usize = 0x1000; -/// Peripheral base address for otbn in top darjeeling. -/// -/// This should be used with #mmio_region_from_addr to access the memory-mapped -/// registers associated with the peripheral (usually via a DIF). -pub const OTBN_BASE_ADDR: usize = 0x22100000; - -/// Peripheral size for otbn in top darjeeling. -/// -/// This is the size (in bytes) of the peripheral's reserved memory area. All -/// memory-mapped registers associated with this peripheral should have an -/// address between #OTBN_BASE_ADDR and -/// `OTBN_BASE_ADDR + OTBN_SIZE_BYTES`. -pub const OTBN_SIZE_BYTES: usize = 0x20000; - /// Peripheral base address for keymgr_dpe in top darjeeling. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped @@ -744,12 +744,12 @@ pub enum PlicPeripheral { PwrmgrAon = 9, /// aon_timer_aon AonTimerAon = 10, + /// acc + Acc = 11, /// hmac - Hmac = 11, + Hmac = 12, /// kmac - Kmac = 12, - /// otbn - Otbn = 13, + Kmac = 13, /// keymgr_dpe KeymgrDpe = 14, /// csrng @@ -803,9 +803,9 @@ impl TryFrom for PlicPeripheral { 8 => Ok(Self::SpiHost0), 9 => Ok(Self::PwrmgrAon), 10 => Ok(Self::AonTimerAon), - 11 => Ok(Self::Hmac), - 12 => Ok(Self::Kmac), - 13 => Ok(Self::Otbn), + 11 => Ok(Self::Acc), + 12 => Ok(Self::Hmac), + 13 => Ok(Self::Kmac), 14 => Ok(Self::KeymgrDpe), 15 => Ok(Self::Csrng), 16 => Ok(Self::EntropySrc), @@ -990,20 +990,20 @@ pub enum PlicIrqId { AonTimerAonWkupTimerExpired = 75, /// aon_timer_aon_wdog_timer_bark AonTimerAonWdogTimerBark = 76, + /// acc_done + AccDone = 77, /// hmac_hmac_done - HmacHmacDone = 77, + HmacHmacDone = 78, /// hmac_fifo_empty - HmacFifoEmpty = 78, + HmacFifoEmpty = 79, /// hmac_hmac_err - HmacHmacErr = 79, + HmacHmacErr = 80, /// kmac_kmac_done - KmacKmacDone = 80, + KmacKmacDone = 81, /// kmac_fifo_empty - KmacFifoEmpty = 81, + KmacFifoEmpty = 82, /// kmac_kmac_err - KmacKmacErr = 82, - /// otbn_done - OtbnDone = 83, + KmacKmacErr = 83, /// keymgr_dpe_op_done KeymgrDpeOpDone = 84, /// csrng_cs_cmd_req_done @@ -1183,13 +1183,13 @@ impl TryFrom for PlicIrqId { 74 => Ok(Self::PwrmgrAonWakeup), 75 => Ok(Self::AonTimerAonWkupTimerExpired), 76 => Ok(Self::AonTimerAonWdogTimerBark), - 77 => Ok(Self::HmacHmacDone), - 78 => Ok(Self::HmacFifoEmpty), - 79 => Ok(Self::HmacHmacErr), - 80 => Ok(Self::KmacKmacDone), - 81 => Ok(Self::KmacFifoEmpty), - 82 => Ok(Self::KmacKmacErr), - 83 => Ok(Self::OtbnDone), + 77 => Ok(Self::AccDone), + 78 => Ok(Self::HmacHmacDone), + 79 => Ok(Self::HmacFifoEmpty), + 80 => Ok(Self::HmacHmacErr), + 81 => Ok(Self::KmacKmacDone), + 82 => Ok(Self::KmacFifoEmpty), + 83 => Ok(Self::KmacKmacErr), 84 => Ok(Self::KeymgrDpeOpDone), 85 => Ok(Self::CsrngCsCmdReqDone), 86 => Ok(Self::CsrngCsEntropyReq), @@ -1413,6 +1413,8 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 132] = [ PlicPeripheral::AonTimerAon, // AonTimerAonWdogTimerBark -> PlicPeripheral::AonTimerAon PlicPeripheral::AonTimerAon, + // AccDone -> PlicPeripheral::Acc + PlicPeripheral::Acc, // HmacHmacDone -> PlicPeripheral::Hmac PlicPeripheral::Hmac, // HmacFifoEmpty -> PlicPeripheral::Hmac @@ -1425,8 +1427,6 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 132] = [ PlicPeripheral::Kmac, // KmacKmacErr -> PlicPeripheral::Kmac PlicPeripheral::Kmac, - // OtbnDone -> PlicPeripheral::Otbn - PlicPeripheral::Otbn, // KeymgrDpeOpDone -> PlicPeripheral::KeymgrDpe PlicPeripheral::KeymgrDpe, // CsrngCsCmdReqDone -> PlicPeripheral::Csrng @@ -1568,14 +1568,14 @@ pub enum AlertPeripheral { RvDm = 16, /// rv_plic RvPlic = 17, + /// acc + Acc = 18, /// aes - Aes = 18, + Aes = 19, /// hmac - Hmac = 19, + Hmac = 20, /// kmac - Kmac = 20, - /// otbn - Otbn = 21, + Kmac = 21, /// keymgr_dpe KeymgrDpe = 22, /// csrng @@ -1683,20 +1683,20 @@ pub enum AlertId { RvDmFatalFault = 23, /// rv_plic_fatal_fault RvPlicFatalFault = 24, + /// acc_fatal + AccFatal = 25, + /// acc_recov + AccRecov = 26, /// aes_recov_ctrl_update_err - AesRecovCtrlUpdateErr = 25, + AesRecovCtrlUpdateErr = 27, /// aes_fatal_fault - AesFatalFault = 26, + AesFatalFault = 28, /// hmac_fatal_fault - HmacFatalFault = 27, + HmacFatalFault = 29, /// kmac_recov_operation_err - KmacRecovOperationErr = 28, + KmacRecovOperationErr = 30, /// kmac_fatal_fault_err - KmacFatalFaultErr = 29, - /// otbn_fatal - OtbnFatal = 30, - /// otbn_recov - OtbnRecov = 31, + KmacFatalFaultErr = 31, /// keymgr_dpe_recov_operation_err KeymgrDpeRecovOperationErr = 32, /// keymgr_dpe_fatal_fault_err @@ -1818,13 +1818,13 @@ impl TryFrom for AlertId { 22 => Ok(Self::SramCtrlRetAonFatalError), 23 => Ok(Self::RvDmFatalFault), 24 => Ok(Self::RvPlicFatalFault), - 25 => Ok(Self::AesRecovCtrlUpdateErr), - 26 => Ok(Self::AesFatalFault), - 27 => Ok(Self::HmacFatalFault), - 28 => Ok(Self::KmacRecovOperationErr), - 29 => Ok(Self::KmacFatalFaultErr), - 30 => Ok(Self::OtbnFatal), - 31 => Ok(Self::OtbnRecov), + 25 => Ok(Self::AccFatal), + 26 => Ok(Self::AccRecov), + 27 => Ok(Self::AesRecovCtrlUpdateErr), + 28 => Ok(Self::AesFatalFault), + 29 => Ok(Self::HmacFatalFault), + 30 => Ok(Self::KmacRecovOperationErr), + 31 => Ok(Self::KmacFatalFaultErr), 32 => Ok(Self::KeymgrDpeRecovOperationErr), 33 => Ok(Self::KeymgrDpeFatalFaultErr), 34 => Ok(Self::CsrngRecovAlert), @@ -1930,6 +1930,10 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 77] = [ AlertPeripheral::RvDm, // RvPlicFatalFault -> AlertPeripheral::RvPlic AlertPeripheral::RvPlic, + // AccFatal -> AlertPeripheral::Acc + AlertPeripheral::Acc, + // AccRecov -> AlertPeripheral::Acc + AlertPeripheral::Acc, // AesRecovCtrlUpdateErr -> AlertPeripheral::Aes AlertPeripheral::Aes, // AesFatalFault -> AlertPeripheral::Aes @@ -1940,10 +1944,6 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 77] = [ AlertPeripheral::Kmac, // KmacFatalFaultErr -> AlertPeripheral::Kmac AlertPeripheral::Kmac, - // OtbnFatal -> AlertPeripheral::Otbn - AlertPeripheral::Otbn, - // OtbnRecov -> AlertPeripheral::Otbn - AlertPeripheral::Otbn, // KeymgrDpeRecovOperationErr -> AlertPeripheral::KeymgrDpe AlertPeripheral::KeymgrDpe, // KeymgrDpeFatalFaultErr -> AlertPeripheral::KeymgrDpe @@ -2461,14 +2461,14 @@ pub enum GateableClocks { #[derive(Copy, Clone, PartialEq, Eq)] #[repr(u32)] pub enum HintableClocks { + /// Clock clk_main_acc in group trans + MainAcc = 0, /// Clock clk_main_aes in group trans - MainAes = 0, + MainAes = 1, /// Clock clk_main_hmac in group trans - MainHmac = 1, + MainHmac = 2, /// Clock clk_main_kmac in group trans - MainKmac = 2, - /// Clock clk_main_otbn in group trans - MainOtbn = 3, + MainKmac = 3, } /// MMIO Region diff --git a/hw/top_darjeeling/sw/autogen/tests/BUILD b/hw/top_darjeeling/sw/autogen/tests/BUILD index 105cf81c287..942329603b0 100644 --- a/hw/top_darjeeling/sw/autogen/tests/BUILD +++ b/hw/top_darjeeling/sw/autogen/tests/BUILD @@ -55,6 +55,7 @@ NR_IRQ_PERIPH_TESTS = 2 "//hw/top_darjeeling/sw/autogen:top_darjeeling", "//sw/device/lib/arch:boot_stage", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif/autogen:acc", "//sw/device/lib/dif/autogen:alert_handler", "//sw/device/lib/dif/autogen:aon_timer", "//sw/device/lib/dif/autogen:csrng", @@ -67,7 +68,6 @@ NR_IRQ_PERIPH_TESTS = 2 "//sw/device/lib/dif/autogen:keymgr_dpe", "//sw/device/lib/dif/autogen:kmac", "//sw/device/lib/dif/autogen:mbx", - "//sw/device/lib/dif/autogen:otbn", "//sw/device/lib/dif/autogen:otp_ctrl", "//sw/device/lib/dif/autogen:pwrmgr", "//sw/device/lib/dif/autogen:rv_plic", @@ -105,6 +105,7 @@ opentitan_test( "//sw/device/lib/arch:boot_stage", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif/autogen:acc", "//sw/device/lib/dif/autogen:aes", "//sw/device/lib/dif/autogen:alert_handler", "//sw/device/lib/dif/autogen:aon_timer", @@ -120,7 +121,6 @@ opentitan_test( "//sw/device/lib/dif/autogen:kmac", "//sw/device/lib/dif/autogen:lc_ctrl", "//sw/device/lib/dif/autogen:mbx", - "//sw/device/lib/dif/autogen:otbn", "//sw/device/lib/dif/autogen:otp_ctrl", "//sw/device/lib/dif/autogen:pinmux", "//sw/device/lib/dif/autogen:pwrmgr", diff --git a/hw/top_darjeeling/sw/autogen/tests/alert_test.c b/hw/top_darjeeling/sw/autogen/tests/alert_test.c index ab192b7af0e..9b8748afe42 100644 --- a/hw/top_darjeeling/sw/autogen/tests/alert_test.c +++ b/hw/top_darjeeling/sw/autogen/tests/alert_test.c @@ -10,6 +10,7 @@ // -o hw/top_darjeeling/ #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/autogen/dif_acc_autogen.h" #include "sw/device/lib/dif/autogen/dif_aes_autogen.h" #include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h" #include "sw/device/lib/dif/autogen/dif_aon_timer_autogen.h" @@ -25,7 +26,6 @@ #include "sw/device/lib/dif/autogen/dif_kmac_autogen.h" #include "sw/device/lib/dif/autogen/dif_lc_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_mbx_autogen.h" -#include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_pinmux_autogen.h" #include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h" @@ -51,6 +51,7 @@ OTTF_DEFINE_TEST_CONFIG(); static dif_alert_handler_t alert_handler; +static dif_acc_t acc; static dif_aes_t aes; static dif_aon_timer_t aon_timer_aon; static dif_clkmgr_t clkmgr_aon; @@ -75,7 +76,6 @@ static dif_mbx_t mbx6; static dif_mbx_t mbx_jtag; static dif_mbx_t mbx_pcie0; static dif_mbx_t mbx_pcie1; -static dif_otbn_t otbn; static dif_otp_ctrl_t otp_ctrl; static dif_pinmux_t pinmux_aon; static dif_pwrmgr_t pwrmgr_aon; @@ -102,6 +102,9 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR); CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); + base_addr = mmio_region_from_addr(TOP_DARJEELING_ACC_BASE_ADDR); + CHECK_DIF_OK(dif_acc_init(base_addr, &acc)); + base_addr = mmio_region_from_addr(TOP_DARJEELING_AES_BASE_ADDR); CHECK_DIF_OK(dif_aes_init(base_addr, &aes)); @@ -174,9 +177,6 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_pcie1)); - base_addr = mmio_region_from_addr(TOP_DARJEELING_OTBN_BASE_ADDR); - CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); - base_addr = mmio_region_from_addr(TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); @@ -286,6 +286,21 @@ static void trigger_alert_test(void) { bool is_cause; dif_alert_handler_alert_t exp_alert; + // Write acc's alert_test reg and check alert_cause. + for (dif_acc_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_acc_alert_force(&acc, kDifAccAlertFatal + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingAlertIdAccFatal + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + // Write aes's alert_test reg and check alert_cause. for (dif_aes_alert_t i = 0; i < 2; ++i) { CHECK_DIF_OK(dif_aes_alert_force(&aes, kDifAesAlertRecovCtrlUpdateErr + i)); @@ -646,21 +661,6 @@ static void trigger_alert_test(void) { &alert_handler, exp_alert)); } - // Write otbn's alert_test reg and check alert_cause. - for (dif_otbn_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_otbn_alert_force(&otbn, kDifOtbnAlertFatal + i)); - - // Verify that alert handler received it. - exp_alert = kTopDarjeelingAlertIdOtbnFatal + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - // TODO(lowrisc/opentitan#20348): Enable otp_ctrl when this is fixed. if (kBootStage != kBootStageOwner) { // Write otp_ctrl's alert_test reg and check alert_cause. diff --git a/hw/top_darjeeling/sw/autogen/tests/plic_all_irqs_test.c b/hw/top_darjeeling/sw/autogen/tests/plic_all_irqs_test.c index 19874fd051e..c27ecca33c7 100644 --- a/hw/top_darjeeling/sw/autogen/tests/plic_all_irqs_test.c +++ b/hw/top_darjeeling/sw/autogen/tests/plic_all_irqs_test.c @@ -28,6 +28,7 @@ #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/csr.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/autogen/dif_acc_autogen.h" #include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h" #include "sw/device/lib/dif/autogen/dif_aon_timer_autogen.h" #include "sw/device/lib/dif/autogen/dif_csrng_autogen.h" @@ -40,7 +41,6 @@ #include "sw/device/lib/dif/autogen/dif_keymgr_dpe_autogen.h" #include "sw/device/lib/dif/autogen/dif_kmac_autogen.h" #include "sw/device/lib/dif/autogen/dif_mbx_autogen.h" -#include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h" #include "sw/device/lib/dif/autogen/dif_rv_plic_autogen.h" @@ -59,95 +59,95 @@ #include "hw/top_darjeeling/sw/autogen/top_darjeeling.h" #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL -static dif_alert_handler_t alert_handler; +static dif_acc_t acc; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL -static dif_aon_timer_t aon_timer_aon; +static dif_alert_handler_t alert_handler; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL -static dif_csrng_t csrng; +static dif_aon_timer_t aon_timer_aon; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL -static dif_dma_t dma; +static dif_csrng_t csrng; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +static dif_dma_t dma; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static dif_edn_t edn0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static dif_edn_t edn1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL static dif_entropy_src_t entropy_src; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static dif_gpio_t gpio; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static dif_hmac_t hmac; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL static dif_i2c_t i2c0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static dif_keymgr_dpe_t keymgr_dpe; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL static dif_kmac_t kmac; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx2; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx3; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx4; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx5; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx6; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx_jtag; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static dif_mbx_t mbx_pcie0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL -static dif_mbx_t mbx_pcie1; -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL -static dif_otbn_t otbn; +static dif_mbx_t mbx_pcie1; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL @@ -194,70 +194,70 @@ static volatile top_darjeeling_plic_peripheral_t peripheral_expected; */ #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_acc_irq_t acc_irq_expected; +static volatile dif_acc_irq_t acc_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_alert_handler_irq_t alert_handler_irq_expected; static volatile dif_alert_handler_irq_t alert_handler_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_aon_timer_irq_t aon_timer_irq_expected; static volatile dif_aon_timer_irq_t aon_timer_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_csrng_irq_t csrng_irq_expected; static volatile dif_csrng_irq_t csrng_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_dma_irq_t dma_irq_expected; static volatile dif_dma_irq_t dma_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_edn_irq_t edn_irq_expected; static volatile dif_edn_irq_t edn_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_entropy_src_irq_t entropy_src_irq_expected; static volatile dif_entropy_src_irq_t entropy_src_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_gpio_irq_t gpio_irq_expected; static volatile dif_gpio_irq_t gpio_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_hmac_irq_t hmac_irq_expected; static volatile dif_hmac_irq_t hmac_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_i2c_irq_t i2c_irq_expected; static volatile dif_i2c_irq_t i2c_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_keymgr_dpe_irq_t keymgr_dpe_irq_expected; static volatile dif_keymgr_dpe_irq_t keymgr_dpe_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_kmac_irq_t kmac_irq_expected; static volatile dif_kmac_irq_t kmac_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_mbx_irq_t mbx_irq_expected; static volatile dif_mbx_irq_t mbx_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_otbn_irq_t otbn_irq_expected; -static volatile dif_otbn_irq_t otbn_irq_serviced; -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_expected; static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_serviced; @@ -313,6 +313,29 @@ void ottf_external_isr(uint32_t *exc_info) { switch (peripheral) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingPlicPeripheralAcc: { + dif_acc_irq_t irq = + (dif_acc_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingPlicIrqIdAccDone); + CHECK(irq == acc_irq_expected, + "Incorrect acc IRQ triggered: exp = %d, obs = %d", + acc_irq_expected, irq); + acc_irq_serviced = irq; + + dif_acc_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_acc_irq_get_state(&acc, &snapshot)); + CHECK(snapshot == (dif_acc_irq_state_snapshot_t)(1 << irq), + "Only acc IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_acc_irq_acknowledge(&acc, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralAlertHandler: { dif_alert_handler_irq_t irq = (dif_alert_handler_irq_t)(plic_irq_id - @@ -335,7 +358,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralAonTimerAon: { dif_aon_timer_irq_t irq = (dif_aon_timer_irq_t)(plic_irq_id - @@ -358,7 +381,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralCsrng: { dif_csrng_irq_t irq = (dif_csrng_irq_t)(plic_irq_id - @@ -381,7 +404,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralDma: { dif_dma_irq_t irq = (dif_dma_irq_t)(plic_irq_id - @@ -417,7 +440,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralEdn0: { dif_edn_irq_t irq = (dif_edn_irq_t)(plic_irq_id - @@ -440,7 +463,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralEdn1: { dif_edn_irq_t irq = (dif_edn_irq_t)(plic_irq_id - @@ -463,7 +486,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralEntropySrc: { dif_entropy_src_irq_t irq = (dif_entropy_src_irq_t)(plic_irq_id - @@ -486,7 +509,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralGpio: { dif_gpio_irq_t irq = (dif_gpio_irq_t)(plic_irq_id - @@ -509,7 +532,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralHmac: { dif_hmac_irq_t irq = (dif_hmac_irq_t)(plic_irq_id - @@ -545,7 +568,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralI2c0: { dif_i2c_irq_t irq = (dif_i2c_irq_t)(plic_irq_id - @@ -581,7 +604,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralKeymgrDpe: { dif_keymgr_dpe_irq_t irq = (dif_keymgr_dpe_irq_t)(plic_irq_id - @@ -604,7 +627,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralKmac: { dif_kmac_irq_t irq = (dif_kmac_irq_t)(plic_irq_id - @@ -640,7 +663,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbx0: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -663,7 +686,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbx1: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -686,7 +709,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbx2: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -709,7 +732,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbx3: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -732,7 +755,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbx4: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -755,7 +778,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbx5: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -778,7 +801,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbx6: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -801,7 +824,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbxJtag: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -824,7 +847,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbxPcie0: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -847,7 +870,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralMbxPcie1: { dif_mbx_irq_t irq = (dif_mbx_irq_t)(plic_irq_id - @@ -870,29 +893,6 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - case kTopDarjeelingPlicPeripheralOtbn: { - dif_otbn_irq_t irq = - (dif_otbn_irq_t)(plic_irq_id - - (dif_rv_plic_irq_id_t) - kTopDarjeelingPlicIrqIdOtbnDone); - CHECK(irq == otbn_irq_expected, - "Incorrect otbn IRQ triggered: exp = %d, obs = %d", - otbn_irq_expected, irq); - otbn_irq_serviced = irq; - - dif_otbn_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_otbn_irq_get_state(&otbn, &snapshot)); - CHECK(snapshot == (dif_otbn_irq_state_snapshot_t)(1 << irq), - "Only otbn IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - CHECK_DIF_OK(dif_otbn_irq_acknowledge(&otbn, irq)); - break; - } -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL case kTopDarjeelingPlicPeripheralOtpCtrl: { dif_otp_ctrl_irq_t irq = @@ -1085,120 +1085,120 @@ static void peripherals_init(void) { mmio_region_t base_addr; #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_ACC_BASE_ADDR); + CHECK_DIF_OK(dif_acc_init(base_addr, &acc)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR); CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR); CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_CSRNG_BASE_ADDR); CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_DMA_BASE_ADDR); CHECK_DIF_OK(dif_dma_init(base_addr, &dma)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_EDN0_BASE_ADDR); CHECK_DIF_OK(dif_edn_init(base_addr, &edn0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_EDN1_BASE_ADDR); CHECK_DIF_OK(dif_edn_init(base_addr, &edn1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_ENTROPY_SRC_BASE_ADDR); CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_GPIO_BASE_ADDR); CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_HMAC_BASE_ADDR); CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_I2C0_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR); CHECK_DIF_OK(dif_keymgr_dpe_init(base_addr, &keymgr_dpe)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_KMAC_BASE_ADDR); CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX0_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX1_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX2_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX3_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx3)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX4_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx4)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX5_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx5)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX6_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx6)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_jtag)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_pcie0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR); CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_pcie1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_DARJEELING_OTBN_BASE_ADDR); - CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); @@ -1238,95 +1238,95 @@ static void peripherals_init(void) { */ static void peripheral_irqs_clear(void) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler)); + CHECK_DIF_OK(dif_acc_irq_acknowledge_all(&acc)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon)); + CHECK_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng)); + CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_dma_irq_acknowledge_all(&dma)); + CHECK_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_dma_irq_acknowledge_all(&dma)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_entropy_src_irq_acknowledge_all(&entropy_src)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_hmac_irq_acknowledge_all(&hmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_keymgr_dpe_irq_acknowledge_all(&keymgr_dpe)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx3)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx4)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx5)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx6)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx_jtag)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx_pcie0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx_pcie1)); -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn)); + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx_pcie1)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL @@ -1361,65 +1361,65 @@ static void peripheral_irqs_clear(void) { */ static void peripheral_irqs_enable(void) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + dif_acc_irq_state_snapshot_t acc_irqs = + (dif_acc_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL dif_alert_handler_irq_state_snapshot_t alert_handler_irqs = (dif_alert_handler_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL dif_csrng_irq_state_snapshot_t csrng_irqs = (dif_csrng_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL dif_dma_irq_state_snapshot_t dma_irqs = (dif_dma_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL dif_edn_irq_state_snapshot_t edn_irqs = (dif_edn_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL dif_entropy_src_irq_state_snapshot_t entropy_src_irqs = (dif_entropy_src_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL dif_gpio_irq_state_snapshot_t gpio_irqs = (dif_gpio_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL dif_hmac_irq_state_snapshot_t hmac_irqs = (dif_hmac_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL dif_i2c_irq_state_snapshot_t i2c_irqs = (dif_i2c_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL dif_keymgr_dpe_irq_state_snapshot_t keymgr_dpe_irqs = (dif_keymgr_dpe_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL dif_kmac_irq_state_snapshot_t kmac_irqs = (dif_kmac_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL dif_mbx_irq_state_snapshot_t mbx_irqs = (dif_mbx_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - dif_otbn_irq_state_snapshot_t otbn_irqs = - (dif_otbn_irq_state_snapshot_t)0xffffffff; -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL dif_otp_ctrl_irq_state_snapshot_t otp_ctrl_irqs = (dif_otp_ctrl_irq_state_snapshot_t)0xffffffff; @@ -1455,91 +1455,91 @@ static void peripheral_irqs_enable(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_acc_irq_restore_all(&acc, &acc_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_alert_handler_irq_restore_all(&alert_handler, &alert_handler_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_csrng_irq_restore_all(&csrng, &csrng_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_dma_irq_restore_all(&dma, &dma_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_restore_all(&edn0, &edn_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_restore_all(&edn1, &edn_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_entropy_src_irq_restore_all(&entropy_src, &entropy_src_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_gpio_irq_restore_all(&gpio, &gpio_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_hmac_irq_restore_all(&hmac, &hmac_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c0, &i2c_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_keymgr_dpe_irq_restore_all(&keymgr_dpe, &keymgr_dpe_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_kmac_irq_restore_all(&kmac, &kmac_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx0, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx1, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx2, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx3, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx4, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx5, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx6, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx_jtag, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx_pcie0, &mbx_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx_pcie1, &mbx_irqs)); -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_otbn_irq_restore_all(&otbn, &otbn_irqs)); + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx_pcie1, &mbx_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL @@ -1589,6 +1589,21 @@ static void peripheral_irqs_trigger(void) { (void)status_default_mask; #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingPlicPeripheralAcc; + for (dif_acc_irq_t irq = kDifAccIrqDone; irq <= kDifAccIrqDone; + ++irq) { + acc_irq_expected = irq; + LOG_INFO("Triggering acc IRQ %d.", irq); + CHECK_DIF_OK(dif_acc_irq_force(&acc, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(acc_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from acc is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralAlertHandler; for (dif_alert_handler_irq_t irq = kDifAlertHandlerIrqClassa; irq <= kDifAlertHandlerIrqClassd; ++irq) { @@ -1603,7 +1618,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. @@ -1625,7 +1640,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralCsrng; for (dif_csrng_irq_t irq = kDifCsrngIrqCsCmdReqDone; irq <= kDifCsrngIrqCsFatalErr; ++irq) { @@ -1640,7 +1655,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralDma; status_default_mask = 0x0; for (dif_dma_irq_t irq = kDifDmaIrqDmaDone; irq <= kDifDmaIrqDmaError; @@ -1664,7 +1679,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralEdn0; for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; irq <= kDifEdnIrqEdnFatalErr; ++irq) { @@ -1679,7 +1694,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralEdn1; for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; irq <= kDifEdnIrqEdnFatalErr; ++irq) { @@ -1694,7 +1709,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralEntropySrc; for (dif_entropy_src_irq_t irq = kDifEntropySrcIrqEsEntropyValid; irq <= kDifEntropySrcIrqEsFatalErr; ++irq) { @@ -1709,7 +1724,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralGpio; for (dif_gpio_irq_t irq = kDifGpioIrqGpio0; irq <= kDifGpioIrqGpio31; ++irq) { @@ -1724,7 +1739,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralHmac; status_default_mask = 0x0; for (dif_hmac_irq_t irq = kDifHmacIrqHmacDone; irq <= kDifHmacIrqHmacErr; @@ -1748,7 +1763,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralI2c0; status_default_mask = 0x0; for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; @@ -1772,7 +1787,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralKeymgrDpe; for (dif_keymgr_dpe_irq_t irq = kDifKeymgrDpeIrqOpDone; irq <= kDifKeymgrDpeIrqOpDone; ++irq) { @@ -1787,7 +1802,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralKmac; status_default_mask = 0x0; for (dif_kmac_irq_t irq = kDifKmacIrqKmacDone; irq <= kDifKmacIrqKmacErr; @@ -1811,7 +1826,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbx0; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1826,7 +1841,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbx1; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1841,7 +1856,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbx2; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1856,7 +1871,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbx3; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1871,7 +1886,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbx4; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1886,7 +1901,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbx5; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1901,7 +1916,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbx6; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1916,7 +1931,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbxJtag; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1931,7 +1946,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbxPcie0; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1946,7 +1961,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopDarjeelingPlicPeripheralMbxPcie1; for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; ++irq) { @@ -1961,21 +1976,6 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopDarjeelingPlicPeripheralOtbn; - for (dif_otbn_irq_t irq = kDifOtbnIrqDone; irq <= kDifOtbnIrqDone; - ++irq) { - otbn_irq_expected = irq; - LOG_INFO("Triggering otbn IRQ %d.", irq); - CHECK_DIF_OK(dif_otbn_irq_force(&otbn, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(otbn_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from otbn is serviced.", irq); - } -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL // Skip OTP_CTRL in boot stage owner since ROM_EXT configures all accesses // to OTP_CTRL and AST to be illegal. diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.c b/hw/top_darjeeling/sw/autogen/top_darjeeling.c index 9d65a5296e0..77fec7976b1 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling.c +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.c @@ -42,13 +42,13 @@ const top_darjeeling_alert_peripheral_t [kTopDarjeelingAlertIdSramCtrlRetAonFatalError] = kTopDarjeelingAlertPeripheralSramCtrlRetAon, [kTopDarjeelingAlertIdRvDmFatalFault] = kTopDarjeelingAlertPeripheralRvDm, [kTopDarjeelingAlertIdRvPlicFatalFault] = kTopDarjeelingAlertPeripheralRvPlic, + [kTopDarjeelingAlertIdAccFatal] = kTopDarjeelingAlertPeripheralAcc, + [kTopDarjeelingAlertIdAccRecov] = kTopDarjeelingAlertPeripheralAcc, [kTopDarjeelingAlertIdAesRecovCtrlUpdateErr] = kTopDarjeelingAlertPeripheralAes, [kTopDarjeelingAlertIdAesFatalFault] = kTopDarjeelingAlertPeripheralAes, [kTopDarjeelingAlertIdHmacFatalFault] = kTopDarjeelingAlertPeripheralHmac, [kTopDarjeelingAlertIdKmacRecovOperationErr] = kTopDarjeelingAlertPeripheralKmac, [kTopDarjeelingAlertIdKmacFatalFaultErr] = kTopDarjeelingAlertPeripheralKmac, - [kTopDarjeelingAlertIdOtbnFatal] = kTopDarjeelingAlertPeripheralOtbn, - [kTopDarjeelingAlertIdOtbnRecov] = kTopDarjeelingAlertPeripheralOtbn, [kTopDarjeelingAlertIdKeymgrDpeRecovOperationErr] = kTopDarjeelingAlertPeripheralKeymgrDpe, [kTopDarjeelingAlertIdKeymgrDpeFatalFaultErr] = kTopDarjeelingAlertPeripheralKeymgrDpe, [kTopDarjeelingAlertIdCsrngRecovAlert] = kTopDarjeelingAlertPeripheralCsrng, @@ -181,13 +181,13 @@ const top_darjeeling_plic_peripheral_t [kTopDarjeelingPlicIrqIdPwrmgrAonWakeup] = kTopDarjeelingPlicPeripheralPwrmgrAon, [kTopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired] = kTopDarjeelingPlicPeripheralAonTimerAon, [kTopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark] = kTopDarjeelingPlicPeripheralAonTimerAon, + [kTopDarjeelingPlicIrqIdAccDone] = kTopDarjeelingPlicPeripheralAcc, [kTopDarjeelingPlicIrqIdHmacHmacDone] = kTopDarjeelingPlicPeripheralHmac, [kTopDarjeelingPlicIrqIdHmacFifoEmpty] = kTopDarjeelingPlicPeripheralHmac, [kTopDarjeelingPlicIrqIdHmacHmacErr] = kTopDarjeelingPlicPeripheralHmac, [kTopDarjeelingPlicIrqIdKmacKmacDone] = kTopDarjeelingPlicPeripheralKmac, [kTopDarjeelingPlicIrqIdKmacFifoEmpty] = kTopDarjeelingPlicPeripheralKmac, [kTopDarjeelingPlicIrqIdKmacKmacErr] = kTopDarjeelingPlicPeripheralKmac, - [kTopDarjeelingPlicIrqIdOtbnDone] = kTopDarjeelingPlicPeripheralOtbn, [kTopDarjeelingPlicIrqIdKeymgrDpeOpDone] = kTopDarjeelingPlicPeripheralKeymgrDpe, [kTopDarjeelingPlicIrqIdCsrngCsCmdReqDone] = kTopDarjeelingPlicPeripheralCsrng, [kTopDarjeelingPlicIrqIdCsrngCsEntropyReq] = kTopDarjeelingPlicPeripheralCsrng, diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.h b/hw/top_darjeeling/sw/autogen/top_darjeeling.h index 15f531ba830..e5db128c7d2 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling.h +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.h @@ -408,6 +408,24 @@ extern "C" { */ #define TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000u +/** + * Peripheral base address for acc in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ACC_BASE_ADDR 0x22100000u + +/** + * Peripheral size for acc in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ACC_BASE_ADDR and + * `TOP_DARJEELING_ACC_BASE_ADDR + TOP_DARJEELING_ACC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ACC_SIZE_BYTES 0x20000u + /** * Peripheral base address for aes in top darjeeling. * @@ -462,24 +480,6 @@ extern "C" { */ #define TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000u -/** - * Peripheral base address for otbn in top darjeeling. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_DARJEELING_OTBN_BASE_ADDR 0x22100000u - -/** - * Peripheral size for otbn in top darjeeling. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_DARJEELING_OTBN_BASE_ADDR and - * `TOP_DARJEELING_OTBN_BASE_ADDR + TOP_DARJEELING_OTBN_SIZE_BYTES`. - */ -#define TOP_DARJEELING_OTBN_SIZE_BYTES 0x20000u - /** * Peripheral base address for keymgr_dpe in top darjeeling. * @@ -956,9 +956,9 @@ typedef enum top_darjeeling_plic_peripheral { kTopDarjeelingPlicPeripheralSpiHost0 = 8, /**< spi_host0 */ kTopDarjeelingPlicPeripheralPwrmgrAon = 9, /**< pwrmgr_aon */ kTopDarjeelingPlicPeripheralAonTimerAon = 10, /**< aon_timer_aon */ - kTopDarjeelingPlicPeripheralHmac = 11, /**< hmac */ - kTopDarjeelingPlicPeripheralKmac = 12, /**< kmac */ - kTopDarjeelingPlicPeripheralOtbn = 13, /**< otbn */ + kTopDarjeelingPlicPeripheralAcc = 11, /**< acc */ + kTopDarjeelingPlicPeripheralHmac = 12, /**< hmac */ + kTopDarjeelingPlicPeripheralKmac = 13, /**< kmac */ kTopDarjeelingPlicPeripheralKeymgrDpe = 14, /**< keymgr_dpe */ kTopDarjeelingPlicPeripheralCsrng = 15, /**< csrng */ kTopDarjeelingPlicPeripheralEntropySrc = 16, /**< entropy_src */ @@ -1064,13 +1064,13 @@ typedef enum top_darjeeling_plic_irq_id { kTopDarjeelingPlicIrqIdPwrmgrAonWakeup = 74, /**< pwrmgr_aon_wakeup */ kTopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired = 75, /**< aon_timer_aon_wkup_timer_expired */ kTopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark = 76, /**< aon_timer_aon_wdog_timer_bark */ - kTopDarjeelingPlicIrqIdHmacHmacDone = 77, /**< hmac_hmac_done */ - kTopDarjeelingPlicIrqIdHmacFifoEmpty = 78, /**< hmac_fifo_empty */ - kTopDarjeelingPlicIrqIdHmacHmacErr = 79, /**< hmac_hmac_err */ - kTopDarjeelingPlicIrqIdKmacKmacDone = 80, /**< kmac_kmac_done */ - kTopDarjeelingPlicIrqIdKmacFifoEmpty = 81, /**< kmac_fifo_empty */ - kTopDarjeelingPlicIrqIdKmacKmacErr = 82, /**< kmac_kmac_err */ - kTopDarjeelingPlicIrqIdOtbnDone = 83, /**< otbn_done */ + kTopDarjeelingPlicIrqIdAccDone = 77, /**< acc_done */ + kTopDarjeelingPlicIrqIdHmacHmacDone = 78, /**< hmac_hmac_done */ + kTopDarjeelingPlicIrqIdHmacFifoEmpty = 79, /**< hmac_fifo_empty */ + kTopDarjeelingPlicIrqIdHmacHmacErr = 80, /**< hmac_hmac_err */ + kTopDarjeelingPlicIrqIdKmacKmacDone = 81, /**< kmac_kmac_done */ + kTopDarjeelingPlicIrqIdKmacFifoEmpty = 82, /**< kmac_fifo_empty */ + kTopDarjeelingPlicIrqIdKmacKmacErr = 83, /**< kmac_kmac_err */ kTopDarjeelingPlicIrqIdKeymgrDpeOpDone = 84, /**< keymgr_dpe_op_done */ kTopDarjeelingPlicIrqIdCsrngCsCmdReqDone = 85, /**< csrng_cs_cmd_req_done */ kTopDarjeelingPlicIrqIdCsrngCsEntropyReq = 86, /**< csrng_cs_entropy_req */ @@ -1168,10 +1168,10 @@ typedef enum top_darjeeling_alert_peripheral { kTopDarjeelingAlertPeripheralSramCtrlRetAon = 15, /**< sram_ctrl_ret_aon */ kTopDarjeelingAlertPeripheralRvDm = 16, /**< rv_dm */ kTopDarjeelingAlertPeripheralRvPlic = 17, /**< rv_plic */ - kTopDarjeelingAlertPeripheralAes = 18, /**< aes */ - kTopDarjeelingAlertPeripheralHmac = 19, /**< hmac */ - kTopDarjeelingAlertPeripheralKmac = 20, /**< kmac */ - kTopDarjeelingAlertPeripheralOtbn = 21, /**< otbn */ + kTopDarjeelingAlertPeripheralAcc = 18, /**< acc */ + kTopDarjeelingAlertPeripheralAes = 19, /**< aes */ + kTopDarjeelingAlertPeripheralHmac = 20, /**< hmac */ + kTopDarjeelingAlertPeripheralKmac = 21, /**< kmac */ kTopDarjeelingAlertPeripheralKeymgrDpe = 22, /**< keymgr_dpe */ kTopDarjeelingAlertPeripheralCsrng = 23, /**< csrng */ kTopDarjeelingAlertPeripheralEntropySrc = 24, /**< entropy_src */ @@ -1231,13 +1231,13 @@ typedef enum top_darjeeling_alert_id { kTopDarjeelingAlertIdSramCtrlRetAonFatalError = 22, /**< sram_ctrl_ret_aon_fatal_error */ kTopDarjeelingAlertIdRvDmFatalFault = 23, /**< rv_dm_fatal_fault */ kTopDarjeelingAlertIdRvPlicFatalFault = 24, /**< rv_plic_fatal_fault */ - kTopDarjeelingAlertIdAesRecovCtrlUpdateErr = 25, /**< aes_recov_ctrl_update_err */ - kTopDarjeelingAlertIdAesFatalFault = 26, /**< aes_fatal_fault */ - kTopDarjeelingAlertIdHmacFatalFault = 27, /**< hmac_fatal_fault */ - kTopDarjeelingAlertIdKmacRecovOperationErr = 28, /**< kmac_recov_operation_err */ - kTopDarjeelingAlertIdKmacFatalFaultErr = 29, /**< kmac_fatal_fault_err */ - kTopDarjeelingAlertIdOtbnFatal = 30, /**< otbn_fatal */ - kTopDarjeelingAlertIdOtbnRecov = 31, /**< otbn_recov */ + kTopDarjeelingAlertIdAccFatal = 25, /**< acc_fatal */ + kTopDarjeelingAlertIdAccRecov = 26, /**< acc_recov */ + kTopDarjeelingAlertIdAesRecovCtrlUpdateErr = 27, /**< aes_recov_ctrl_update_err */ + kTopDarjeelingAlertIdAesFatalFault = 28, /**< aes_fatal_fault */ + kTopDarjeelingAlertIdHmacFatalFault = 29, /**< hmac_fatal_fault */ + kTopDarjeelingAlertIdKmacRecovOperationErr = 30, /**< kmac_recov_operation_err */ + kTopDarjeelingAlertIdKmacFatalFaultErr = 31, /**< kmac_fatal_fault_err */ kTopDarjeelingAlertIdKeymgrDpeRecovOperationErr = 32, /**< keymgr_dpe_recov_operation_err */ kTopDarjeelingAlertIdKeymgrDpeFatalFaultErr = 33, /**< keymgr_dpe_fatal_fault_err */ kTopDarjeelingAlertIdCsrngRecovAlert = 34, /**< csrng_recov_alert */ @@ -1515,10 +1515,10 @@ typedef enum top_darjeeling_gateable_clocks { * but the clock manager is in control of whether the clock actually is stopped. */ typedef enum top_darjeeling_hintable_clocks { - kTopDarjeelingHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */ - kTopDarjeelingHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */ - kTopDarjeelingHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */ - kTopDarjeelingHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */ + kTopDarjeelingHintableClocksMainAcc = 0, /**< Clock clk_main_acc in group trans */ + kTopDarjeelingHintableClocksMainAes = 1, /**< Clock clk_main_aes in group trans */ + kTopDarjeelingHintableClocksMainHmac = 2, /**< Clock clk_main_hmac in group trans */ + kTopDarjeelingHintableClocksMainKmac = 3, /**< Clock clk_main_kmac in group trans */ kTopDarjeelingHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */ } top_darjeeling_hintable_clocks_t; diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h index f9941c9aea7..c84a135ce9f 100644 --- a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h @@ -443,6 +443,23 @@ * `TOP_DARJEELING_RV_PLIC_BASE_ADDR + TOP_DARJEELING_RV_PLIC_SIZE_BYTES`. */ #define TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000 +/** + * Peripheral base address for acc in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ACC_BASE_ADDR 0x22100000 + +/** + * Peripheral size for acc in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ACC_BASE_ADDR and + * `TOP_DARJEELING_ACC_BASE_ADDR + TOP_DARJEELING_ACC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ACC_SIZE_BYTES 0x20000 /** * Peripheral base address for aes in top darjeeling. * @@ -494,23 +511,6 @@ * `TOP_DARJEELING_KMAC_BASE_ADDR + TOP_DARJEELING_KMAC_SIZE_BYTES`. */ #define TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000 -/** - * Peripheral base address for otbn in top darjeeling. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_DARJEELING_OTBN_BASE_ADDR 0x22100000 - -/** - * Peripheral size for otbn in top darjeeling. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_DARJEELING_OTBN_BASE_ADDR and - * `TOP_DARJEELING_OTBN_BASE_ADDR + TOP_DARJEELING_OTBN_SIZE_BYTES`. - */ -#define TOP_DARJEELING_OTBN_SIZE_BYTES 0x20000 /** * Peripheral base address for keymgr_dpe in top darjeeling. * diff --git a/hw/top_darjeeling/templates/chiplevel.sv.tpl b/hw/top_darjeeling/templates/chiplevel.sv.tpl index daf39b96537..d48e03e4cba 100644 --- a/hw/top_darjeeling/templates/chiplevel.sv.tpl +++ b/hw/top_darjeeling/templates/chiplevel.sv.tpl @@ -939,10 +939,10 @@ module chip_${top["name"]}_${target["name"]} #( .sram_ctrl_main_ram_1p_cfg_rsp_o ( ), .sram_ctrl_mbox_ram_1p_cfg_i ( ram_1p_cfg ), .sram_ctrl_mbox_ram_1p_cfg_rsp_o ( ), - .otbn_imem_ram_1p_cfg_i ( ram_1p_cfg ), - .otbn_imem_ram_1p_cfg_rsp_o ( ), - .otbn_dmem_ram_1p_cfg_i ( ram_1p_cfg ), - .otbn_dmem_ram_1p_cfg_rsp_o ( ), + .acc_imem_ram_1p_cfg_i ( ram_1p_cfg ), + .acc_imem_ram_1p_cfg_rsp_o ( ), + .acc_dmem_ram_1p_cfg_i ( ram_1p_cfg ), + .acc_dmem_ram_1p_cfg_rsp_o ( ), .rv_core_ibex_icache_tag_ram_1p_cfg_i ( ram_1p_cfg ), .rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o ( ), .rv_core_ibex_icache_data_ram_1p_cfg_i ( ram_1p_cfg ), diff --git a/hw/top_darjeeling/top_darjeeling.core b/hw/top_darjeeling/top_darjeeling.core index b5a58e4437c..d401ec1fd31 100644 --- a/hw/top_darjeeling/top_darjeeling.core +++ b/hw/top_darjeeling/top_darjeeling.core @@ -28,7 +28,7 @@ filesets: - lowrisc:ip:dma - lowrisc:ip:hmac - lowrisc:ip:kmac - - lowrisc:ip:otbn + - lowrisc:ip:acc - lowrisc:ip:otp_macro - lowrisc:prim:ram_1p_scr - lowrisc:ip:sram_ctrl diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl index 0d3b26324e2..50747b1f6e4 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl @@ -62,7 +62,7 @@ set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkm set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_aes_hint.q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_hmac_hint.q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_kmac_hint.q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} -set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_otbn_hint.q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} +set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_clkmgr_aon.u_reg.u_clk_hints_clk_main_acc_hint.q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][15:8]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.dout_locked_q[7:0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} diff --git a/hw/top_earlgrey/data/autogen/defs.bzl b/hw/top_earlgrey/data/autogen/defs.bzl index 7051a17da9e..48fcea0a919 100644 --- a/hw/top_earlgrey/data/autogen/defs.bzl +++ b/hw/top_earlgrey/data/autogen/defs.bzl @@ -7,6 +7,7 @@ # util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson # -o hw/top_earlgrey/ +load("//hw/ip/acc:defs.bzl", "ACC") load("//hw/ip/adc_ctrl:defs.bzl", "ADC_CTRL") load("//hw/ip/aes:defs.bzl", "AES") load("//hw/top_earlgrey/ip_autogen/alert_handler:defs.bzl", "ALERT_HANDLER") @@ -23,7 +24,6 @@ load("//hw/ip/i2c:defs.bzl", "I2C") load("//hw/ip/keymgr:defs.bzl", "KEYMGR") load("//hw/ip/kmac:defs.bzl", "KMAC") load("//hw/ip/lc_ctrl:defs.bzl", "LC_CTRL") -load("//hw/ip/otbn:defs.bzl", "OTBN") load("//hw/top_earlgrey/ip_autogen/otp_ctrl:defs.bzl", "OTP_CTRL") load("//hw/ip/otp_macro:defs.bzl", "OTP_MACRO") load("//hw/ip/pattgen:defs.bzl", "PATTGEN") @@ -45,6 +45,7 @@ load("//hw/ip/uart:defs.bzl", "UART") load("//hw/ip/usbdev:defs.bzl", "USBDEV") EARLGREY_IPS = [ + ACC, ADC_CTRL, AES, ALERT_HANDLER, @@ -61,7 +62,6 @@ EARLGREY_IPS = [ KEYMGR, KMAC, LC_CTRL, - OTBN, OTP_CTRL, OTP_MACRO, PATTGEN, @@ -126,13 +126,13 @@ EARLGREY_ALERTS = [ "flash_ctrl_recov_prim_flash_alert", "rv_dm_fatal_fault", "rv_plic_fatal_fault", + "acc_fatal", + "acc_recov", "aes_recov_ctrl_update_err", "aes_fatal_fault", "hmac_fatal_fault", "kmac_recov_operation_err", "kmac_fatal_fault_err", - "otbn_fatal", - "otbn_recov", "keymgr_recov_operation_err", "keymgr_fatal_fault_err", "csrng_recov_alert", diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 27bba06f212..b8fd734bdcc 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -112,10 +112,10 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } { @@ -609,7 +609,7 @@ aes hmac kmac - otbn + acc keymgr csrng entropy_src @@ -2056,9 +2056,9 @@ index: -1 } { - name: otbn_otp_key - desc: Key derivation interface for OTBN scrambling devices. - struct: otbn_otp_key + name: acc_otp_key + desc: Key derivation interface for ACC scrambling devices. + struct: acc_otp_key package: otp_ctrl_pkg type: req_rsp act: rsp @@ -2066,7 +2066,7 @@ default: "'0" inst_name: otp_ctrl end_idx: -1 - top_signame: otp_ctrl_otbn_otp_key + top_signame: otp_ctrl_acc_otp_key index: -1 } { @@ -6988,6 +6988,296 @@ "0" ] } + { + name: acc + type: acc + param_decl: + { + AccPQCEn: "0" + } + clock_srcs: + { + clk_i: + { + clock: main + group: trans + } + clk_edn_i: + { + clock: main + group: secure + } + clk_otp_i: + { + clock: io_div4 + group: secure + } + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_acc + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure + } + memory: {} + param_list: + [ + { + name: Stub + desc: Stub out the core of Acc logic + type: bit + default: "0" + local: "false" + expose: "true" + name_top: AccStub + } + { + name: RegFile + desc: Selection of the register file implementation. See acc_pkg.sv. + type: acc_pkg::regfile_e + default: acc_pkg::RegFileFF + local: "false" + expose: "true" + name_top: AccRegFile + } + { + name: SecMuteUrnd + desc: + ''' + If enabled (1), URND is advanced only when data is needed. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecAccMuteUrnd + } + { + name: SecSkipUrndReseedAtStart + desc: + ''' + If enabled (1), URND reseed is skipped at the start of an operation. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecAccSkipUrndReseedAtStart + } + { + name: AccPQCEn + desc: If enabled (1), vector ISA extension for PQC is enabled. + type: bit + default: "0" + local: "false" + expose: "true" + name_top: AccAccPQCEn + } + ] + inter_signal_list: + [ + { + name: acc_otp_key + struct: acc_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: acc + top_signame: otp_ctrl_acc_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn0_edn + index: 6 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: kmac_app + index: 3 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: acc + default: "" + top_signame: clkmgr_aon_idle + index: 0 + } + { + name: ram_cfg_imem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: acc + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: ram_cfg_dmem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: acc + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: ram_cfg_rsp_imem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: acc + index: -1 + } + { + name: ram_cfg_rsp_dmem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: acc + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_flash_rma_ack + index: 1 + } + { + name: keymgr_key + struct: acc_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: acc + default: "" + top_signame: keymgr_acc_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: acc + default: "" + end_idx: -1 + top_signame: acc_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x41300000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } { name: aes type: aes @@ -7108,7 +7398,7 @@ inst_name: aes default: "" top_signame: clkmgr_aon_idle - index: 0 + index: 1 } { name: lc_escalate_en @@ -7208,7 +7498,7 @@ inst_name: hmac default: "" top_signame: clkmgr_aon_idle - index: 1 + index: 2 } { name: tl @@ -7342,7 +7632,7 @@ ''' type: kmac_pkg::app_config_t unpacked_dimensions: "[KmacNumAppIntf]" - default: "'{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgOTBN}" + default: "'{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgACC}" local: "false" expose: "true" name_top: KmacAppCfg @@ -7408,322 +7698,32 @@ inst_name: kmac default: "" top_signame: clkmgr_aon_idle - index: 2 - } - { - name: en_masking - struct: logic - type: uni - act: req - width: 1 - inst_name: kmac - default: "" - package: "" - end_idx: -1 - top_type: broadcast - top_signame: kmac_en_masking - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: kmac - top_signame: lc_ctrl_lc_escalate_en - index: -1 - } - { - name: tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: kmac - default: "" - end_idx: -1 - top_signame: kmac_tl - index: -1 - } - ] - base_addrs: - { - null: - { - hart: 0x41120000 - } - } - generate_dif: true - domain: - [ - "0" - ] - } - { - name: otbn - type: otbn - param_decl: - { - OtbnPQCEn: "0" - } - clock_srcs: - { - clk_i: - { - clock: main - group: trans - } - clk_edn_i: - { - clock: main - group: secure - } - clk_otp_i: - { - clock: io_div4 - group: secure - } - } - clock_group: trans - reset_connections: - { - rst_ni: - { - name: lc - domain: "0" - } - rst_edn_ni: - { - name: lc - domain: "0" - } - rst_otp_ni: - { - name: lc_io_div4 - domain: "0" - } - } - clock_connections: - { - clk_i: clkmgr_aon_clocks.clk_main_otbn - clk_edn_i: clkmgr_aon_clocks.clk_main_secure - clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure - } - memory: {} - param_list: - [ - { - name: Stub - desc: Stub out the core of Otbn logic - type: bit - default: "0" - local: "false" - expose: "true" - name_top: OtbnStub - } - { - name: RegFile - desc: Selection of the register file implementation. See otbn_pkg.sv. - type: otbn_pkg::regfile_e - default: otbn_pkg::RegFileFF - local: "false" - expose: "true" - name_top: OtbnRegFile - } - { - name: SecMuteUrnd - desc: - ''' - If enabled (1), URND is advanced only when data is needed. - Disabled (0) by default. - Useful for SCA measurements only. - ''' - type: bit - default: "0" - local: "false" - expose: "true" - name_top: SecOtbnMuteUrnd - } - { - name: SecSkipUrndReseedAtStart - desc: - ''' - If enabled (1), URND reseed is skipped at the start of an operation. - Disabled (0) by default. - Useful for SCA measurements only. - ''' - type: bit - default: "0" - local: "false" - expose: "true" - name_top: SecOtbnSkipUrndReseedAtStart - } - { - name: OtbnPQCEn - desc: If enabled (1), vector ISA extension for PQC is enabled. - type: bit - default: "0" - local: "false" - expose: "true" - name_top: OtbnOtbnPQCEn - } - ] - inter_signal_list: - [ - { - name: otbn_otp_key - struct: otbn_otp_key - package: otp_ctrl_pkg - type: req_rsp - act: req - width: 1 - default: "'0" - inst_name: otbn - top_signame: otp_ctrl_otbn_otp_key - index: -1 - } - { - name: edn_rnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn1_edn - index: 0 - } - { - name: edn_urnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn0_edn - index: 6 - } - { - name: kmac_data - struct: app - package: kmac_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: kmac_app - index: 3 - } - { - name: idle - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: clkmgr_aon_idle - index: 3 - } - { - name: ram_cfg_imem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - top_signame: ast_ram_1p_cfg - index: -1 - } - { - name: ram_cfg_dmem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - top_signame: ast_ram_1p_cfg - index: -1 - } - { - name: ram_cfg_rsp_imem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - index: -1 - } - { - name: ram_cfg_rsp_dmem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_escalate_en - index: -1 + index: 3 } { - name: lc_rma_req - struct: lc_tx - package: lc_ctrl_pkg + name: en_masking + struct: logic type: uni - act: rcv + act: req width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_flash_rma_req + inst_name: kmac + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: kmac_en_masking index: -1 } { - name: lc_rma_ack + name: lc_escalate_en struct: lc_tx package: lc_ctrl_pkg type: uni - act: req - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_flash_rma_ack - index: 1 - } - { - name: keymgr_key - struct: otbn_key_req - package: keymgr_pkg - type: uni act: rcv width: 1 - inst_name: otbn - default: "" - top_signame: keymgr_otbn_key + default: lc_ctrl_pkg::Off + inst_name: kmac + top_signame: lc_ctrl_lc_escalate_en index: -1 } { @@ -7733,10 +7733,10 @@ type: req_rsp act: rsp width: 1 - inst_name: otbn + inst_name: kmac default: "" end_idx: -1 - top_signame: otbn_tl + top_signame: kmac_tl index: -1 } ] @@ -7744,7 +7744,7 @@ { null: { - hart: 0x41300000 + hart: 0x41120000 } } generate_dif: true @@ -7852,8 +7852,8 @@ index: -1 } { - name: otbn_key - struct: otbn_key_req + name: acc_key + struct: acc_key_req package: keymgr_pkg type: uni act: req @@ -7862,7 +7862,7 @@ default: "" end_idx: -1 top_type: broadcast - top_signame: keymgr_otbn_key + top_signame: keymgr_acc_key index: -1 } { @@ -9975,8 +9975,8 @@ ] ast.ram_1p_cfg: [ - otbn.ram_cfg_imem - otbn.ram_cfg_dmem + acc.ram_cfg_imem + acc.ram_cfg_dmem i2c0.ram_cfg i2c1.ram_cfg i2c2.ram_cfg @@ -10093,12 +10093,12 @@ lc_ctrl.lc_flash_rma_req: [ flash_ctrl.rma_req - otbn.lc_rma_req + acc.lc_rma_req ] lc_ctrl.lc_flash_rma_ack: [ flash_ctrl.rma_ack - otbn.lc_rma_ack + acc.lc_rma_ack ] usbdev.usb_dp_pullup: [ @@ -10140,16 +10140,16 @@ kmac.entropy alert_handler.edn aes.edn - otbn.edn_urnd + acc.edn_urnd rv_core_ibex.edn ] edn1.edn: [ - otbn.edn_rnd + acc.edn_rnd ] - otp_ctrl.otbn_otp_key: + otp_ctrl.acc_otp_key: [ - otbn.otbn_otp_key + acc.acc_otp_key ] otp_ctrl.otp_keymgr_key: [ @@ -10163,16 +10163,16 @@ [ kmac.keymgr_key ] - keymgr.otbn_key: + keymgr.acc_key: [ - otbn.keymgr_key + acc.keymgr_key ] kmac.app: [ keymgr.kmac_data lc_ctrl.kmac_data rom_ctrl.kmac_data - otbn.kmac_data + acc.kmac_data ] kmac.en_masking: [ @@ -10180,10 +10180,10 @@ ] clkmgr_aon.idle: [ + acc.idle aes.idle hmac.idle kmac.idle - otbn.idle ] pinmux_aon.lc_jtag: [ @@ -10259,7 +10259,7 @@ [ aes.lc_escalate_en kmac.lc_escalate_en - otbn.lc_escalate_en + acc.lc_escalate_en otp_ctrl.lc_escalate_en sram_ctrl_main.lc_escalate_en sram_ctrl_ret_aon.lc_escalate_en @@ -10444,9 +10444,9 @@ [ main.tl_rv_plic ] - otbn.tl: + acc.tl: [ - main.tl_otbn + main.tl_acc ] keymgr.tl: [ @@ -10728,7 +10728,7 @@ edn1 hmac rv_plic - otbn + acc keymgr kmac sram_ctrl_main.regs @@ -10755,7 +10755,7 @@ edn1 hmac rv_plic - otbn + acc keymgr kmac sram_ctrl_main.regs @@ -11229,13 +11229,13 @@ pipeline: true } { - name: otbn + name: acc type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: false rsp_fifo_pass: false - inst_type: otbn + inst_type: acc addr_range: [ { @@ -11615,7 +11615,7 @@ index: -1 } { - name: tl_otbn + name: tl_acc struct: tl package: tlul_pkg type: req_rsp @@ -11623,7 +11623,7 @@ inst_name: main width: 1 default: "" - top_signame: otbn_tl + top_signame: acc_tl index: -1 } { @@ -15792,6 +15792,28 @@ lpg_name: secure_lc_0 lpg_idx: 19 } + { + name: acc_fatal + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: acc + desc: acc fatal alert + lpg_name: acc_trans_lc_0 + lpg_idx: 20 + } + { + name: acc_recov + width: 1 + type: alert + async: "1" + handler: alert_handler + module_name: acc + desc: acc recov alert + lpg_name: acc_trans_lc_0 + lpg_idx: 20 + } { name: aes_recov_ctrl_update_err width: 1 @@ -15801,7 +15823,7 @@ module_name: aes desc: aes recov_ctrl_update_err alert lpg_name: aes_trans_lc_0 - lpg_idx: 20 + lpg_idx: 21 } { name: aes_fatal_fault @@ -15812,7 +15834,7 @@ module_name: aes desc: aes fatal_fault alert lpg_name: aes_trans_lc_0 - lpg_idx: 20 + lpg_idx: 21 } { name: hmac_fatal_fault @@ -15823,7 +15845,7 @@ module_name: hmac desc: hmac fatal_fault alert lpg_name: hmac_trans_lc_0 - lpg_idx: 21 + lpg_idx: 22 } { name: kmac_recov_operation_err @@ -15834,7 +15856,7 @@ module_name: kmac desc: kmac recov_operation_err alert lpg_name: kmac_trans_lc_0 - lpg_idx: 22 + lpg_idx: 23 } { name: kmac_fatal_fault_err @@ -15845,28 +15867,6 @@ module_name: kmac desc: kmac fatal_fault_err alert lpg_name: kmac_trans_lc_0 - lpg_idx: 22 - } - { - name: otbn_fatal - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: otbn - desc: otbn fatal alert - lpg_name: otbn_trans_lc_0 - lpg_idx: 23 - } - { - name: otbn_recov - width: 1 - type: alert - async: "1" - handler: alert_handler - module_name: otbn - desc: otbn recov alert - lpg_name: otbn_trans_lc_0 lpg_idx: 23 } { @@ -17657,6 +17657,18 @@ plic: rv_plic outgoing: false } + { + name: acc_done + width: 1 + type: interrupt + module_name: acc + desc: acc done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } { name: hmac_hmac_done width: 1 @@ -17729,18 +17741,6 @@ plic: rv_plic outgoing: false } - { - name: otbn_done - width: 1 - type: interrupt - module_name: otbn - desc: otbn done interrupt - intr_type: IntrType.Event - default_val: false - incoming: false - plic: rv_plic - outgoing: false - } { name: keymgr_op_done width: 1 @@ -17930,10 +17930,10 @@ flash_ctrl rv_dm rv_plic + acc aes hmac kmac - otbn keymgr csrng entropy_src @@ -18248,47 +18248,47 @@ alert_handler[41]: fatal_fault ] } - module_aes: + module_acc: { tx_expr: alert_tx[43:42] rx_expr: alert_rx[43:42] async_expr: alert_handler_reg_pkg::AsyncOn[43:42] comments: [ - alert_handler[42]: recov_ctrl_update_err - alert_handler[43]: fatal_fault + alert_handler[42]: fatal + alert_handler[43]: recov ] } - module_hmac: + module_aes: { - tx_expr: alert_tx[44:44] - rx_expr: alert_rx[44:44] - async_expr: alert_handler_reg_pkg::AsyncOn[44:44] + tx_expr: alert_tx[45:44] + rx_expr: alert_rx[45:44] + async_expr: alert_handler_reg_pkg::AsyncOn[45:44] comments: [ - alert_handler[44]: fatal_fault + alert_handler[44]: recov_ctrl_update_err + alert_handler[45]: fatal_fault ] } - module_kmac: + module_hmac: { - tx_expr: alert_tx[46:45] - rx_expr: alert_rx[46:45] - async_expr: alert_handler_reg_pkg::AsyncOn[46:45] + tx_expr: alert_tx[46:46] + rx_expr: alert_rx[46:46] + async_expr: alert_handler_reg_pkg::AsyncOn[46:46] comments: [ - alert_handler[45]: recov_operation_err - alert_handler[46]: fatal_fault_err + alert_handler[46]: fatal_fault ] } - module_otbn: + module_kmac: { tx_expr: alert_tx[48:47] rx_expr: alert_rx[48:47] async_expr: alert_handler_reg_pkg::AsyncOn[48:47] comments: [ - alert_handler[47]: fatal - alert_handler[48]: recov + alert_handler[47]: recov_operation_err + alert_handler[48]: fatal_fault_err ] } module_keymgr: @@ -18404,9 +18404,9 @@ aon_timer_aon sensor_ctrl_aon flash_ctrl + acc hmac kmac - otbn keymgr csrng entropy_src @@ -18928,7 +18928,7 @@ } } { - name: aes_trans_lc_0 + name: acc_trans_lc_0 clock_group: { name: trans @@ -18937,13 +18937,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_aes + clock_connection: clkmgr_aon_clocks.clk_main_acc unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -18953,7 +18953,7 @@ } } { - name: hmac_trans_lc_0 + name: aes_trans_lc_0 clock_group: { name: trans @@ -18962,13 +18962,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_hmac + clock_connection: clkmgr_aon_clocks.clk_main_aes unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -18978,7 +18978,7 @@ } } { - name: kmac_trans_lc_0 + name: hmac_trans_lc_0 clock_group: { name: trans @@ -18987,13 +18987,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_kmac + clock_connection: clkmgr_aon_clocks.clk_main_hmac unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -19003,7 +19003,7 @@ } } { - name: otbn_trans_lc_0 + name: kmac_trans_lc_0 clock_group: { name: trans @@ -19012,13 +19012,13 @@ unique: yes clocks: { + clk_main_acc: main clk_main_aes: main clk_main_hmac: main clk_main_kmac: main - clk_main_otbn: main } } - clock_connection: clkmgr_aon_clocks.clk_main_otbn + clock_connection: clkmgr_aon_clocks.clk_main_kmac unmanaged_clock: false unmanaged_reset: false reset_connection: @@ -19910,9 +19910,9 @@ index: -1 } { - name: otbn_otp_key - desc: Key derivation interface for OTBN scrambling devices. - struct: otbn_otp_key + name: acc_otp_key + desc: Key derivation interface for ACC scrambling devices. + struct: acc_otp_key package: otp_ctrl_pkg type: req_rsp act: rsp @@ -19920,7 +19920,7 @@ default: "'0" inst_name: otp_ctrl end_idx: -1 - top_signame: otp_ctrl_otbn_otp_key + top_signame: otp_ctrl_acc_otp_key index: -1 } { @@ -23128,92 +23128,257 @@ type: uni act: req width: 1 - inst_name: rv_dm - index: -1 + inst_name: rv_dm + index: -1 + } + { + name: sba_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_dm + default: "" + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: mem_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_mem_tl_d + index: -1 + } + { + name: dbg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + index: -1 + } + { + name: irq + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_irq + index: -1 + } + { + name: irq_id + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + index: -1 + } + { + name: msip + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_msip + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_plic + default: "" + end_idx: -1 + top_signame: rv_plic_tl + index: -1 + } + { + name: acc_otp_key + struct: acc_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: acc + top_signame: otp_ctrl_acc_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: edn0_edn + index: 6 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: acc + default: "" + top_signame: kmac_app + index: 3 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: acc + default: "" + top_signame: clkmgr_aon_idle + index: 0 } { - name: sba_tl_h - struct: tl - package: tlul_pkg - type: req_rsp - act: req + name: ram_cfg_imem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv width: 1 - inst_name: rv_dm + inst_name: acc default: "" - top_signame: main_tl_rv_dm__sba + top_signame: ast_ram_1p_cfg index: -1 } { - name: regs_tl_d - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp + name: ram_cfg_dmem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv width: 1 - inst_name: rv_dm + inst_name: acc default: "" - end_idx: -1 - top_signame: rv_dm_regs_tl_d + top_signame: ast_ram_1p_cfg index: -1 } { - name: mem_tl_d - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp + name: ram_cfg_rsp_imem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req width: 1 - inst_name: rv_dm - default: "" - end_idx: -1 - top_signame: rv_dm_mem_tl_d + inst_name: acc index: -1 } { - name: dbg_tl_d - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp + name: ram_cfg_rsp_dmem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req width: 1 - inst_name: rv_dm + inst_name: acc index: -1 } { - name: irq - struct: logic + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg type: uni - act: req + act: rcv width: 1 - inst_name: rv_plic - default: "" - package: "" - end_idx: -1 - top_type: broadcast - top_signame: rv_plic_irq + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_escalate_en index: -1 } { - name: irq_id - struct: logic + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg type: uni - act: req + act: rcv width: 1 - inst_name: rv_plic + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_flash_rma_req index: -1 } { - name: msip - struct: logic + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg type: uni act: req width: 1 - inst_name: rv_plic + default: lc_ctrl_pkg::Off + inst_name: acc + top_signame: lc_ctrl_lc_flash_rma_ack + index: 1 + } + { + name: keymgr_key + struct: acc_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: acc default: "" - package: "" - end_idx: -1 - top_type: broadcast - top_signame: rv_plic_msip + top_signame: keymgr_acc_key index: -1 } { @@ -23223,10 +23388,10 @@ type: req_rsp act: rsp width: 1 - inst_name: rv_plic + inst_name: acc default: "" end_idx: -1 - top_signame: rv_plic_tl + top_signame: acc_tl index: -1 } { @@ -23239,7 +23404,7 @@ inst_name: aes default: "" top_signame: clkmgr_aon_idle - index: 0 + index: 1 } { name: lc_escalate_en @@ -23300,7 +23465,7 @@ inst_name: hmac default: "" top_signame: clkmgr_aon_idle - index: 1 + index: 2 } { name: tl @@ -23373,7 +23538,7 @@ inst_name: kmac default: "" top_signame: clkmgr_aon_idle - index: 2 + index: 3 } { name: en_masking @@ -23414,171 +23579,6 @@ top_signame: kmac_tl index: -1 } - { - name: otbn_otp_key - struct: otbn_otp_key - package: otp_ctrl_pkg - type: req_rsp - act: req - width: 1 - default: "'0" - inst_name: otbn - top_signame: otp_ctrl_otbn_otp_key - index: -1 - } - { - name: edn_rnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn1_edn - index: 0 - } - { - name: edn_urnd - struct: edn - package: edn_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: edn0_edn - index: 6 - } - { - name: kmac_data - struct: app - package: kmac_pkg - type: req_rsp - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: kmac_app - index: 3 - } - { - name: idle - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: req - width: 1 - inst_name: otbn - default: "" - top_signame: clkmgr_aon_idle - index: 3 - } - { - name: ram_cfg_imem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - top_signame: ast_ram_1p_cfg - index: -1 - } - { - name: ram_cfg_dmem - struct: ram_1p_cfg - package: prim_ram_1p_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - top_signame: ast_ram_1p_cfg - index: -1 - } - { - name: ram_cfg_rsp_imem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - index: -1 - } - { - name: ram_cfg_rsp_dmem - struct: ram_1p_cfg_rsp - package: prim_ram_1p_pkg - type: uni - act: req - width: 1 - inst_name: otbn - index: -1 - } - { - name: lc_escalate_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_escalate_en - index: -1 - } - { - name: lc_rma_req - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_flash_rma_req - index: -1 - } - { - name: lc_rma_ack - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: req - width: 1 - default: lc_ctrl_pkg::Off - inst_name: otbn - top_signame: lc_ctrl_lc_flash_rma_ack - index: 1 - } - { - name: keymgr_key - struct: otbn_key_req - package: keymgr_pkg - type: uni - act: rcv - width: 1 - inst_name: otbn - default: "" - top_signame: keymgr_otbn_key - index: -1 - } - { - name: tl - struct: tl - package: tlul_pkg - type: req_rsp - act: rsp - width: 1 - inst_name: otbn - default: "" - end_idx: -1 - top_signame: otbn_tl - index: -1 - } { name: edn struct: edn @@ -23620,8 +23620,8 @@ index: -1 } { - name: otbn_key - struct: otbn_key_req + name: acc_key + struct: acc_key_req package: keymgr_pkg type: uni act: req @@ -23630,7 +23630,7 @@ default: "" end_idx: -1 top_type: broadcast - top_signame: keymgr_otbn_key + top_signame: keymgr_acc_key index: -1 } { @@ -24984,7 +24984,7 @@ index: -1 } { - name: tl_otbn + name: tl_acc struct: tl package: tlul_pkg type: req_rsp @@ -24992,7 +24992,7 @@ inst_name: main width: 1 default: "" - top_signame: otbn_tl + top_signame: acc_tl index: -1 } { @@ -26767,8 +26767,8 @@ } { package: otp_ctrl_pkg - struct: otbn_otp_key_req - signame: otp_ctrl_otbn_otp_key_req + struct: acc_otp_key_req + signame: otp_ctrl_acc_otp_key_req width: 1 type: req_rsp end_idx: -1 @@ -26778,8 +26778,8 @@ } { package: otp_ctrl_pkg - struct: otbn_otp_key_rsp - signame: otp_ctrl_otbn_otp_key_rsp + struct: acc_otp_key_rsp + signame: otp_ctrl_acc_otp_key_rsp width: 1 type: req_rsp end_idx: -1 @@ -26822,14 +26822,14 @@ } { package: keymgr_pkg - struct: otbn_key_req - signame: keymgr_otbn_key + struct: acc_key_req + signame: keymgr_acc_key width: 1 type: uni end_idx: -1 act: req suffix: "" - default: keymgr_pkg::OTBN_KEY_REQ_DEFAULT + default: keymgr_pkg::ACC_KEY_REQ_DEFAULT } { package: kmac_pkg @@ -27844,7 +27844,7 @@ { package: tlul_pkg struct: tl_h2d - signame: otbn_tl_req + signame: acc_tl_req width: 1 type: req_rsp end_idx: -1 @@ -27855,7 +27855,7 @@ { package: tlul_pkg struct: tl_d2h - signame: otbn_tl_rsp + signame: acc_tl_rsp width: 1 type: req_rsp end_idx: -1 diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson index f61915664a3..dfd8da7fe71 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson @@ -47,7 +47,7 @@ randcount: 40 randtype: data name_top: RndCnstOtpCtrlLfsrSeed - default: 0x7a29b920b7 + default: 0xab60da8b65 randwidth: 40 } { @@ -57,7 +57,7 @@ randcount: 40 randtype: perm name_top: RndCnstOtpCtrlLfsrPerm - default: 0x8a8477c06204249c615c65b9834cd59131552388e25e74168b1085d23e5 + default: 0x3d30e520d90c6040015098de85c15268a98b1d788255141d3995a07c69db randwidth: 240 } { @@ -67,7 +67,7 @@ randcount: 256 randtype: data name_top: RndCnstOtpCtrlScrmblKeyInit - default: 0x51bf1196b12e5259bded90261100c8ccc2b1be4599775614975d3d2b32e933d8 + default: 0xe933d88e2e1cf65460f23fb780499e6fcce64ceafd282c0e33fd2c07986c2a51 randwidth: 256 } { @@ -2885,7 +2885,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivInvalid - default: 0x8e2e1cf65460f23fb780499e6fcce64c + default: 0x1755f072ee7a8e2fc45e111df07fa067 randwidth: 128 } { @@ -2895,7 +2895,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivTestUnlocked - default: 0xeafd282c0e33fd2c07986c2a511755f0 + default: 0xf64056d9bf30d48543bec2e9a075d7d5 randwidth: 128 } { @@ -2905,7 +2905,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivDev - default: 0x72ee7a8e2fc45e111df07fa067f64056 + default: 0x36d6f82505255ea0645554dd5f9355f5 randwidth: 128 } { @@ -2915,7 +2915,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivProduction - default: 0xd9bf30d48543bec2e9a075d7d536d6f8 + default: 0xa89085a95a12ab13e0ec9ccd04512f5c randwidth: 128 } { @@ -2925,7 +2925,7 @@ randcount: 128 randtype: data name_top: RndCnstLcCtrlLcKeymgrDivRma - default: 0x2505255ea0645554dd5f9355f5a89085 + default: 0x1d8958ef421d22bb77013624b5a4bff randwidth: 128 } { @@ -2935,7 +2935,7 @@ randcount: 1024 randtype: data name_top: RndCnstLcCtrlInvalidTokens - default: 0xa95a12ab13e0ec9ccd04512f5c01d8958ef421d22bb77013624b5a4bff0bdd4dd6b30b717aa80ff777a157878a468d23eecbd09de6b8f9faeaf1a70e57e8eda03a353b76a2f833509acc7b3aa3fa7dac233e2b782306af306a1f36165ee14a00ee9ff9382af33b479718558e6759764645aad1fb21c18124635e3d50a88f6808 + default: 0xbdd4dd6b30b717aa80ff777a157878a468d23eecbd09de6b8f9faeaf1a70e57e8eda03a353b76a2f833509acc7b3aa3fa7dac233e2b782306af306a1f36165ee14a00ee9ff9382af33b479718558e6759764645aad1fb21c18124635e3d50a88f6808045627ac18f377d9071beca6f194ef96f3e535b58f2adad82b175fe9ea randwidth: 1024 } ] @@ -2960,7 +2960,7 @@ randcount: 32 randtype: data name_top: RndCnstAlertHandlerLfsrSeed - default: 0x45627ac + default: 0x1c326a66 randwidth: 32 } { @@ -2970,7 +2970,7 @@ randcount: 32 randtype: perm name_top: RndCnstAlertHandlerLfsrPerm - default: 0xe5ea97aa68690ec0f6d0d2c592c4d8953e0dbbc3 + default: 0x1a9e9284fe911733700dec6d0dea95be58877f02 randwidth: 160 } ] @@ -3011,7 +3011,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetAonSramKey - default: 0x478c14db070a6129bb2945b88dc6cfcf + default: 0xb666a5e22d3320f89caa47e5ced5d29c randwidth: 128 } { @@ -3021,7 +3021,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlRetAonSramNonce - default: 0x2ae02f47010cb666a5e22d3320f89caa + default: 0xc9cdb468773ebacec14da34c505aedc7 randwidth: 128 } { @@ -3031,7 +3031,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlRetAonLfsrSeed - default: 0x47e5ced5d29cc9cd + default: 0xea184c7a34193d5 randwidth: 64 } { @@ -3041,7 +3041,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlRetAonLfsrPerm - default: 0xf9e548a4cec7e41d7c5d84891a02ac34e1519a2f6311f64296bc9bbc0fcbdaad1c9e443a8770f1594e284f0cee3dd6ad + default: 0x65e836cd53e143ab2b32e192468c7f3b85e960877709f97404de54f1ac0a8a61ed245135f838dbec0ca4aaf2d3f56727 randwidth: 384 } ] @@ -3095,7 +3095,7 @@ randcount: 128 randtype: data name_top: RndCnstFlashCtrlAddrKey - default: 0xce1cf9e2029207396945c95c9b54bae6 + default: 0xa63a8e6604338151b9a23c08f9eed04c randwidth: 128 } { @@ -3105,7 +3105,7 @@ randcount: 128 randtype: data name_top: RndCnstFlashCtrlDataKey - default: 0xaef30d8577834ccc6caaa63a8e660433 + default: 0xa1ebb0bdd305ffb6c4818054e0e0edb0 randwidth: 128 } { @@ -3115,7 +3115,7 @@ randcount: 512 randtype: data name_top: RndCnstFlashCtrlAllSeeds - default: 0x8151b9a23c08f9eed04ca1ebb0bdd305ffb6c4818054e0e0edb0acd0b040fc629ea7f8b17fa88fee02e3f0864223a2e23a8cc31e2de5e578d43d2dce49e360cf + default: 0xacd0b040fc629ea7f8b17fa88fee02e3f0864223a2e23a8cc31e2de5e578d43d2dce49e360cfb594acddf170684f6ead2b7febfe895523d7bc4846a485956c7f randwidth: 512 } { @@ -3125,7 +3125,7 @@ randcount: 32 randtype: data name_top: RndCnstFlashCtrlLfsrSeed - default: 0xb594acdd + default: 0x904b9ede randwidth: 32 } { @@ -3135,12 +3135,57 @@ randcount: 32 randtype: perm name_top: RndCnstFlashCtrlLfsrPerm - default: 0x6041f31d621e6d3bcb54c6e08e1151796bd4b5de + default: 0xfe2aeb5f2259647e011d0c3cf191896eccaa467a randwidth: 160 } ] template_type: flash_ctrl } + { + name: acc + type: acc + base_addrs: + { + null: + { + hart: 0x41300000 + } + } + memory: {} + param_list: + [ + { + name: RndCnstUrndPrngSeed + desc: Default seed of the PRNG used for URND. + type: acc_pkg::urnd_prng_seed_t + randcount: 256 + randtype: data + name_top: RndCnstAccUrndPrngSeed + default: 0xb87118af11cdbe78d67060615a20b9c0740f07969ccd2d10a1a6e7988fa528ac + randwidth: 256 + } + { + name: RndCnstAccKey + desc: Compile-time random reset value for IMem/DMem scrambling key. + type: otp_ctrl_pkg::acc_key_t + randcount: 128 + randtype: data + name_top: RndCnstAccAccKey + default: 0x32e0a6138cb8316ff95c65cd7a1a768 + randwidth: 128 + } + { + name: RndCnstAccNonce + desc: Compile-time random reset value for IMem/DMem scrambling nonce. + type: otp_ctrl_pkg::acc_nonce_t + randcount: 64 + randtype: data + name_top: RndCnstAccAccNonce + default: 0xb06e0106d60eda0f + randwidth: 64 + } + ] + } { name: aes type: aes @@ -3161,7 +3206,7 @@ randcount: 64 randtype: data name_top: RndCnstAesClearingLfsrSeed - default: 0xecb11ce3b87aaa7a + default: 0x1bc67adf85bd9a56 randwidth: 64 } { @@ -3171,7 +3216,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingLfsrPerm - default: 0xf9b3702f842ec6a2a527f8d71cceb40278b2b5a5391594d2043b085a662bd44d9c768f5fa4f477573ede3bc8060a486f + default: 0x625a41fed1b9d54496922d13359ce0bc8297a213cb9fec1ee3b41ddc31f1cbd6df440bbc25c3b6985b2b5446aa3230ba randwidth: 384 } { @@ -3181,7 +3226,7 @@ randcount: 64 randtype: perm name_top: RndCnstAesClearingSharePerm - default: 0x7a2601d37a75920c161b15104b3fe79573cbefe2b63594c87680c7b6ee5b7d103825c3b2f45b2bf046aa3230ba566be1 + default: 0x4af431780ad6db89798cb5ce21d3fffada4cb9b34ac28261eaaf7b4e20b2066f077f7d44554634911b337190da1859e0 randwidth: 384 } { @@ -3191,7 +3236,7 @@ randcount: 288 randtype: data name_top: RndCnstAesMaskingLfsrSeed - default: 0x819d1518690e6473cdb2479391635057ca1045b9e1917e1ff0189b04a4f7fba960fe098a + default: 0x5041a1b896350c9636d6814d23e2f5ff1275ef19959aaa8b6a004d5574984ded1cc79bd randwidth: 288 } { @@ -3201,7 +3246,7 @@ randcount: 160 randtype: perm name_top: RndCnstAesMaskingLfsrPerm - default: 0x7648238f2a754d9f8a9a718d530925186e6b7b5857981c7259687826807d013b3846459084076c2e0b86883d7a9406653f515f3a820c70839173205d39672d223749606d305a4a61032110291e8135624e277f16854000978b871232157911521d638c335e3c9242242b6a02505b96552c4c74132f9d1f9b0a34997e642831449c1a040593770f41476f3e5c43087c198914668e569e540d4b360e951b17694f + default: 0x412893d8b73114b3646052e795f7845815b8c1523951c0726566c4c637b7d517f4a7a7e331a6250168d8a315d14642b0e85492f5e481382301d7701550296090a1f03389a6a392d6f943f343e524d4391753290861029478497749b0f4f190d179d5c1e6e9258930c767c8e617041086d1871590b28274069729c5a4437548f3b986024209f064221533c356b9e4e882c5780001b998325652a68223a668767 randwidth: 1280 } ] @@ -3226,7 +3271,7 @@ randcount: 288 randtype: data name_top: RndCnstKmacLfsrSeed - default: 0x42a75ecc25d4e2267e3bff26e003aacbf7d513aea01e9ee420d5b523f6b00c81bded728 + default: 0xcd252956ba81616362b27eafb903ec79bddf0a4f7dff07db05de63910e4ee4d8a2c7d402 randwidth: 288 } { @@ -3236,7 +3281,7 @@ randcount: 800 randtype: perm name_top: RndCnstKmacLfsrPerm - default: 0xc3c6781e219715ab852397d520f0e8b631018cf2820b961c9770864a931806b0360d2ca9a57ae13350545a202849a8689e1457d7fbb4fb8b48d2cd4a69228229a17c1a34657590a67315dc9224f12ec78599692f061c59e7bed59e700b329bc571e711ce0d12b1266a6e2e7bd2be422b4801a68fc9e3ce80aec4a446603d499a371b9608b7941b98dee01e4a4005603b1d3b0b760a3183473acf08be46d6dc6566ce57fc875523a291d61566e1d1db65dcdb116cb51e8a89c7261ec9c9c185647b5aa8be93aba1f3075100dca9501feb82b2b746154d13bf5b91320c7c8c14629a5ba616746cac1293da52594164c870a0d6d4802d0c2ada71d2b01e6add02a84795de22b388c8d05d959738142a165e34363752c326ee1ca064c2ae996a0efa4d8c8f1b0448681e80c6f2324294e34a6faf2eb9f571456da3359f06496a942534cb29896a222cda753c054278e0832b116b4ac987d1b3fc6e86d059d0bf570d0411bd6951c537110ccf950ae63911f4e0b1a1dea1ff126fe9f7782f1f5b53a9e9321f841ab19662e93466146bf4bdd4424be8a675bfe4e9a44f275564f4daab1f572f054d43d5f4c6a54141d8af2f58b96e82c353943824510a0729d7868cfb2c8e31e6da242c80d31119253c6aa540b8a6278bf006bd404898915f81e55567bfa91c251abc86a74eef8f55bc3054360a2365e055da03e04e63dc3b44f79dd8d205222693e82e3315f1c6412e1ca5e6b05a805593708038a2b0892864cfe082117f040b4ca7924c94d9af9f0895d0849026b5917b5d9842d4a3c293b7ae4516c137c43f7602b624ae58921656df351ae107074a812344dd7749227297287191f9da11613b213017e96828d7721cfa427e78444b6563046aba3efbb0a513b97a0c5378a83e33a352b50738714bc51d602de76401788a62180d0602179ecfb5d465c87885d171f143216843f5a23305c64a02646ee94008841ba919036619aa9d7c5ae306adbe355d5b284737e9e581346d0f4546b67b61e1a4ed42e8a36c77742ae9ecc26da412d2db7243677f1a9501c008c00015eae94f4b5c5810605e30e30ed083abd32e68135adb1636a1625865819ff178ec09c0af6672656a4ba8262f8e6dc7ec100e96f7471f31158b945e3a4ca5a46f35a6c12052990425a0e06ca245310c38df65268e0e1277e5c603c9b14c82975f4ba5cc586a35211e9e89f10ee2861aabb0a8450950285039c26c12f3b0cb6abd0f6202e8f947ad5fdc06f89c4bb0d62c1ad24a81942aa1d23e44a52a91d40b88e5396ac190d3f6c6b95c1c083da7c2e55a32922c0fc9cd0157403818589d894c4d99188f03ea709983b24cbca2c3963b1607df70a6f7b91fa62985ba8a5880e6b8d86bc1796cc2305cde848eb7907b01566b1890 + default: 0x39b0b1d7ec6423a3de08898652a0b1958c22d4d0a9cb5960d4cdacb751898e75c1975b22b087c347207ac4b1a396ed230307bf1771ef4b69544eabf81d13989ec5de60760d7918b78c6f321d232650d066b14092065d71258f554e3a70ee1872991b4974e23272a6d1ccee8b43c501a69301a095cd2a60058ea4b992a7e870885dd272a8856c9126aa6f4564589e8ba8ab0ce61ee4984a3d45510aeab819ef91b0320a2b65ccc1b120aa78ec6754bb6e5f54a514f0cd66c68b5e9dc512b18ee3779f7a718757c166fed81769fa562905d4e692b486ac2104d2505193eece1c5f85ba275b4f66de0878d0095d262af07a12dfa94743a1a55fe6a6824b42845261f2c456ab525b377002928b8add350aad8a80cbd7037507931512285a8850ef076e50dcf2936bb5e9452e508b426b1869a9e71d76e421f84c685c280e786e1322345f6582d129fc73a7cc32fd3ce80164647cc552cd5c62d29b58eb0a44b34cb2a36f7222ec24b025681509e4e444832b2abafa59b2a963fc6e96105bda0c5f4d04111bc26ae4716c784333e6ebadce447d564b0b1b2dcfa4c7f9bec6c6dee3442f1f5da3aa283201141acfa0aff59866146de4bd83424be8f290c7e35a0c4f276134f70f36982112b37c5ea4d43d678c6ac8141d8af2f6857ae74bf8a58150e80544281f0ba24f33eea238c774aa60b2d24c446494f19b9502e1d77069701b15011b52459f0795559f1e6f287ab29146a1b1aac0c3afc56ef8150d8288d904957710f81398f7a27b3df0a634814889a4fad1c724815c056412e1ca77a89b916a16564dc200e2902114a1933f82089acd102f229de5325366be98bb974212567fd645ed76611e62d4a36293b4c23316c137d43f7f82b624ae58921656e03528191c2468dbbbc1399863475a372281b2fc076ba8822422949e9770314de3f0f8ce914ad41ce16cf1047580c35d9005e22988603418085e79a65c519721e21745c7c50c85bc4fd688cc1719280991af686022106ea5e40d9866ac55f16b8c2386adbe355d5ba44737ebc581346d250928f4546d57b61e1a4ed42ea736c77742cc9f8c26da412d2fa726670d9df79254070023000057ad953d2d7160418178880c3bbe0e9cadc32e7d9a04d6b6e48dae7896196069b37a3b0258ec599c9967f6a4ba8262f8e6fb7ec100e96f744903128956304178e9329691bcd69b04814a6410968382a16ca245310c38df65268e0e1277e5c603c9b14c82975f4c21cc586a35211e9e89f10f01861aab4f0b2a1142540a140e70981fc4ee22daaf43d880ba3e51eb57f439c62712ec358b06b492a0650aa8748f91294aa47502e2394e5ab06434fdb1ae5707020f69d859568ca48b03f2734055d00f05818589d8945e599188f03ea709983b24cbc randwidth: 8000 } { @@ -3246,7 +3291,7 @@ randcount: 800 randtype: data name_top: RndCnstKmacBufferLfsrSeed - default: 0xa9aaca4db84a32e5c6985a1a6435118b5f5f3fd3b9313116b67192d856dd742d40e072e417ad9a5f261204cbcc69a2147819b290a4bb0264347c0f91b0cec93c0129d85b95801dbe03f17e69dc260a79998eff5c710b67838adfb99a5eca671672cf19bc + default: 0xb67838adfb99a5eca671672cf19bca6adc1ebfab611f19e7262e0a491970e51b28e7026d0e5dce9e265a416a812231cfa76e3d982f8fdcec9ae1af0b8cd9e17606ec981060e94795a1d573089578c104a36a647e90ffaff9760f5e838bd8e2413ab956b randwidth: 800 } { @@ -3256,56 +3301,11 @@ randcount: 64 randtype: perm name_top: RndCnstKmacMsgPerm - default: 0xe4d3967ccc7d4325616a64ef7a88ae097ed1d4accb3d2040d1bdfe1a074723ca85d992788ec503964fd872712deb0ae9 + default: 0x728ad40862dde22812c09c8c7804d81f1f50917bead2e6adee3f27225d4db21591cdf0ce1763d9ebe2b7579066fe96c4 randwidth: 384 } ] } - { - name: otbn - type: otbn - base_addrs: - { - null: - { - hart: 0x41300000 - } - } - memory: {} - param_list: - [ - { - name: RndCnstUrndPrngSeed - desc: Default seed of the PRNG used for URND. - type: otbn_pkg::urnd_prng_seed_t - randcount: 256 - randtype: data - name_top: RndCnstOtbnUrndPrngSeed - default: 0x9a07effee457dee82b6e06663c291739ff0e7d644758fee1c58564cf346d9622 - randwidth: 256 - } - { - name: RndCnstOtbnKey - desc: Compile-time random reset value for IMem/DMem scrambling key. - type: otp_ctrl_pkg::otbn_key_t - randcount: 128 - randtype: data - name_top: RndCnstOtbnOtbnKey - default: 0xe5371091366efbd61b0cb470b944ef80 - randwidth: 128 - } - { - name: RndCnstOtbnNonce - desc: Compile-time random reset value for IMem/DMem scrambling nonce. - type: otp_ctrl_pkg::otbn_nonce_t - randcount: 64 - randtype: data - name_top: RndCnstOtbnOtbnNonce - default: 0x6e573b44b643ebf0 - randwidth: 64 - } - ] - } { name: keymgr type: keymgr @@ -3326,7 +3326,7 @@ randcount: 64 randtype: data name_top: RndCnstKeymgrLfsrSeed - default: 0xc5de019fc073c4c5 + default: 0x32fcc4d3092bd638 randwidth: 64 } { @@ -3336,7 +3336,7 @@ randcount: 64 randtype: perm name_top: RndCnstKeymgrLfsrPerm - default: 0x6c3c15db9ae5852658a4859dffab075d306ade3cf569f020e2d172baf9c610b7b4a0f38a08c24dfb1efd710464f22526 + default: 0x89362c32395757bbbdb4747ee20e7c0df76bc699f759091a348caa080cd26d905c87f16627038ad4610beb4bde528d8f randwidth: 384 } { @@ -3346,7 +3346,7 @@ randcount: 32 randtype: perm name_top: RndCnstKeymgrRandPerm - default: 0x74c7fe918685399b1c3e88a58055a5d2ee97ed0a + default: 0xa9333d8587160c945d4d7497cd7a25053f6ebc70 randwidth: 160 } { @@ -3356,7 +3356,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrRevisionSeed - default: 0xadcdfc5c5f76d4a8e259d88dfe9b670aa0dd992bfe5d2e12489d22504aa7ac1c + default: 0x504aa7ac1c67f59cba5482c1e35e6e3335c20cc778fc309917b9c870abe0895d randwidth: 256 } { @@ -3366,7 +3366,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrCreatorIdentitySeed - default: 0x67f59cba5482c1e35e6e3335c20cc778fc309917b9c870abe0895d76f862ef81 + default: 0x76f862ef81f419e3c6cdc8662c71eac141666e443c6492d9bcf7a82420750e5d randwidth: 256 } { @@ -3376,7 +3376,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOwnerIntIdentitySeed - default: 0xf419e3c6cdc8662c71eac141666e443c6492d9bcf7a82420750e5dfc5e3ed4f2 + default: 0xfc5e3ed4f2907532e179ebec7ed7d3a5ef4982f73ed91c4b1cd0c85ec5e548b4 randwidth: 256 } { @@ -3386,7 +3386,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrOwnerIdentitySeed - default: 0x907532e179ebec7ed7d3a5ef4982f73ed91c4b1cd0c85ec5e548b40184a69eb1 + default: 0x184a69eb1e54396460e36c55c459efe9e43836fe878e464337ebcae3238dcdf randwidth: 256 } { @@ -3396,7 +3396,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrSoftOutputSeed - default: 0xe54396460e36c55c459efe9e43836fe878e464337ebcae3238dcdf7de88b56b4 + default: 0x7de88b56b405e02bbfd73849c511f7f0b79f91dcd1d589b4cac4372c385f89d9 randwidth: 256 } { @@ -3406,7 +3406,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrHardOutputSeed - default: 0x5e02bbfd73849c511f7f0b79f91dcd1d589b4cac4372c385f89d902019dabb6 + default: 0x2019dabb6dd57022c77ede8609c409d905b3c7819b26a674328819928c5d79b randwidth: 256 } { @@ -3416,7 +3416,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrAesSeed - default: 0xdd57022c77ede8609c409d905b3c7819b26a674328819928c5d79bf1db63d11e + default: 0xf1db63d11e1c31bbc9a8c73fc4cc3d14ca6bc0b96812de7c775a54ff19343cb3 randwidth: 256 } { @@ -3426,17 +3426,17 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrKmacSeed - default: 0x1c31bbc9a8c73fc4cc3d14ca6bc0b96812de7c775a54ff19343cb32040b34907 + default: 0x2040b3490768889d27e0ba8588d34c05bcf127dae58b65d6a251088099b37107 randwidth: 256 } { - name: RndCnstOtbnSeed - desc: Compile-time random bits for generation seed when otbn destination selected + name: RndCnstAccSeed + desc: Compile-time random bits for generation seed when acc destination selected type: keymgr_pkg::seed_t randcount: 256 randtype: data - name_top: RndCnstKeymgrOtbnSeed - default: 0x68889d27e0ba8588d34c05bcf127dae58b65d6a251088099b37107b1cccf1a95 + name_top: RndCnstKeymgrAccSeed + default: 0xb1cccf1a955f03de1a8447bf83b69c50e149cf51784a9d7ac691306e5c56ce38 randwidth: 256 } { @@ -3446,7 +3446,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrCdi - default: 0x5f03de1a8447bf83b69c50e149cf51784a9d7ac691306e5c56ce38cd7d7e3b1a + default: 0xcd7d7e3b1abfb7978189a21ae856f1d908e3f70de343d2226e9e864465a8ee55 randwidth: 256 } { @@ -3456,7 +3456,7 @@ randcount: 256 randtype: data name_top: RndCnstKeymgrNoneSeed - default: 0xbfb7978189a21ae856f1d908e3f70de343d2226e9e864465a8ee55ec0e6a2967 + default: 0xec0e6a296789ded5c0af59ee62f1fd1bbebeac2205b1fa5e94e72eb7eb1a713a randwidth: 256 } ] @@ -3481,7 +3481,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivNonProduction - default: 0x89ded5c0af59ee62f1fd1bbebeac2205b1fa5e94e72eb7eb1a713ad15d2565d9ab4fbcd2e17c406f48d1401f8a6a5228 + default: 0xd15d2565d9ab4fbcd2e17c406f48d1401f8a6a52286f6954c27a9aefbe0bc9ee440c514ccacb019995f31fa958859293 randwidth: 384 } { @@ -3491,7 +3491,7 @@ randcount: 384 randtype: data name_top: RndCnstCsrngCsKeymgrDivProduction - default: 0x6f6954c27a9aefbe0bc9ee440c514ccacb019995f31fa958859293c5591ae604a92a303760eb8d7785a7bbdce1d6a02b + default: 0xc5591ae604a92a303760eb8d7785a7bbdce1d6a02b6f0f24f5db8ef02f9fb0a4023d8f96a41f062bb66b228701e8317c randwidth: 384 } ] @@ -3531,7 +3531,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramKey - default: 0x6f0f24f5db8ef02f9fb0a4023d8f96a4 + default: 0xd4bf08bd6684a1d596cc57e137a0321f randwidth: 128 } { @@ -3541,7 +3541,7 @@ randcount: 128 randtype: data name_top: RndCnstSramCtrlMainSramNonce - default: 0x1f062bb66b228701e8317cd4bf08bd66 + default: 0xb803bfd2de7a90a1357e743ce460442c randwidth: 128 } { @@ -3551,7 +3551,7 @@ randcount: 64 randtype: data name_top: RndCnstSramCtrlMainLfsrSeed - default: 0x84a1d596cc57e137 + default: 0x10686e82613de080 randwidth: 64 } { @@ -3561,7 +3561,7 @@ randcount: 64 randtype: perm name_top: RndCnstSramCtrlMainLfsrPerm - default: 0x876e107192350a20ca4cec975a5195512f01efaf8916c9ad9f38e9e7daeac7081b6842d160f75f37f91edf4bc0b87328 + default: 0x77fe01b8ff706a327247b85cd92433c55b26967f2f17e78650ad03a5911738caada24582022e532f52207fa62b347ddb randwidth: 384 } ] @@ -3601,7 +3601,7 @@ randcount: 64 randtype: data name_top: RndCnstRomCtrlScrNonce - default: 0xbef1f0b924c470ac + default: 0x5f4ea1e463032a3a randwidth: 64 } { @@ -3611,7 +3611,7 @@ randcount: 128 randtype: data name_top: RndCnstRomCtrlScrKey - default: 0x5a99809985dc415ba1eaced382d54c9e + default: 0x8e24b4547f8b0db0c77e902776b104c3 randwidth: 128 } ] @@ -3636,7 +3636,7 @@ randcount: 32 randtype: data name_top: RndCnstRvCoreIbexLfsrSeed - default: 0x378d030e + default: 0xa9da0203 randwidth: 32 } { @@ -3646,7 +3646,7 @@ randcount: 32 randtype: perm name_top: RndCnstRvCoreIbexLfsrPerm - default: 0xd55033fa315db644a7824765cf3e9580fe63b54 + default: 0xfc2dbe9af10a1e24e3ca634b99c86bab8fcd5080 randwidth: 160 } { @@ -3656,7 +3656,7 @@ randcount: 128 randtype: data name_top: RndCnstRvCoreIbexIbexKeyDefault - default: 0xa4d3d73871fdaf5ad0c1dd1e95f99d71 + default: 0x91c2bd316277126ea6934d3749740a7c randwidth: 128 } { @@ -3666,7 +3666,7 @@ randcount: 64 randtype: data name_top: RndCnstRvCoreIbexIbexNonceDefault - default: 0x29ca6861a4425b9c + default: 0xe7c92a49f71747d5 randwidth: 64 } ] diff --git a/hw/top_earlgrey/data/chip_conn_testplan.hjson b/hw/top_earlgrey/data/chip_conn_testplan.hjson index dffde0384d3..8fa7ec5e680 100644 --- a/hw/top_earlgrey/data/chip_conn_testplan.hjson +++ b/hw/top_earlgrey/data/chip_conn_testplan.hjson @@ -178,8 +178,8 @@ name: ast_dft_ram_1p_cfg desc: '''Verify ast model's single port configuration bits are connected to the single port RAMs in the following blocks: - - otbn_imem - - otbn_dmem + - acc_imem + - acc_dmem - rv_core_ibex_tag0 - rv_core_ibex_tag1 - rv_core_ibex_data0 @@ -189,8 +189,8 @@ - rom ''' stage: V2 - tests: ["ast_dft_otbn_imem_ram_1p_cfg", - "ast_dft_otbn_dmem_ram_1p_cfg", + tests: ["ast_dft_acc_imem_ram_1p_cfg", + "ast_dft_acc_dmem_ram_1p_cfg", "ast_dft_rv_core_ibex_tag0_ram_1p_cfg", "ast_dft_rv_core_ibex_tag1_ram_1p_cfg", "ast_dft_rv_core_ibex_data0_ram_1p_cfg", @@ -370,7 +370,7 @@ - index 0 to aes's `idle_o` - index 1 to hmac's `idle_o` - index 2 to kmac's `idle_o` - - index 3 to otbn's `idle_o` + - index 3 to acc's `idle_o` ''' stage: V2 tests: ["clkmgr_idle0", "clkmgr_idle1", "clkmgr_idle2", "clkmgr_idle3"] @@ -622,7 +622,7 @@ input: - alert_handler clk_i - lc_ctrl clk_i - - otbn clk_otp_i + - acc clk_otp_i - otp_ctrl clk_i - pwrmgr clk_lc_i - rv_core_ibex clk_esc_i @@ -632,7 +632,7 @@ stage: V2 tests: ["clkmgr_secure_clk_alert_handler_clk", "clkmgr_secure_clk_lc_ctrl_clk", - "clkmgr_secure_clk_otbn_otp_clk", + "clkmgr_secure_clk_acc_otp_clk", "clkmgr_secure_clk_otp_ctrl_clk", "clkmgr_secure_clk_rv_core_ibex_clk", "clkmgr_secure_clk_rv_core_ibex_otp_clk", @@ -651,7 +651,7 @@ - keymgr clk_i - keymgr clk_edn_i - lc_ctrl clk_kmac_i - - otbn clk_edn_i + - acc clk_edn_i - otp_ctrl clk_edn_i - rv_plic clk_i ''' @@ -664,7 +664,7 @@ "clkmgr_secure_clk_keymgr_clk", "clkmgr_secure_clk_keymgr_edn_clk", "clkmgr_secure_clk_lc_ctrl_kmac_clk", - "clkmgr_secure_clk_otbn_edn_clk", + "clkmgr_secure_clk_acc_edn_clk", "clkmgr_secure_clk_otp_ctrl_edn_clk", "clkmgr_secure_clk_rv_plic_clk"] si_stage: NA @@ -736,10 +736,10 @@ tags: ["conn"] } { - name: clk_main_otbn - desc: '''Verify clkmgr's clk_main_otbn is connected to otbn's clk_i.''' + name: clk_main_acc + desc: '''Verify clkmgr's clk_main_acc is connected to acc's clk_i.''' stage: V2 - tests: ["clkmgr_trans_otbn"] + tests: ["clkmgr_trans_acc"] si_stage: NA tags: ["conn"] } @@ -810,7 +810,7 @@ - flash_ctrl - aes - kmac - - otbn + - acc ''' stage: V2 tests: ["lc_escalate_en_otp", @@ -820,7 +820,7 @@ "lc_escalate_en_flash", "lc_escalate_en_aes", "lc_escalate_en_kmac", - "lc_escalate_en_otbn"] + "lc_escalate_en_acc"] si_stage: NA tags: ["conn"] } @@ -874,13 +874,13 @@ tags: ["conn"] } { - name: lc_flash_otbn_rma + name: lc_flash_acc_rma desc: "Verify lc_ctrl's RMA request connections." stage: V2 tests: ["lc_rma_seed_flash_ctrl", "lc_rma_req_flash_ctrl", - "flash_ctrl_rma_ack_otbn", - "otbn_rma_ack_lc"] + "flash_ctrl_rma_ack_acc", + "acc_rma_ack_lc"] si_stage: NA tags: ["conn"] } @@ -1028,7 +1028,7 @@ desc: '''Verify rstmgr's rst_lc_io_div4_n[1] is connected to the following: - alert_handler's rst_ni - lc_ctrl's rst_ni - - otbn's rst_otp_ni + - acc's rst_otp_ni - otp_ctrl's rst_ni - pwrmgr's rst_lc_ni - rv_core_ibex's rst_esc_ni @@ -1038,7 +1038,7 @@ stage: V2 tests: ["rstmgr_lc_io_div4_d0_alert_handler_rst_ni", "rstmgr_lc_io_div4_d0_lc_ctrl_rst_ni", - "rstmgr_lc_io_div4_d0_otbn_rst_otp_ni", + "rstmgr_lc_io_div4_d0_acc_rst_otp_ni", "rstmgr_lc_io_div4_d0_otp_ctrl_rst_ni", "rstmgr_lc_io_div4_d0_rv_core_ibex_rst_esc_ni", "rstmgr_lc_io_div4_d0_rv_core_ibex_rst_otp_ni", @@ -1268,8 +1268,8 @@ - keymgr's rst_ni - kmac's rst_edn_ni - kmac's rst_ni - - otbn's rst_edn_ni - - otbn's rst_ni + - acc's rst_edn_ni + - acc's rst_ni - lc_ctrl's rst_kmac_ni - otp_ctrl's rst_edn_ni - rv_core_ibex's rst_edn_ni @@ -1292,8 +1292,8 @@ "rstmgr_sys_d0_keymgr_rst_ni", "rstmgr_sys_d0_kmac_rst_edn_ni", "rstmgr_sys_d0_kmac_rst_ni", - "rstmgr_sys_d0_otbn_rst_edn_ni", - "rstmgr_sys_d0_otbn_rst_ni", + "rstmgr_sys_d0_acc_rst_edn_ni", + "rstmgr_sys_d0_acc_rst_ni", "rstmgr_sys_d0_lc_ctrl_rst_kmac_ni", "rstmgr_sys_d0_otp_ctrl_rst_edn_ni", "rstmgr_sys_d0_rv_core_ibex_rst_edn_ni", diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson index bac667f447f..76d6e87a9b0 100644 --- a/hw/top_earlgrey/data/chip_testplan.hjson +++ b/hw/top_earlgrey/data/chip_testplan.hjson @@ -37,7 +37,7 @@ "hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson", "hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson", "hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson", - "hw/top_earlgrey/data/ip/chip_otbn_testplan.hjson", + "hw/top_earlgrey/data/ip/chip_acc_testplan.hjson", "hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson", "hw/top_earlgrey/data/ip/chip_pwm_testplan.hjson", "hw/top_earlgrey/data/ip/chip_pwrmgr_testplan.hjson", @@ -397,7 +397,7 @@ tests: ["chip_sw_clkmgr_jitter", "chip_sw_flash_ctrl_ops_jitter_en", "chip_sw_flash_ctrl_access_jitter_en", - "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_acc_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", "chip_sw_keymgr_key_derivation_jitter_en", @@ -516,7 +516,7 @@ "chip_sw_gpio_smoketest", "chip_sw_hmac_smoketest", "chip_sw_kmac_smoketest", - "chip_sw_otbn_smoketest", + "chip_sw_acc_smoketest", "chip_sw_pwrmgr_smoketest", "chip_sw_pwrmgr_usbdev_smoketest", "chip_sw_rv_plic_smoketest", @@ -535,7 +535,7 @@ "//sw/device/tests:gpio_smoketest", "//sw/device/tests:hmac_smoketest", "//sw/device/tests:kmac_smoketest", - "//sw/device/tests:otbn_smoketest", + "//sw/device/tests:acc_smoketest", "//sw/device/tests:pmp_smoketest_napot", "//sw/device/tests:pmp_smoketest_tor", "//sw/device/tests:pwrmgr_smoketest", @@ -626,7 +626,7 @@ RAW_UNLOCK mode of operation. - Switch TAP interface to rv_dm and configure the ROM_EXEC_EN OTP to enable ROM execution. - - If running with the production ROM, enable signature verification via OTBN to + - If running with the production ROM, enable signature verification via ACC to improve simulation time. - Perform POR to apply OTP changes. - With rv_dm TAP still selected, switch to external clock via clkmgr using extclk @@ -657,11 +657,11 @@ Blocks / functionality to run simultaneously in this test: - The ADC is continuously sampling new data - - Staggered activation of OTBN, aes, KMAC/HMAC. + - Staggered activation of ACC, aes, KMAC/HMAC. - KMAC / aes would need to take turns being fed data - KMAC activation should be a combination of otp background, key manager background and software - - for OTBN, any signature verification / signing event is sufficient + - for ACC, any signature verification / signing event is sufficient - Entropy complex ongoing - reseed / update operation ongoing - Flash scramble ongoing (ideally both instruction and data, but data should be sufficient diff --git a/hw/top_earlgrey/data/ip/chip_acc_testplan.hjson b/hw/top_earlgrey/data/ip/chip_acc_testplan.hjson new file mode 100644 index 00000000000..359e1fcf611 --- /dev/null +++ b/hw/top_earlgrey/data/ip/chip_acc_testplan.hjson @@ -0,0 +1,165 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: acc + testpoints: [ + { + name: chip_sw_acc_isa + desc: '''Run every ACC instruction and check final state. + + Utilizing the existing ACC smoke test which uses every instruction + (hw/ip/acc/dv/smoke/smoke_test.s). Check the final register state matches the + expected values (in hw/ip/acc/dv/smoke/smoke_expected.txt). Check ACC completed + successfully without errors. This will require a modified version of the smoke test + which dumps register state to memory. + + Following the smoke test run a new program just to dump out the register state to + dmem, check the values do not match the previous values from the smoke test run to + ensure the internal state secure wipe has worked. + ''' + stage: V2 + si_stage: SV3 + tests: [] + bazel: ["//sw/device/tests:acc_isa_test"] + lc_states: ["PROD"] + features: [ + "ACC.ISA", + "ACC.SECUREWIPE" + ] + } + { + name: chip_sw_acc_op + desc: '''Verify an ACC operation. + + - SW test directs the ACC engine to perform an ECDSA operation. + - SW validates the reception of the acc done interrupt once the operation is complete. + - SW verifies the correctness of the result with the expected value which is + pre-computed using a reference model. + ''' + stage: V2 + si_stage: SV3 + tests: ["chip_sw_acc_ecdsa_op_irq", + "chip_sw_acc_ecdsa_op_irq_jitter_en"] + bazel: [ + "//sw/device/tests:acc_ecdsa_op_irq_test", + "//sw/device/tests:acc_irq_test", + "//sw/device/tests:acc_rsa_test", + "//sw/device/tests:acc_smoketest" + ] + lc_states: ["PROD"] + features: [ + "ACC.ISA" + ] + } + { + name: chip_sw_acc_rnd_entropy + desc: '''Verify ACC can fetch RND numbers from the entropy src. + + - SW initializes the entropy subsystem to generate randomness. + - SW loads an ACC app that executes instructions to read the RND bits. + - The ACC app ensures that the values when read consecutively do not match, and that no + value is all 0s or all 1s, as a basic measure to ensure that the entropy subsystem is + returning some data. + ''' + stage: V2 + si_stage: SV3 + tests: ["chip_sw_acc_randomness"] + bazel: ["//sw/device/tests:acc_randomness_test"] + lc_states: ["PROD"] + features: [ + "ACC.RANDOM" + ] + } + { + name: chip_sw_acc_urnd_entropy + desc: '''Verify ACC can fetch URND numbers from the entropy src. + + - Similar to chip_acc_rnd_entropy, but verifies the URND bits. + ''' + stage: V2 + si_stage: SV3 + tests: ["chip_sw_acc_randomness"] + bazel: ["//sw/device/tests:acc_randomness_test"] + lc_states: ["PROD"] + features: [ + "ACC.RANDOM" + ] + } + { + name: chip_sw_acc_idle + desc: '''Verify the ACC idle signal to clkmgr. + + - Write the ACC clk hint to 0 within clkmgr to indicate ACC clk can be gated + and verify that the ACC clk hint status within clkmgr reads 0 (ACC is disabled). + - Write the ACC clk hint to 1 within clkmgr to indicate ACC clk can be enabled. + Verify that the ACC clk hint status within clkmgr reads 1 (ACC is enabled). + - Start an ACC operation, write the ACC clk hint to 0 within clkmgr and verify that + the ACC clk hint status within clkmgr reads 1 (ACC is enabled) before the + ACC operation is complete. + - After the ACC operation is complete, verify that the ACC clk hint status within + clkmgr now reads 0 again (ACC is disabled). + - Write the ACC clk hint to 1, read and check the ACC output for correctness. + ''' + stage: V2 + si_stage: SV3 + tests: ["chip_sw_acc_randomness"] + bazel: ["//sw/device/tests:acc_randomness_test"] + lc_states: ["PROD"] + features: [] + } + { + name: chip_sw_acc_mem_scramble + desc: '''Verify the ACC can receive keys from the OTP to scramble the ACC imem and dmem. + + - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already + done by the test_rom startup code). + - Extract random address offsets from RV_CORE_IBEX_RND_DATA. + - Wait for ACC to be idle. + - Write random address offsets in ACC imem and dmem. + - Read back the written address offsets and compare against expected values. All values + must match, no integrity errors must be triggered. + - Have ACC fetch new keys and nonces from the OTP_CTRL. + - Wait for ACC to be idle. + - Read back the written address offsets. Most reads should trigger integrity errors. It + is possible that after re-scrambling the integrity bits are still valid. But this is + expected to happen rarely. If the number of observed integrity errors is below a + chosen threshold, the test fails. + - Verify the validity of EDN's output to OTP_CTRL via assertions + (unique, non-zero data). + ''' + stage: V2 + si_stage: SV3 + tests: ["chip_sw_acc_mem_scramble"] + bazel: ["//sw/device/tests:acc_mem_scramble_test"] + lc_states: ["PROD"] + features: [ + "ACC.MEM_SCRAMBLE", + "ACC.SECUREWIPE" + ] + } + { + name: chip_sw_acc_keymgr + desc: '''Check the ACC keymgr connection is functional. + + Setup the keymgr and any other blocks required to provide ACC with a valid sideload + key. Run an ACC program to read the key via the KEY_S[0|1]_[H|L] WSRs and write it to + dmem. Sanity check the returned value (e.g. != 0) and check ACC completed successfully + with no errors. + ''' + stage: V2 + si_stage: SV2 + tests: [] + bazel: [ + "//sw/device/tests:keymgr_sideload_acc_simple_test", + "//sw/device/tests/crypto:ecdh_p256_sideload_functest", + "//sw/device/tests/crypto:ecdsa_p256_sideload_functest", + "//sw/device/tests:keymgr_sideload_acc_test" + ] + lc_states: ["PROD"] + features: [ + "ACC.KEYMGR", + ] + } + ] +} diff --git a/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson b/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson index a9ce2989d22..76dcc07e85d 100644 --- a/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson @@ -23,19 +23,19 @@ "CLKMGR.HINT.AES", "CLKMGR.HINT.HMAC", "CLKMGR.HINT.KMAC", - "CLKMGR.HINT.OTBN", + "CLKMGR.HINT.ACC", ] tests: [ "chip_sw_aes_idle", "chip_sw_hmac_enc_idle", "chip_sw_kmac_idle", - "chip_sw_otbn_randomness", + "chip_sw_acc_randomness", ] bazel: [ "//sw/device/tests:aes_idle_test", "//sw/device/tests:hmac_enc_idle_test", "//sw/device/tests:kmac_idle_test", - "//sw/device/tests:otbn_randomness_test", + "//sw/device/tests:acc_randomness_test", ] } { @@ -57,19 +57,19 @@ "CLKMGR.HINT.AES", "CLKMGR.HINT.HMAC", "CLKMGR.HINT.KMAC", - "CLKMGR.HINT.OTBN", + "CLKMGR.HINT.ACC", ] tests: [ "chip_sw_clkmgr_off_aes_trans", "chip_sw_clkmgr_off_hmac_trans", "chip_sw_clkmgr_off_kmac_trans", - "chip_sw_clkmgr_off_otbn_trans", + "chip_sw_clkmgr_off_acc_trans", ] bazel: [ "//sw/device/tests:clkmgr_off_aes_trans_test", "//sw/device/tests:clkmgr_off_hmac_trans_test", "//sw/device/tests:clkmgr_off_kmac_trans_test", - "//sw/device/tests:clkmgr_off_otbn_trans_test", + "//sw/device/tests:clkmgr_off_acc_trans_test", ] } { @@ -200,7 +200,7 @@ "chip_sw_clkmgr_jitter", "chip_sw_flash_ctrl_ops_jitter_en", "chip_sw_flash_ctrl_access_jitter_en", - "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_acc_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", "chip_sw_keymgr_key_derivation_jitter_en", @@ -262,7 +262,7 @@ - flash_ctrl initialization - flash_ctrl program, read and erase operations - - AES, HMAC, KMAC and OTBN operations + - AES, HMAC, KMAC and ACC operations - Keymgr key derivation - Scramble-enabled access from the main SRAM - Csrng edn concurrency @@ -276,7 +276,7 @@ "chip_sw_clkmgr_jitter_reduced_freq", "chip_sw_flash_ctrl_ops_jitter_en_reduced_freq", "chip_sw_flash_ctrl_access_jitter_en_reduced_freq", - "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq", + "chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq", "chip_sw_aes_enc_jitter_en_reduced_freq", "chip_sw_hmac_enc_jitter_en_reduced_freq", "chip_sw_keymgr_key_derivation_jitter_en_reduced_freq", diff --git a/hw/top_earlgrey/data/ip/chip_csrng_testplan.hjson b/hw/top_earlgrey/data/ip/chip_csrng_testplan.hjson index 646b38dda5e..a654d41c4d8 100644 --- a/hw/top_earlgrey/data/ip/chip_csrng_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_csrng_testplan.hjson @@ -11,12 +11,12 @@ - Have each EDN instance issue an instantiate, reseed and generate command to CSRNG. - On each command done, verify the reception of edn_cmd_req_done interrupt. - - Run OTBN randomness test to test the output from EDN0 and EDN1. + - Run ACC randomness test to test the output from EDN0 and EDN1. - Check the data returned to EDN via connectivity assertion checks. Notes for silicon targets: - In silicon, the connectivity cannot be checked using assertions. - However, checking that the OTBN randomness test finishes allows to quickly assess if both EDNs deliver any entropy which is very fundamental. + However, checking that the ACC randomness test finishes allows to quickly assess if both EDNs deliver any entropy which is very fundamental. ''' features: [ "CSRNG.INTERFACE.HARDWARE0", diff --git a/hw/top_earlgrey/data/ip/chip_edn_testplan.hjson b/hw/top_earlgrey/data/ip/chip_edn_testplan.hjson index 4fc809909fa..baf140be9ab 100644 --- a/hw/top_earlgrey/data/ip/chip_edn_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_edn_testplan.hjson @@ -35,30 +35,30 @@ - Disable the entropy complex. - Enable ENTROPY_SRC in boot-time mode, e.g., by setting CONF.FIPS_ENABLE to kMultiBitBool4False. - Enable CSRNG. - - Enable EDN1 (the one connected to OTBN RND) in boot-time request mode. + - Enable EDN1 (the one connected to ACC RND) in boot-time request mode. - Disable ENTROPY_SRC. - - Since EDN1 provides entropy only to the OTBN, CSRNG will be idle. + - Since EDN1 provides entropy only to the ACC, CSRNG will be idle. - Enable ENTROPY_SRC in FIPS mode. - - Enable EDN0 (the one connected to OTBN URND and other endpoints) in auto request mode. - - Launch an OTBN program consuming entropy via both the RND and the URND interface. - - Verify that the OTBN program completes (entropy available) and that OTBN sets ERR_BITS.RND_FIPS_CHK_FAIL to indicate the reception of non-FIPS/CC-compliant entropy over the RND interface. + - Enable EDN0 (the one connected to ACC URND and other endpoints) in auto request mode. + - Launch an ACC program consuming entropy via both the RND and the URND interface. + - Verify that the ACC program completes (entropy available) and that ACC sets ERR_BITS.RND_FIPS_CHK_FAIL to indicate the reception of non-FIPS/CC-compliant entropy over the RND interface. - Consume entropy through rv_core_ibex.RND_DATA and verify, using rv_core_ibex.RND_STATUS, that the received bits are FIPS compliant. - Disable the entropy complex. - Enable ENTROPY_SRC in FIPS mode. - Enable CSRNG. - - Enable EDN1 (the one connected to OTBN RND) in auto request mode. + - Enable EDN1 (the one connected to ACC RND) in auto request mode. - Disable ENTROPY_SRC. - Enable ENTROPY_SRC in boot-time mode. - - Enable EDN0 (the one connected to OTBN URND and other endpoints) in boot-time request mode. - - Launch an OTBN program consuming entropy via both the RND and the URND interface. - - Verify that the OTBN program completes (entropy available) and that OTBN does not set ERR_BITS.RND_FIPS_CHK_FAIL. + - Enable EDN0 (the one connected to ACC URND and other endpoints) in boot-time request mode. + - Launch an ACC program consuming entropy via both the RND and the URND interface. + - Verify that the ACC program completes (entropy available) and that ACC does not set ERR_BITS.RND_FIPS_CHK_FAIL. - Consume entropy through rv_core_ibex.RND_DATA and verify, using rv_core_ibex.RND_STATUS, that the received bits are FIPS NON-compliant. - Disable the entropy complex. - Enable ENTROPY_SRC in FIPS mode. - Enable CSRNG. - Enable EDN1 and EDN0 in auto request mode and with non-deterministic seeds (flag0 = kMultiBitBool4False for Instantiate and Reseed commands). - - Re-launch the OTBN program. - - Verify that the OTBN program completes (entropy available) and that OTBN does not set ERR_BITS.RND_FIPS_CHK_FAIL. + - Re-launch the ACC program. + - Verify that the ACC program completes (entropy available) and that ACC does not set ERR_BITS.RND_FIPS_CHK_FAIL. - Consume entropy through rv_core_ibex.RND_DATA and verify, using rv_core_ibex.RND_STATUS, that the received bits are FIPS compliant. ''' features: [ diff --git a/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson b/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson index 50a642f6ffc..8f217e7cc1b 100644 --- a/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson @@ -120,8 +120,8 @@ - Enable both EDNs in boot-time request mode. - Trigger the execution of a cryptographic hardware block consuming entropy (e.g. AES) to test EDN0. - Verify the entropy consuming endpoint finishes its operation. - - Trigger the execution of an OTBN program requiring entropy from both EDN1 and EDN0. - - Verify the OTBN program hangs. + - Trigger the execution of an ACC program requiring entropy from both EDN1 and EDN0. + - Verify the ACC program hangs. - Disable the entropy complex. - Configure unrealistically stringent health test threshold values for boot-time / bypass mode. - Configure an alert threshold value of 1 in the ALERT_THRESHOLD register. diff --git a/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson b/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson index 6ca9d1b9240..6d205778daf 100644 --- a/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson @@ -121,19 +121,19 @@ ] } { - name: chip_sw_keymgr_sideload_otbn - desc: '''Verify the keymgr sideload interface to OTBN. + name: chip_sw_keymgr_sideload_acc + desc: '''Verify the keymgr sideload interface to ACC. - Load OTBN binary image, the rest is similar to `chip_keymgr_sideload_kmac`, except - sideloading to otbn. + Load ACC binary image, the rest is similar to `chip_keymgr_sideload_kmac`, except + sideloading to acc. Clear the sideload key once done. ''' - features: ["KEYMGR.SIDELOAD.OTBN"] + features: ["KEYMGR.SIDELOAD.ACC"] stage: V2 si_stage: SV3 lc_states: ["PROD"] - tests: ["chip_sw_keymgr_sideload_otbn"] + tests: ["chip_sw_keymgr_sideload_acc"] bazel: [ "//sw/device/tests/crypto:ecdh_p256_sideload_functest", "//sw/device/tests/crypto:ecdsa_p256_sideload_functest", @@ -147,7 +147,7 @@ - For each keymgr operational state: `CreatorRootKey`, `OwnerIntKey` and `OwnerKey`: - Generate identity SW output for the Attestation CDI. - - Generate OTBN sideload output for the Attestation CDI. + - Generate ACC sideload output for the Attestation CDI. - Ensure that the key output changes after calculating the previous steps after a keymgr advance operation. - The keymgr shall be able to reproduce the same keys for a give device configuration @@ -176,7 +176,7 @@ tests: ["chip_sw_keymgr_derive_attestation"] bazel: [ // Covers all points in the test except for the software binding registers. - "//sw/device/silicon_creator/lib:otbn_boot_services_functest", + "//sw/device/silicon_creator/lib:acc_boot_services_functest", "//sw/device/tests:keymgr_derive_attestation_test", ] } diff --git a/hw/top_earlgrey/data/ip/chip_otbn_testplan.hjson b/hw/top_earlgrey/data/ip/chip_otbn_testplan.hjson deleted file mode 100644 index 764eb5d7989..00000000000 --- a/hw/top_earlgrey/data/ip/chip_otbn_testplan.hjson +++ /dev/null @@ -1,165 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - name: otbn - testpoints: [ - { - name: chip_sw_otbn_isa - desc: '''Run every OTBN instruction and check final state. - - Utilizing the existing OTBN smoke test which uses every instruction - (hw/ip/otbn/dv/smoke/smoke_test.s). Check the final register state matches the - expected values (in hw/ip/otbn/dv/smoke/smoke_expected.txt). Check OTBN completed - successfully without errors. This will require a modified version of the smoke test - which dumps register state to memory. - - Following the smoke test run a new program just to dump out the register state to - dmem, check the values do not match the previous values from the smoke test run to - ensure the internal state secure wipe has worked. - ''' - stage: V2 - si_stage: SV3 - tests: [] - bazel: ["//sw/device/tests:otbn_isa_test"] - lc_states: ["PROD"] - features: [ - "OTBN.ISA", - "OTBN.SECUREWIPE" - ] - } - { - name: chip_sw_otbn_op - desc: '''Verify an OTBN operation. - - - SW test directs the OTBN engine to perform an ECDSA operation. - - SW validates the reception of the otbn done interrupt once the operation is complete. - - SW verifies the correctness of the result with the expected value which is - pre-computed using a reference model. - ''' - stage: V2 - si_stage: SV3 - tests: ["chip_sw_otbn_ecdsa_op_irq", - "chip_sw_otbn_ecdsa_op_irq_jitter_en"] - bazel: [ - "//sw/device/tests:otbn_ecdsa_op_irq_test", - "//sw/device/tests:otbn_irq_test", - "//sw/device/tests:otbn_rsa_test", - "//sw/device/tests:otbn_smoketest" - ] - lc_states: ["PROD"] - features: [ - "OTBN.ISA" - ] - } - { - name: chip_sw_otbn_rnd_entropy - desc: '''Verify OTBN can fetch RND numbers from the entropy src. - - - SW initializes the entropy subsystem to generate randomness. - - SW loads an OTBN app that executes instructions to read the RND bits. - - The OTBN app ensures that the values when read consecutively do not match, and that no - value is all 0s or all 1s, as a basic measure to ensure that the entropy subsystem is - returning some data. - ''' - stage: V2 - si_stage: SV3 - tests: ["chip_sw_otbn_randomness"] - bazel: ["//sw/device/tests:otbn_randomness_test"] - lc_states: ["PROD"] - features: [ - "OTBN.RANDOM" - ] - } - { - name: chip_sw_otbn_urnd_entropy - desc: '''Verify OTBN can fetch URND numbers from the entropy src. - - - Similar to chip_otbn_rnd_entropy, but verifies the URND bits. - ''' - stage: V2 - si_stage: SV3 - tests: ["chip_sw_otbn_randomness"] - bazel: ["//sw/device/tests:otbn_randomness_test"] - lc_states: ["PROD"] - features: [ - "OTBN.RANDOM" - ] - } - { - name: chip_sw_otbn_idle - desc: '''Verify the OTBN idle signal to clkmgr. - - - Write the OTBN clk hint to 0 within clkmgr to indicate OTBN clk can be gated - and verify that the OTBN clk hint status within clkmgr reads 0 (OTBN is disabled). - - Write the OTBN clk hint to 1 within clkmgr to indicate OTBN clk can be enabled. - Verify that the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled). - - Start an OTBN operation, write the OTBN clk hint to 0 within clkmgr and verify that - the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled) before the - OTBN operation is complete. - - After the OTBN operation is complete, verify that the OTBN clk hint status within - clkmgr now reads 0 again (OTBN is disabled). - - Write the OTBN clk hint to 1, read and check the OTBN output for correctness. - ''' - stage: V2 - si_stage: SV3 - tests: ["chip_sw_otbn_randomness"] - bazel: ["//sw/device/tests:otbn_randomness_test"] - lc_states: ["PROD"] - features: [] - } - { - name: chip_sw_otbn_mem_scramble - desc: '''Verify the OTBN can receive keys from the OTP to scramble the OTBN imem and dmem. - - - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already - done by the test_rom startup code). - - Extract random address offsets from RV_CORE_IBEX_RND_DATA. - - Wait for OTBN to be idle. - - Write random address offsets in OTBN imem and dmem. - - Read back the written address offsets and compare against expected values. All values - must match, no integrity errors must be triggered. - - Have OTBN fetch new keys and nonces from the OTP_CTRL. - - Wait for OTBN to be idle. - - Read back the written address offsets. Most reads should trigger integrity errors. It - is possible that after re-scrambling the integrity bits are still valid. But this is - expected to happen rarely. If the number of observed integrity errors is below a - chosen threshold, the test fails. - - Verify the validity of EDN's output to OTP_CTRL via assertions - (unique, non-zero data). - ''' - stage: V2 - si_stage: SV3 - tests: ["chip_sw_otbn_mem_scramble"] - bazel: ["//sw/device/tests:otbn_mem_scramble_test"] - lc_states: ["PROD"] - features: [ - "OTBN.MEM_SCRAMBLE", - "OTBN.SECUREWIPE" - ] - } - { - name: chip_sw_otbn_keymgr - desc: '''Check the OTBN keymgr connection is functional. - - Setup the keymgr and any other blocks required to provide OTBN with a valid sideload - key. Run an OTBN program to read the key via the KEY_S[0|1]_[H|L] WSRs and write it to - dmem. Sanity check the returned value (e.g. != 0) and check OTBN completed successfully - with no errors. - ''' - stage: V2 - si_stage: SV2 - tests: [] - bazel: [ - "//sw/device/tests:keymgr_sideload_otbn_simple_test", - "//sw/device/tests/crypto:ecdh_p256_sideload_functest", - "//sw/device/tests/crypto:ecdsa_p256_sideload_functest", - "//sw/device/tests:keymgr_sideload_otbn_test" - ] - lc_states: ["PROD"] - features: [ - "OTBN.KEYMGR", - ] - } - ] -} diff --git a/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson index 38502b6ecac..7be371554e8 100644 --- a/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson @@ -33,7 +33,7 @@ - chip_sw_sram_scrambled_access - chip_sw_flash_scramble - chip_sw_keymgr_key_derivation - - chip_sw_otbn_mem_scramble + - chip_sw_acc_mem_scramble For sival, this test can be done by - manuf_ft_sku_individualization - manuf_ft_provision_rma_token_and_personalization @@ -46,7 +46,7 @@ "chip_sw_sram_ctrl_scrambled_access", "chip_sw_flash_init", "chip_sw_keymgr_key_derivation", - "chip_sw_otbn_mem_scramble", + "chip_sw_acc_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] bazel: ["//sw/device/silicon_creator/manuf/lib:individualize_functest"] } @@ -55,7 +55,7 @@ desc: '''Verify the entropy interface from OTP ctrl to EDN. This is X-ref'ed with the chip_otp_ctrl_keys test, which needs to handshake with the EDN - to receive some entropy bits before the keys for SRAM ctrl and OTBN are computed. + to receive some entropy bits before the keys for SRAM ctrl and ACC are computed. For sival, this test can be done by - manuf_ft_sku_individualization - manuf_ft_provision_rma_token_and_personalization @@ -67,7 +67,7 @@ tests: ["chip_sw_sram_ctrl_scrambled_access", "chip_sw_flash_init", "chip_sw_keymgr_key_derivation", - "chip_sw_otbn_mem_scramble", + "chip_sw_acc_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] bazel: ["//sw/device/silicon_creator/manuf/base:ft_provision_sival"] } diff --git a/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson b/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson index a97383815db..0cd597b89c5 100644 --- a/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson @@ -39,7 +39,7 @@ Verify accessibility of all the memories in the chip over JTAG. This test will target the following memories in the chip: - sram_main, sram_ret, otbn i|dmem, ROM + sram_main, sram_ret, acc i|dmem, ROM - Shuffle the list of memories first to remove the effect of ordering. - Write a location in a randomly chosen set of addresses within each memory via JTAG diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index f444d097131..5b68c3c8c26 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -254,7 +254,7 @@ "aes", "hmac", "kmac", - "otbn", + "acc", "keymgr", "csrng", "entropy_src", @@ -852,6 +852,31 @@ attr: "ipgen", targets: ["rv_core_ibex"] }, + { name: "acc", + type: "acc", + param_decl: { + AccPQCEn: "0" + } + clock_srcs: { + clk_i: { + clock: "main", + group: "trans" + }, + clk_edn_i: { + clock: "main", + group: "secure" + }, + clk_otp_i: { + clock: "io_div4", + group: "secure" + }, + }, + clock_group: "trans", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc", rst_otp_ni: "lc_io_div4"}, + base_addr: { + hart: "0x41300000", + }, + }, { name: "aes", type: "aes", clock_srcs: {clk_i: "main", clk_edn_i: "main"}, @@ -886,31 +911,6 @@ hart: "0x41120000", } }, - { name: "otbn", - type: "otbn", - param_decl: { - OtbnPQCEn: "0" - } - clock_srcs: { - clk_i: { - clock: "main", - group: "trans" - }, - clk_edn_i: { - clock: "main", - group: "secure" - }, - clk_otp_i: { - clock: "io_div4", - group: "secure" - }, - }, - clock_group: "trans", - reset_connections: {rst_ni: "lc", rst_edn_ni: "lc", rst_otp_ni: "lc_io_div4"}, - base_addr: { - hart: "0x41300000", - }, - }, { name: "keymgr", type: "keymgr", clock_srcs: {clk_i: "main", clk_edn_i: "main"}, @@ -1149,8 +1149,8 @@ 'connect': { 'ast.obs_ctrl' : ['flash_ctrl.obs_ctrl', 'otp_macro.obs_ctrl'], - 'ast.ram_1p_cfg' : ['otbn.ram_cfg_imem', - 'otbn.ram_cfg_dmem', + 'ast.ram_1p_cfg' : ['acc.ram_cfg_imem', + 'acc.ram_cfg_dmem', 'i2c0.ram_cfg', 'i2c1.ram_cfg', 'i2c2.ram_cfg', @@ -1194,9 +1194,9 @@ 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], // LC RMA req/ack interface: LC --> Flash -> LC - // |-> OTBN -> LC - 'lc_ctrl.lc_flash_rma_req' : ['flash_ctrl.rma_req', 'otbn.lc_rma_req'], - 'lc_ctrl.lc_flash_rma_ack' : ['flash_ctrl.rma_ack', 'otbn.lc_rma_ack'], + // |-> ACC -> LC + 'lc_ctrl.lc_flash_rma_req' : ['flash_ctrl.rma_req', 'acc.lc_rma_req'], + 'lc_ctrl.lc_flash_rma_ack' : ['flash_ctrl.rma_ack', 'acc.lc_rma_ack'], // usbdev connection to pinmux 'usbdev.usb_dp_pullup' : ['pinmux_aon.usbdev_dppullup_en'], @@ -1210,24 +1210,24 @@ // Edn connections 'edn0.edn' : ['keymgr.edn', 'otp_ctrl.edn', 'ast.edn', 'kmac.entropy', - 'alert_handler.edn', 'aes.edn', 'otbn.edn_urnd', + 'alert_handler.edn', 'aes.edn', 'acc.edn_urnd', 'rv_core_ibex.edn'], - 'edn1.edn' : ['otbn.edn_rnd'], + 'edn1.edn' : ['acc.edn_rnd'], - // OTBN OTP scramble key - 'otp_ctrl.otbn_otp_key' : ['otbn.otbn_otp_key'], + // ACC OTP scramble key + 'otp_ctrl.acc_otp_key' : ['acc.acc_otp_key'], // KeyMgr Sideload & KDF function 'otp_ctrl.otp_keymgr_key' : ['keymgr.otp_key'], 'keymgr.aes_key' : ['aes.keymgr_key'], 'keymgr.kmac_key' : ['kmac.keymgr_key'], - 'keymgr.otbn_key' : ['otbn.keymgr_key'], + 'keymgr.acc_key' : ['acc.keymgr_key'], // KMAC Application Interface 'kmac.app' : ['keymgr.kmac_data', // Keymgr needs to be at index 0 'lc_ctrl.kmac_data', // LC needs to be at index 1 'rom_ctrl.kmac_data', // ROM needs to be at index 2 - 'otbn.kmac_data'], // OTBN needs to be at index 3 + 'acc.kmac_data'], // ACC needs to be at index 3 'kmac.en_masking' : ['keymgr.kmac_en_masking'], // The idle connection is automatically connected through topgen. @@ -1276,7 +1276,7 @@ 'lc_ctrl.lc_keymgr_en' : ['keymgr.lc_keymgr_en'], 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en', 'kmac.lc_escalate_en', - 'otbn.lc_escalate_en', + 'acc.lc_escalate_en', 'otp_ctrl.lc_escalate_en', 'sram_ctrl_main.lc_escalate_en', 'sram_ctrl_ret_aon.lc_escalate_en', diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson index 717b7b9e3c5..5220d97df13 100644 --- a/hw/top_earlgrey/data/xbar_main.hjson +++ b/hw/top_earlgrey/data/xbar_main.hjson @@ -182,7 +182,7 @@ req_fifo_pass: false, rsp_fifo_pass: false, }, - { name: "otbn", + { name: "acc", type: "device", clock: "clk_main_i" reset: "rst_main_ni" @@ -224,7 +224,7 @@ "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1", "usbdev", "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", - "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", + "rv_plic", "acc", "keymgr", "kmac", "sram_ctrl_main.regs", "rv_core_ibex.cfg" ], rv_dm.sba: [ @@ -232,7 +232,7 @@ "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1", "usbdev", "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", - "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", + "rv_plic", "acc", "keymgr", "kmac", "sram_ctrl_main.regs", "rv_core_ibex.cfg", ], }, diff --git a/hw/top_earlgrey/doc/datasheet.md b/hw/top_earlgrey/doc/datasheet.md index e5190ab9eda..89c6810dcc3 100644 --- a/hw/top_earlgrey/doc/datasheet.md +++ b/hw/top_earlgrey/doc/datasheet.md @@ -50,7 +50,7 @@ The OpenTitan Earl Grey chip provides the following features:
      • AES-128/192/256 with ECB/CBC/CFB/OFB/CTR modes
      • HMAC / SHA2-256
      • KMAC / SHA3-224, 256, 384, 512, [c]SHAKE-128, 256
        • -
      • Programmable big number accelerator for RSA and ECC (OTBN)
        • +
      • Programmable big number accelerator for RSA and ECC (ACC)
      • NIST-compliant cryptographically secure random number generator (CSRNG)
      • Digital wrapper for analog entropy source with FIPS and CC-compliant health checks
      • Key manager with DICE support
        • @@ -101,7 +101,7 @@ The OpenTitan Earl Grey chip provides the following features:
        • Boot ROM code implementing secure boot and chip configuration
        • Bare metal top-level tests
          • -
        • OpenTitan Crypto Library with OTBN accelerated standard algorithms for
          • +
        • OpenTitan Crypto Library with ACC accelerated standard algorithms for
          • RSA 2K, 3K, 4K
          • ECC with NIST P256/P384, Brainpool P256r1 or X25519/Ed25519
            • diff --git a/hw/top_earlgrey/doc/design/README.md b/hw/top_earlgrey/doc/design/README.md index f2e42674d39..f4526e86abf 100644 --- a/hw/top_earlgrey/doc/design/README.md +++ b/hw/top_earlgrey/doc/design/README.md @@ -390,8 +390,8 @@ For the purpose of `top_earlgrey`, the first option has been chosen to benefit s ## Entropy Distribution Network `top_earlgrey` has two [EDN](../../../ip/edn/README.md) instances, which are connected to one [CSRNG](../../../ip/csrng/README.md) instance (which in turn is connected to one [Entropy Source](../../../ip/entropy_src/README.md) instance). -The first EDN instance, `u_edn0`, has eight endpoints, which are connected to: Key Manager, OTP Controller, Analog Sensor Top, KMAC Accelerator, Alert Handler, AES Accelerator, the `URND` port of OTBN, and the Ibex RISC-V Core. -The second EDN instance, `u_edn1`, has one endpoint that is connected to the `RND` port of OTBN and seven endpoints that are tied off. +The first EDN instance, `u_edn0`, has eight endpoints, which are connected to: Key Manager, OTP Controller, Analog Sensor Top, KMAC Accelerator, Alert Handler, AES Accelerator, the `URND` port of ACC, and the Ibex RISC-V Core. +The second EDN instance, `u_edn1`, has one endpoint that is connected to the `RND` port of ACC and seven endpoints that are tied off. The second EDN instance, `u_edn1` is intended to be configured to deliver highest-quality entropy, e.g., for the generation of cryptographic secrets. The first EDN instance, `u_edn0` is intended to be configured to deliver entropy at a higher rate and thus slightly lower quality. diff --git a/hw/top_earlgrey/doc/memory_map.md b/hw/top_earlgrey/doc/memory_map.md index 042523461ff..9c7fb133bfe 100644 --- a/hw/top_earlgrey/doc/memory_map.md +++ b/hw/top_earlgrey/doc/memory_map.md @@ -50,10 +50,10 @@ The main address space, shared between the CPU and DM | rv_dm | mem | `0x10000` | `0x1000` | `0x400` | mem device on rv_dm | | rv_dm | dbg | `0x1000` | `0x200` | `0x80` | dbg device on rv_dm | | rv_plic | default | `0x48000000` | `0x8000000` | `0x2000000` | rv_plic | +| acc | default | `0x41300000` | `0x20000` | `0x8000` | acc | | aes | default | `0x41100000` | `0x100` | `0x40` | aes | | hmac | default | `0x41110000` | `0x2000` | `0x800` | hmac | | kmac | default | `0x41120000` | `0x1000` | `0x400` | kmac | -| otbn | default | `0x41300000` | `0x20000` | `0x8000` | otbn | | keymgr | default | `0x41140000` | `0x100` | `0x40` | keymgr | | csrng | default | `0x41150000` | `0x80` | `0x20` | csrng | | entropy_src | default | `0x41160000` | `0x100` | `0x40` | entropy_src | diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index 83bfbd8efa3..b8f91ebe8ed 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv @@ -46,13 +46,13 @@ assign alert_if[38].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; assign alert_if[39].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[4]; assign alert_if[40].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0]; assign alert_if[41].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; -assign alert_if[42].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; -assign alert_if[43].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; -assign alert_if[44].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; -assign alert_if[45].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; -assign alert_if[46].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; -assign alert_if[47].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[48].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[42].alert_tx = `CHIP_HIER.u_acc.alert_tx_o[0]; +assign alert_if[43].alert_tx = `CHIP_HIER.u_acc.alert_tx_o[1]; +assign alert_if[44].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[45].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[46].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[47].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[48].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; assign alert_if[49].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; assign alert_if[50].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; assign alert_if[51].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index bbf446c6f6f..03afd4f3aa4 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv @@ -59,7 +59,7 @@ tl_if csrng_tl_if(clk_main, rst_n); tl_if edn0_tl_if(clk_main, rst_n); tl_if edn1_tl_if(clk_main, rst_n); tl_if rv_plic_tl_if(clk_main, rst_n); -tl_if otbn_tl_if(clk_main, rst_n); +tl_if acc_tl_if(clk_main, rst_n); tl_if keymgr_tl_if(clk_main, rst_n); tl_if rv_core_ibex__cfg_tl_if(clk_main, rst_n); tl_if sram_ctrl_main__regs_tl_if(clk_main, rst_n); @@ -141,7 +141,7 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(edn0, edn0, tl) `DRIVE_CHIP_TL_DEVICE_IF(edn1, edn1, tl) `DRIVE_CHIP_TL_DEVICE_IF(rv_plic, rv_plic, tl) - `DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl) + `DRIVE_CHIP_TL_DEVICE_IF(acc, acc, tl) `DRIVE_CHIP_TL_DEVICE_IF(keymgr, keymgr, tl) `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex__cfg, rv_core_ibex, cfg_tl_d) `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__regs, sram_ctrl_main, regs_tl) diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index ba018f7bbe3..e4e221fe3ac 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv @@ -61,7 +61,7 @@ tl_device_t xbar_devices[$] = '{ '{"rv_plic", '{ '{32'h48000000, 32'h4fffffff} }}, - '{"otbn", '{ + '{"acc", '{ '{32'h41300000, 32'h4131ffff} }}, '{"keymgr", '{ @@ -212,7 +212,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr", "kmac", "sram_ctrl_main__regs", @@ -264,7 +264,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr", "kmac", "sram_ctrl_main__regs", diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg index 4b3f548df4c..fb7c7139874 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg @@ -92,10 +92,10 @@ -node tb.dut*.u_edn1 tl_*i.a_address[31:31] -node tb.dut*.u_rv_plic tl_*i.a_address[29:28] -node tb.dut*.u_rv_plic tl_*i.a_address[31:31] --node tb.dut*.u_otbn tl_*i.a_address[19:17] --node tb.dut*.u_otbn tl_*i.a_address[23:22] --node tb.dut*.u_otbn tl_*i.a_address[29:25] --node tb.dut*.u_otbn tl_*i.a_address[31:31] +-node tb.dut*.u_acc tl_*i.a_address[19:17] +-node tb.dut*.u_acc tl_*i.a_address[23:22] +-node tb.dut*.u_acc tl_*i.a_address[29:25] +-node tb.dut*.u_acc tl_*i.a_address[31:31] -node tb.dut*.u_keymgr tl_*i.a_address[17:8] -node tb.dut*.u_keymgr tl_*i.a_address[19:19] -node tb.dut*.u_keymgr tl_*i.a_address[23:21] diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index 5d0a1b043ba..f6de5e3d510 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -59,10 +59,10 @@ // "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", // xbar tests "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson", - // Config files to get the correct flags for otbn_memutil and otbn_tracer + // Config files to get the correct flags for acc_memutil and acc_tracer "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson", - "{proj_root}/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson", - "{proj_root}/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson", + "{proj_root}/hw/ip/acc/dv/memutil/acc_memutil_sim_opts.hjson", + "{proj_root}/hw/ip/acc/dv/tracer/acc_tracer_sim_opts.hjson", "{top_dv_path}/chip_smoketests.hjson", "{top_dv_path}/chip_rom_tests.hjson", // Enable C compilation of chip level dpi @@ -230,10 +230,10 @@ } ] - // Add options needed to compile against otbn_memutil, otbn_tracer, + // Add options needed to compile against acc_memutil, acc_tracer, // memutil_dpi_scrambled, and AES C model - en_build_modes: ["{tool}_otbn_memutil_build_opts", - "{tool}_otbn_tracer_build_opts", + en_build_modes: ["{tool}_acc_memutil_build_opts", + "{tool}_acc_tracer_build_opts", "{tool}_memutil_dpi_scrambled_build_opts", "{tool}_aes_model_build_opts", "{tool}_dpi_build_opts"] @@ -395,7 +395,7 @@ // to know what type of image is it: // - 0 for Boot ROM, // - 1 for SW test (loaded in flash), - // - 2 for OTBN test, and + // - 2 for ACC test, and // - 3 for OTP. // This allows an arbitrary number of SW images to be supplied to the TB. // @@ -1246,32 +1246,32 @@ run_opts: ["+sw_test_timeout_ns=18_000_000"] } { - name: chip_sw_otbn_randomness + name: chip_sw_acc_randomness uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_randomness_test:1:new_rules"] + sw_images: ["//sw/device/tests:acc_randomness_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=18_000_000","+rng_srate_value=30"] } { - name: chip_sw_otbn_ecdsa_op_irq + name: chip_sw_acc_ecdsa_op_irq uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1:new_rules"] + sw_images: ["//sw/device/tests:acc_ecdsa_op_irq_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=28_000_000", "+rng_srate_value=30"] run_timeout_mins: 400 } { - name: chip_sw_otbn_ecdsa_op_irq_jitter_en + name: chip_sw_acc_ecdsa_op_irq_jitter_en uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1:new_rules"] + sw_images: ["//sw/device/tests:acc_ecdsa_op_irq_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=33_000_000", "+rng_srate_value=30", "+en_jitter=1"] run_timeout_mins: 400 } { - name: chip_sw_otbn_mem_scramble + name: chip_sw_acc_mem_scramble uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_mem_scramble_test:1:new_rules"] + sw_images: ["//sw/device/tests:acc_mem_scramble_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=15_000_000", "+en_scb_tl_err_chk=0", "+bypass_alert_ready_to_end_check=1"] @@ -1591,9 +1591,9 @@ run_opts: ["+sw_test_timeout_ns=20_000_000"] } { - name: chip_sw_keymgr_sideload_otbn + name: chip_sw_keymgr_sideload_acc uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:keymgr_sideload_otbn_test:1:new_rules"] + sw_images: ["//sw/device/tests:keymgr_sideload_acc_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=20_000_000"] run_timeout_mins: 180 @@ -1783,9 +1783,9 @@ en_run_modes: ["sw_test_mode_test_rom"] } { - name: chip_sw_clkmgr_off_otbn_trans + name: chip_sw_clkmgr_off_acc_trans uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:clkmgr_off_otbn_trans_test:1:new_rules"] + sw_images: ["//sw/device/tests:clkmgr_off_acc_trans_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] } { @@ -2078,9 +2078,9 @@ run_opts: ["+en_jitter=1", "+cal_sys_clk_70mhz=1"] } { - name: chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq + name: chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1:new_rules"] + sw_images: ["//sw/device/tests:acc_ecdsa_op_irq_test:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=33_000_000", "+rng_srate_value=30", "+en_jitter=1", "+cal_sys_clk_70mhz=1"] run_timeout_mins: 1000 @@ -2225,7 +2225,7 @@ tests: ["chip_sw_clkmgr_jitter", "chip_sw_flash_ctrl_ops_jitter_en", "chip_sw_flash_ctrl_access_jitter_en", - "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_acc_ecdsa_op_irq_jitter_en", "chip_sw_aes_enc_jitter_en", "chip_sw_hmac_enc_jitter_en", "chip_sw_keymgr_key_derivation_jitter_en", @@ -2237,7 +2237,7 @@ tests: ["chip_sw_clkmgr_jitter_reduced_freq", "chip_sw_flash_ctrl_ops_jitter_en_reduced_freq", "chip_sw_flash_ctrl_access_jitter_en_reduced_freq", - "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq", + "chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq", "chip_sw_aes_enc_jitter_en_reduced_freq", "chip_sw_hmac_enc_jitter_en_reduced_freq", "chip_sw_keymgr_key_derivation_jitter_en_reduced_freq", diff --git a/hw/top_earlgrey/dv/chip_smoketests.hjson b/hw/top_earlgrey/dv/chip_smoketests.hjson index d5f16ac34bb..50d93fa9f4d 100644 --- a/hw/top_earlgrey/dv/chip_smoketests.hjson +++ b/hw/top_earlgrey/dv/chip_smoketests.hjson @@ -57,9 +57,9 @@ en_run_modes: ["sw_test_mode_test_rom"] } { - name: chip_sw_otbn_smoketest + name: chip_sw_acc_smoketest uvm_test_seq: chip_sw_base_vseq - sw_images: ["//sw/device/tests:otbn_smoketest:1:new_rules"] + sw_images: ["//sw/device/tests:acc_smoketest:1:new_rules"] en_run_modes: ["sw_test_mode_test_rom"] } { @@ -129,7 +129,7 @@ "chip_sw_gpio_smoketest", "chip_sw_hmac_smoketest", "chip_sw_kmac_smoketest", - "chip_sw_otbn_smoketest", + "chip_sw_acc_smoketest", "chip_sw_otp_ctrl_smoketest", "chip_sw_rv_plic_smoketest", "chip_sw_pwrmgr_smoketest", diff --git a/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg b/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg index 82f5d011117..63aaa64e5ab 100644 --- a/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg +++ b/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg @@ -38,7 +38,7 @@ +node tb.dut.top_earlgrey.u_aes *tl_* +node tb.dut.top_earlgrey.u_hmac *tl_* +node tb.dut.top_earlgrey.u_kmac *tl_* -+node tb.dut.top_earlgrey.u_otbn *tl_* ++node tb.dut.top_earlgrey.u_acc *tl_* +node tb.dut.top_earlgrey.u_keymgr *tl_* +node tb.dut.top_earlgrey.u_csrng *tl_* +node tb.dut.top_earlgrey.u_entropy_src *tl_* diff --git a/hw/top_earlgrey/dv/cov/conn_ast_mem_cfg.el b/hw/top_earlgrey/dv/cov/conn_ast_mem_cfg.el index 5b889dd3f6e..c1f726ee799 100644 --- a/hw/top_earlgrey/dv/cov/conn_ast_mem_cfg.el +++ b/hw/top_earlgrey/dv/cov/conn_ast_mem_cfg.el @@ -9,7 +9,7 @@ // ExclMode: default //================================================== CHECKSUM: "1723488990 3787458315" -INSTANCE: tb.dut.top_earlgrey.u_otbn +INSTANCE: tb.dut.top_earlgrey.u_acc ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en" ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv" diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index 719464ebe5b..45a362d84b1 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv @@ -48,13 +48,13 @@ parameter string LIST_OF_ALERTS[NUM_ALERTS] = { "flash_ctrl_recov_prim_flash_alert", "rv_dm_fatal_fault", "rv_plic_fatal_fault", + "acc_fatal", + "acc_recov", "aes_recov_ctrl_update_err", "aes_fatal_fault", "hmac_fatal_fault", "kmac_recov_operation_err", "kmac_fatal_fault_err", - "otbn_fatal", - "otbn_recov", "keymgr_recov_operation_err", "keymgr_fatal_fault_err", "csrng_recov_alert", diff --git a/hw/top_earlgrey/dv/env/chip_env.sv b/hw/top_earlgrey/dv/env/chip_env.sv index 48015e28977..94d30df6d09 100644 --- a/hw/top_earlgrey/dv/env/chip_env.sv +++ b/hw/top_earlgrey/dv/env/chip_env.sv @@ -44,8 +44,8 @@ class chip_env extends cip_base_env #( is_invalid |= mem inside {[RamRet0:RamRet15]} && (int'(mem - RamRet0) > cfg.num_ram_ret_tiles - 1); - is_invalid |= mem inside {[OtbnDmem0:OtbnDmem15]} && (int'(mem - OtbnDmem0) > - cfg.num_otbn_dmem_tiles - 1); + is_invalid |= mem inside {[AccDmem0:AccDmem15]} && (int'(mem - AccDmem0) > + cfg.num_acc_dmem_tiles - 1); if (is_invalid) continue; if (!uvm_config_db#(mem_bkdr_util)::get(this, "", inst, cfg.mem_bkdr_util_h[mem])) begin `uvm_fatal(`gfn, {"failed to get ", inst, " from uvm_config_db"}) diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv index c98e2566d48..2fffdab147d 100644 --- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv +++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv @@ -87,7 +87,7 @@ class chip_env_cfg #(type RAL_T = chip_ral_pkg::chip_reg_block) extends cip_base // Number of RAM tiles for each RAM instance. uint num_ram_main_tiles; uint num_ram_ret_tiles; - uint num_otbn_dmem_tiles; + uint num_acc_dmem_tiles; // ext component cfgs rand uart_agent_cfg m_uart_agent_cfgs[NUM_UARTS]; @@ -235,7 +235,7 @@ class chip_env_cfg #(type RAL_T = chip_ral_pkg::chip_reg_block) extends cip_base `DV_CHECK_LE_FATAL(num_ram_main_tiles, 16) `DV_CHECK_LE_FATAL(num_ram_ret_tiles, 16) - `DV_CHECK_LE_FATAL(num_otbn_dmem_tiles, 16) + `DV_CHECK_LE_FATAL(num_acc_dmem_tiles, 16) // ral_model_names = chip_reg_block // 1 entry if (use_jtag_dmi == 1) begin @@ -272,7 +272,7 @@ class chip_env_cfg #(type RAL_T = chip_ral_pkg::chip_reg_block) extends cip_base // Set the number of RAM tiles (1 each). num_ram_main_tiles = 1; num_ram_ret_tiles = 1; - num_otbn_dmem_tiles = 1; + num_acc_dmem_tiles = 1; endfunction // Disable functional coverage of comportable IP-specific specialized registers. diff --git a/hw/top_earlgrey/dv/env/chip_env_pkg.sv b/hw/top_earlgrey/dv/env/chip_env_pkg.sv index fe3ab5d6e50..ac59c00f882 100644 --- a/hw/top_earlgrey/dv/env/chip_env_pkg.sv +++ b/hw/top_earlgrey/dv/env/chip_env_pkg.sv @@ -92,21 +92,21 @@ package chip_env_pkg; ICacheWay0Data, ICacheWay1Data, UsbdevBuf, - OtbnDmem[16], - OtbnImem, + AccDmem[16], + AccImem, Otp, RamMain[16], RamRet[16], Rom } chip_mem_e; - // On OpenTitan, we deal with 4 types of SW - ROM, the main test, the OTBN test and the OTP image. + // On OpenTitan, we deal with 4 types of SW - ROM, the main test, the ACC test and the OTP image. // This basically puts these SW types into 'slots' that the external regression tool can set. typedef enum { SwTypeRom = 0, // Ibex SW - first stage boot ROM. SwTypeTestSlotA = 1, // Ibex SW - test SW in (flash) slot A. SwTypeTestSlotB = 2, // Ibex SW - test SW in (flash) slot B. - SwTypeOtbn = 3, // Otbn SW + SwTypeAcc = 3, // Acc SW SwTypeOtp = 4, // Customized OTP image SwTypeDebug = 5 // Debug SW - injected into SRAM. } sw_type_e; diff --git a/hw/top_earlgrey/dv/env/chip_if.sv b/hw/top_earlgrey/dv/env/chip_if.sv index 58c081b6e85..d27bb7b32a0 100644 --- a/hw/top_earlgrey/dv/env/chip_if.sv +++ b/hw/top_earlgrey/dv/env/chip_if.sv @@ -59,7 +59,7 @@ interface chip_if; `define LC_CTRL_HIER `TOP_HIER.u_lc_ctrl `define OTP_CTRL_HIER `TOP_HIER.u_otp_ctrl `define OTP_MACRO_HIER `TOP_HIER.u_otp_macro -`define OTBN_HIER `TOP_HIER.u_otbn +`define ACC_HIER `TOP_HIER.u_acc `define PATTGEN_HIER `TOP_HIER.u_pattgen `define PINMUX_HIER `TOP_HIER.u_pinmux_aon `define PWM_HIER `TOP_HIER.u_pwm_aon @@ -770,7 +770,7 @@ interface chip_if; wire aes_clk_is_enabled = 0; wire hmac_clk_is_enabled = 0; wire kmac_clk_is_enabled = 0; - wire otbn_clk_is_enabled = 0; + wire acc_clk_is_enabled = 0; wire usbdev_clk_is_enabled = 0; wire io_clk_is_enabled = 0; @@ -780,7 +780,7 @@ interface chip_if; wire aes_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_aes_val.d; wire hmac_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_hmac_val.d; wire kmac_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_kmac_val.d; - wire otbn_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_otbn_val.d; + wire acc_clk_is_enabled = `CLKMGR_HIER.u_reg.hw2reg.clk_hints_status.clk_main_acc_val.d; wire usbdev_clk_is_enabled = `CLKMGR_HIER.u_reg.reg2hw.clk_enables.clk_usb_peri_en.q; wire io_clk_is_enabled = `CLKMGR_HIER.u_reg.reg2hw.clk_enables.clk_io_peri_en.q; @@ -1099,7 +1099,7 @@ interface chip_if; PeripheralKeymgr: path = {path, ".", `DV_STRINGIFY(`KEYMGR_HIER)}; PeripheralKmac: path = {path, ".", `DV_STRINGIFY(`KMAC_HIER)}; PeripheralLcCtrl: path = {path, ".", `DV_STRINGIFY(`LC_CTRL_HIER)}; - PeripheralOtbn: path = {path, ".", `DV_STRINGIFY(`OTBN_HIER)}; + PeripheralAcc: path = {path, ".", `DV_STRINGIFY(`ACC_HIER)}; PeripheralOtpCtrl: path = {path, ".", `DV_STRINGIFY(`OTP_CTRL_HIER)}; PeripheralPattgen: path = {path, ".", `DV_STRINGIFY(`PATTGEN_HIER)}; PeripheralPinmuxAon: path = {path, ".", `DV_STRINGIFY(`PINMUX_HIER)}; @@ -1336,11 +1336,11 @@ assign spi_host_1_state = {tb.dut.top_earlgrey.u_spi_host1.u_spi_core.u_fsm.stat `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_kmac_fsm_state, kmac_fsm_state, 6) - // Signal probe function for `state_q` OTBN_START_STOP_CONTROL - wire [6:0] otbn_fsm_state; - assign otbn_fsm_state = `OTBN_HIER.u_otbn_core.u_otbn_start_stop_control.u_state_regs.state_o; - `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_otbn_fsm_state, - otbn_fsm_state, 7) + // Signal probe function for `state_q` ACC_START_STOP_CONTROL + wire [6:0] acc_fsm_state; + assign acc_fsm_state = `ACC_HIER.u_acc_core.u_acc_start_stop_control.u_state_regs.state_o; + `DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_acc_fsm_state, + acc_fsm_state, 7) // Signal probe function for `state_q` of EDN_0_MAIN_SM wire [8:0] edn_0_fsm_state; @@ -1417,7 +1417,7 @@ assign spi_host_1_state = {tb.dut.top_earlgrey.u_spi_host1.u_spi_core.u_fsm.stat `undef LC_CTRL_HIER `undef OTP_CTRL_HIER `undef OTP_MACRO_HIER -`undef OTBN_HIER +`undef ACC_HIER `undef PATTGEN_HIER `undef PINMUX_HIER `undef PWM_HIER diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv index 21aa3683d1c..1ee5d5e77b4 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv @@ -151,11 +151,11 @@ class chip_base_vseq #( initialize_otp_lc_state(); initialize_otp_creator_sw_cfg_ast_cfg(); // Initialize selected memories to all 0. This is required for some chip-level tests such as - // otbn_mem_scramble that may intentionally read memories before writing them. Reading these + // acc_mem_scramble that may intentionally read memories before writing them. Reading these // memories still triggers ECC integrity errors that need to be handled by the test. - cfg.mem_bkdr_util_h[OtbnImem].clear_mem(); - for (int ram_idx = 0; ram_idx < cfg.num_otbn_dmem_tiles; ram_idx++) begin - cfg.mem_bkdr_util_h[chip_mem_e'(OtbnDmem0 + ram_idx)].clear_mem(); + cfg.mem_bkdr_util_h[AccImem].clear_mem(); + for (int ram_idx = 0; ram_idx < cfg.num_acc_dmem_tiles; ram_idx++) begin + cfg.mem_bkdr_util_h[chip_mem_e'(AccDmem0 + ram_idx)].clear_mem(); end // Early cpu init if (cfg.early_cpu_init) cpu_init(); diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_jtag_mem_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_jtag_mem_vseq.sv index 22cae7bf52b..b451ff29eb8 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_jtag_mem_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_jtag_mem_vseq.sv @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 // This test write and read back test through jtag interface for -// following memories : otbn.imem, otbn.dmem, sram_ctrl_main_ram.ram, sram_ctrl_ret_aon_ram.ram +// following memories : acc.imem, acc.dmem, sram_ctrl_main_ram.ram, sram_ctrl_ret_aon_ram.ram // Also preload random data to rom_ctrl_rom.rom and check read data integrity // through jtag interface class chip_jtag_mem_vseq extends chip_common_vseq; diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv index 7749a335daf..28e2dd583d1 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_all_escalation_resets_vseq.sv @@ -36,7 +36,7 @@ class chip_sw_all_escalation_resets_vseq extends chip_sw_base_vseq; // TODO TopEarlgreyAlertIdLcCtrlFatalProgError: done in sw/device/tests/sim_dv/lc_ctrl_program_error.c? '{"*lc_ctrl*state_regs*", TopEarlgreyAlertIdLcCtrlFatalStateError}, '{"*lc_ctrl*prim_reg_we_check*", TopEarlgreyAlertIdLcCtrlFatalBusIntegError}, - '{"*otbn*prim_reg_we_check*", TopEarlgreyAlertIdOtbnFatal}, + '{"*acc*prim_reg_we_check*", TopEarlgreyAlertIdAccFatal}, // TopEarlgreyAlertIdOtpCtrlFatalMacroError: done in chip_sw_otp_ctrl_escalation_vseq '{"*otp_ctrl*u_otp_ctrl_dai*", TopEarlgreyAlertIdOtpCtrlFatalCheckError}, '{"*otp_ctrl*prim_reg_we_check*", TopEarlgreyAlertIdOtpCtrlFatalBusIntegError}, diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_keymgr_key_derivation_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_keymgr_key_derivation_vseq.sv index 78fffaecdfd..4f63a354c1c 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_keymgr_key_derivation_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_keymgr_key_derivation_vseq.sv @@ -92,10 +92,10 @@ class chip_sw_keymgr_key_derivation_vseq extends chip_sw_base_vseq; top_earlgrey_rnd_cnst_pkg::RndCnstKeymgrAesSeed, top_earlgrey_rnd_cnst_pkg::RndCnstKeymgrHardOutputSeed}; - localparam gen_out_data_t GenOtbnOutData = '{ + localparam gen_out_data_t GenAccOutData = '{ SwKeyVersion, Salt, - top_earlgrey_rnd_cnst_pkg::RndCnstKeymgrOtbnSeed, + top_earlgrey_rnd_cnst_pkg::RndCnstKeymgrAccSeed, top_earlgrey_rnd_cnst_pkg::RndCnstKeymgrHardOutputSeed}; bit lc_at_prod; @@ -146,7 +146,7 @@ class chip_sw_keymgr_key_derivation_vseq extends chip_sw_base_vseq; endtask virtual task check_op_in_owner_int_state(bit [keymgr_pkg::KeyWidth-1:0] unmasked_key); - string path_otbn_key = "tb.dut.top_earlgrey.u_keymgr.otbn_key_o"; + string path_acc_key = "tb.dut.top_earlgrey.u_keymgr.acc_key_o"; bit [keymgr_pkg::KeyWidth-1:0] exp_digest; bit [keymgr_pkg::KeyWidth-1:0] unused_key; @@ -162,20 +162,20 @@ class chip_sw_keymgr_key_derivation_vseq extends chip_sw_base_vseq; check_aes_sideload(unmasked_key, unused_key); - // otbn sideload key is 384 bit, so it's treated a bit differently + // acc sideload key is 384 bit, so it's treated a bit differently begin - keymgr_pkg::otbn_key_req_t otbn_key; + keymgr_pkg::acc_key_req_t acc_key; bit [7:0] data_arr[]; bit [kmac_pkg::AppDigestW-1:0] unmask_act_key, unmask_exp_key; `DV_WAIT(cfg.sw_logger_vif.printed_log == - "Keymgr generated HW output for Otbn at OwnerIntKey State") - `DV_CHECK_FATAL(uvm_hdl_check_path(path_otbn_key)) - `DV_CHECK_FATAL(uvm_hdl_read(path_otbn_key, otbn_key)) - `DV_CHECK_EQ(otbn_key.valid, 1) + "Keymgr generated HW output for Acc at OwnerIntKey State") + `DV_CHECK_FATAL(uvm_hdl_check_path(path_acc_key)) + `DV_CHECK_FATAL(uvm_hdl_read(path_acc_key, acc_key)) + `DV_CHECK_EQ(acc_key.valid, 1) - unmask_act_key = otbn_key.key[0] ^ otbn_key.key[1]; + unmask_act_key = acc_key.key[0] ^ acc_key.key[1]; - {<< byte {data_arr}} = GenOtbnOutData; + {<< byte {data_arr}} = GenAccOutData; unmask_exp_key = get_kmac_digest(unmasked_key, data_arr); `DV_CHECK_EQ(unmask_act_key, unmask_exp_key) diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_virus_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_virus_vseq.sv index 9e5259dcaf3..f768f4ad8e0 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_virus_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_power_virus_vseq.sv @@ -165,7 +165,7 @@ class chip_sw_power_virus_vseq extends chip_sw_base_vseq; logic [3:0] aes_ctrl_rnd_ctr; logic [2:0] hmac_fsm_state; logic [5:0] kmac_fsm_state; - logic [6:0] otbn_fsm_state; + logic [6:0] acc_fsm_state; logic [8:0] edn_0_fsm_state; logic [8:0] edn_1_fsm_state; logic [8:0] entropy_src_fsm_state; @@ -184,7 +184,7 @@ class chip_sw_power_virus_vseq extends chip_sw_base_vseq; `_DV_PROBE_AND_CHECK_IDLE(aes_ctrl_rnd_ctr, 4'b0000) `_DV_PROBE_AND_CHECK_IDLE(hmac_fsm_state, 3'b000) `_DV_PROBE_AND_CHECK_IDLE(kmac_fsm_state, 6'b011000) - `_DV_PROBE_AND_CHECK_IDLE(otbn_fsm_state, otbn_pkg::OtbnStartStopStateInitial) + `_DV_PROBE_AND_CHECK_IDLE(acc_fsm_state, acc_pkg::AccStartStopStateInitial) `_DV_PROBE_AND_CHECK_IDLE(edn_0_fsm_state, edn_pkg::Idle) `_DV_PROBE_AND_CHECK_IDLE(edn_1_fsm_state, edn_pkg::Idle) `_DV_PROBE_AND_CHECK_IDLE(entropy_src_fsm_state, entropy_src_main_sm_pkg::Idle) diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index 01527d7047b..4b68e95a5d9 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh @@ -26,7 +26,7 @@ `define UART_HIER `CHIP_HIER.u_uart `define USBDEV_HIER `CHIP_HIER.u_usbdev `define PWRMGR_HIER `CHIP_HIER.u_pwrmgr_aon -`define OTBN_HIER `CHIP_HIER.u_otbn +`define ACC_HIER `CHIP_HIER.u_acc // The path to the actual memory array in rom_ctrl. This is a bit of a hack to allow a long path // without overflowing 100 characters or including any whitespace (which breaks a DV_STRINGIFY call @@ -58,6 +58,6 @@ `define RAM_RET_MEM_HIER `RAM_RET_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB `define ROM_MEM_HIER `ROM_CTRL_HIER.`ROM_CTRL_INT_PATH `define OTP_MEM_HIER `OTP_MACRO_HIER.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB -`define OTBN_IMEM_HIER `OTBN_HIER.u_imem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB -`define OTBN_DMEM_HIER `OTBN_HIER.u_dmem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ACC_IMEM_HIER `ACC_HIER.u_imem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB +`define ACC_DMEM_HIER `ACC_HIER.u_dmem.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB `define USBDEV_BUF_HIER `USBDEV_HIER.gen_no_stubbed_memory.u_memory_1p.gen_ram_inst[0].u_mem.`MEM_ARRAY_SUB diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv index 9fd7c149543..c7fc69224fb 100644 --- a/hw/top_earlgrey/dv/tb/tb.sv +++ b/hw/top_earlgrey/dv/tb/tb.sv @@ -607,21 +607,21 @@ module tb; `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[Rom], `ROM_MEM_HIER) end - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for OTBN IMEM", UVM_MEDIUM) - m_mem_bkdr_util[OtbnImem] = new(.name ("mem_bkdr_util[OtbnImem]"), - .path (`DV_STRINGIFY(`OTBN_IMEM_HIER)), - .depth ($size(`OTBN_IMEM_HIER)), - .n_bits($bits(`OTBN_IMEM_HIER)), + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for ACC IMEM", UVM_MEDIUM) + m_mem_bkdr_util[AccImem] = new(.name ("mem_bkdr_util[AccImem]"), + .path (`DV_STRINGIFY(`ACC_IMEM_HIER)), + .depth ($size(`ACC_IMEM_HIER)), + .n_bits($bits(`ACC_IMEM_HIER)), .err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32)); - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[OtbnImem], `OTBN_IMEM_HIER) + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[AccImem], `ACC_IMEM_HIER) - `uvm_info("tb.sv", "Creating mem_bkdr_util instance for OTBN DMEM", UVM_MEDIUM) - m_mem_bkdr_util[OtbnDmem0] = new(.name ("mem_bkdr_util[OtbnDmem0]"), - .path (`DV_STRINGIFY(`OTBN_DMEM_HIER)), - .depth ($size(`OTBN_DMEM_HIER)), - .n_bits($bits(`OTBN_DMEM_HIER)), + `uvm_info("tb.sv", "Creating mem_bkdr_util instance for ACC DMEM", UVM_MEDIUM) + m_mem_bkdr_util[AccDmem0] = new(.name ("mem_bkdr_util[AccDmem0]"), + .path (`DV_STRINGIFY(`ACC_DMEM_HIER)), + .depth ($size(`ACC_DMEM_HIER)), + .n_bits($bits(`ACC_DMEM_HIER)), .err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32)); - `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[OtbnDmem0], `OTBN_DMEM_HIER) + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[AccDmem0], `ACC_DMEM_HIER) `uvm_info("tb.sv", "Creating mem_bkdr_util instance for USBDEV BUFFER", UVM_MEDIUM) m_mem_bkdr_util[UsbdevBuf] = new(.name ("mem_bkdr_util[UsbdevBuf]"), @@ -634,7 +634,7 @@ module tb; do begin if (mem inside {[RamMain1:RamMain15]} || mem inside {[RamRet1:RamRet15]} || - mem inside {[OtbnDmem1:OtbnDmem15]}) begin + mem inside {[AccDmem1:AccDmem15]}) begin mem = mem.next(); continue; end diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson index ff814318e93..6219ff24744 100644 --- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson +++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson @@ -33,7 +33,7 @@ "{proj_root}/hw/ip/kmac/dv/kmac_unmasked_sim_cfg.hjson", "{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_disabled_sim_cfg.hjson", "{proj_root}/hw/ip/lc_ctrl/dv/lc_ctrl_volatile_unlock_enabled_sim_cfg.hjson", - "{proj_root}/hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson", + "{proj_root}/hw/ip/acc/dv/uvm/acc_sim_cfg.hjson", "{proj_root}/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson", "{proj_root}/hw/ip/prim/dv/prim_alert/prim_alert_sim_cfg.hjson", "{proj_root}/hw/ip/prim/dv/prim_esc/prim_esc_sim_cfg.hjson", diff --git a/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson b/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson index a8bd0944ea6..947662de605 100644 --- a/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson @@ -57,7 +57,7 @@ // needed as a run time switch to Verilator. '''{eval_cmd} \ opts=; \ - types=(rom flash otbn otp); \ + types=(rom flash acc otp); \ exts=(scr.39.vmem elf elf vmem); \ images=`echo {sw_images}`; \ for image in $images; do \ @@ -81,7 +81,7 @@ // to know what type of image is it: // - 0 for Boot ROM, // - 1 for SW test (loaded in flash), - // - 2 for OTBN test, + // - 2 for ACC test, // - 3 for OTP. // This allows an arbitrary number of SW images to be supplied to the TB. // @@ -136,8 +136,8 @@ sw_images: ["//sw/device/tests:crt_test:1"] } { - name: otbn_smoketest_rtl - sw_images: ["//sw/device/tests:otbn_smoketest:1"] + name: acc_smoketest_rtl + sw_images: ["//sw/device/tests:acc_smoketest:1"] } { name: otp_ctrl_smoketest diff --git a/hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv b/hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv index 846ee9d9069..2b852d9b46b 100644 --- a/hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv +++ b/hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv @@ -20,9 +20,9 @@ CONNECTION, AST_DFT_SPI_DEVICE_RAM_2P_CFG, u_ast.u_ast_dft, "{12'h0, dpram_rml_o}", top_earlgrey.u_spi_device.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem, cfg_i # Single port RAMs. -# To otbn. -CONNECTION, AST_DFT_OTBN_IMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_earlgrey.u_otbn.u_imem.u_prim_ram_1p_adv.u_mem, cfg_i -CONNECTION, AST_DFT_OTBN_DMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_earlgrey.u_otbn.u_dmem.u_prim_ram_1p_adv.u_mem, cfg_i +# To acc. +CONNECTION, AST_DFT_ACC_IMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_earlgrey.u_acc.u_imem.u_prim_ram_1p_adv.u_mem, cfg_i +CONNECTION, AST_DFT_ACC_DMEM_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_earlgrey.u_acc.u_dmem.u_prim_ram_1p_adv.u_mem, cfg_i # To rv_core_ibex. CONNECTION, AST_DFT_RV_CORE_IBEX_TAG0_RAM_1P_CFG, u_ast.u_ast_dft, "{spram_rm_o, sprgf_rm_o}", top_earlgrey.u_rv_core_ibex.u_core.gen_rams.gen_rams_inner[0].gen_scramble_rams.tag_bank.u_prim_ram_1p_adv.u_mem, cfg_i diff --git a/hw/top_earlgrey/formal/conn_csvs/clkmgr_idle.csv b/hw/top_earlgrey/formal/conn_csvs/clkmgr_idle.csv index dd3d9bc8234..f11cb1daeb5 100644 --- a/hw/top_earlgrey/formal/conn_csvs/clkmgr_idle.csv +++ b/hw/top_earlgrey/formal/conn_csvs/clkmgr_idle.csv @@ -11,4 +11,4 @@ CONNECTION, CLKMGR_IDLE0, top_earlgrey.u_aes, idle_o, top_earlgrey.u_clkmgr_aon, idle_i[0] CONNECTION, CLKMGR_IDLE1, top_earlgrey.u_hmac, idle_o, top_earlgrey.u_clkmgr_aon, idle_i[1] CONNECTION, CLKMGR_IDLE2, top_earlgrey.u_kmac, idle_o, top_earlgrey.u_clkmgr_aon, idle_i[2] -CONNECTION, CLKMGR_IDLE3, top_earlgrey.u_otbn, idle_o, top_earlgrey.u_clkmgr_aon, idle_i[3] +CONNECTION, CLKMGR_IDLE3, top_earlgrey.u_acc, idle_o, top_earlgrey.u_clkmgr_aon, idle_i[3] diff --git a/hw/top_earlgrey/formal/conn_csvs/clkmgr_secure.csv b/hw/top_earlgrey/formal/conn_csvs/clkmgr_secure.csv index 5953027ae36..36fc2fd2288 100644 --- a/hw/top_earlgrey/formal/conn_csvs/clkmgr_secure.csv +++ b/hw/top_earlgrey/formal/conn_csvs/clkmgr_secure.csv @@ -24,8 +24,8 @@ CONNECTION, CLKMGR_SECURE_CLK_KEYMGR_EDN_CLK, top_earlgrey.u_clkmgr_aon, clocks_ CONNECTION, CLKMGR_SECURE_CLK_LC_CTRL, top_earlgrey.u_clkmgr_aon, clocks_o.clk_io_div4_secure, top_earlgrey.u_lc_ctrl, clk_i CONNECTION, CLKMGR_SECURE_KMAC_CLK_LC_CTRL, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_secure, top_earlgrey.u_lc_ctrl, clk_kmac_i -CONNECTION, CLKMGR_SECURE_CLK_OTBN_EDN_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_secure, top_earlgrey.u_otbn, clk_edn_i -CONNECTION, CLKMGR_SECURE_CLK_OTBN_OTP_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.clk_io_div4_secure, top_earlgrey.u_otbn, clk_otp_i +CONNECTION, CLKMGR_SECURE_CLK_ACC_EDN_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_secure, top_earlgrey.u_acc, clk_edn_i +CONNECTION, CLKMGR_SECURE_CLK_ACC_OTP_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.clk_io_div4_secure, top_earlgrey.u_acc, clk_otp_i CONNECTION, CLKMGR_SECURE_CLK_OTP_CTRL_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.clk_io_div4_secure, top_earlgrey.u_otp_ctrl, clk_i CONNECTION, CLKMGR_SECURE_CLK_OTP_CTRL_EDN_CLK, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_secure, top_earlgrey.u_otp_ctrl, clk_edn_i diff --git a/hw/top_earlgrey/formal/conn_csvs/clkmgr_trans.csv b/hw/top_earlgrey/formal/conn_csvs/clkmgr_trans.csv index 136bc3ad0a1..b511eee1003 100644 --- a/hw/top_earlgrey/formal/conn_csvs/clkmgr_trans.csv +++ b/hw/top_earlgrey/formal/conn_csvs/clkmgr_trans.csv @@ -13,4 +13,4 @@ CONNECTION,CLKMGR_TRANS_AES_EDN, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_a CONNECTION,CLKMGR_TRANS_HMAC, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_hmac, top_earlgrey.u_hmac,clk_i CONNECTION,CLKMGR_TRANS_KMAC, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_kmac, top_earlgrey.u_kmac,clk_i CONNECTION,CLKMGR_TRANS_KMAC_EDN, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_kmac, top_earlgrey.u_kmac,clk_edn_i -CONNECTION,CLKMGR_TRANS_OTBN, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_otbn, top_earlgrey.u_otbn,clk_i +CONNECTION,CLKMGR_TRANS_ACC, top_earlgrey.u_clkmgr_aon, clocks_o.clk_main_acc, top_earlgrey.u_acc,clk_i diff --git a/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv b/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv index a499ede0408..95c98c44e10 100644 --- a/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv +++ b/hw/top_earlgrey/formal/conn_csvs/lc_ctrl_broadcast.csv @@ -15,7 +15,7 @@ CONNECTION, LC_ESCALATE_EN_SRAM_RET, top_earlgrey.u_lc_ctrl, lc_escalate_en_o, CONNECTION, LC_ESCALATE_EN_FLASH, top_earlgrey.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.u_flash_ctrl, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_AES, top_earlgrey.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.u_aes, lc_escalate_en_i CONNECTION, LC_ESCALATE_EN_KMAC, top_earlgrey.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.u_kmac, lc_escalate_en_i -CONNECTION, LC_ESCALATE_EN_OTBN, top_earlgrey.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.u_otbn, lc_escalate_en_i +CONNECTION, LC_ESCALATE_EN_ACC, top_earlgrey.u_lc_ctrl, lc_escalate_en_o, top_earlgrey.u_acc, lc_escalate_en_i # Verify that lc_ctrl's keymanager enable signal and diversification value are correctly connected to the keymgr. CONNECTION, LC_KEYMGR_EN_KEYMGR, top_earlgrey.u_lc_ctrl, lc_keymgr_en_o, top_earlgrey.u_keymgr, lc_keymgr_en_i @@ -45,8 +45,8 @@ CONNECTION, LC_DFT_EN_AST, top_earlgrey.u_lc_ctrl, lc_dft_en_o, u_ast, CONNECTION, LC_RMA_SEED_FLASH_CTRL, top_earlgrey.u_lc_ctrl, lc_flash_rma_seed_o, top_earlgrey.u_flash_ctrl, rma_seed_i CONNECTION, LC_RMA_REQ_FLASH_CTRL, top_earlgrey.u_lc_ctrl, lc_flash_rma_req_o, top_earlgrey.u_flash_ctrl, rma_req_i CONNECTION, FLASH_CTRL_RMA_ACK_LC, top_earlgrey.u_flash_ctrl, rma_ack_o, top_earlgrey.u_lc_ctrl, lc_flash_rma_ack_i[0] -CONNECTION, LC_RMA_REQ_OTBN, top_earlgrey.u_lc_ctrl, lc_flash_rma_req_o, top_earlgrey.u_otbn, lc_rma_req_i -CONNECTION, OTBN_RMA_ACK_LC, top_earlgrey.u_otbn, lc_rma_ack_o, top_earlgrey.u_lc_ctrl, lc_flash_rma_ack_i[1] +CONNECTION, LC_RMA_REQ_ACC, top_earlgrey.u_lc_ctrl, lc_flash_rma_req_o, top_earlgrey.u_acc, lc_rma_req_i +CONNECTION, ACC_RMA_ACK_LC, top_earlgrey.u_acc, lc_rma_ack_o, top_earlgrey.u_lc_ctrl, lc_flash_rma_ack_i[1] # Verify lc_ctrl's clock bypass request connections. CONNECTION, LC_CLK_BYP_REQ_CLKMGR, top_earlgrey.u_lc_ctrl, lc_clk_byp_req_o, top_earlgrey.u_clkmgr_aon, lc_clk_byp_req_i diff --git a/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv b/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv index 36fab8ee319..f15f1abde0d 100644 --- a/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv +++ b/hw/top_earlgrey/formal/conn_csvs/rstmgr_resets_o.csv @@ -77,9 +77,9 @@ CONNECTION, RSTMGR_LC_D0_HMAC_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc CONNECTION, RSTMGR_LC_D0_KMAC_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_kmac, rst_ni CONNECTION, RSTMGR_LC_SHADOWED_D0_KMAC_RST_SHADOWED_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_shadowed_n[1], top_earlgrey.u_kmac, rst_shadowed_ni CONNECTION, RSTMGR_LC_D0_KMAC_RST_EDN_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_kmac, rst_edn_ni -CONNECTION, RSTMGR_LC_D0_OTBN_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_otbn, rst_ni -CONNECTION, RSTMGR_LC_D0_OTBN_RST_EDN_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_otbn, rst_edn_ni -CONNECTION, RSTMGR_LC_IO_DIV4_D0_OTBN_RST_OTP_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_io_div4_n[1], top_earlgrey.u_otbn, rst_otp_ni +CONNECTION, RSTMGR_LC_D0_ACC_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_acc, rst_ni +CONNECTION, RSTMGR_LC_D0_ACC_RST_EDN_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_acc, rst_edn_ni +CONNECTION, RSTMGR_LC_IO_DIV4_D0_ACC_RST_OTP_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_io_div4_n[1], top_earlgrey.u_acc, rst_otp_ni CONNECTION, RSTMGR_LC_D0_KEYMGR_RST_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_keymgr, rst_ni CONNECTION, RSTMGR_LC_SHADOWED_D0_KEYMGR_RST_SHADOWED_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_shadowed_n[1], top_earlgrey.u_keymgr, rst_shadowed_ni CONNECTION, RSTMGR_LC_D0_KEYMGR_RST_EDN_NI, top_earlgrey.u_rstmgr_aon, resets_o.rst_lc_n[1], top_earlgrey.u_keymgr, rst_edn_ni diff --git a/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson b/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson index 9c7803489d7..aaf68804457 100644 --- a/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson +++ b/hw/top_earlgrey/formal/top_earlgrey_fpv_sec_cm_cfgs.hjson @@ -134,11 +134,11 @@ task: "FpvSecCm" } { - name: otbn_sec_cm - dut: otbn - fusesoc_core: lowrisc:dv:otbn_sva + name: acc_sec_cm + dut: acc + fusesoc_core: lowrisc:dv:acc_sva import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"] - rel_path: "hw/ip/otbn/{sub_flow}/{tool}" + rel_path: "hw/ip/acc/{sub_flow}/{tool}" stopats: ["*u_state_regs.state_o"] task: "FpvSecCm" } @@ -174,7 +174,7 @@ dut: rv_core_ibex fusesoc_core: lowrisc:earlgrey_dv:rv_core_ibex_sva import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"] - rel_path: "hw/ip/otbn/{sub_flow}/{tool}" + rel_path: "hw/ip/acc/{sub_flow}/{tool}" stopats: ["*if_stage_i.pc_mismatch_alert_o", "*icache_i.ecc_error_o", "*gen_regfile_ecc.rf_ecc_err_a", diff --git a/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc b/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc index c8fe774ef73..84d964c6666 100644 --- a/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc +++ b/hw/top_earlgrey/ip/ast/data/ast_cdc_abstract.sgdc @@ -341,7 +341,7 @@ abstract_port -ports "sns_clks_i[clk_io_div2_infra]" -ignore -comment "hanging p abstract_port -ports "sns_clks_i[clk_io_infra]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_infra]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_io_div4_infra]" -ignore -comment "hanging path" -abstract_port -ports "sns_clks_i[clk_main_otbn]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_acc]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_kmac]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_hmac]" -ignore -comment "hanging path" abstract_port -ports "sns_clks_i[clk_main_aes]" -ignore -comment "hanging path" diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 05fd4b0f926..93f9c504384 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -88,7 +88,7 @@ edn1 hmac rv_plic - otbn + acc keymgr kmac sram_ctrl_main.regs @@ -115,7 +115,7 @@ edn1 hmac rv_plic - otbn + acc keymgr kmac sram_ctrl_main.regs @@ -589,13 +589,13 @@ pipeline: true } { - name: otbn + name: acc type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: false rsp_fifo_pass: false - inst_type: otbn + inst_type: acc addr_range: [ { @@ -975,7 +975,7 @@ index: -1 } { - name: tl_otbn + name: tl_acc struct: tl package: tlul_pkg type: req_rsp @@ -983,7 +983,7 @@ inst_name: main width: 1 default: "" - top_signame: otbn_tl + top_signame: acc_tl index: -1 } { diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson index 06b93790393..5ffb5519fc2 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson @@ -147,7 +147,7 @@ } { struct: "tl" type: "req_rsp" - name: "tl_otbn" + name: "tl_acc" act: "req" package: "tlul_pkg" } diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 84f165db01c..798a33bb135 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -50,7 +50,7 @@ initial force dut.rst_spi_host1_ni = rst_n; `CONNECT_TL_DEVICE_IF(edn0, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(edn1, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(acc, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(keymgr, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rv_core_ibex__cfg, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(sram_ctrl_main__regs, dut, clk_main_i, rst_n) diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index de8866fb711..57b09ad29fa 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -90,10 +90,10 @@ -node tb.dut tl_edn1_o.a_address[31:31] -node tb.dut tl_rv_plic_o.a_address[29:28] -node tb.dut tl_rv_plic_o.a_address[31:31] --node tb.dut tl_otbn_o.a_address[19:17] --node tb.dut tl_otbn_o.a_address[23:22] --node tb.dut tl_otbn_o.a_address[29:25] --node tb.dut tl_otbn_o.a_address[31:31] +-node tb.dut tl_acc_o.a_address[19:17] +-node tb.dut tl_acc_o.a_address[23:22] +-node tb.dut tl_acc_o.a_address[29:25] +-node tb.dut tl_acc_o.a_address[31:31] -node tb.dut tl_keymgr_o.a_address[17:8] -node tb.dut tl_keymgr_o.a_address[19:19] -node tb.dut tl_keymgr_o.a_address[23:21] diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index 800ab22e991..1d632e22421 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -65,7 +65,7 @@ tl_device_t xbar_devices[$] = '{ '{"rv_plic", '{ '{32'h48000000, 32'h4fffffff} }}, - '{"otbn", '{ + '{"acc", '{ '{32'h41300000, 32'h4131ffff} }}, '{"keymgr", '{ @@ -109,7 +109,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr", "kmac", "sram_ctrl_main__regs", @@ -135,7 +135,7 @@ tl_host_t xbar_hosts[$] = '{ "edn1", "hmac", "rv_plic", - "otbn", + "acc", "keymgr", "kmac", "sram_ctrl_main__regs", diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index fe56a65c6db..dfe14bfd77d 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -140,11 +140,11 @@ module xbar_main_bind; .h2d (tl_rv_plic_o), .d2h (tl_rv_plic_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_otbn ( + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_acc ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .h2d (tl_otbn_o), - .d2h (tl_otbn_i) + .h2d (tl_acc_o), + .d2h (tl_acc_i) ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_keymgr ( .clk_i (clk_main_i), diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 9393377e872..7d0a51b3136 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -28,7 +28,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_SPACE_EDN0 = 32'h 41170000; localparam logic [31:0] ADDR_SPACE_EDN1 = 32'h 41180000; localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 48000000; - localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 41300000; + localparam logic [31:0] ADDR_SPACE_ACC = 32'h 41300000; localparam logic [31:0] ADDR_SPACE_KEYMGR = 32'h 41140000; localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX__CFG = 32'h 411f0000; localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__REGS = 32'h 411c0000; @@ -56,7 +56,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_EDN0 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff; - localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0001ffff; + localparam logic [31:0] ADDR_MASK_ACC = 32'h 0001ffff; localparam logic [31:0] ADDR_MASK_KEYMGR = 32'h 000000ff; localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG = 32'h 000000ff; localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f; @@ -85,7 +85,7 @@ package tl_main_pkg; TlEdn0 = 16, TlEdn1 = 17, TlRvPlic = 18, - TlOtbn = 19, + TlAcc = 19, TlKeymgr = 20, TlRvCoreIbexCfg = 21, TlSramCtrlMainRegs = 22, diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv index a5bee7720f9..9283c621c38 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -61,7 +61,7 @@ // -> sm1_51 // -> rv_plic // -> sm1_52 -// -> otbn +// -> acc // -> sm1_53 // -> keymgr // -> sm1_54 @@ -115,7 +115,7 @@ // -> sm1_51 // -> rv_plic // -> sm1_52 -// -> otbn +// -> acc // -> sm1_53 // -> keymgr // -> sm1_54 @@ -184,8 +184,8 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_edn1_i, output tlul_pkg::tl_h2d_t tl_rv_plic_o, input tlul_pkg::tl_d2h_t tl_rv_plic_i, - output tlul_pkg::tl_h2d_t tl_otbn_o, - input tlul_pkg::tl_d2h_t tl_otbn_i, + output tlul_pkg::tl_h2d_t tl_acc_o, + input tlul_pkg::tl_d2h_t tl_acc_i, output tlul_pkg::tl_h2d_t tl_keymgr_o, input tlul_pkg::tl_d2h_t tl_keymgr_i, output tlul_pkg::tl_h2d_t tl_rv_core_ibex__cfg_o, @@ -657,8 +657,8 @@ module xbar_main ( assign tl_rv_plic_o = tl_sm1_51_ds_h2d; assign tl_sm1_51_ds_d2h = tl_rv_plic_i; - assign tl_otbn_o = tl_sm1_52_ds_h2d; - assign tl_sm1_52_ds_d2h = tl_otbn_i; + assign tl_acc_o = tl_sm1_52_ds_h2d; + assign tl_sm1_52_ds_d2h = tl_acc_i; assign tl_keymgr_o = tl_sm1_53_ds_h2d; assign tl_sm1_53_ds_d2h = tl_keymgr_i; @@ -778,7 +778,7 @@ end dev_sel_s1n_32 = 5'd18; end else if ((tl_s1n_32_us_h2d.a_address & - ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + ~(ADDR_MASK_ACC)) == ADDR_SPACE_ACC) begin dev_sel_s1n_32 = 5'd19; end else if ((tl_s1n_32_us_h2d.a_address & @@ -881,7 +881,7 @@ end dev_sel_s1n_57 = 5'd18; end else if ((tl_s1n_57_us_h2d.a_address & - ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + ~(ADDR_MASK_ACC)) == ADDR_SPACE_ACC) begin dev_sel_s1n_57 = 5'd19; end else if ((tl_s1n_57_us_h2d.a_address & diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson index ca14e38ad48..21a56fa7542 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson @@ -90,7 +90,7 @@ 5'd23, 5'd23, 5'd22, - 5'd22, + 5'd21, 5'd21, 5'd20, 5'd20, diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson index 10ee78d58e2..2d250bc3bf9 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson @@ -128,7 +128,7 @@ 5'd20 5'd20 5'd21 - 5'd22 + 5'd21 5'd22 5'd23 5'd23 diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv index 6ad3baacd6a..e7e11bd14e6 100644 --- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -30,7 +30,7 @@ package alert_handler_reg_pkg; 5'd23, 5'd23, 5'd22, - 5'd22, + 5'd21, 5'd21, 5'd20, 5'd20, diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr.hjson b/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr.hjson index 3f8ed4b8ae2..7b0ef4c7ee6 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr.hjson +++ b/hw/top_earlgrey/ip_autogen/clkmgr/data/clkmgr.hjson @@ -96,6 +96,9 @@ { name: "CLKMGR.ENABLE.USB", desc: "Gating of USB peripheral clock." } + { name: "CLKMGR.HINT.ACC", + desc: "Gating of ACC transactional clock." + } { name: "CLKMGR.HINT.AES", desc: "Gating of AES transactional clock." } @@ -105,9 +108,6 @@ { name: "CLKMGR.HINT.KMAC", desc: "Gating of KMAC transactional clock." } - { name: "CLKMGR.HINT.OTBN", - desc: "Gating of OTBN transactional clock." - } { name: "CLKMGR.MEAS_CTRL.REGWEN", desc: '''Control modification of all clock frequency and timeout measurements. @@ -515,6 +515,15 @@ fields: [ { bits: "0", + name: "CLK_MAIN_ACC_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_ACC can be disabled. + 1 CLK_MAIN_ACC is enabled. + ''' + } + { + bits: "1", name: "CLK_MAIN_AES_HINT", resval: 1, desc: ''' @@ -523,7 +532,7 @@ ''' } { - bits: "1", + bits: "2", name: "CLK_MAIN_HMAC_HINT", resval: 1, desc: ''' @@ -532,7 +541,7 @@ ''' } { - bits: "2", + bits: "3", name: "CLK_MAIN_KMAC_HINT", resval: 1, desc: ''' @@ -540,15 +549,6 @@ 1 CLK_MAIN_KMAC is enabled. ''' } - { - bits: "3", - name: "CLK_MAIN_OTBN_HINT", - resval: 1, - desc: ''' - 0 CLK_MAIN_OTBN can be disabled. - 1 CLK_MAIN_OTBN is enabled. - ''' - } ] // the CLK_HINT register cannot be written. // During top level randomized tests, it is possible to disable the clocks to transactional blocks @@ -567,6 +567,15 @@ fields: [ { bits: "0", + name: "CLK_MAIN_ACC_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_ACC is disabled. + 1 CLK_MAIN_ACC is enabled. + ''' + } + { + bits: "1", name: "CLK_MAIN_AES_VAL", resval: 1, desc: ''' @@ -575,7 +584,7 @@ ''' } { - bits: "1", + bits: "2", name: "CLK_MAIN_HMAC_VAL", resval: 1, desc: ''' @@ -584,7 +593,7 @@ ''' } { - bits: "2", + bits: "3", name: "CLK_MAIN_KMAC_VAL", resval: 1, desc: ''' @@ -592,15 +601,6 @@ 1 CLK_MAIN_KMAC is enabled. ''' } - { - bits: "3", - name: "CLK_MAIN_OTBN_VAL", - resval: 1, - desc: ''' - 0 CLK_MAIN_OTBN is disabled. - 1 CLK_MAIN_OTBN is enabled. - ''' - } ] // the CLK_HINT_STATUS register is read-only and cannot be checked. // This register's value depends on the IDLE inputs, so cannot be predicted. diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson index e2656bef809..2b5338c11f8 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/clkmgr/data/top_earlgrey_clkmgr.ipconfig.hjson @@ -210,6 +210,11 @@ } hint_clks: { + clk_main_acc: + { + src_name: main + endpoint_ip: acc + } clk_main_aes: { src_name: main @@ -225,19 +230,14 @@ src_name: main endpoint_ip: kmac } - clk_main_otbn: - { - src_name: main - endpoint_ip: otbn - } } } hint_names: { + clk_main_acc: HintMainAcc clk_main_aes: HintMainAes clk_main_hmac: HintMainHmac clk_main_kmac: HintMainKmac - clk_main_otbn: HintMainOtbn } parent_child_clks: { diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/doc/registers.md b/hw/top_earlgrey/ip_autogen/clkmgr/doc/registers.md index f5e86d97394..8faa827ef88 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/doc/registers.md +++ b/hw/top_earlgrey/ip_autogen/clkmgr/doc/registers.md @@ -211,16 +211,16 @@ feedback in this case. ### Fields ```wavejson -{"reg": [{"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +{"reg": [{"name": "CLK_MAIN_ACC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} ``` | Bits | Type | Reset | Name | Description | |:------:|:------:|:-------:|:-------------------|:-------------------------------------------------------------| | 31:4 | | | | Reserved | -| 3 | rw | 0x1 | CLK_MAIN_OTBN_HINT | 0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled. | -| 2 | rw | 0x1 | CLK_MAIN_KMAC_HINT | 0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled. | -| 1 | rw | 0x1 | CLK_MAIN_HMAC_HINT | 0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled. | -| 0 | rw | 0x1 | CLK_MAIN_AES_HINT | 0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled. | +| 3 | rw | 0x1 | CLK_MAIN_KMAC_HINT | 0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled. | +| 2 | rw | 0x1 | CLK_MAIN_HMAC_HINT | 0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled. | +| 1 | rw | 0x1 | CLK_MAIN_AES_HINT | 0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled. | +| 0 | rw | 0x1 | CLK_MAIN_ACC_HINT | 0 CLK_MAIN_ACC can be disabled. 1 CLK_MAIN_ACC is enabled. | ## CLK_HINTS_STATUS Since the final state of [`CLK_HINTS`](#clk_hints) is not always determined by software, @@ -233,16 +233,16 @@ this register provides read feedback for the current clock state. ### Fields ```wavejson -{"reg": [{"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +{"reg": [{"name": "CLK_MAIN_ACC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} ``` | Bits | Type | Reset | Name | Description | |:------:|:------:|:-------:|:------------------|:---------------------------------------------------------| | 31:4 | | | | Reserved | -| 3 | ro | 0x1 | CLK_MAIN_OTBN_VAL | 0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled. | -| 2 | ro | 0x1 | CLK_MAIN_KMAC_VAL | 0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled. | -| 1 | ro | 0x1 | CLK_MAIN_HMAC_VAL | 0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled. | -| 0 | ro | 0x1 | CLK_MAIN_AES_VAL | 0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled. | +| 3 | ro | 0x1 | CLK_MAIN_KMAC_VAL | 0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled. | +| 2 | ro | 0x1 | CLK_MAIN_HMAC_VAL | 0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled. | +| 1 | ro | 0x1 | CLK_MAIN_AES_VAL | 0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled. | +| 0 | ro | 0x1 | CLK_MAIN_ACC_VAL | 0 CLK_MAIN_ACC is disabled. 1 CLK_MAIN_ACC is enabled. | ## MEASURE_CTRL_REGWEN Measurement control write enable diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/doc/theory_of_operation.md b/hw/top_earlgrey/ip_autogen/clkmgr/doc/theory_of_operation.md index 6836a2c953f..58f34778ff3 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/doc/theory_of_operation.md +++ b/hw/top_earlgrey/ip_autogen/clkmgr/doc/theory_of_operation.md @@ -19,7 +19,7 @@ The table shows the group name, the modules that belong to each group, and wheth | Group | Frequencies | Modules | Software | Wait for Interrupt | | ------------- | ------------------------------ | -------------------------------------------------------------- | -------------- | ------------------ | | Power-up | 100~200KHz, 24MHz | Clock Manager, Power Manager, Reset Manager, Pinmux | No | No | -| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Otbn | Yes (1) | Yes (2) | +| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Acc | Yes (1) | Yes (2) | | Infrastructural | 24MHz, ~100MHz | Fabric, Fabric gaskets (iopmp), Memories | No | Yes (3) | | Security | 24MHz, ~100MHz | Alert handler, Entropy, Life cycle, Plic, Sensors | No | No | | Peripheral | 24MHz, 48MHz, 96MHz | I2c, Spi, Uart, Usb, others | Yes | Yes | @@ -175,7 +175,7 @@ Note, the power manager's request to turn off clocks supersedes all other local This means even if a particular clock is turned on by the clock manager (for example a transactional unit that is ongoing or a peripheral that is enabled), the power manager requests will still turn clocks on / off at the root. This makes it software's responsibility to ensure low power entry requests (which can only be initiated by software) do not conflict with any ongoing activities controlled by software. -For example, software should ensure that Aes / Otbn activities have completed before initializing a low power entry process. +For example, software should ensure that Aes / Acc activities have completed before initializing a low power entry process. ### Clock Division diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/README.md b/hw/top_earlgrey/ip_autogen/clkmgr/dv/README.md index 1619c98549b..a4e3438c900 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/README.md +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/README.md @@ -57,7 +57,7 @@ All common types and methods defined at the package level can be found in PeriIo, PeriUsb } peri_e; - typedef enum int {TransAes, TransHmac, TransKmac, TransOtbn} trans_e; + typedef enum int {TransAes, TransHmac, TransKmac, TransAcc} trans_e; ``` ### TL_agent diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el b/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el index ca5f99828dd..326e1d3c68c 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el @@ -24,7 +24,7 @@ INSTANCE: tb.dut.u_clk_main_kmac_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "2301929872 1660332954" -INSTANCE: tb.dut.u_clk_main_otbn_trans.u_idle_cnt +INSTANCE: tb.dut.u_clk_main_acc_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "953655365 3155586170" diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el b/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el index 85e292d7a9f..761e9fac2e7 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el @@ -25,7 +25,7 @@ INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3274445021" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3554514034" @@ -47,7 +47,7 @@ Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" CHECKSUM: "2972535896 3554514034" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv index 596ff403326..c28b698b8fc 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv @@ -70,16 +70,16 @@ package clkmgr_env_pkg; } clk_enables_t; typedef enum int { + TransAcc, TransAes, TransHmac, - TransKmac, - TransOtbn + TransKmac } trans_e; typedef struct packed { - logic otbn; logic kmac; logic hmac; logic aes; + logic acc; } clk_hints_t; typedef struct { diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_if.sv b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_if.sv index 5af3e7f9b0f..4b226420555 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_if.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/clkmgr_if.sv @@ -73,19 +73,19 @@ interface clkmgr_if ( clk_hints_t clk_hints_csr; always_comb clk_hints_csr = '{ - otbn: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_otbn_hint.q, kmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_kmac_hint.q, hmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_hmac_hint.q, - aes: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_aes_hint.q + aes: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_aes_hint.q, + acc: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_acc_hint.q }; clk_hints_t clk_hints_status_csr; always_comb clk_hints_status_csr = '{ - otbn: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_otbn_val_qs, kmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_kmac_val_qs, hmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_hmac_val_qs, - aes: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_aes_val_qs + aes: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_aes_val_qs, + acc: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_acc_val_qs }; prim_mubi_pkg::mubi4_t extclk_ctrl_csr_sel; diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv index 6807809aec3..520c511f26c 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv @@ -68,10 +68,10 @@ class clkmgr_smoke_vseq extends clkmgr_base_vseq; uvm_reg_field value_bit; } trans_descriptor_t; trans_descriptor_t trans_descriptors[NUM_TRANS] = '{ + '{TransAcc, ral.clk_hints.clk_main_acc_hint, ral.clk_hints_status.clk_main_acc_val}, '{TransAes, ral.clk_hints.clk_main_aes_hint, ral.clk_hints_status.clk_main_aes_val}, '{TransHmac, ral.clk_hints.clk_main_hmac_hint, ral.clk_hints_status.clk_main_hmac_val}, - '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val}, - '{TransOtbn, ral.clk_hints.clk_main_otbn_hint, ral.clk_hints_status.clk_main_otbn_val} + '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val} }; idle = 0; // Changes in idle take at least 10 cycles to stick. diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv b/hw/top_earlgrey/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv index ff8887b93bd..a46c4cf14a1 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv @@ -71,6 +71,16 @@ module clkmgr_bind; ); // Assertions for transactional clocks. + bind clkmgr clkmgr_trans_sva_if clkmgr_acc_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_acc_hint.q), + .idle(idle_i[HintMainAcc] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_acc_val.d), + .trans_clk(clocks_o.clk_main_acc) + ); + bind clkmgr clkmgr_trans_sva_if clkmgr_aes_trans_sva_if ( .clk(clk_main_i), .rst_n(rst_main_ni), @@ -101,16 +111,6 @@ module clkmgr_bind; .trans_clk(clocks_o.clk_main_kmac) ); - bind clkmgr clkmgr_trans_sva_if clkmgr_otbn_trans_sva_if ( - .clk(clk_main_i), - .rst_n(rst_main_ni), - .hint(reg2hw.clk_hints.clk_main_otbn_hint.q), - .idle(idle_i[HintMainOtbn] == prim_mubi_pkg::MuBi4True), - .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), - .status(hw2reg.clk_hints_status.clk_main_otbn_val.d), - .trans_clk(clocks_o.clk_main_otbn) - ); - bind clkmgr clkmgr_extclk_sva_if clkmgr_extclk_sva_if ( .clk_i, .rst_ni, @@ -292,6 +292,15 @@ module clkmgr_bind; ); // Hint controlled gating enables. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_acc ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_acc_trans.sw_hint_synced || !u_clk_main_acc_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_acc == prim_mubi_pkg::MuBi4True) + ); + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_aes ( .clk(clk_main_i), .rst_n(rst_main_ni), @@ -319,15 +328,6 @@ module clkmgr_bind; .cg_en(cg_en_o.main_kmac == prim_mubi_pkg::MuBi4True) ); - bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_otbn ( - .clk(clk_main_i), - .rst_n(rst_main_ni), - .ip_clk_en(clk_main_en), - .sw_clk_en(u_clk_main_otbn_trans.sw_hint_synced || !u_clk_main_otbn_trans.idle_valid), - .scanmode(prim_mubi_pkg::MuBi4False), - .cg_en(cg_en_o.main_otbn == prim_mubi_pkg::MuBi4True) - ); - // Calibration assertions. bind clkmgr clkmgr_lost_calib_regwen_sva_if clkmgr_lost_calib_regwen_sva_if ( .clk(clk_i), diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/dv/tb.sv b/hw/top_earlgrey/ip_autogen/clkmgr/dv/tb.sv index 022e0d237a6..e2c8aa933db 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/dv/tb.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/dv/tb.sv @@ -115,7 +115,7 @@ module tb; reg2hw.clk_enables.clk_io_div2_peri_en.q, reg2hw.clk_enables.clk_io_div4_peri_en.q}), .clk_hints({ - reg2hw.clk_hints.clk_main_otbn_hint.q, + reg2hw.clk_hints.clk_main_acc_hint.q, reg2hw.clk_hints.clk_main_kmac_hint.q, reg2hw.clk_hints.clk_main_hmac_hint.q, reg2hw.clk_hints.clk_main_aes_hint.q}) diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv index 15ce77cd4a5..86337807407 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr.sv @@ -974,6 +974,28 @@ logic [3:0] idle_cnt_err; + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_acc_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainAcc]), + .sw_hint_i(reg2hw.clk_hints.clk_main_acc_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_acc), + .clk_o(clocks_o.clk_main_acc), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_acc_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainAcc]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainAccCountCheck_A, + u_clk_main_acc_trans.u_idle_cnt, + alert_tx_o[1]) + clkmgr_trans #( .FpgaBufGlobal(1'b0) // This clock is used primarily locally. ) u_clk_main_aes_trans ( @@ -1039,36 +1061,14 @@ ClkMainKmacCountCheck_A, u_clk_main_kmac_trans.u_idle_cnt, alert_tx_o[1]) - - clkmgr_trans #( - .FpgaBufGlobal(1'b0) // This clock is used primarily locally. - ) u_clk_main_otbn_trans ( - .clk_i(clk_main), - .clk_gated_i(clk_main_root), - .rst_ni(rst_main_ni), - .en_i(clk_main_en), - .idle_i(idle_i[HintMainOtbn]), - .sw_hint_i(reg2hw.clk_hints.clk_main_otbn_hint.q), - .scanmode_i, - .alert_cg_en_o(cg_en_o.main_otbn), - .clk_o(clocks_o.clk_main_otbn), - .clk_reg_i(clk_i), - .rst_reg_ni(rst_ni), - .reg_en_o(hw2reg.clk_hints_status.clk_main_otbn_val.d), - .reg_cnt_err_o(idle_cnt_err[HintMainOtbn]) - ); - `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( - ClkMainOtbnCountCheck_A, - u_clk_main_otbn_trans.u_idle_cnt, - alert_tx_o[1]) assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1; assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err; // state readback + assign hw2reg.clk_hints_status.clk_main_acc_val.de = 1'b1; assign hw2reg.clk_hints_status.clk_main_aes_val.de = 1'b1; assign hw2reg.clk_hints_status.clk_main_hmac_val.de = 1'b1; assign hw2reg.clk_hints_status.clk_main_kmac_val.de = 1'b1; - assign hw2reg.clk_hints_status.clk_main_otbn_val.de = 1'b1; // SEC_CM: JITTER.CONFIG.MUBI assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q); diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv index a768ab6e184..25fbd9bfe1b 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv @@ -5,10 +5,10 @@ package clkmgr_pkg; typedef enum int { - HintMainAes = 0, - HintMainHmac = 1, - HintMainKmac = 2, - HintMainOtbn = 3 + HintMainAcc = 0, + HintMainAes = 1, + HintMainHmac = 2, + HintMainKmac = 3 } hint_names_e; // clocks generated and broadcast @@ -22,10 +22,10 @@ package clkmgr_pkg; logic clk_aon_secure; logic clk_aon_peri; logic clk_aon_timers; + logic clk_main_acc; logic clk_main_aes; logic clk_main_hmac; logic clk_main_kmac; - logic clk_main_otbn; logic clk_io_div4_infra; logic clk_main_infra; logic clk_usb_infra; @@ -51,10 +51,10 @@ package clkmgr_pkg; prim_mubi_pkg::mubi4_t aon_secure; prim_mubi_pkg::mubi4_t aon_peri; prim_mubi_pkg::mubi4_t aon_timers; + prim_mubi_pkg::mubi4_t main_acc; prim_mubi_pkg::mubi4_t main_aes; prim_mubi_pkg::mubi4_t main_hmac; prim_mubi_pkg::mubi4_t main_kmac; - prim_mubi_pkg::mubi4_t main_otbn; prim_mubi_pkg::mubi4_t io_div4_infra; prim_mubi_pkg::mubi4_t main_infra; prim_mubi_pkg::mubi4_t usb_infra; diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv index f0faeca39e1..df8ea382784 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv @@ -68,9 +68,6 @@ package clkmgr_reg_pkg; } clkmgr_reg2hw_clk_enables_reg_t; typedef struct packed { - struct packed { - logic q; - } clk_main_otbn_hint; struct packed { logic q; } clk_main_kmac_hint; @@ -80,6 +77,9 @@ package clkmgr_reg_pkg; struct packed { logic q; } clk_main_aes_hint; + struct packed { + logic q; + } clk_main_acc_hint; } clkmgr_reg2hw_clk_hints_reg_t; typedef struct packed { @@ -168,10 +168,6 @@ package clkmgr_reg_pkg; } clkmgr_hw2reg_extclk_status_reg_t; typedef struct packed { - struct packed { - logic d; - logic de; - } clk_main_otbn_val; struct packed { logic d; logic de; @@ -184,6 +180,10 @@ package clkmgr_reg_pkg; logic d; logic de; } clk_main_aes_val; + struct packed { + logic d; + logic de; + } clk_main_acc_val; } clkmgr_hw2reg_clk_hints_status_reg_t; typedef struct packed { diff --git a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv index af8e55bbab3..410c0cdafc7 100644 --- a/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv +++ b/hw/top_earlgrey/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv @@ -164,18 +164,18 @@ module clkmgr_reg_top ( logic clk_enables_clk_usb_peri_en_qs; logic clk_enables_clk_usb_peri_en_wd; logic clk_hints_we; + logic clk_hints_clk_main_acc_hint_qs; + logic clk_hints_clk_main_acc_hint_wd; logic clk_hints_clk_main_aes_hint_qs; logic clk_hints_clk_main_aes_hint_wd; logic clk_hints_clk_main_hmac_hint_qs; logic clk_hints_clk_main_hmac_hint_wd; logic clk_hints_clk_main_kmac_hint_qs; logic clk_hints_clk_main_kmac_hint_wd; - logic clk_hints_clk_main_otbn_hint_qs; - logic clk_hints_clk_main_otbn_hint_wd; + logic clk_hints_status_clk_main_acc_val_qs; logic clk_hints_status_clk_main_aes_val_qs; logic clk_hints_status_clk_main_hmac_val_qs; logic clk_hints_status_clk_main_kmac_val_qs; - logic clk_hints_status_clk_main_otbn_val_qs; logic measure_ctrl_regwen_we; logic measure_ctrl_regwen_qs; logic measure_ctrl_regwen_wd; @@ -1004,19 +1004,19 @@ module clkmgr_reg_top ( // R[clk_hints]: V(False) - // F[clk_main_aes_hint]: 0:0 + // F[clk_main_acc_hint]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_aes_hint ( + ) u_clk_hints_clk_main_acc_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_aes_hint_wd), + .wd (clk_hints_clk_main_acc_hint_wd), // from internal hardware .de (1'b0), @@ -1024,26 +1024,26 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_aes_hint.q), + .q (reg2hw.clk_hints.clk_main_acc_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_aes_hint_qs) + .qs (clk_hints_clk_main_acc_hint_qs) ); - // F[clk_main_hmac_hint]: 1:1 + // F[clk_main_aes_hint]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_hmac_hint ( + ) u_clk_hints_clk_main_aes_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_hmac_hint_wd), + .wd (clk_hints_clk_main_aes_hint_wd), // from internal hardware .de (1'b0), @@ -1051,26 +1051,26 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_hmac_hint.q), + .q (reg2hw.clk_hints.clk_main_aes_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_hmac_hint_qs) + .qs (clk_hints_clk_main_aes_hint_qs) ); - // F[clk_main_kmac_hint]: 2:2 + // F[clk_main_hmac_hint]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_kmac_hint ( + ) u_clk_hints_clk_main_hmac_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_kmac_hint_wd), + .wd (clk_hints_clk_main_hmac_hint_wd), // from internal hardware .de (1'b0), @@ -1078,26 +1078,26 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_kmac_hint.q), + .q (reg2hw.clk_hints.clk_main_hmac_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_kmac_hint_qs) + .qs (clk_hints_clk_main_hmac_hint_qs) ); - // F[clk_main_otbn_hint]: 3:3 + // F[clk_main_kmac_hint]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_clk_main_otbn_hint ( + ) u_clk_hints_clk_main_kmac_hint ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (clk_hints_we), - .wd (clk_hints_clk_main_otbn_hint_wd), + .wd (clk_hints_clk_main_kmac_hint_wd), // from internal hardware .de (1'b0), @@ -1105,22 +1105,22 @@ module clkmgr_reg_top ( // to internal hardware .qe (), - .q (reg2hw.clk_hints.clk_main_otbn_hint.q), + .q (reg2hw.clk_hints.clk_main_kmac_hint.q), .ds (), // to register interface (read) - .qs (clk_hints_clk_main_otbn_hint_qs) + .qs (clk_hints_clk_main_kmac_hint_qs) ); // R[clk_hints_status]: V(False) - // F[clk_main_aes_val]: 0:0 + // F[clk_main_acc_val]: 0:0 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_aes_val ( + ) u_clk_hints_status_clk_main_acc_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1129,8 +1129,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_aes_val.de), - .d (hw2reg.clk_hints_status.clk_main_aes_val.d), + .de (hw2reg.clk_hints_status.clk_main_acc_val.de), + .d (hw2reg.clk_hints_status.clk_main_acc_val.d), // to internal hardware .qe (), @@ -1138,16 +1138,16 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_aes_val_qs) + .qs (clk_hints_status_clk_main_acc_val_qs) ); - // F[clk_main_hmac_val]: 1:1 + // F[clk_main_aes_val]: 1:1 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_hmac_val ( + ) u_clk_hints_status_clk_main_aes_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1156,8 +1156,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_hmac_val.de), - .d (hw2reg.clk_hints_status.clk_main_hmac_val.d), + .de (hw2reg.clk_hints_status.clk_main_aes_val.de), + .d (hw2reg.clk_hints_status.clk_main_aes_val.d), // to internal hardware .qe (), @@ -1165,16 +1165,16 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_hmac_val_qs) + .qs (clk_hints_status_clk_main_aes_val_qs) ); - // F[clk_main_kmac_val]: 2:2 + // F[clk_main_hmac_val]: 2:2 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_kmac_val ( + ) u_clk_hints_status_clk_main_hmac_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1183,8 +1183,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_kmac_val.de), - .d (hw2reg.clk_hints_status.clk_main_kmac_val.d), + .de (hw2reg.clk_hints_status.clk_main_hmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_hmac_val.d), // to internal hardware .qe (), @@ -1192,16 +1192,16 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_kmac_val_qs) + .qs (clk_hints_status_clk_main_hmac_val_qs) ); - // F[clk_main_otbn_val]: 3:3 + // F[clk_main_kmac_val]: 3:3 prim_subreg #( .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) - ) u_clk_hints_status_clk_main_otbn_val ( + ) u_clk_hints_status_clk_main_kmac_val ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1210,8 +1210,8 @@ module clkmgr_reg_top ( .wd ('0), // from internal hardware - .de (hw2reg.clk_hints_status.clk_main_otbn_val.de), - .d (hw2reg.clk_hints_status.clk_main_otbn_val.d), + .de (hw2reg.clk_hints_status.clk_main_kmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_kmac_val.d), // to internal hardware .qe (), @@ -1219,7 +1219,7 @@ module clkmgr_reg_top ( .ds (), // to register interface (read) - .qs (clk_hints_status_clk_main_otbn_val_qs) + .qs (clk_hints_status_clk_main_kmac_val_qs) ); @@ -2509,13 +2509,13 @@ module clkmgr_reg_top ( assign clk_enables_clk_usb_peri_en_wd = reg_wdata[3]; assign clk_hints_we = addr_hit[7] & reg_we & !reg_error; - assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0]; + assign clk_hints_clk_main_acc_hint_wd = reg_wdata[0]; - assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1]; + assign clk_hints_clk_main_aes_hint_wd = reg_wdata[1]; - assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2]; + assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[2]; - assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3]; + assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[3]; assign measure_ctrl_regwen_we = addr_hit[9] & reg_we & !reg_error; assign measure_ctrl_regwen_wd = reg_wdata[0]; @@ -2637,17 +2637,17 @@ module clkmgr_reg_top ( end addr_hit[7]: begin - reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs; - reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs; - reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs; - reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs; + reg_rdata_next[0] = clk_hints_clk_main_acc_hint_qs; + reg_rdata_next[1] = clk_hints_clk_main_aes_hint_qs; + reg_rdata_next[2] = clk_hints_clk_main_hmac_hint_qs; + reg_rdata_next[3] = clk_hints_clk_main_kmac_hint_qs; end addr_hit[8]: begin - reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs; - reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs; - reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs; - reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs; + reg_rdata_next[0] = clk_hints_status_clk_main_acc_val_qs; + reg_rdata_next[1] = clk_hints_status_clk_main_aes_val_qs; + reg_rdata_next[2] = clk_hints_status_clk_main_hmac_val_qs; + reg_rdata_next[3] = clk_hints_status_clk_main_kmac_val_qs; end addr_hit[9]: begin diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl.hjson b/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl.hjson index 966353ac42d..bc78a3b701a 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl.hjson +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl.hjson @@ -1912,14 +1912,14 @@ package: "otp_ctrl_pkg" desc: "Array with key derivation interfaces for SRAM scrambling devices." } - // Key request from OTBN RAM Scrambler - { struct: "otbn_otp_key" + // Key request from ACC RAM Scrambler + { struct: "acc_otp_key" type: "req_rsp" - name: "otbn_otp_key" + name: "acc_otp_key" act: "rsp" default: "'0" package: "otp_ctrl_pkg" - desc: "Key derivation interface for OTBN scrambling devices." + desc: "Key derivation interface for ACC scrambling devices." } // Hardware config partition { struct: "otp_broadcast" diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson b/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson index 2b60cdc05b1..c2217409e34 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson @@ -40,7 +40,7 @@ - drive pwrmgr's request pin to trigger OTP initialization after reset, check status after OTP initialization - - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `otbn` + - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `acc` - randomly issue LC program request - write random values to random addresses within each OTP partition - read out the random selected write addresses, check if the readout values are expected @@ -143,7 +143,7 @@ { name: interface_key_check desc: ''' - OTP_CTRL will generate keys to `flash`, `sram`, and `otbn` upon their requests. + OTP_CTRL will generate keys to `flash`, `sram`, and `acc` upon their requests. Based on the DAI access sequence, this test will run key requests sequence in parallel, and check if correct keys are generated. ''' @@ -271,8 +271,8 @@ desc: '''Covers whether secret1 partition is locked during all `srams` key request.''' } { - name: otbn_req_cg - desc: '''Covers whether secret1 partition is locked during `otbn` key request.''' + name: acc_req_cg + desc: '''Covers whether secret1 partition is locked during `acc` key request.''' } { name: lc_prog_cg @@ -385,7 +385,7 @@ ''' } { - name: otbn_req_condition_cg + name: acc_req_condition_cg desc: '''Covers the following conditions when `lc_escalation_en` is On: - whether any key requests is in progress - whether DAI interface is busy diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/interfaces.md b/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/interfaces.md index f3a9041e54f..2132890ccc5 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/interfaces.md +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/interfaces.md @@ -40,7 +40,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt | otp_keymgr_key | otp_ctrl_pkg::otp_keymgr_key | uni | req | 1 | Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. | | flash_otp_key | otp_ctrl_pkg::flash_otp_key | req_rsp | rsp | 1 | Key derivation interface for FLASH scrambling. | | sram_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | rsp | 4 | Array with key derivation interfaces for SRAM scrambling devices. | -| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | rsp | 1 | Key derivation interface for OTBN scrambling devices. | +| acc_otp_key | otp_ctrl_pkg::acc_otp_key | req_rsp | rsp | 1 | Key derivation interface for ACC scrambling devices. | | otp_broadcast | otp_ctrl_part_pkg::otp_broadcast | uni | req | 1 | Output of the HW partitions with breakout data types. | | otp_macro | otp_ctrl_macro_pkg::otp_ctrl_macro | req_rsp | req | 1 | Data interface for the OTP macro. | | core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | @@ -214,21 +214,21 @@ Otherwise, this signal is tied to a random netlist constant. Since the key manager may run in a different clock domain, key manager is responsible for synchronizing the `otp_keymgr_key_o` signals. -### Interfaces to SRAM and OTBN Scramblers +### Interfaces to SRAM and ACC Scramblers -The interfaces to the SRAM and OTBN scrambling devices follow a req / ack protocol, where the scrambling device first requests a new ephemeral key by asserting the request channel (`sram_otp_key_i[*]`, `otbn_otp_key_i`). +The interfaces to the SRAM and ACC scrambling devices follow a req / ack protocol, where the scrambling device first requests a new ephemeral key by asserting the request channel (`sram_otp_key_i[*]`, `acc_otp_key_i`). The OTP controller then fetches entropy from EDN and derives an ephemeral key using the SRAM_DATA_KEY_SEED and the [PRESENT scrambling data path](#scrambling-datapath). -Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `otbn_otp_key_o`), which complete the req / ack handshake. -The wave diagram below illustrates this process for the OTBN scrambling device. +Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `acc_otp_key_o`), which complete the req / ack handshake. +The wave diagram below illustrates this process for the ACC scrambling device. ```wavejson {signal: [ {name: 'clk_i', wave: 'p.......'}, - {name: 'otbn_otp_key_i.req', wave: '01.|..0.'}, - {name: 'otbn_otp_key_o.ack', wave: '0..|.10.'}, - {name: 'otbn_otp_key_o.nonce', wave: '0..|.30.'}, - {name: 'otbn_otp_key_o.key', wave: '0..|.30.'}, - {name: 'otbn_otp_key_o.seed_valid', wave: '0..|.10.'}, + {name: 'acc_otp_key_i.req', wave: '01.|..0.'}, + {name: 'acc_otp_key_o.ack', wave: '0..|.10.'}, + {name: 'acc_otp_key_o.nonce', wave: '0..|.30.'}, + {name: 'acc_otp_key_o.key', wave: '0..|.30.'}, + {name: 'acc_otp_key_o.seed_valid', wave: '0..|.10.'}, ]} ``` @@ -268,7 +268,7 @@ If the key seeds have not yet been provisioned, the keys are derived from all-ze The resulting scrambling key is still ephemeral (i.e., it is derived using entropy from CSRNG) and okay to be used. Note that the req/ack protocol runs on the OTP clock. -It is the task of the scrambling device to perform the synchronization as described in the previous subsection on the [interface to SRAM and OTBN scramblers](#interface-to-sram-and-otbn-scramblers). +It is the task of the scrambling device to perform the synchronization as described in the previous subsection on the [interface to SRAM and ACC scramblers](#interface-to-sram-and-acc-scramblers). ### Hardware Config Bits diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/theory_of_operation.md b/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/theory_of_operation.md index ced9c642c8d..b283427e41e 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/theory_of_operation.md +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/theory_of_operation.md @@ -426,7 +426,7 @@ In case of unrecoverable OTP errors, the FSM signals an error to the life cycle ![Key Derivation Interface FSM](otp_ctrl_kdi_fsm.svg) Upon reset release the KDI FSM waits until the OTP controller has initialized and the KDI gets enabled. -Once it is in the idle state, key derivation can be requested via the [flash](interfaces.md#interface-to-flash-scrambler) and [sram](interfaces.md#interface-to-sram-and-otbn-scramblers) interfaces. +Once it is in the idle state, key derivation can be requested via the [flash](interfaces.md#interface-to-flash-scrambler) and [sram](interfaces.md#interface-to-sram-and-acc-scramblers) interfaces. Based on which interface makes the request, the KDI controller will evaluate a variant of the PRESENT digest mechanism as described in more detail below. ### Scrambling Datapath diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/README.md b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/README.md index 9be5f533377..6503de79487 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/README.md +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/README.md @@ -64,7 +64,7 @@ fatal_check_alert and fatal_macro_alert. The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in OTP_CTRL device. ### OTP_CTRL interface -OTP_CTRL design has specific inputs and outputs to communicate with other IPs including LC_CTRL, OTBN, SRAM, FLASH etc. +OTP_CTRL design has specific inputs and outputs to communicate with other IPs including LC_CTRL, ACC, SRAM, FLASH etc. This interface is created to initialize, use simple task to drive, and use assertions to monitor these signals. ### Memory backdoor interface @@ -107,7 +107,7 @@ It creates the following analysis ports to retrieve the data monitored by corres * tl_d_chan_fifo: tl data channel * alert_fifos: alert handshakes * sram_fifos: sram requests -* otbn_fifo: otbn request +* acc_fifo: acc request * lc_prog_fifo: life cycle programming request * lc_token_fifo: life cycle token request * flash_addr_fifo: flash address request diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv index 06b9f4cce51..d9364c91ab7 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv @@ -33,7 +33,7 @@ module otp_ctrl_cov_bind; .lc_escalate_en_i (lc_escalate_en_i), .flash_otp_key_i (flash_otp_key_i), .sram_otp_key_i (sram_otp_key_i), - .otbn_otp_key_i (otbn_otp_key_i) + .acc_otp_key_i (acc_otp_key_i) ); bind otp_ctrl cip_lc_tx_cov_if u_lc_creator_seed_sw_rw_en_cov_if ( diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv index 106178b8806..e2e654b9673 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv @@ -12,7 +12,7 @@ interface otp_ctrl_cov_if input bit [3:0] lc_escalate_en_i, input otp_ctrl_pkg::flash_otp_key_req_t flash_otp_key_i, input otp_ctrl_pkg::sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, - input otp_ctrl_pkg::otbn_otp_key_req_t otbn_otp_key_i + input otp_ctrl_pkg::acc_otp_key_req_t acc_otp_key_i ); import uvm_pkg::*; @@ -24,7 +24,7 @@ interface otp_ctrl_cov_if lc_esc_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; lc_esc_during_sram_0_req: coverpoint sram_otp_key_i[0].req; lc_esc_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - lc_esc_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_esc_during_acc_req: coverpoint acc_otp_key_i.req; lc_esc_during_otp_idle: coverpoint pwr_otp_o.otp_idle; lc_esc_during_lc_otp_prog_req: coverpoint lc_otp_program_i.req; endgroup @@ -37,7 +37,7 @@ interface otp_ctrl_cov_if flash_data_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; flash_data_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; flash_data_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - flash_data_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + flash_data_req_during_acc_req: coverpoint acc_otp_key_i.req; flash_data_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -49,7 +49,7 @@ interface otp_ctrl_cov_if flash_addr_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; flash_addr_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; flash_addr_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - flash_addr_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + flash_addr_req_during_acc_req: coverpoint acc_otp_key_i.req; flash_addr_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -61,7 +61,7 @@ interface otp_ctrl_cov_if sram_0_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; sram_0_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; sram_0_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - sram_0_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_0_req_during_acc_req: coverpoint acc_otp_key_i.req; sram_0_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -73,20 +73,20 @@ interface otp_ctrl_cov_if sram_1_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; sram_1_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; sram_1_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; - sram_1_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_1_req_during_acc_req: coverpoint acc_otp_key_i.req; sram_1_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup - covergroup otbn_req_condition_cg @(otbn_otp_key_i.req); - otbn_req_during_lc_esc: coverpoint lc_escalate_en_i { + covergroup acc_req_condition_cg @(acc_otp_key_i.req); + acc_req_during_lc_esc: coverpoint lc_escalate_en_i { bins lc_esc_on = {lc_ctrl_pkg::On}; bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; } - otbn_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; - otbn_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; - otbn_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; - otbn_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - otbn_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + acc_req_during_flash_addr_req: coverpoint flash_otp_key_i.addr_req; + acc_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; + acc_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + acc_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + acc_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup covergroup lc_prog_req_condition_cg @(lc_otp_program_i.req); @@ -98,7 +98,7 @@ interface otp_ctrl_cov_if lc_prog_req_during_flash_data_req: coverpoint flash_otp_key_i.data_req; lc_prog_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; lc_prog_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; - lc_prog_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_prog_req_during_acc_req: coverpoint acc_otp_key_i.req; lc_prog_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; endgroup @@ -107,7 +107,7 @@ interface otp_ctrl_cov_if `DV_FCOV_INSTANTIATE_CG(flash_addr_req_condition_cg) `DV_FCOV_INSTANTIATE_CG(sram_0_req_condition_cg) `DV_FCOV_INSTANTIATE_CG(sram_1_req_condition_cg) - `DV_FCOV_INSTANTIATE_CG(otbn_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(acc_req_condition_cg) `DV_FCOV_INSTANTIATE_CG(lc_prog_req_condition_cg) endinterface diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv index 454d14df149..502929b4df5 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv @@ -19,7 +19,7 @@ class otp_ctrl_env #( `uvm_component_new push_pull_agent#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent[NumSramKeyReqSlots]; - push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent; + push_pull_agent#(.DeviceDataWidth(ACC_DATA_SIZE)) m_acc_pull_agent; push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_addr_pull_agent; push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_data_pull_agent; push_pull_agent#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) m_lc_prog_pull_agent; @@ -36,11 +36,11 @@ class otp_ctrl_env #( $sformatf("%0s*", sram_agent_name), "cfg", cfg.m_sram_pull_agent_cfg[i]); end - // build otbn-otp pull agent - m_otbn_pull_agent = push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id::create( - "m_otbn_pull_agent", this); - uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set( - this, "m_otbn_pull_agent", "cfg", cfg.m_otbn_pull_agent_cfg); + // build acc-otp pull agent + m_acc_pull_agent = push_pull_agent#(.DeviceDataWidth(ACC_DATA_SIZE))::type_id::create( + "m_acc_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE)))::set( + this, "m_acc_pull_agent", "cfg", cfg.m_acc_pull_agent_cfg); // build flash-otp pull agent m_flash_addr_pull_agent = push_pull_agent#(.DeviceDataWidth(FLASH_DATA_SIZE))::type_id::create( @@ -85,13 +85,13 @@ class otp_ctrl_env #( end end - virtual_sequencer.otbn_pull_sequencer_h = m_otbn_pull_agent.sequencer; + virtual_sequencer.acc_pull_sequencer_h = m_acc_pull_agent.sequencer; virtual_sequencer.flash_addr_pull_sequencer_h = m_flash_addr_pull_agent.sequencer; virtual_sequencer.flash_data_pull_sequencer_h = m_flash_data_pull_agent.sequencer; virtual_sequencer.lc_prog_pull_sequencer_h = m_lc_prog_pull_agent.sequencer; if (cfg.en_scb) begin - m_otbn_pull_agent.monitor.analysis_port.connect(scoreboard.otbn_fifo.analysis_export); + m_acc_pull_agent.monitor.analysis_port.connect(scoreboard.acc_fifo.analysis_export); m_flash_addr_pull_agent.monitor.analysis_port.connect( scoreboard.flash_addr_fifo.analysis_export); m_flash_data_pull_agent.monitor.analysis_port.connect( diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv index 76809de4c17..fd992e86917 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv @@ -19,7 +19,7 @@ class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block // ext component cfgs rand push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent_cfg[NumSramKeyReqSlots]; - rand push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent_cfg; + rand push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE)) m_acc_pull_agent_cfg; rand push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_data_pull_agent_cfg; rand push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE)) m_flash_addr_pull_agent_cfg; rand push_pull_agent_cfg#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) @@ -75,9 +75,9 @@ class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block m_sram_pull_agent_cfg[i].agent_type = PullAgent; end - m_otbn_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id - ::create("m_otbn_pull_agent_cfg"); - m_otbn_pull_agent_cfg.agent_type = PullAgent; + m_acc_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(ACC_DATA_SIZE))::type_id + ::create("m_acc_pull_agent_cfg"); + m_acc_pull_agent_cfg.agent_type = PullAgent; m_flash_data_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(FLASH_DATA_SIZE))::type_id ::create("m_flash_data_pull_agent_cfg"); diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv index a28ddfce88f..321b7f16d84 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv @@ -153,7 +153,7 @@ class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); bit_toggle_cg_wrap lc_prog_cg; - bit_toggle_cg_wrap otbn_req_cg; + bit_toggle_cg_wrap acc_req_cg; bit_toggle_cg_wrap status_csr_cg[OtpStatusFieldSize]; // covergroups @@ -426,7 +426,7 @@ class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); super.build_phase(phase); // Create instances from bit_toggle_cg_wrapper. lc_prog_cg = new("lc_prog_cg", "", 0); - otbn_req_cg = new("otbn_req_cg", "", 0); + acc_req_cg = new("acc_req_cg", "", 0); foreach (status_csr_cg[i]) begin otp_status_e index = otp_status_e'(i); status_csr_cg[i]= new(index.name, "status_csr_cg", 0); diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv index c12ad938cfd..6f9d2a0db0c 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv @@ -58,15 +58,15 @@ package otp_ctrl_env_pkg; // sram rsp data has 1 bit for seed_valid, the rest are for key and nonce parameter uint SRAM_DATA_SIZE = 1 + SramKeyWidth + SramNonceWidth; - // otbn rsp data has 1 bit for seed_valid, the rest are for key and nonce - parameter uint OTBN_DATA_SIZE = 1 + OtbnKeyWidth + OtbnNonceWidth; + // acc rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint ACC_DATA_SIZE = 1 + AccKeyWidth + AccNonceWidth; // flash rsp data has 1 bit for seed_valid, the rest are for key parameter uint FLASH_DATA_SIZE = 1 + FlashKeyWidth; // lc program data has lc_state data and lc_cnt data parameter uint LC_PROG_DATA_SIZE = LcStateWidth + LcCountWidth; parameter uint NUM_SRAM_EDN_REQ = 12; - parameter uint NUM_OTBN_EDN_REQ = 10; + parameter uint NUM_ACC_EDN_REQ = 10; // This is used to randomize CHECK_TIMEOUT in sequences, set to a low value // so it will certainly cause a check error due to a timeout. diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv index f196dd561b6..4fd266b6cd6 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv @@ -69,7 +69,7 @@ interface otp_ctrl_if(input clk_i, input rst_ni); logic lc_prog_err_dly1, lc_prog_no_sta_check; // Connect push_pull interfaces ack signals for assertion checks. - logic otbn_ack, lc_prog_ack; + logic acc_ack, lc_prog_ack; logic [1:0] flash_acks; logic [NumSramKeyReqSlots-1:0] sram_acks; @@ -364,7 +364,7 @@ interface otp_ctrl_if(input clk_i, input rst_ni); `OTP_FATAL_ERR_ASSERT(LcProgAck_A, lc_prog_ack == 0) `OTP_FATAL_ERR_ASSERT(FlashAcks_A, flash_acks == 0) `OTP_FATAL_ERR_ASSERT(SramAcks_A, sram_acks == 0) - `OTP_FATAL_ERR_ASSERT(OtbnAck_A, otbn_ack == 0) + `OTP_FATAL_ERR_ASSERT(AccAck_A, acc_ack == 0) `undef OTP_ASSERT_WO_LC_ESC `undef OTP_FATAL_ERR_ASSERT diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv index 79b8aa2dba7..6db8233429a 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv @@ -46,7 +46,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) // TLM agent fifos uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE))) sram_fifos[NumSramKeyReqSlots]; - uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE))) otbn_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(ACC_DATA_SIZE))) acc_fifo; uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_addr_fifo; uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(FLASH_DATA_SIZE))) flash_data_fifo; uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE))) @@ -61,7 +61,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) for (int i = 0; i < NumSramKeyReqSlots; i++) begin sram_fifos[i] = new($sformatf("sram_fifos[%0d]", i), this); end - otbn_fifo = new("otbn_fifo", this); + acc_fifo = new("acc_fifo", this); flash_addr_fifo = new("flash_addr_fifo", this); flash_data_fifo = new("flash_data_fifo", this); lc_prog_fifo = new("lc_prog_fifo", this); @@ -79,7 +79,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) process_lc_esc(); process_lc_prog_req(); process_edn_req(); - check_otbn_rsp(); + check_acc_rsp(); check_flash_rsps(); check_sram_rsps(); recover_lc_prog_req(); @@ -390,32 +390,32 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) end endtask - virtual task check_otbn_rsp(); + virtual task check_acc_rsp(); forever begin - push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE)) rcv_item; + push_pull_item#(.DeviceDataWidth(ACC_DATA_SIZE)) rcv_item; bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; - bit [OtbnKeyWidth-1:0] key, exp_key; - bit [OtbnNonceWidth-1:0] nonce, exp_nonce; + bit [AccKeyWidth-1:0] key, exp_key; + bit [AccNonceWidth-1:0] nonce, exp_nonce; bit seed_valid; bit part_locked; - otbn_fifo.get(rcv_item); + acc_fifo.get(rcv_item); seed_valid = rcv_item.d_data[0]; - nonce = rcv_item.d_data[1+:OtbnNonceWidth]; - key = rcv_item.d_data[OtbnNonceWidth+1+:OtbnKeyWidth]; + nonce = rcv_item.d_data[1+:AccNonceWidth]; + key = rcv_item.d_data[AccNonceWidth+1+:AccKeyWidth]; part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; // seed is valid as long as secret1 is locked - `DV_CHECK_EQ(seed_valid, part_locked, "otbn seed_valid mismatch") + `DV_CHECK_EQ(seed_valid, part_locked, "acc seed_valid mismatch") - // If edn_data_q matches the OTBN requested size, check OTBN outputs - if (edn_data_q.size() == NUM_OTBN_EDN_REQ) begin + // If edn_data_q matches the ACC requested size, check ACC outputs + if (edn_data_q.size() == NUM_ACC_EDN_REQ) begin {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; // check nonce value - `DV_CHECK_EQ(nonce, exp_nonce, "otbn nonce mismatch") + `DV_CHECK_EQ(nonce, exp_nonce, "acc nonce mismatch") // calculate key sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); @@ -433,16 +433,16 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) .second_key(edn_key2), .num_round(2)); exp_key = {exp_key_higher, exp_key_lower}; - `DV_CHECK_EQ(key, exp_key, "otbn key mismatch") + `DV_CHECK_EQ(key, exp_key, "acc key mismatch") - if (cfg.en_cov) cov.otbn_req_cg.sample(part_locked); + if (cfg.en_cov) cov.acc_req_cg.sample(part_locked); - // If during OTBN key request, the LFSR timer expired and trigger an EDN request to acquire - // two EDN keys, then ignore the OTBN output checking, because scb did not know which EDN + // If during ACC key request, the LFSR timer expired and trigger an EDN request to acquire + // two EDN keys, then ignore the ACC output checking, because scb did not know which EDN // keys are used for LFSR. // Thus any edn_data_q size equal to (16+2*N) is exempted from checking. - end else if ((edn_data_q.size() - NUM_OTBN_EDN_REQ) % 2 != 0) begin - `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during OTBN request", + end else if ((edn_data_q.size() - NUM_ACC_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during ACC request", edn_data_q.size())) end edn_data_q.delete(); @@ -517,7 +517,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) // seed is valid as long as secret1 is locked `DV_CHECK_EQ(seed_valid, part_locked, $sformatf("sram_%0d seed_valid mismatch", index)) - // If edn_data_q matches the OTBN requested size, check OTBN outputs + // If edn_data_q matches the ACC requested size, check ACC outputs if (edn_data_q.size() == NUM_SRAM_EDN_REQ) begin {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; @@ -1391,7 +1391,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) recover_interrupted_op(); super.reset(kind); // flush fifos - otbn_fifo.flush(); + acc_fifo.flush(); flash_addr_fifo.flush(); flash_data_fifo.flush(); lc_prog_fifo.flush(); @@ -1429,7 +1429,7 @@ class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) // write secret until KDI request is completed. Since the KDI process time could // vary depends on the push-pull-agent, we are going to ignore the checking if // this scenario happens. - cfg.m_otbn_pull_agent_cfg.vif.req || + cfg.m_acc_pull_agent_cfg.vif.req || cfg.m_flash_data_pull_agent_cfg.vif.req || cfg.m_flash_addr_pull_agent_cfg.vif.req || cfg.m_sram_pull_agent_cfg[0].vif.req || diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv index 4780a806599..2aaa3433cca 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv @@ -11,7 +11,7 @@ class otp_ctrl_virtual_sequencer extends cip_base_virtual_sequencer #( `uvm_component_new push_pull_sequencer#(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_pull_sequencer_h[NumSramKeyReqSlots]; - push_pull_sequencer#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_sequencer_h; + push_pull_sequencer#(.DeviceDataWidth(ACC_DATA_SIZE)) acc_pull_sequencer_h; push_pull_sequencer#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_data_pull_sequencer_h; push_pull_sequencer#(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_addr_pull_sequencer_h; push_pull_sequencer#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv index 40b07a5b116..e3fa23c17bc 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv @@ -610,15 +610,15 @@ class otp_ctrl_base_vseq extends cip_base_vseq #( for (int i = 0; i < NumSramKeyReqSlots; i++) req_sram_key(i, blocking); endtask - virtual task req_otbn_key(bit blocking = default_req_blocking); - if (cfg.m_otbn_pull_agent_cfg.vif.req === 1'b1) return; + virtual task req_acc_key(bit blocking = default_req_blocking); + if (cfg.m_acc_pull_agent_cfg.vif.req === 1'b1) return; if (blocking) begin - req_otbn_key_sub(); + req_acc_key_sub(); end else begin fork begin - req_otbn_key_sub(); + req_acc_key_sub(); end join_none; // Add #0 to ensure that this thread starts executing before any subsequent call @@ -626,12 +626,12 @@ class otp_ctrl_base_vseq extends cip_base_vseq #( end endtask - virtual task req_otbn_key_sub(); - push_pull_host_seq#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_seq; + virtual task req_acc_key_sub(); + push_pull_host_seq#(.DeviceDataWidth(ACC_DATA_SIZE)) acc_pull_seq; wait(cfg.under_reset == 0); - `uvm_create_on(otbn_pull_seq, p_sequencer.otbn_pull_sequencer_h); - `DV_CHECK_RANDOMIZE_FATAL(otbn_pull_seq) - `uvm_send(otbn_pull_seq) + `uvm_create_on(acc_pull_seq, p_sequencer.acc_pull_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(acc_pull_seq) + `uvm_send(acc_pull_seq) endtask virtual task req_flash_addr_key(bit blocking = default_req_blocking); diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv index f8c98bcc1aa..65f974c2d9f 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv @@ -192,7 +192,7 @@ class otp_ctrl_common_vseq extends otp_ctrl_base_vseq; write_sw_digests(); // Access OTP via app interface. - if ($urandom_range(0, 1)) req_otbn_key(0); + if ($urandom_range(0, 1)) req_acc_key(0); if ($urandom_range(0, 1)) req_flash_addr_key(0); if ($urandom_range(0, 1)) req_flash_data_key(0); if ($urandom_range(0, 1)) req_all_sram_keys(0); diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv index 125c62efac2..9910b5f6b18 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_key_req_vseq.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This sequence will randomly issue key otbn, sram, flash key requests during or after partition +// This sequence will randomly issue key acc, sram, flash key requests during or after partition // is locked. // This sequence will check if nonce, seed_valid, and output keys are correct via scb. @@ -22,10 +22,10 @@ class otp_ctrl_parallel_key_req_vseq extends otp_ctrl_parallel_base_vseq; fork begin - // get otbn keys + // get acc keys if ($urandom_range(0, 1)) begin wait_clk_or_reset($urandom_range(0, 500)); - if (!base_vseq_done && !cfg.under_reset) req_otbn_key(); + if (!base_vseq_done && !cfg.under_reset) req_acc_key(); end end begin diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv index 18c03928f26..194c400079b 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv @@ -77,7 +77,7 @@ class otp_ctrl_parallel_lc_esc_vseq extends otp_ctrl_dai_lock_vseq; virtual task set_lc_esc_and_check(); // Random issue key requests before lc_esc_en is issued. randcase - 1: req_otbn_key(0); + 1: req_acc_key(0); 1: req_flash_addr_key(0); 1: req_flash_data_key(0); 1: req_all_sram_keys(0); diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv index a46dca6e0f9..345b6e27513 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_smoke_vseq.sv @@ -142,7 +142,7 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; force_mubi_part_access(); if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs) begin - req_otbn_key(); + req_acc_key(); req_flash_addr_key(); req_flash_data_key(); req_all_sram_keys(); @@ -252,7 +252,7 @@ class otp_ctrl_smoke_vseq extends otp_ctrl_base_vseq; end if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs && !cfg.smoke_test) begin - req_otbn_key(); + req_acc_key(); req_flash_addr_key(); req_flash_data_key(); req_all_sram_keys(); diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/tb.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/tb.sv index 9d586bc36a9..bcbcff223b4 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/tb.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/dv/tb.sv @@ -38,8 +38,8 @@ module tb; wire otp_ctrl_pkg::flash_otp_key_req_t flash_req; wire otp_ctrl_pkg::flash_otp_key_rsp_t flash_rsp; - wire otp_ctrl_pkg::otbn_otp_key_req_t otbn_req; - wire otp_ctrl_pkg::otbn_otp_key_rsp_t otbn_rsp; + wire otp_ctrl_pkg::acc_otp_key_req_t acc_req; + wire otp_ctrl_pkg::acc_otp_key_rsp_t acc_rsp; wire otp_ctrl_pkg::sram_otp_key_req_t[NumSramKeyReqSlots-1:0] sram_req; wire otp_ctrl_pkg::sram_otp_key_rsp_t[NumSramKeyReqSlots-1:0] sram_rsp; @@ -61,7 +61,7 @@ module tb; lc_prog_if(.clk(clk), .rst_n(rst_n)); push_pull_if #(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_if[NumSramKeyReqSlots](.clk(clk), .rst_n(rst_n)); - push_pull_if #(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_if(.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(ACC_DATA_SIZE)) acc_if(.clk(clk), .rst_n(rst_n)); push_pull_if #(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_addr_if(.clk(clk), .rst_n(rst_n)); push_pull_if #(.DeviceDataWidth(FLASH_DATA_SIZE)) flash_data_if(.clk(clk), .rst_n(rst_n)); @@ -81,7 +81,7 @@ module tb; // Assign to otp_ctrl_if for assertion checks. assign otp_ctrl_if.lc_prog_ack = lc_prog_if.ack; assign otp_ctrl_if.flash_acks = flash_data_if.ack; - assign otp_ctrl_if.otbn_ack = otbn_if.ack; + assign otp_ctrl_if.acc_ack = acc_if.ack; // This signal probes design's alert request to avoid additional logic for triggering alert and // disable assertions. @@ -144,9 +144,9 @@ module tb; // sram .sram_otp_key_i (sram_req), .sram_otp_key_o (sram_rsp), - // otbn - .otbn_otp_key_i (otbn_req), - .otbn_otp_key_o (otbn_rsp), + // acc + .acc_otp_key_i (acc_req), + .acc_otp_key_o (acc_rsp), .otp_broadcast_o (otp_ctrl_if.otp_broadcast_o), @@ -201,9 +201,9 @@ module tb; $sformatf("*env.m_sram_pull_agent[%0d]*", i), "vif", sram_if[i]); end end - assign otbn_req = otbn_if.req; - assign otbn_if.ack = otbn_rsp.ack; - assign otbn_if.d_data = {otbn_rsp.key, otbn_rsp.nonce, otbn_rsp.seed_valid}; + assign acc_req = acc_if.req; + assign acc_if.ack = acc_rsp.ack; + assign acc_if.d_data = {acc_rsp.key, acc_rsp.nonce, acc_rsp.seed_valid}; assign flash_req = {flash_data_if.req, flash_addr_if.req}; assign flash_data_if.ack = flash_rsp.data_ack; @@ -258,8 +258,8 @@ module tb; "vif", tl_if); uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_otp_macro_prim_reg_block", "vif", prim_tl_if); - uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set(null, - "*env.m_otbn_pull_agent*", "vif", otbn_if); + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(ACC_DATA_SIZE)))::set(null, + "*env.m_acc_pull_agent*", "vif", acc_if); uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(FLASH_DATA_SIZE)))::set(null, "*env.m_flash_data_pull_agent*", "vif", flash_data_if); uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(FLASH_DATA_SIZE)))::set(null, diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv index 069274a0fde..0535ca8d143 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv @@ -82,8 +82,8 @@ module otp_ctrl output flash_otp_key_rsp_t flash_otp_key_o, input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, - input otbn_otp_key_req_t otbn_otp_key_i, - output otbn_otp_key_rsp_t otbn_otp_key_o, + input acc_otp_key_req_t acc_otp_key_i, + output acc_otp_key_rsp_t acc_otp_key_o, // Interface to OTP_MACRO output otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_macro_o, @@ -915,7 +915,7 @@ end // case. For one example, see // // https://opentitan.org/book/hw/top_earlgrey/ - // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-otbn-scramblers + // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-acc-scramblers // Note: as opposed to the OTP arbitration above, we do not perform cycle-wise arbitration, but @@ -1149,8 +1149,8 @@ end .flash_otp_key_o, .sram_otp_key_i, .sram_otp_key_o, - .otbn_otp_key_i, - .otbn_otp_key_o, + .acc_otp_key_i, + .acc_otp_key_o, .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[KdiIdx] ), .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[KdiIdx] ), .scrmbl_cmd_o ( part_scrmbl_req_bundle[KdiIdx].cmd ), @@ -1563,7 +1563,7 @@ end `ASSERT_KNOWN(OtpKeymgrKeyKnown_A, otp_keymgr_key_o) `ASSERT_KNOWN(FlashOtpKeyRspKnown_A, flash_otp_key_o) `ASSERT_KNOWN(OtpSramKeyKnown_A, sram_otp_key_o) - `ASSERT_KNOWN(OtpOtgnKeyKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(OtpOtgnKeyKnown_A, acc_otp_key_o) `ASSERT_KNOWN(OtpBroadcastKnown_A, otp_broadcast_o) // Alert assertions for sparse FSMs. diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv index 8be3973e59e..4bfca7ef0c0 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv @@ -38,8 +38,8 @@ module otp_ctrl_kdi output flash_otp_key_rsp_t flash_otp_key_o, input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, - input otbn_otp_key_req_t otbn_otp_key_i, - output otbn_otp_key_rsp_t otbn_otp_key_o, + input acc_otp_key_req_t acc_otp_key_i, + output acc_otp_key_rsp_t acc_otp_key_o, // Scrambling mutex request output logic scrmbl_mtx_req_o, input scrmbl_mtx_gnt_i, @@ -60,7 +60,7 @@ module otp_ctrl_kdi // Integration Checks // //////////////////////// - // 2xFlash, OTBN + SRAM slots + // 2xFlash, ACC + SRAM slots localparam int NumReq = 3 + NumSramKeyReqSlots; // Make sure key sizes in the system are multiples of 64bit and not larger than 256bit. `ASSERT_INIT(KeyNonceSize0_A, (FlashKeySeedWidth <= 256) && ((FlashKeySeedWidth % 64) == 0)) @@ -68,8 +68,8 @@ module otp_ctrl_kdi `ASSERT_INIT(KeyNonceSize2_A, (FlashKeyWidth <= 256) && ((FlashKeyWidth % 64) == 0)) `ASSERT_INIT(KeyNonceSize3_A, (SramKeyWidth <= 256) && ((SramKeyWidth % 64) == 0)) `ASSERT_INIT(KeyNonceSize4_A, (SramNonceWidth <= 256) && ((SramNonceWidth % 64) == 0)) - `ASSERT_INIT(KeyNonceSize5_A, (OtbnKeyWidth <= 256) && ((OtbnKeyWidth % 64) == 0)) - `ASSERT_INIT(KeyNonceSize6_A, (OtbnNonceWidth <= 256) && ((OtbnNonceWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize5_A, (AccKeyWidth <= 256) && ((AccKeyWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize6_A, (AccNonceWidth <= 256) && ((AccNonceWidth % 64) == 0)) // Make sure EDN interface has compatible width. `ASSERT_INIT(EntropyWidthDividesDigestBlockWidth_A, (ScrmblKeyWidth % EdnDataWidth) == 0) @@ -113,11 +113,11 @@ module otp_ctrl_kdi assign req[0] = flash_otp_key_i.data_req; assign req[1] = flash_otp_key_i.addr_req; - assign req[2] = otbn_otp_key_i.req; + assign req[2] = acc_otp_key_i.req; assign flash_otp_key_o.data_ack = gnt[0]; assign flash_otp_key_o.addr_ack = gnt[1]; - assign otbn_otp_key_o.ack = gnt[2]; + assign acc_otp_key_o.ack = gnt[2]; // anchored seeds logic [FlashKeySeedWidth-1:0] flash_data_key_seed; @@ -161,12 +161,12 @@ module otp_ctrl_kdi nonce_size: '0, seed_valid: scrmbl_key_seed_valid_i, seed: flash_addr_key_seed}; // 2x128bit - // OTBN key + // ACC key assign req_bundles[2] = '{ingest_entropy: 1'b1, // ingest random data chained_digest: 1'b0, // revert to netlist IV between blocks digest_sel: SramDataKey, fetch_nonce: 1'b1, // fetch nonce - nonce_size: 2'(OtbnNonceWidth/EdnDataWidth-1), + nonce_size: 2'(AccNonceWidth/EdnDataWidth-1), seed_valid: scrmbl_key_seed_valid_i, seed: {sram_data_key_seed, // reuse same seed sram_data_key_seed}}; @@ -282,9 +282,9 @@ module otp_ctrl_kdi .q_o(key_out_q) ); - assign otbn_otp_key_o.key = key_out_q; - assign otbn_otp_key_o.nonce = nonce_out_q[OtbnNonceSel-1:0]; - assign otbn_otp_key_o.seed_valid = seed_valid_q; + assign acc_otp_key_o.key = key_out_q; + assign acc_otp_key_o.nonce = nonce_out_q[AccNonceSel-1:0]; + assign acc_otp_key_o.seed_valid = seed_valid_q; assign flash_otp_key_o.key = key_out_q; assign flash_otp_key_o.rand_key = nonce_out_q[FlashNonceSel-1:0]; @@ -593,7 +593,7 @@ module otp_ctrl_kdi `ASSERT_KNOWN(EdnReqKnown_A, edn_req_o) `ASSERT_KNOWN(FlashOtpKeyRspKnown_A, flash_otp_key_o) `ASSERT_KNOWN(SramOtpKeyRspKnown_A, sram_otp_key_o) - `ASSERT_KNOWN(OtbnOtpKeyRspKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(AccOtpKeyRspKnown_A, acc_otp_key_o) `ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) `ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) `ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv index da93a2762ea..1061e2fafd1 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv @@ -97,8 +97,8 @@ package otp_ctrl_top_specific_pkg; // Get maximum nonce width localparam int NumNonceChunks = - (OtbnNonceWidth > FlashKeyWidth) ? - ((OtbnNonceWidth > SramNonceWidth) ? OtbnNonceSel : SramNonceSel) : + (AccNonceWidth > FlashKeyWidth) ? + ((AccNonceWidth > SramNonceWidth) ? AccNonceSel : SramNonceSel) : ((FlashKeyWidth > SramNonceWidth) ? FlashNonceSel : SramNonceSel); /////////////////////////////////////////// diff --git a/hw/top_earlgrey/lint/top_earlgrey.waiver b/hw/top_earlgrey/lint/top_earlgrey.waiver index 8db46dcd53e..86a7e0f9d59 100644 --- a/hw/top_earlgrey/lint/top_earlgrey.waiver +++ b/hw/top_earlgrey/lint/top_earlgrey.waiver @@ -62,11 +62,11 @@ waive -rules CLOCK_USE -location {top_earlgrey.sv} -regexp {'clkmgr_aon_clocks.c # Since these functions / parameters / signals live in different scopes, this is acceptable, and we can waive them. waive -rules SAME_NAME_TYPE -location {aes_sbox_canright_pkg.sv keccak_2share.sv} -regexp {'theta' is used as a (reg|function) here, and as a (function|reg) at} \ -comment {This is acceptable, since these are used in different hierarchies.} -waive -rules SAME_NAME_TYPE -location {keccak_round.sv otbn_pkg.sv} -regexp {'L' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ +waive -rules SAME_NAME_TYPE -location {keccak_round.sv acc_pkg.sv} -regexp {'L' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ -comment {This is acceptable, since these are used in different hierarchies.} waive -rules SAME_NAME_TYPE -location {spi_device.sv rstmgr_pkg.sv} -regexp {'spi_device' is used as a (module|reg) here, and as a (reg|module) at } \ -comment {This is acceptable, since these are used in different hierarchies.} -waive -rules SAME_NAME_TYPE -location {tlul_socket_m1.sv otbn_pkg.sv} -regexp {'M' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ +waive -rules SAME_NAME_TYPE -location {tlul_socket_m1.sv acc_pkg.sv} -regexp {'M' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ -comment {This is acceptable, since these are used in different hierarchies.} waive -rules SAME_NAME_TYPE -location {prim_trivium.sv prim_xoshiro256pp.sv} -regexp {'state_update' is used as a (reg|function) here, and as a (function|reg) at} \ -comment {This is acceptable, since these are used in different hierarchies.} diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index 8535419e5a9..fbd4c8da9dc 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -129,11 +129,11 @@ additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" rel_path: "hw/ip/keymgr/lint/{tool}" }, - { name: otbn - fusesoc_core: lowrisc:ip:otbn + { name: acc + fusesoc_core: lowrisc:ip:acc import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" - rel_path: "hw/ip/otbn/lint/{tool}" + rel_path: "hw/ip/acc/lint/{tool}" }, { name: otp_ctrl fusesoc_core: lowrisc:earlgrey_ip:otp_ctrl diff --git a/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl b/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl index 1ceed38c2d2..740b59f90d0 100644 --- a/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl +++ b/hw/top_earlgrey/rdc/chip_earlgrey_asic_scenario.tcl @@ -44,7 +44,7 @@ set_reset_scenario { \ { top_earlgrey.clkmgr_aon_clocks.clk_main_aes { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_main_hmac { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_main_kmac { constraint { @t0 0 } } } \ - { top_earlgrey.clkmgr_aon_clocks.clk_main_otbn { constraint { @t0 0 } } } \ + { top_earlgrey.clkmgr_aon_clocks.clk_main_acc { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_io_div4_infra { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_main_infra { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_usb_infra { constraint { @t0 0 } } } \ @@ -78,7 +78,7 @@ set_reset_scenario { \ { top_earlgrey.clkmgr_aon_clocks.clk_main_aes { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_main_hmac { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_main_kmac { constraint { @t0 0 } } } \ - { top_earlgrey.clkmgr_aon_clocks.clk_main_otbn { constraint { @t0 0 } } } \ + { top_earlgrey.clkmgr_aon_clocks.clk_main_acc { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_io_div4_infra { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_main_infra { constraint { @t0 0 } } } \ { top_earlgrey.clkmgr_aon_clocks.clk_usb_infra { constraint { @t0 0 } } } \ diff --git a/hw/top_earlgrey/rdc/rdc_waivers.tcl b/hw/top_earlgrey/rdc/rdc_waivers.tcl index 08fd333f4af..836fecd991e 100644 --- a/hw/top_earlgrey/rdc/rdc_waivers.tcl +++ b/hw/top_earlgrey/rdc/rdc_waivers.tcl @@ -103,12 +103,12 @@ set_rule_status -rule E_RST_METASTABILITY -status Waived \ (MetaStableFlop=~"*u_clk_main_kmac_trans.u_cg.*en_latch")} \ -comment {POR_N resets KMAC module too.} -# OTBN Clock Gating +# ACC Clock Gating set_rule_status -rule E_RST_METASTABILITY -status Waived \ -expression {(SourceReset=="POR_N") && \ - (ResetFlop=~"*clk_main_otbn_trans*") && \ - (MetaStableFlop=~"*u_clk_main_otbn_trans.u_cg.*en_latch")} \ - -comment {POR_N resets OTBN module too.} + (ResetFlop=~"*clk_main_acc_trans*") && \ + (MetaStableFlop=~"*u_clk_main_acc_trans.u_cg.*en_latch")} \ + -comment {POR_N resets ACC module too.} # SW_EN to CG create_view_criteria -name PorNSwEnCg -rule E_RST_METASTABILITY \ diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv index 3cead80a399..3c592169819 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv @@ -1064,9 +1064,9 @@ module chip_earlgrey_cw310 #( .SecAesStartTriggerDelay(0), .SecAesAllowForcingMasks(1'b1), .CsrngSBoxImpl(aes_pkg::SBoxImplLut), - .OtbnRegFile(otbn_pkg::RegFileFPGA), - .SecOtbnMuteUrnd(1'b0), - .SecOtbnSkipUrndReseedAtStart(1'b0), + .AccRegFile(acc_pkg::RegFileFPGA), + .SecAccMuteUrnd(1'b0), + .SecAccSkipUrndReseedAtStart(1'b0), .OtpMacroMemInitFile(OtpMacroMemInitFile), .RvCoreIbexPipeLine(1), .SramCtrlRetAonInstrExec(0), @@ -1184,7 +1184,7 @@ module chip_earlgrey_cw310 #( // AES - 00 - 0 // HMAC - 01 - 1 - not implemented on CW305 // KMAC - 10 - 2 - not implemented on CW305 - // OTBN - 11 - 3 - not implemented on CW305 + // ACC - 11 - 3 - not implemented on CW305 // // GPIO9 is used for gating the selected capture trigger in software. Alternatively, GPIO8 // can be used to implement a less precise but fully software-controlled capture trigger @@ -1200,7 +1200,7 @@ module chip_earlgrey_cw310 #( 2'b00: trigger_sel = clkmgr_pkg::HintMainAes; 2'b01: trigger_sel = clkmgr_pkg::HintMainHmac; 2'b10: trigger_sel = clkmgr_pkg::HintMainKmac; - 2'b11: trigger_sel = clkmgr_pkg::HintMainOtbn; + 2'b11: trigger_sel = clkmgr_pkg::HintMainAcc; default: trigger_sel = clkmgr_pkg::HintMainAes; endcase; end diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv index 5f07bfa8a2c..c23ade6afec 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv @@ -1050,9 +1050,9 @@ module chip_earlgrey_cw340 #( .SecAesStartTriggerDelay(0), .SecAesAllowForcingMasks(1'b1), .CsrngSBoxImpl(aes_pkg::SBoxImplLut), - .OtbnRegFile(otbn_pkg::RegFileFPGA), - .SecOtbnMuteUrnd(1'b0), - .SecOtbnSkipUrndReseedAtStart(1'b0), + .AccRegFile(acc_pkg::RegFileFPGA), + .SecAccMuteUrnd(1'b0), + .SecAccSkipUrndReseedAtStart(1'b0), .OtpMacroMemInitFile(OtpMacroMemInitFile), .RvCoreIbexPipeLine(1), .SramCtrlRetAonInstrExec(0), @@ -1168,7 +1168,7 @@ module chip_earlgrey_cw340 #( // AES - 00 - 0 // HMAC - 01 - 1 - not implemented on CW305 // KMAC - 10 - 2 - not implemented on CW305 - // OTBN - 11 - 3 - not implemented on CW305 + // ACC - 11 - 3 - not implemented on CW305 // // GPIO9 is used for gating the selected capture trigger in software. Alternatively, GPIO8 // can be used to implement a less precise but fully software-controlled capture trigger @@ -1184,7 +1184,7 @@ module chip_earlgrey_cw340 #( 2'b00: trigger_sel = clkmgr_pkg::HintMainAes; 2'b01: trigger_sel = clkmgr_pkg::HintMainHmac; 2'b10: trigger_sel = clkmgr_pkg::HintMainKmac; - 2'b11: trigger_sel = clkmgr_pkg::HintMainOtbn; + 2'b11: trigger_sel = clkmgr_pkg::HintMainAcc; default: trigger_sel = clkmgr_pkg::HintMainAes; endcase; end diff --git a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv index 48aabea470e..04a52c29d16 100644 --- a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_rnd_cnst_pkg.sv @@ -19,17 +19,17 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter otp_ctrl_top_specific_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = { - 40'h7A_29B920B7 + 40'hAB_60DA8B65 }; // Compile-time random permutation for LFSR output parameter otp_ctrl_top_specific_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = { - 240'h08A8_477C0620_4249C615_C65B9834_CD591315_52388E25_E74168B1_085D23E5 + 240'h3D30_E520D90C_60400150_98DE85C1_5268A98B_1D788255_141D3995_A07C69DB }; // Compile-time random permutation for scrambling key/nonce register reset value parameter otp_ctrl_top_specific_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = { - 256'h51BF1196_B12E5259_BDED9026_1100C8CC_C2B1BE45_99775614_975D3D2B_32E933D8 + 256'hE933D88E_2E1CF654_60F23FB7_80499E6F_CCE64CEA_FD282C0E_33FD2C07_986C2A51 }; // Compile-time scrambling key @@ -236,35 +236,35 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Diversification value used for all invalid life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = { - 128'h8E2E1CF6_5460F23F_B780499E_6FCCE64C + 128'h1755F072_EE7A8E2F_C45E111D_F07FA067 }; // Diversification value used for the TEST_UNLOCKED* life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestUnlocked = { - 128'hEAFD282C_0E33FD2C_07986C2A_511755F0 + 128'hF64056D9_BF30D485_43BEC2E9_A075D7D5 }; // Diversification value used for the DEV life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivDev = { - 128'h72EE7A8E_2FC45E11_1DF07FA0_67F64056 + 128'h36D6F825_05255EA0_645554DD_5F9355F5 }; // Diversification value used for the PROD/PROD_END life cycle states. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = { - 128'hD9BF30D4_8543BEC2_E9A075D7_D536D6F8 + 128'hA89085A9_5A12AB13_E0EC9CCD_04512F5C }; // Diversification value used for the RMA life cycle state. parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivRma = { - 128'h2505255E_A0645554_DD5F9355_F5A89085 + 128'h01D8958E_F421D22B_B7701362_4B5A4BFF }; // Compile-time random bits used for invalid tokens in the token mux parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = { - 256'hA95A12AB_13E0EC9C_CD04512F_5C01D895_8EF421D2_2BB77013_624B5A4B_FF0BDD4D, - 256'hD6B30B71_7AA80FF7_77A15787_8A468D23_EECBD09D_E6B8F9FA_EAF1A70E_57E8EDA0, - 256'h3A353B76_A2F83350_9ACC7B3A_A3FA7DAC_233E2B78_2306AF30_6A1F3616_5EE14A00, - 256'hEE9FF938_2AF33B47_9718558E_67597646_45AAD1FB_21C18124_635E3D50_A88F6808 + 256'h0BDD4DD6_B30B717A_A80FF777_A157878A_468D23EE_CBD09DE6_B8F9FAEA_F1A70E57, + 256'hE8EDA03A_353B76A2_F833509A_CC7B3AA3_FA7DAC23_3E2B7823_06AF306A_1F36165E, + 256'hE14A00EE_9FF9382A_F33B4797_18558E67_59764645_AAD1FB21_C1812463_5E3D50A8, + 256'h8F680804_5627AC18_F377D907_1BECA6F1_94EF96F3_E535B58F_2ADAD82B_175FE9EA }; //////////////////////////////////////////// @@ -272,12 +272,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter alert_handler_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = { - 32'h045627AC + 32'h1C326A66 }; // Compile-time random permutation for LFSR output parameter alert_handler_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = { - 160'hE5EA97AA_68690EC0_F6D0D2C5_92C4D895_3E0DBBC3 + 160'h1A9E9284_FE911733_700DEC6D_0DEA95BE_58877F02 }; //////////////////////////////////////////// @@ -285,23 +285,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetAonSramKey = { - 128'h478C14DB_070A6129_BB2945B8_8DC6CFCF + 128'hB666A5E2_2D3320F8_9CAA47E5_CED5D29C }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetAonSramNonce = { - 128'h2AE02F47_010CB666_A5E22D33_20F89CAA + 128'hC9CDB468_773EBACE_C14DA34C_505AEDC7 }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetAonLfsrSeed = { - 64'h47E5CED5_D29CC9CD + 64'h0EA184C7_A34193D5 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetAonLfsrPerm = { - 128'hF9E548A4_CEC7E41D_7C5D8489_1A02AC34, - 256'hE1519A2F_6311F642_96BC9BBC_0FCBDAAD_1C9E443A_8770F159_4E284F0C_EE3DD6AD + 128'h65E836CD_53E143AB_2B32E192_468C7F3B, + 256'h85E96087_7709F974_04DE54F1_AC0A8A61_ED245135_F838DBEC_0CA4AAF2_D3F56727 }; //////////////////////////////////////////// @@ -309,28 +309,46 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for default address key parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlAddrKey = { - 128'hCE1CF9E2_02920739_6945C95C_9B54BAE6 + 128'hA63A8E66_04338151_B9A23C08_F9EED04C }; // Compile-time random bits for default data key parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlDataKey = { - 128'hAEF30D85_77834CCC_6CAAA63A_8E660433 + 128'hA1EBB0BD_D305FFB6_C4818054_E0E0EDB0 }; // Compile-time random bits for default seeds parameter flash_ctrl_top_specific_pkg::all_seeds_t RndCnstFlashCtrlAllSeeds = { - 256'h8151B9A2_3C08F9EE_D04CA1EB_B0BDD305_FFB6C481_8054E0E0_EDB0ACD0_B040FC62, - 256'h9EA7F8B1_7FA88FEE_02E3F086_4223A2E2_3A8CC31E_2DE5E578_D43D2DCE_49E360CF + 256'hACD0B040_FC629EA7_F8B17FA8_8FEE02E3_F0864223_A2E23A8C_C31E2DE5_E578D43D, + 256'h2DCE49E3_60CFB594_ACDDF170_684F6EAD_2B7FEBFE_895523D7_BC4846A4_85956C7F }; // Compile-time random bits for initial LFSR seed parameter flash_ctrl_top_specific_pkg::lfsr_seed_t RndCnstFlashCtrlLfsrSeed = { - 32'hB594ACDD + 32'h904B9EDE }; // Compile-time random permutation for LFSR output parameter flash_ctrl_top_specific_pkg::lfsr_perm_t RndCnstFlashCtrlLfsrPerm = { - 160'h6041F31D_621E6D3B_CB54C6E0_8E115179_6BD4B5DE + 160'hFE2AEB5F_2259647E_011D0C3C_F191896E_CCAA467A + }; + + //////////////////////////////////////////// + // acc + //////////////////////////////////////////// + // Default seed of the PRNG used for URND. + parameter acc_pkg::urnd_prng_seed_t RndCnstAccUrndPrngSeed = { + 256'hB87118AF_11CDBE78_D6706061_5A20B9C0_740F0796_9CCD2D10_A1A6E798_8FA528AC + }; + + // Compile-time random reset value for IMem/DMem scrambling key. + parameter otp_ctrl_pkg::acc_key_t RndCnstAccAccKey = { + 128'h032E0A61_38CB8316_FF95C65C_D7A1A768 + }; + + // Compile-time random reset value for IMem/DMem scrambling nonce. + parameter otp_ctrl_pkg::acc_nonce_t RndCnstAccAccNonce = { + 64'hB06E0106_D60EDA0F }; //////////////////////////////////////////// @@ -338,34 +356,34 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for register clearing. parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = { - 64'hECB11CE3_B87AAA7A + 64'h1BC67ADF_85BD9A56 }; // Permutation applied to the LFSR of the PRNG used for clearing. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = { - 128'hF9B3702F_842EC6A2_A527F8D7_1CCEB402, - 256'h78B2B5A5_391594D2_043B085A_662BD44D_9C768F5F_A4F47757_3EDE3BC8_060A486F + 128'h625A41FE_D1B9D544_96922D13_359CE0BC, + 256'h8297A213_CB9FEC1E_E3B41DDC_31F1CBD6_DF440BBC_25C3B698_5B2B5446_AA3230BA }; // Permutation applied to the clearing PRNG output for clearing the second share of registers. parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = { - 128'h7A2601D3_7A75920C_161B1510_4B3FE795, - 256'h73CBEFE2_B63594C8_7680C7B6_EE5B7D10_3825C3B2_F45B2BF0_46AA3230_BA566BE1 + 128'h4AF43178_0AD6DB89_798CB5CE_21D3FFFA, + 256'hDA4CB9B3_4AC28261_EAAF7B4E_20B2066F_077F7D44_55463491_1B337190_DA1859E0 }; // Default seed of the PRNG used for masking. parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = { - 32'h819D1518, - 256'h690E6473_CDB24793_91635057_CA1045B9_E1917E1F_F0189B04_A4F7FBA9_60FE098A + 32'h05041A1B, + 256'h896350C9_636D6814_D23E2F5F_F1275EF1_9959AAA8_B6A004D5_574984DE_D1CC79BD }; // Permutation applied to the output of the PRNG used for masking. parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = { - 256'h7648238F_2A754D9F_8A9A718D_53092518_6E6B7B58_57981C72_59687826_807D013B, - 256'h38464590_84076C2E_0B86883D_7A940665_3F515F3A_820C7083_9173205D_39672D22, - 256'h3749606D_305A4A61_03211029_1E813562_4E277F16_85400097_8B871232_15791152, - 256'h1D638C33_5E3C9242_242B6A02_505B9655_2C4C7413_2F9D1F9B_0A34997E_64283144, - 256'h9C1A0405_93770F41_476F3E5C_43087C19_8914668E_569E540D_4B360E95_1B17694F + 256'h0412893D_8B73114B_3646052E_795F7845_815B8C15_23951C07_26566C4C_637B7D51, + 256'h7F4A7A7E_331A6250_168D8A31_5D14642B_0E85492F_5E481382_301D7701_55029609, + 256'h0A1F0338_9A6A392D_6F943F34_3E524D43_91753290_86102947_8497749B_0F4F190D, + 256'h179D5C1E_6E925893_0C767C8E_61704108_6D187159_0B282740_69729C5A_4437548F, + 256'h3B986024_209F0642_21533C35_6B9E4E88_2C578000_1B998325_652A6822_3A668767 }; //////////////////////////////////////////// @@ -373,76 +391,58 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random data for PRNG default seed parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = { - 32'h042A75EC, - 256'hC25D4E22_67E3BFF2_6E003AAC_BF7D513A_EA01E9EE_420D5B52_3F6B00C8_1BDED728 + 32'hCD252956, + 256'hBA816163_62B27EAF_B903EC79_BDDF0A4F_7DFF07DB_05DE6391_0E4EE4D8_A2C7D402 }; // Compile-time random permutation for PRNG output parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = { - 64'hC3C6781E_219715AB, - 256'h852397D5_20F0E8B6_31018CF2_820B961C_9770864A_931806B0_360D2CA9_A57AE133, - 256'h50545A20_2849A868_9E1457D7_FBB4FB8B_48D2CD4A_69228229_A17C1A34_657590A6, - 256'h7315DC92_24F12EC7_8599692F_061C59E7_BED59E70_0B329BC5_71E711CE_0D12B126, - 256'h6A6E2E7B_D2BE422B_4801A68F_C9E3CE80_AEC4A446_603D499A_371B9608_B7941B98, - 256'hDEE01E4A_4005603B_1D3B0B76_0A318347_3ACF08BE_46D6DC65_66CE57FC_875523A2, - 256'h91D61566_E1D1DB65_DCDB116C_B51E8A89_C7261EC9_C9C18564_7B5AA8BE_93ABA1F3, - 256'h075100DC_A9501FEB_82B2B746_154D13BF_5B91320C_7C8C1462_9A5BA616_746CAC12, - 256'h93DA5259_4164C870_A0D6D480_2D0C2ADA_71D2B01E_6ADD02A8_4795DE22_B388C8D0, - 256'h5D959738_142A165E_34363752_C326EE1C_A064C2AE_996A0EFA_4D8C8F1B_0448681E, - 256'h80C6F232_4294E34A_6FAF2EB9_F571456D_A3359F06_496A9425_34CB2989_6A222CDA, - 256'h753C0542_78E0832B_116B4AC9_87D1B3FC_6E86D059_D0BF570D_0411BD69_51C53711, - 256'h0CCF950A_E63911F4_E0B1A1DE_A1FF126F_E9F7782F_1F5B53A9_E9321F84_1AB19662, - 256'hE9346614_6BF4BDD4_424BE8A6_75BFE4E9_A44F2755_64F4DAAB_1F572F05_4D43D5F4, - 256'hC6A54141_D8AF2F58_B96E82C3_53943824_510A0729_D7868CFB_2C8E31E6_DA242C80, - 256'hD3111925_3C6AA540_B8A6278B_F006BD40_4898915F_81E55567_BFA91C25_1ABC86A7, - 256'h4EEF8F55_BC305436_0A2365E0_55DA03E0_4E63DC3B_44F79DD8_D2052226_93E82E33, - 256'h15F1C641_2E1CA5E6_B05A8055_93708038_A2B08928_64CFE082_117F040B_4CA7924C, - 256'h94D9AF9F_0895D084_9026B591_7B5D9842_D4A3C293_B7AE4516_C137C43F_7602B624, - 256'hAE589216_56DF351A_E107074A_812344DD_77492272_97287191_F9DA1161_3B213017, - 256'hE96828D7_721CFA42_7E78444B_6563046A_BA3EFBB0_A513B97A_0C5378A8_3E33A352, - 256'hB5073871_4BC51D60_2DE76401_788A6218_0D060217_9ECFB5D4_65C87885_D171F143, - 256'h216843F5_A23305C6_4A02646E_E9400884_1BA91903_6619AA9D_7C5AE306_ADBE355D, - 256'h5B284737_E9E58134_6D0F4546_B67B61E1_A4ED42E8_A36C7774_2AE9ECC2_6DA412D2, - 256'hDB724367_7F1A9501_C008C000_15EAE94F_4B5C5810_605E30E3_0ED083AB_D32E6813, - 256'h5ADB1636_A1625865_819FF178_EC09C0AF_6672656A_4BA8262F_8E6DC7EC_100E96F7, - 256'h471F3115_8B945E3A_4CA5A46F_35A6C120_52990425_A0E06CA2_45310C38_DF65268E, - 256'h0E1277E5_C603C9B1_4C82975F_4BA5CC58_6A35211E_9E89F10E_E2861AAB_B0A84509, - 256'h50285039_C26C12F3_B0CB6ABD_0F6202E8_F947AD5F_DC06F89C_4BB0D62C_1AD24A81, - 256'h942AA1D2_3E44A52A_91D40B88_E5396AC1_90D3F6C6_B95C1C08_3DA7C2E5_5A32922C, - 256'h0FC9CD01_57403818_589D894C_4D99188F_03EA7099_83B24CBC_A2C3963B_1607DF70, - 256'hA6F7B91F_A62985BA_8A5880E6_B8D86BC1_796CC230_5CDE848E_B7907B01_566B1890 + 64'h039B0B1D_7EC6423A, + 256'h3DE08898_652A0B19_58C22D4D_0A9CB596_0D4CDACB_751898E7_5C1975B2_2B087C34, + 256'h7207AC4B_1A396ED2_30307BF1_771EF4B6_9544EABF_81D13989_EC5DE607_60D7918B, + 256'h78C6F321_D232650D_066B1409_2065D712_58F554E3_A70EE187_2991B497_4E23272A, + 256'h6D1CCEE8_B43C501A_69301A09_5CD2A600_58EA4B99_2A7E8708_85DD272A_8856C912, + 256'h6AA6F456_4589E8BA_8AB0CE61_EE4984A3_D45510AE_AB819EF9_1B0320A2_B65CCC1B, + 256'h120AA78E_C6754BB6_E5F54A51_4F0CD66C_68B5E9DC_512B18EE_3779F7A7_18757C16, + 256'h6FED8176_9FA56290_5D4E692B_486AC210_4D250519_3EECE1C5_F85BA275_B4F66DE0, + 256'h878D0095_D262AF07_A12DFA94_743A1A55_FE6A6824_B4284526_1F2C456A_B525B377, + 256'h002928B8_ADD350AA_D8A80CBD_70375079_31512285_A8850EF0_76E50DCF_2936BB5E, + 256'h9452E508_B426B186_9A9E71D7_6E421F84_C685C280_E786E132_2345F658_2D129FC7, + 256'h3A7CC32F_D3CE8016_4647CC55_2CD5C62D_29B58EB0_A44B34CB_2A36F722_2EC24B02, + 256'h5681509E_4E444832_B2ABAFA5_9B2A963F_C6E96105_BDA0C5F4_D04111BC_26AE4716, + 256'hC784333E_6EBADCE4_47D564B0_B1B2DCFA_4C7F9BEC_6C6DEE34_42F1F5DA_3AA28320, + 256'h1141ACFA_0AFF5986_6146DE4B_D83424BE_8F290C7E_35A0C4F2_76134F70_F3698211, + 256'h2B37C5EA_4D43D678_C6AC8141_D8AF2F68_57AE74BF_8A58150E_80544281_F0BA24F3, + 256'h3EEA238C_774AA60B_2D24C446_494F19B9_502E1D77_069701B1_5011B524_59F07955, + 256'h59F1E6F2_87AB2914_6A1B1AAC_0C3AFC56_EF8150D8_288D9049_57710F81_398F7A27, + 256'hB3DF0A63_4814889A_4FAD1C72_4815C056_412E1CA7_7A89B916_A16564DC_200E2902, + 256'h114A1933_F82089AC_D102F229_DE532536_6BE98BB9_74212567_FD645ED7_6611E62D, + 256'h4A36293B_4C23316C_137D43F7_F82B624A_E5892165_6E035281_91C2468D_BBBC1399, + 256'h863475A3_72281B2F_C076BA88_22422949_E9770314_DE3F0F8C_E914AD41_CE16CF10, + 256'h47580C35_D9005E22_98860341_8085E79A_65C51972_1E21745C_7C50C85B_C4FD688C, + 256'hC1719280_991AF686_022106EA_5E40D986_6AC55F16_B8C2386A_DBE355D5_BA44737E, + 256'hBC581346_D250928F_4546D57B_61E1A4ED_42EA736C_77742CC9_F8C26DA4_12D2FA72, + 256'h6670D9DF_79254070_02300005_7AD953D2_D7160418_178880C3_BBE0E9CA_DC32E7D9, + 256'hA04D6B6E_48DAE789_6196069B_37A3B025_8EC599C9_967F6A4B_A8262F8E_6FB7EC10, + 256'h0E96F744_90312895_6304178E_9329691B_CD69B048_14A64109_68382A16_CA245310, + 256'hC38DF652_68E0E127_7E5C603C_9B14C829_75F4C21C_C586A352_11E9E89F_10F01861, + 256'hAAB4F0B2_A1142540_A140E709_81FC4EE2_2DAAF43D_880BA3E5_1EB57F43_9C62712E, + 256'hC358B06B_492A0650_AA8748F9_1294AA47_502E2394_E5AB0643_4FDB1AE5_707020F6, + 256'h9D859568_CA48B03F_2734055D_00F05818_589D8945_E599188F_03EA7099_83B24CBC }; // Compile-time random data for PRNG buffer default seed parameter kmac_pkg::buffer_lfsr_seed_t RndCnstKmacBufferLfsrSeed = { - 32'hA9AACA4D, - 256'hB84A32E5_C6985A1A_6435118B_5F5F3FD3_B9313116_B67192D8_56DD742D_40E072E4, - 256'h17AD9A5F_261204CB_CC69A214_7819B290_A4BB0264_347C0F91_B0CEC93C_0129D85B, - 256'h95801DBE_03F17E69_DC260A79_998EFF5C_710B6783_8ADFB99A_5ECA6716_72CF19BC + 32'h0B67838A, + 256'hDFB99A5E_CA671672_CF19BCA6_ADC1EBFA_B611F19E_7262E0A4_91970E51_B28E7026, + 256'hD0E5DCE9_E265A416_A812231C_FA76E3D9_82F8FDCE_C9AE1AF0_B8CD9E17_606EC981, + 256'h060E9479_5A1D5730_89578C10_4A36A647_E90FFAFF_9760F5E8_38BD8E24_13AB956B }; // Compile-time random permutation for LFSR Message output parameter kmac_pkg::msg_perm_t RndCnstKmacMsgPerm = { - 128'hE4D3967C_CC7D4325_616A64EF_7A88AE09, - 256'h7ED1D4AC_CB3D2040_D1BDFE1A_074723CA_85D99278_8EC50396_4FD87271_2DEB0AE9 - }; - - //////////////////////////////////////////// - // otbn - //////////////////////////////////////////// - // Default seed of the PRNG used for URND. - parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = { - 256'h9A07EFFE_E457DEE8_2B6E0666_3C291739_FF0E7D64_4758FEE1_C58564CF_346D9622 - }; - - // Compile-time random reset value for IMem/DMem scrambling key. - parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = { - 128'hE5371091_366EFBD6_1B0CB470_B944EF80 - }; - - // Compile-time random reset value for IMem/DMem scrambling nonce. - parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = { - 64'h6E573B44_B643EBF0 + 128'h728AD408_62DDE228_12C09C8C_7804D81F, + 256'h1F50917B_EAD2E6AD_EE3F2722_5D4DB215_91CDF0CE_1763D9EB_E2B75790_66FE96C4 }; //////////////////////////////////////////// @@ -450,73 +450,73 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for initial LFSR seed parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrLfsrSeed = { - 64'hC5DE019F_C073C4C5 + 64'h32FCC4D3_092BD638 }; // Compile-time random permutation for LFSR output parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrLfsrPerm = { - 128'h6C3C15DB_9AE58526_58A4859D_FFAB075D, - 256'h306ADE3C_F569F020_E2D172BA_F9C610B7_B4A0F38A_08C24DFB_1EFD7104_64F22526 + 128'h89362C32_395757BB_BDB4747E_E20E7C0D, + 256'hF76BC699_F759091A_348CAA08_0CD26D90_5C87F166_27038AD4_610BEB4B_DE528D8F }; // Compile-time random permutation for entropy used in share overriding parameter keymgr_pkg::rand_perm_t RndCnstKeymgrRandPerm = { - 160'h74C7FE91_8685399B_1C3E88A5_8055A5D2_EE97ED0A + 160'hA9333D85_87160C94_5D4D7497_CD7A2505_3F6EBC70 }; // Compile-time random bits for revision seed parameter keymgr_pkg::seed_t RndCnstKeymgrRevisionSeed = { - 256'hADCDFC5C_5F76D4A8_E259D88D_FE9B670A_A0DD992B_FE5D2E12_489D2250_4AA7AC1C + 256'h504AA7AC_1C67F59C_BA5482C1_E35E6E33_35C20CC7_78FC3099_17B9C870_ABE0895D }; // Compile-time random bits for creator identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrCreatorIdentitySeed = { - 256'h67F59CBA_5482C1E3_5E6E3335_C20CC778_FC309917_B9C870AB_E0895D76_F862EF81 + 256'h76F862EF_81F419E3_C6CDC866_2C71EAC1_41666E44_3C6492D9_BCF7A824_20750E5D }; // Compile-time random bits for owner intermediate identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIntIdentitySeed = { - 256'hF419E3C6_CDC8662C_71EAC141_666E443C_6492D9BC_F7A82420_750E5DFC_5E3ED4F2 + 256'hFC5E3ED4_F2907532_E179EBEC_7ED7D3A5_EF4982F7_3ED91C4B_1CD0C85E_C5E548B4 }; // Compile-time random bits for owner identity seed parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIdentitySeed = { - 256'h907532E1_79EBEC7E_D7D3A5EF_4982F73E_D91C4B1C_D0C85EC5_E548B401_84A69EB1 + 256'h0184A69E_B1E54396_460E36C5_5C459EFE_9E43836F_E878E464_337EBCAE_3238DCDF }; // Compile-time random bits for software generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrSoftOutputSeed = { - 256'hE5439646_0E36C55C_459EFE9E_43836FE8_78E46433_7EBCAE32_38DCDF7D_E88B56B4 + 256'h7DE88B56_B405E02B_BFD73849_C511F7F0_B79F91DC_D1D589B4_CAC4372C_385F89D9 }; // Compile-time random bits for hardware generation seed parameter keymgr_pkg::seed_t RndCnstKeymgrHardOutputSeed = { - 256'h05E02BBF_D73849C5_11F7F0B7_9F91DCD1_D589B4CA_C4372C38_5F89D902_019DABB6 + 256'h02019DAB_B6DD5702_2C77EDE8_609C409D_905B3C78_19B26A67_43288199_28C5D79B }; // Compile-time random bits for generation seed when aes destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrAesSeed = { - 256'hDD57022C_77EDE860_9C409D90_5B3C7819_B26A6743_28819928_C5D79BF1_DB63D11E + 256'hF1DB63D1_1E1C31BB_C9A8C73F_C4CC3D14_CA6BC0B9_6812DE7C_775A54FF_19343CB3 }; // Compile-time random bits for generation seed when kmac destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrKmacSeed = { - 256'h1C31BBC9_A8C73FC4_CC3D14CA_6BC0B968_12DE7C77_5A54FF19_343CB320_40B34907 + 256'h2040B349_0768889D_27E0BA85_88D34C05_BCF127DA_E58B65D6_A2510880_99B37107 }; - // Compile-time random bits for generation seed when otbn destination selected - parameter keymgr_pkg::seed_t RndCnstKeymgrOtbnSeed = { - 256'h68889D27_E0BA8588_D34C05BC_F127DAE5_8B65D6A2_51088099_B37107B1_CCCF1A95 + // Compile-time random bits for generation seed when acc destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrAccSeed = { + 256'hB1CCCF1A_955F03DE_1A8447BF_83B69C50_E149CF51_784A9D7A_C691306E_5C56CE38 }; // Compile-time random bits for generation seed when no CDI is selected parameter keymgr_pkg::seed_t RndCnstKeymgrCdi = { - 256'h5F03DE1A_8447BF83_B69C50E1_49CF5178_4A9D7AC6_91306E5C_56CE38CD_7D7E3B1A + 256'hCD7D7E3B_1ABFB797_8189A21A_E856F1D9_08E3F70D_E343D222_6E9E8644_65A8EE55 }; // Compile-time random bits for generation seed when no destination selected parameter keymgr_pkg::seed_t RndCnstKeymgrNoneSeed = { - 256'hBFB79781_89A21AE8_56F1D908_E3F70DE3_43D2226E_9E864465_A8EE55EC_0E6A2967 + 256'hEC0E6A29_6789DED5_C0AF59EE_62F1FD1B_BEBEAC22_05B1FA5E_94E72EB7_EB1A713A }; //////////////////////////////////////////// @@ -524,14 +524,14 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = { - 128'h89DED5C0_AF59EE62_F1FD1BBE_BEAC2205, - 256'hB1FA5E94_E72EB7EB_1A713AD1_5D2565D9_AB4FBCD2_E17C406F_48D1401F_8A6A5228 + 128'hD15D2565_D9AB4FBC_D2E17C40_6F48D140, + 256'h1F8A6A52_286F6954_C27A9AEF_BE0BC9EE_440C514C_CACB0199_95F31FA9_58859293 }; // Compile-time random bits for csrng state group diversification value parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = { - 128'h6F6954C2_7A9AEFBE_0BC9EE44_0C514CCA, - 256'hCB019995_F31FA958_859293C5_591AE604_A92A3037_60EB8D77_85A7BBDC_E1D6A02B + 128'hC5591AE6_04A92A30_3760EB8D_7785A7BB, + 256'hDCE1D6A0_2B6F0F24_F5DB8EF0_2F9FB0A4_023D8F96_A41F062B_B66B2287_01E8317C }; //////////////////////////////////////////// @@ -539,23 +539,23 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Compile-time random reset value for SRAM scrambling key. parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = { - 128'h6F0F24F5_DB8EF02F_9FB0A402_3D8F96A4 + 128'hD4BF08BD_6684A1D5_96CC57E1_37A0321F }; // Compile-time random reset value for SRAM scrambling nonce. parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = { - 128'h1F062BB6_6B228701_E8317CD4_BF08BD66 + 128'hB803BFD2_DE7A90A1_357E743C_E460442C }; // Compile-time random bits for initial LFSR seed parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = { - 64'h84A1D596_CC57E137 + 64'h10686E82_613DE080 }; // Compile-time random permutation for LFSR output parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = { - 128'h876E1071_92350A20_CA4CEC97_5A519551, - 256'h2F01EFAF_8916C9AD_9F38E9E7_DAEAC708_1B6842D1_60F75F37_F91EDF4B_C0B87328 + 128'h77FE01B8_FF706A32_7247B85C_D92433C5, + 256'h5B26967F_2F17E786_50AD03A5_911738CA_ADA24582_022E532F_52207FA6_2B347DDB }; //////////////////////////////////////////// @@ -563,12 +563,12 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Fixed nonce used for address / data scrambling parameter bit [63:0] RndCnstRomCtrlScrNonce = { - 64'hBEF1F0B9_24C470AC + 64'h5F4EA1E4_63032A3A }; // Randomised constant used as a scrambling key for ROM data parameter bit [127:0] RndCnstRomCtrlScrKey = { - 128'h5A998099_85DC415B_A1EACED3_82D54C9E + 128'h8E24B454_7F8B0DB0_C77E9027_76B104C3 }; //////////////////////////////////////////// @@ -576,22 +576,22 @@ package top_earlgrey_rnd_cnst_pkg; //////////////////////////////////////////// // Default seed of the PRNG used for random instructions. parameter ibex_pkg::lfsr_seed_t RndCnstRvCoreIbexLfsrSeed = { - 32'h378D030E + 32'hA9DA0203 }; // Permutation applied to the LFSR of the PRNG used for random instructions. parameter ibex_pkg::lfsr_perm_t RndCnstRvCoreIbexLfsrPerm = { - 160'h0D55033F_A315DB64_4A782476_5CF3E958_0FE63B54 + 160'hFC2DBE9A_F10A1E24_E3CA634B_99C86BAB_8FCD5080 }; // Default icache scrambling key parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexIbexKeyDefault = { - 128'hA4D3D738_71FDAF5A_D0C1DD1E_95F99D71 + 128'h91C2BD31_6277126E_A6934D37_49740A7C }; // Default icache scrambling nonce parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexIbexNonceDefault = { - 64'h29CA6861_A4425B9C + 64'hE7C92A49_F71747D5 }; endpackage : top_earlgrey_rnd_cnst_pkg diff --git a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core index b04b159d554..e925f2eab4b 100644 --- a/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core +++ b/hw/top_earlgrey/rtl/autogen/testing/top_earlgrey_testing_rnd_cnst_pkg.core @@ -15,12 +15,12 @@ filesets: - lowrisc:earlgrey_ip:flash_ctrl - lowrisc:earlgrey_ip:otp_ctrl_top_specific_pkg - lowrisc:ibex:ibex_pkg + - lowrisc:ip:acc_pkg - lowrisc:ip:aes - lowrisc:ip:csrng_pkg - lowrisc:ip:keymgr_pkg - lowrisc:ip:kmac_pkg - lowrisc:ip:lc_ctrl_pkg - - lowrisc:ip:otbn_pkg - lowrisc:ip:otp_ctrl_pkg - lowrisc:ip:sram_ctrl_pkg files: diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index c5e4cdd8309..f83a9374fd1 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -76,6 +76,12 @@ module top_earlgrey #( parameter bit SecRvDmVolatileRawUnlockEn = 1'b0, parameter logic [tlul_pkg::RsvdWidth-1:0] RvDmTlulHostUserRsvdBits = '0, // parameters for rv_plic + // parameters for acc + parameter bit AccStub = 0, + parameter acc_pkg::regfile_e AccRegFile = acc_pkg::RegFileFF, + parameter bit SecAccMuteUrnd = 0, + parameter bit SecAccSkipUrndReseedAtStart = 0, + parameter bit AccAccPQCEn = 0, // parameters for aes parameter bit SecAesMasking = 1, parameter aes_pkg::sbox_impl_e SecAesSBoxImpl = aes_pkg::SBoxImplDom, @@ -90,13 +96,7 @@ module top_earlgrey #( parameter bit SecKmacIdleAcceptSwMsg = 0, parameter int KmacNumAppIntf = 4, parameter kmac_pkg::app_config_t KmacAppCfg[KmacNumAppIntf] = - '{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgOTBN}, - // parameters for otbn - parameter bit OtbnStub = 0, - parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF, - parameter bit SecOtbnMuteUrnd = 0, - parameter bit SecOtbnSkipUrndReseedAtStart = 0, - parameter bit OtbnOtbnPQCEn = 0, + '{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgACC}, // parameters for keymgr parameter bit KeymgrUseOtpSeedsInsteadOfFlash = 0, parameter bit KeymgrKmacEnMasking = 1, @@ -410,10 +410,10 @@ module top_earlgrey #( logic cio_flash_ctrl_tdo_en_d2p; // rv_dm // rv_plic + // acc // aes // hmac // kmac - // otbn // keymgr // csrng // entropy_src @@ -560,13 +560,13 @@ module top_earlgrey #( logic intr_flash_ctrl_rd_lvl; logic intr_flash_ctrl_op_done; logic intr_flash_ctrl_corr_err; + logic intr_acc_done; logic intr_hmac_hmac_done; logic intr_hmac_fifo_empty; logic intr_hmac_hmac_err; logic intr_kmac_kmac_done; logic intr_kmac_fifo_empty; logic intr_kmac_kmac_err; - logic intr_otbn_done; logic intr_keymgr_op_done; logic intr_csrng_cs_cmd_req_done; logic intr_csrng_cs_entropy_req; @@ -636,12 +636,12 @@ module top_earlgrey #( edn_pkg::edn_rsp_t [7:0] edn0_edn_rsp; edn_pkg::edn_req_t [7:0] edn1_edn_req; edn_pkg::edn_rsp_t [7:0] edn1_edn_rsp; - otp_ctrl_pkg::otbn_otp_key_req_t otp_ctrl_otbn_otp_key_req; - otp_ctrl_pkg::otbn_otp_key_rsp_t otp_ctrl_otbn_otp_key_rsp; + otp_ctrl_pkg::acc_otp_key_req_t otp_ctrl_acc_otp_key_req; + otp_ctrl_pkg::acc_otp_key_rsp_t otp_ctrl_acc_otp_key_rsp; otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key; keymgr_pkg::hw_key_req_t keymgr_aes_key; keymgr_pkg::hw_key_req_t keymgr_kmac_key; - keymgr_pkg::otbn_key_req_t keymgr_otbn_key; + keymgr_pkg::acc_key_req_t keymgr_acc_key; kmac_pkg::app_req_t [KmacNumAppIntf-1:0] kmac_app_req; kmac_pkg::app_rsp_t [KmacNumAppIntf-1:0] kmac_app_rsp; logic kmac_en_masking; @@ -732,8 +732,8 @@ module top_earlgrey #( tlul_pkg::tl_d2h_t edn1_tl_rsp; tlul_pkg::tl_h2d_t rv_plic_tl_req; tlul_pkg::tl_d2h_t rv_plic_tl_rsp; - tlul_pkg::tl_h2d_t otbn_tl_req; - tlul_pkg::tl_d2h_t otbn_tl_rsp; + tlul_pkg::tl_h2d_t acc_tl_req; + tlul_pkg::tl_d2h_t acc_tl_rsp; tlul_pkg::tl_h2d_t keymgr_tl_req; tlul_pkg::tl_d2h_t keymgr_tl_rsp; tlul_pkg::tl_h2d_t rv_core_ibex_cfg_tl_d_req; @@ -964,17 +964,17 @@ module top_earlgrey #( // secure_lc_0 assign lpg_cg_en[19] = clkmgr_aon_cg_en.main_secure; assign lpg_rst_en[19] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // aes_trans_lc_0 - assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_aes; + // acc_trans_lc_0 + assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_acc; assign lpg_rst_en[20] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // hmac_trans_lc_0 - assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_hmac; + // aes_trans_lc_0 + assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_aes; assign lpg_rst_en[21] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // kmac_trans_lc_0 - assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_kmac; + // hmac_trans_lc_0 + assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_hmac; assign lpg_rst_en[22] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; - // otbn_trans_lc_0 - assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_otbn; + // kmac_trans_lc_0 + assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_kmac; assign lpg_rst_en[23] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; @@ -1559,8 +1559,8 @@ module top_earlgrey #( .flash_otp_key_o(flash_ctrl_otp_rsp), .sram_otp_key_i(otp_ctrl_sram_otp_key_req), .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp), - .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req), - .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp), + .acc_otp_key_i(otp_ctrl_acc_otp_key_req), + .acc_otp_key_o(otp_ctrl_acc_otp_key_rsp), .otp_broadcast_o(otp_ctrl_otp_broadcast), .otp_macro_o(otp_ctrl_otp_macro_req), .otp_macro_i(otp_ctrl_otp_macro_rsp), @@ -2429,9 +2429,58 @@ module top_earlgrey #( .clk_i (clkmgr_aon_clocks.clk_main_secure), .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); - aes #( + acc #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]), .AlertSkewCycles(top_pkg::AlertSkewCycles), + .Stub(AccStub), + .RegFile(AccRegFile), + .RndCnstUrndPrngSeed(RndCnstAccUrndPrngSeed), + .SecMuteUrnd(SecAccMuteUrnd), + .SecSkipUrndReseedAtStart(SecAccSkipUrndReseedAtStart), + .RndCnstAccKey(RndCnstAccAccKey), + .RndCnstAccNonce(RndCnstAccAccNonce), + .AccPQCEn(AccAccPQCEn) + ) u_acc ( + + // Interrupt + .intr_done_o (intr_acc_done), + // alert_handler[42]: fatal + // alert_handler[43]: recov + .alert_tx_o ( alert_tx[43:42] ), + .alert_rx_i ( alert_rx[43:42] ), + + // Inter-module signals + .acc_otp_key_o(otp_ctrl_acc_otp_key_req), + .acc_otp_key_i(otp_ctrl_acc_otp_key_rsp), + .edn_rnd_o(edn1_edn_req[0]), + .edn_rnd_i(edn1_edn_rsp[0]), + .edn_urnd_o(edn0_edn_req[6]), + .edn_urnd_i(edn0_edn_rsp[6]), + .kmac_data_o(kmac_app_req[3]), + .kmac_data_i(kmac_app_rsp[3]), + .idle_o(clkmgr_aon_idle[0]), + .ram_cfg_imem_i(ast_ram_1p_cfg), + .ram_cfg_dmem_i(ast_ram_1p_cfg), + .ram_cfg_rsp_imem_o(), + .ram_cfg_rsp_dmem_o(), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_rma_req_i(lc_ctrl_lc_flash_rma_req), + .lc_rma_ack_o(lc_ctrl_lc_flash_rma_ack[1]), + .keymgr_key_i(keymgr_acc_key), + .tl_i(acc_tl_req), + .tl_o(acc_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_acc), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + aes #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:44]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), .AES192Enable(1'b1), .SecMasking(SecAesMasking), .SecSBoxImpl(SecAesSBoxImpl), @@ -2444,13 +2493,13 @@ module top_earlgrey #( .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm) ) u_aes ( - // alert_handler[42]: recov_ctrl_update_err - // alert_handler[43]: fatal_fault - .alert_tx_o ( alert_tx[43:42] ), - .alert_rx_i ( alert_rx[43:42] ), + // alert_handler[44]: recov_ctrl_update_err + // alert_handler[45]: fatal_fault + .alert_tx_o ( alert_tx[45:44] ), + .alert_rx_i ( alert_rx[45:44] ), // Inter-module signals - .idle_o(clkmgr_aon_idle[0]), + .idle_o(clkmgr_aon_idle[1]), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .edn_o(edn0_edn_req[5]), .edn_i(edn0_edn_rsp[5]), @@ -2466,7 +2515,7 @@ module top_earlgrey #( .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); hmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:46]), .AlertSkewCycles(top_pkg::AlertSkewCycles) ) u_hmac ( @@ -2474,12 +2523,12 @@ module top_earlgrey #( .intr_hmac_done_o (intr_hmac_hmac_done), .intr_fifo_empty_o (intr_hmac_fifo_empty), .intr_hmac_err_o (intr_hmac_hmac_err), - // alert_handler[44]: fatal_fault - .alert_tx_o ( alert_tx[44:44] ), - .alert_rx_i ( alert_rx[44:44] ), + // alert_handler[46]: fatal_fault + .alert_tx_o ( alert_tx[46:46] ), + .alert_rx_i ( alert_rx[46:46] ), // Inter-module signals - .idle_o(clkmgr_aon_idle[1]), + .idle_o(clkmgr_aon_idle[2]), .tl_i(hmac_tl_req), .tl_o(hmac_tl_rsp), @@ -2488,7 +2537,7 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); kmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), .AlertSkewCycles(top_pkg::AlertSkewCycles), .EnMasking(KmacEnMasking), .SwKeyMasked(KmacSwKeyMasked), @@ -2506,10 +2555,10 @@ module top_earlgrey #( .intr_kmac_done_o (intr_kmac_kmac_done), .intr_fifo_empty_o (intr_kmac_fifo_empty), .intr_kmac_err_o (intr_kmac_kmac_err), - // alert_handler[45]: recov_operation_err - // alert_handler[46]: fatal_fault_err - .alert_tx_o ( alert_tx[46:45] ), - .alert_rx_i ( alert_rx[46:45] ), + // alert_handler[47]: recov_operation_err + // alert_handler[48]: fatal_fault_err + .alert_tx_o ( alert_tx[48:47] ), + .alert_rx_i ( alert_rx[48:47] ), // Inter-module signals .keymgr_key_i(keymgr_kmac_key), @@ -2517,7 +2566,7 @@ module top_earlgrey #( .app_o(kmac_app_rsp), .entropy_o(edn0_edn_req[3]), .entropy_i(edn0_edn_rsp[3]), - .idle_o(clkmgr_aon_idle[2]), + .idle_o(clkmgr_aon_idle[3]), .en_masking_o(kmac_en_masking), .lc_escalate_en_i(lc_ctrl_lc_escalate_en), .tl_i(kmac_tl_req), @@ -2530,55 +2579,6 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) ); - otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), - .AlertSkewCycles(top_pkg::AlertSkewCycles), - .Stub(OtbnStub), - .RegFile(OtbnRegFile), - .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed), - .SecMuteUrnd(SecOtbnMuteUrnd), - .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart), - .RndCnstOtbnKey(RndCnstOtbnOtbnKey), - .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce), - .OtbnPQCEn(OtbnOtbnPQCEn) - ) u_otbn ( - - // Interrupt - .intr_done_o (intr_otbn_done), - // alert_handler[47]: fatal - // alert_handler[48]: recov - .alert_tx_o ( alert_tx[48:47] ), - .alert_rx_i ( alert_rx[48:47] ), - - // Inter-module signals - .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), - .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp), - .edn_rnd_o(edn1_edn_req[0]), - .edn_rnd_i(edn1_edn_rsp[0]), - .edn_urnd_o(edn0_edn_req[6]), - .edn_urnd_i(edn0_edn_rsp[6]), - .kmac_data_o(kmac_app_req[3]), - .kmac_data_i(kmac_app_rsp[3]), - .idle_o(clkmgr_aon_idle[3]), - .ram_cfg_imem_i(ast_ram_1p_cfg), - .ram_cfg_dmem_i(ast_ram_1p_cfg), - .ram_cfg_rsp_imem_o(), - .ram_cfg_rsp_dmem_o(), - .lc_escalate_en_i(lc_ctrl_lc_escalate_en), - .lc_rma_req_i(lc_ctrl_lc_flash_rma_req), - .lc_rma_ack_o(lc_ctrl_lc_flash_rma_ack[1]), - .keymgr_key_i(keymgr_otbn_key), - .tl_i(otbn_tl_req), - .tl_o(otbn_tl_rsp), - - // Clock and reset connections - .clk_i (clkmgr_aon_clocks.clk_main_otbn), - .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), - .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure), - .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), - .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), - .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) - ); keymgr #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]), .AlertSkewCycles(top_pkg::AlertSkewCycles), @@ -2595,7 +2595,7 @@ module top_earlgrey #( .RndCnstHardOutputSeed(RndCnstKeymgrHardOutputSeed), .RndCnstAesSeed(RndCnstKeymgrAesSeed), .RndCnstKmacSeed(RndCnstKeymgrKmacSeed), - .RndCnstOtbnSeed(RndCnstKeymgrOtbnSeed), + .RndCnstAccSeed(RndCnstKeymgrAccSeed), .RndCnstCdi(RndCnstKeymgrCdi), .RndCnstNoneSeed(RndCnstKeymgrNoneSeed) ) u_keymgr ( @@ -2612,7 +2612,7 @@ module top_earlgrey #( .edn_i(edn0_edn_rsp[0]), .aes_key_o(keymgr_aes_key), .kmac_key_o(keymgr_kmac_key), - .otbn_key_o(keymgr_otbn_key), + .acc_key_o(keymgr_acc_key), .kmac_data_o(kmac_app_req[0]), .kmac_data_i(kmac_app_rsp[0]), .otp_key_i(otp_ctrl_otp_keymgr_key), @@ -2941,13 +2941,13 @@ module top_earlgrey #( intr_csrng_cs_entropy_req, // IDs [175 +: 1] intr_csrng_cs_cmd_req_done, // IDs [174 +: 1] intr_keymgr_op_done, // IDs [173 +: 1] - intr_otbn_done, // IDs [172 +: 1] - intr_kmac_kmac_err, // IDs [171 +: 1] - intr_kmac_fifo_empty, // IDs [170 +: 1] - intr_kmac_kmac_done, // IDs [169 +: 1] - intr_hmac_hmac_err, // IDs [168 +: 1] - intr_hmac_fifo_empty, // IDs [167 +: 1] - intr_hmac_hmac_done, // IDs [166 +: 1] + intr_kmac_kmac_err, // IDs [172 +: 1] + intr_kmac_fifo_empty, // IDs [171 +: 1] + intr_kmac_kmac_done, // IDs [170 +: 1] + intr_hmac_hmac_err, // IDs [169 +: 1] + intr_hmac_fifo_empty, // IDs [168 +: 1] + intr_hmac_hmac_done, // IDs [167 +: 1] + intr_acc_done, // IDs [166 +: 1] intr_flash_ctrl_corr_err, // IDs [165 +: 1] intr_flash_ctrl_op_done, // IDs [164 +: 1] intr_flash_ctrl_rd_lvl, // IDs [163 +: 1] @@ -3186,9 +3186,9 @@ module top_earlgrey #( .tl_rv_plic_o(rv_plic_tl_req), .tl_rv_plic_i(rv_plic_tl_rsp), - // port: tl_otbn - .tl_otbn_o(otbn_tl_req), - .tl_otbn_i(otbn_tl_rsp), + // port: tl_acc + .tl_acc_o(acc_tl_req), + .tl_acc_i(acc_tl_rsp), // port: tl_keymgr .tl_keymgr_o(keymgr_tl_req), diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 527ada911d1..40866e8af97 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -369,6 +369,16 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_RV_PLIC_SIZE_BYTES = 32'h8000000; + /** + * Peripheral base address for acc in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_ACC_BASE_ADDR = 32'h41300000; + + /** + * Peripheral size in bytes for acc in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_ACC_SIZE_BYTES = 32'h20000; + /** * Peripheral base address for aes in top earlgrey. */ @@ -399,16 +409,6 @@ package top_earlgrey_pkg; */ parameter int unsigned TOP_EARLGREY_KMAC_SIZE_BYTES = 32'h1000; - /** - * Peripheral base address for otbn in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_OTBN_BASE_ADDR = 32'h41300000; - - /** - * Peripheral size in bytes for otbn in top earlgrey. - */ - parameter int unsigned TOP_EARLGREY_OTBN_SIZE_BYTES = 32'h20000; - /** * Peripheral base address for keymgr in top earlgrey. */ @@ -561,10 +561,10 @@ package top_earlgrey_pkg; TopEarlgreyAlertPeripheralFlashCtrl = 26, TopEarlgreyAlertPeripheralRvDm = 27, TopEarlgreyAlertPeripheralRvPlic = 28, - TopEarlgreyAlertPeripheralAes = 29, - TopEarlgreyAlertPeripheralHmac = 30, - TopEarlgreyAlertPeripheralKmac = 31, - TopEarlgreyAlertPeripheralOtbn = 32, + TopEarlgreyAlertPeripheralAcc = 29, + TopEarlgreyAlertPeripheralAes = 30, + TopEarlgreyAlertPeripheralHmac = 31, + TopEarlgreyAlertPeripheralKmac = 32, TopEarlgreyAlertPeripheralKeymgr = 33, TopEarlgreyAlertPeripheralCsrng = 34, TopEarlgreyAlertPeripheralEntropySrc = 35, @@ -620,13 +620,13 @@ package top_earlgrey_pkg; TopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 39, TopEarlgreyAlertIdRvDmFatalFault = 40, TopEarlgreyAlertIdRvPlicFatalFault = 41, - TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 42, - TopEarlgreyAlertIdAesFatalFault = 43, - TopEarlgreyAlertIdHmacFatalFault = 44, - TopEarlgreyAlertIdKmacRecovOperationErr = 45, - TopEarlgreyAlertIdKmacFatalFaultErr = 46, - TopEarlgreyAlertIdOtbnFatal = 47, - TopEarlgreyAlertIdOtbnRecov = 48, + TopEarlgreyAlertIdAccFatal = 42, + TopEarlgreyAlertIdAccRecov = 43, + TopEarlgreyAlertIdAesRecovCtrlUpdateErr = 44, + TopEarlgreyAlertIdAesFatalFault = 45, + TopEarlgreyAlertIdHmacFatalFault = 46, + TopEarlgreyAlertIdKmacRecovOperationErr = 47, + TopEarlgreyAlertIdKmacFatalFaultErr = 48, TopEarlgreyAlertIdKeymgrRecovOperationErr = 49, TopEarlgreyAlertIdKeymgrFatalFaultErr = 50, TopEarlgreyAlertIdCsrngRecovAlert = 51, @@ -814,13 +814,13 @@ package top_earlgrey_pkg; TopEarlgreyPlicIrqIdFlashCtrlRdLvl = 163, TopEarlgreyPlicIrqIdFlashCtrlOpDone = 164, TopEarlgreyPlicIrqIdFlashCtrlCorrErr = 165, - TopEarlgreyPlicIrqIdHmacHmacDone = 166, - TopEarlgreyPlicIrqIdHmacFifoEmpty = 167, - TopEarlgreyPlicIrqIdHmacHmacErr = 168, - TopEarlgreyPlicIrqIdKmacKmacDone = 169, - TopEarlgreyPlicIrqIdKmacFifoEmpty = 170, - TopEarlgreyPlicIrqIdKmacKmacErr = 171, - TopEarlgreyPlicIrqIdOtbnDone = 172, + TopEarlgreyPlicIrqIdAccDone = 166, + TopEarlgreyPlicIrqIdHmacHmacDone = 167, + TopEarlgreyPlicIrqIdHmacFifoEmpty = 168, + TopEarlgreyPlicIrqIdHmacHmacErr = 169, + TopEarlgreyPlicIrqIdKmacKmacDone = 170, + TopEarlgreyPlicIrqIdKmacFifoEmpty = 171, + TopEarlgreyPlicIrqIdKmacKmacErr = 172, TopEarlgreyPlicIrqIdKeymgrOpDone = 173, TopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 174, TopEarlgreyPlicIrqIdCsrngCsEntropyReq = 175, @@ -1099,6 +1099,7 @@ package top_earlgrey_pkg; // List of peripheral instantiated in this chip. typedef enum { + PeripheralAcc, PeripheralAdcCtrlAon, PeripheralAes, PeripheralAlertHandler, @@ -1118,7 +1119,6 @@ package top_earlgrey_pkg; PeripheralKeymgr, PeripheralKmac, PeripheralLcCtrl, - PeripheralOtbn, PeripheralOtpCtrl, PeripheralOtpMacro, PeripheralPattgen, diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index 50b60cf632c..8e7b7e5dab7 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -525,6 +525,20 @@ pub const RV_PLIC_BASE_ADDR: usize = 0x48000000; /// `RV_PLIC_BASE_ADDR + RV_PLIC_SIZE_BYTES`. pub const RV_PLIC_SIZE_BYTES: usize = 0x8000000; +/// Peripheral base address for acc in top earlgrey. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ACC_BASE_ADDR: usize = 0x41300000; + +/// Peripheral size for acc in top earlgrey. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ACC_BASE_ADDR and +/// `ACC_BASE_ADDR + ACC_SIZE_BYTES`. +pub const ACC_SIZE_BYTES: usize = 0x20000; + /// Peripheral base address for aes in top earlgrey. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped @@ -567,20 +581,6 @@ pub const KMAC_BASE_ADDR: usize = 0x41120000; /// `KMAC_BASE_ADDR + KMAC_SIZE_BYTES`. pub const KMAC_SIZE_BYTES: usize = 0x1000; -/// Peripheral base address for otbn in top earlgrey. -/// -/// This should be used with #mmio_region_from_addr to access the memory-mapped -/// registers associated with the peripheral (usually via a DIF). -pub const OTBN_BASE_ADDR: usize = 0x41300000; - -/// Peripheral size for otbn in top earlgrey. -/// -/// This is the size (in bytes) of the peripheral's reserved memory area. All -/// memory-mapped registers associated with this peripheral should have an -/// address between #OTBN_BASE_ADDR and -/// `OTBN_BASE_ADDR + OTBN_SIZE_BYTES`. -pub const OTBN_SIZE_BYTES: usize = 0x20000; - /// Peripheral base address for keymgr in top earlgrey. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped @@ -770,12 +770,12 @@ pub enum PlicPeripheral { SensorCtrlAon = 21, /// flash_ctrl FlashCtrl = 22, + /// acc + Acc = 23, /// hmac - Hmac = 23, + Hmac = 24, /// kmac - Kmac = 24, - /// otbn - Otbn = 25, + Kmac = 25, /// keymgr Keymgr = 26, /// csrng @@ -815,9 +815,9 @@ impl TryFrom for PlicPeripheral { 20 => Ok(Self::AonTimerAon), 21 => Ok(Self::SensorCtrlAon), 22 => Ok(Self::FlashCtrl), - 23 => Ok(Self::Hmac), - 24 => Ok(Self::Kmac), - 25 => Ok(Self::Otbn), + 23 => Ok(Self::Acc), + 24 => Ok(Self::Hmac), + 25 => Ok(Self::Kmac), 26 => Ok(Self::Keymgr), 27 => Ok(Self::Csrng), 28 => Ok(Self::EntropySrc), @@ -1167,20 +1167,20 @@ pub enum PlicIrqId { FlashCtrlOpDone = 164, /// flash_ctrl_corr_err FlashCtrlCorrErr = 165, + /// acc_done + AccDone = 166, /// hmac_hmac_done - HmacHmacDone = 166, + HmacHmacDone = 167, /// hmac_fifo_empty - HmacFifoEmpty = 167, + HmacFifoEmpty = 168, /// hmac_hmac_err - HmacHmacErr = 168, + HmacHmacErr = 169, /// kmac_kmac_done - KmacKmacDone = 169, + KmacKmacDone = 170, /// kmac_fifo_empty - KmacFifoEmpty = 170, + KmacFifoEmpty = 171, /// kmac_kmac_err - KmacKmacErr = 171, - /// otbn_done - OtbnDone = 172, + KmacKmacErr = 172, /// keymgr_op_done KeymgrOpDone = 173, /// csrng_cs_cmd_req_done @@ -1379,13 +1379,13 @@ impl TryFrom for PlicIrqId { 163 => Ok(Self::FlashCtrlRdLvl), 164 => Ok(Self::FlashCtrlOpDone), 165 => Ok(Self::FlashCtrlCorrErr), - 166 => Ok(Self::HmacHmacDone), - 167 => Ok(Self::HmacFifoEmpty), - 168 => Ok(Self::HmacHmacErr), - 169 => Ok(Self::KmacKmacDone), - 170 => Ok(Self::KmacFifoEmpty), - 171 => Ok(Self::KmacKmacErr), - 172 => Ok(Self::OtbnDone), + 166 => Ok(Self::AccDone), + 167 => Ok(Self::HmacHmacDone), + 168 => Ok(Self::HmacFifoEmpty), + 169 => Ok(Self::HmacHmacErr), + 170 => Ok(Self::KmacKmacDone), + 171 => Ok(Self::KmacFifoEmpty), + 172 => Ok(Self::KmacKmacErr), 173 => Ok(Self::KeymgrOpDone), 174 => Ok(Self::CsrngCsCmdReqDone), 175 => Ok(Self::CsrngCsEntropyReq), @@ -1752,6 +1752,8 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 186] = [ PlicPeripheral::FlashCtrl, // FlashCtrlCorrErr -> PlicPeripheral::FlashCtrl PlicPeripheral::FlashCtrl, + // AccDone -> PlicPeripheral::Acc + PlicPeripheral::Acc, // HmacHmacDone -> PlicPeripheral::Hmac PlicPeripheral::Hmac, // HmacFifoEmpty -> PlicPeripheral::Hmac @@ -1764,8 +1766,6 @@ pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 186] = [ PlicPeripheral::Kmac, // KmacKmacErr -> PlicPeripheral::Kmac PlicPeripheral::Kmac, - // OtbnDone -> PlicPeripheral::Otbn - PlicPeripheral::Otbn, // KeymgrOpDone -> PlicPeripheral::Keymgr PlicPeripheral::Keymgr, // CsrngCsCmdReqDone -> PlicPeripheral::Csrng @@ -1861,14 +1861,14 @@ pub enum AlertPeripheral { RvDm = 28, /// rv_plic RvPlic = 29, + /// acc + Acc = 30, /// aes - Aes = 30, + Aes = 31, /// hmac - Hmac = 31, + Hmac = 32, /// kmac - Kmac = 32, - /// otbn - Otbn = 33, + Kmac = 33, /// keymgr Keymgr = 34, /// csrng @@ -1978,20 +1978,20 @@ pub enum AlertId { RvDmFatalFault = 40, /// rv_plic_fatal_fault RvPlicFatalFault = 41, + /// acc_fatal + AccFatal = 42, + /// acc_recov + AccRecov = 43, /// aes_recov_ctrl_update_err - AesRecovCtrlUpdateErr = 42, + AesRecovCtrlUpdateErr = 44, /// aes_fatal_fault - AesFatalFault = 43, + AesFatalFault = 45, /// hmac_fatal_fault - HmacFatalFault = 44, + HmacFatalFault = 46, /// kmac_recov_operation_err - KmacRecovOperationErr = 45, + KmacRecovOperationErr = 47, /// kmac_fatal_fault_err - KmacFatalFaultErr = 46, - /// otbn_fatal - OtbnFatal = 47, - /// otbn_recov - OtbnRecov = 48, + KmacFatalFaultErr = 48, /// keymgr_recov_operation_err KeymgrRecovOperationErr = 49, /// keymgr_fatal_fault_err @@ -2072,13 +2072,13 @@ impl TryFrom for AlertId { 39 => Ok(Self::FlashCtrlRecovPrimFlashAlert), 40 => Ok(Self::RvDmFatalFault), 41 => Ok(Self::RvPlicFatalFault), - 42 => Ok(Self::AesRecovCtrlUpdateErr), - 43 => Ok(Self::AesFatalFault), - 44 => Ok(Self::HmacFatalFault), - 45 => Ok(Self::KmacRecovOperationErr), - 46 => Ok(Self::KmacFatalFaultErr), - 47 => Ok(Self::OtbnFatal), - 48 => Ok(Self::OtbnRecov), + 42 => Ok(Self::AccFatal), + 43 => Ok(Self::AccRecov), + 44 => Ok(Self::AesRecovCtrlUpdateErr), + 45 => Ok(Self::AesFatalFault), + 46 => Ok(Self::HmacFatalFault), + 47 => Ok(Self::KmacRecovOperationErr), + 48 => Ok(Self::KmacFatalFaultErr), 49 => Ok(Self::KeymgrRecovOperationErr), 50 => Ok(Self::KeymgrFatalFaultErr), 51 => Ok(Self::CsrngRecovAlert), @@ -2189,6 +2189,10 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 65] = [ AlertPeripheral::RvDm, // RvPlicFatalFault -> AlertPeripheral::RvPlic AlertPeripheral::RvPlic, + // AccFatal -> AlertPeripheral::Acc + AlertPeripheral::Acc, + // AccRecov -> AlertPeripheral::Acc + AlertPeripheral::Acc, // AesRecovCtrlUpdateErr -> AlertPeripheral::Aes AlertPeripheral::Aes, // AesFatalFault -> AlertPeripheral::Aes @@ -2199,10 +2203,6 @@ pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 65] = [ AlertPeripheral::Kmac, // KmacFatalFaultErr -> AlertPeripheral::Kmac AlertPeripheral::Kmac, - // OtbnFatal -> AlertPeripheral::Otbn - AlertPeripheral::Otbn, - // OtbnRecov -> AlertPeripheral::Otbn - AlertPeripheral::Otbn, // KeymgrRecovOperationErr -> AlertPeripheral::Keymgr AlertPeripheral::Keymgr, // KeymgrFatalFaultErr -> AlertPeripheral::Keymgr @@ -3211,14 +3211,14 @@ pub enum GateableClocks { #[derive(Copy, Clone, PartialEq, Eq)] #[repr(u32)] pub enum HintableClocks { + /// Clock clk_main_acc in group trans + MainAcc = 0, /// Clock clk_main_aes in group trans - MainAes = 0, + MainAes = 1, /// Clock clk_main_hmac in group trans - MainHmac = 1, + MainHmac = 2, /// Clock clk_main_kmac in group trans - MainKmac = 2, - /// Clock clk_main_otbn in group trans - MainOtbn = 3, + MainKmac = 3, } /// MMIO Region diff --git a/hw/top_earlgrey/sw/autogen/tests/BUILD b/hw/top_earlgrey/sw/autogen/tests/BUILD index 425a0e28c43..b9fe90b7c71 100644 --- a/hw/top_earlgrey/sw/autogen/tests/BUILD +++ b/hw/top_earlgrey/sw/autogen/tests/BUILD @@ -61,6 +61,7 @@ NR_IRQ_PERIPH_TESTS = 3 "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/arch:boot_stage", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif/autogen:acc", "//sw/device/lib/dif/autogen:adc_ctrl", "//sw/device/lib/dif/autogen:alert_handler", "//sw/device/lib/dif/autogen:aon_timer", @@ -73,7 +74,6 @@ NR_IRQ_PERIPH_TESTS = 3 "//sw/device/lib/dif/autogen:i2c", "//sw/device/lib/dif/autogen:keymgr", "//sw/device/lib/dif/autogen:kmac", - "//sw/device/lib/dif/autogen:otbn", "//sw/device/lib/dif/autogen:otp_ctrl", "//sw/device/lib/dif/autogen:pattgen", "//sw/device/lib/dif/autogen:pwrmgr", @@ -119,6 +119,7 @@ opentitan_test( "//sw/device/lib/arch:boot_stage", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif/autogen:acc", "//sw/device/lib/dif/autogen:adc_ctrl", "//sw/device/lib/dif/autogen:aes", "//sw/device/lib/dif/autogen:alert_handler", @@ -134,7 +135,6 @@ opentitan_test( "//sw/device/lib/dif/autogen:keymgr", "//sw/device/lib/dif/autogen:kmac", "//sw/device/lib/dif/autogen:lc_ctrl", - "//sw/device/lib/dif/autogen:otbn", "//sw/device/lib/dif/autogen:otp_ctrl", "//sw/device/lib/dif/autogen:pattgen", "//sw/device/lib/dif/autogen:pinmux", diff --git a/hw/top_earlgrey/sw/autogen/tests/alert_test.c b/hw/top_earlgrey/sw/autogen/tests/alert_test.c index f40b021a6b0..195b5b18c69 100644 --- a/hw/top_earlgrey/sw/autogen/tests/alert_test.c +++ b/hw/top_earlgrey/sw/autogen/tests/alert_test.c @@ -10,6 +10,7 @@ // -o hw/top_earlgrey/ #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/autogen/dif_acc_autogen.h" #include "sw/device/lib/dif/autogen/dif_adc_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_aes_autogen.h" #include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h" @@ -25,7 +26,6 @@ #include "sw/device/lib/dif/autogen/dif_keymgr_autogen.h" #include "sw/device/lib/dif/autogen/dif_kmac_autogen.h" #include "sw/device/lib/dif/autogen/dif_lc_ctrl_autogen.h" -#include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_pattgen_autogen.h" #include "sw/device/lib/dif/autogen/dif_pinmux_autogen.h" @@ -54,6 +54,7 @@ OTTF_DEFINE_TEST_CONFIG(); static dif_alert_handler_t alert_handler; +static dif_acc_t acc; static dif_adc_ctrl_t adc_ctrl_aon; static dif_aes_t aes; static dif_aon_timer_t aon_timer_aon; @@ -71,7 +72,6 @@ static dif_i2c_t i2c2; static dif_keymgr_t keymgr; static dif_kmac_t kmac; static dif_lc_ctrl_t lc_ctrl; -static dif_otbn_t otbn; static dif_otp_ctrl_t otp_ctrl; static dif_pattgen_t pattgen; static dif_pinmux_t pinmux_aon; @@ -103,6 +103,9 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR); CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR); + CHECK_DIF_OK(dif_acc_init(base_addr, &acc)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR); CHECK_DIF_OK(dif_adc_ctrl_init(base_addr, &adc_ctrl_aon)); @@ -154,9 +157,6 @@ static void init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR); CHECK_DIF_OK(dif_lc_ctrl_init(base_addr, &lc_ctrl)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR); - CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); @@ -281,6 +281,21 @@ static void trigger_alert_test(void) { bool is_cause; dif_alert_handler_alert_t exp_alert; + // Write acc's alert_test reg and check alert_cause. + for (dif_acc_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_acc_alert_force(&acc, kDifAccAlertFatal + i)); + + // Verify that alert handler received it. + exp_alert = kTopEarlgreyAlertIdAccFatal + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + // Write adc_ctrl's alert_test reg and check alert_cause. for (dif_adc_ctrl_alert_t i = 0; i < 1; ++i) { CHECK_DIF_OK(dif_adc_ctrl_alert_force(&adc_ctrl_aon, kDifAdcCtrlAlertFatalFault + i)); @@ -536,21 +551,6 @@ static void trigger_alert_test(void) { &alert_handler, exp_alert)); } - // Write otbn's alert_test reg and check alert_cause. - for (dif_otbn_alert_t i = 0; i < 2; ++i) { - CHECK_DIF_OK(dif_otbn_alert_force(&otbn, kDifOtbnAlertFatal + i)); - - // Verify that alert handler received it. - exp_alert = kTopEarlgreyAlertIdOtbnFatal + i; - CHECK_DIF_OK(dif_alert_handler_alert_is_cause( - &alert_handler, exp_alert, &is_cause)); - CHECK(is_cause, "Expect alert %d!", exp_alert); - - // Clear alert cause register - CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( - &alert_handler, exp_alert)); - } - // TODO(lowrisc/opentitan#20348): Enable otp_ctrl when this is fixed. if (kBootStage != kBootStageOwner) { // Write otp_ctrl's alert_test reg and check alert_cause. diff --git a/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c b/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c index 8e1d1dec341..ffc4b5eac56 100644 --- a/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c +++ b/hw/top_earlgrey/sw/autogen/tests/plic_all_irqs_test.c @@ -28,6 +28,7 @@ #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/csr.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/autogen/dif_acc_autogen.h" #include "sw/device/lib/dif/autogen/dif_adc_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h" #include "sw/device/lib/dif/autogen/dif_aon_timer_autogen.h" @@ -40,7 +41,6 @@ #include "sw/device/lib/dif/autogen/dif_i2c_autogen.h" #include "sw/device/lib/dif/autogen/dif_keymgr_autogen.h" #include "sw/device/lib/dif/autogen/dif_kmac_autogen.h" -#include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" #include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" #include "sw/device/lib/dif/autogen/dif_pattgen_autogen.h" #include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h" @@ -63,67 +63,67 @@ #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL -static dif_adc_ctrl_t adc_ctrl_aon; +static dif_acc_t acc; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL -static dif_alert_handler_t alert_handler; +static dif_adc_ctrl_t adc_ctrl_aon; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL -static dif_aon_timer_t aon_timer_aon; +static dif_alert_handler_t alert_handler; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL -static dif_csrng_t csrng; +static dif_aon_timer_t aon_timer_aon; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +static dif_csrng_t csrng; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static dif_edn_t edn0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static dif_edn_t edn1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL static dif_entropy_src_t entropy_src; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static dif_flash_ctrl_t flash_ctrl; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static dif_gpio_t gpio; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL static dif_hmac_t hmac; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static dif_i2c_t i2c0; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static dif_i2c_t i2c1; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL -static dif_i2c_t i2c2; -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL -static dif_keymgr_t keymgr; +static dif_i2c_t i2c2; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL -static dif_kmac_t kmac; +static dif_keymgr_t keymgr; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL -static dif_otbn_t otbn; +static dif_kmac_t kmac; #endif #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL @@ -202,70 +202,70 @@ static volatile top_earlgrey_plic_peripheral_t peripheral_expected; */ #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_acc_irq_t acc_irq_expected; +static volatile dif_acc_irq_t acc_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_adc_ctrl_irq_t adc_ctrl_irq_expected; static volatile dif_adc_ctrl_irq_t adc_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_alert_handler_irq_t alert_handler_irq_expected; static volatile dif_alert_handler_irq_t alert_handler_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_aon_timer_irq_t aon_timer_irq_expected; static volatile dif_aon_timer_irq_t aon_timer_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_csrng_irq_t csrng_irq_expected; static volatile dif_csrng_irq_t csrng_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_edn_irq_t edn_irq_expected; static volatile dif_edn_irq_t edn_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_entropy_src_irq_t entropy_src_irq_expected; static volatile dif_entropy_src_irq_t entropy_src_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_expected; static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_gpio_irq_t gpio_irq_expected; static volatile dif_gpio_irq_t gpio_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_hmac_irq_t hmac_irq_expected; static volatile dif_hmac_irq_t hmac_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_i2c_irq_t i2c_irq_expected; static volatile dif_i2c_irq_t i2c_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_keymgr_irq_t keymgr_irq_expected; static volatile dif_keymgr_irq_t keymgr_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_kmac_irq_t kmac_irq_expected; static volatile dif_kmac_irq_t kmac_irq_serviced; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL -static volatile dif_otbn_irq_t otbn_irq_expected; -static volatile dif_otbn_irq_t otbn_irq_serviced; -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_expected; static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_serviced; @@ -341,6 +341,29 @@ void ottf_external_isr(uint32_t *exc_info) { switch (peripheral) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + case kTopEarlgreyPlicPeripheralAcc: { + dif_acc_irq_t irq = + (dif_acc_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopEarlgreyPlicIrqIdAccDone); + CHECK(irq == acc_irq_expected, + "Incorrect acc IRQ triggered: exp = %d, obs = %d", + acc_irq_expected, irq); + acc_irq_serviced = irq; + + dif_acc_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_acc_irq_get_state(&acc, &snapshot)); + CHECK(snapshot == (dif_acc_irq_state_snapshot_t)(1 << irq), + "Only acc IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_acc_irq_acknowledge(&acc, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralAdcCtrlAon: { dif_adc_ctrl_irq_t irq = (dif_adc_ctrl_irq_t)(plic_irq_id - @@ -376,7 +399,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralAlertHandler: { dif_alert_handler_irq_t irq = (dif_alert_handler_irq_t)(plic_irq_id - @@ -399,7 +422,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralAonTimerAon: { dif_aon_timer_irq_t irq = (dif_aon_timer_irq_t)(plic_irq_id - @@ -422,7 +445,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralCsrng: { dif_csrng_irq_t irq = (dif_csrng_irq_t)(plic_irq_id - @@ -445,7 +468,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralEdn0: { dif_edn_irq_t irq = (dif_edn_irq_t)(plic_irq_id - @@ -468,7 +491,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralEdn1: { dif_edn_irq_t irq = (dif_edn_irq_t)(plic_irq_id - @@ -491,7 +514,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralEntropySrc: { dif_entropy_src_irq_t irq = (dif_entropy_src_irq_t)(plic_irq_id - @@ -514,7 +537,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralFlashCtrl: { dif_flash_ctrl_irq_t irq = (dif_flash_ctrl_irq_t)(plic_irq_id - @@ -550,7 +573,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralGpio: { dif_gpio_irq_t irq = (dif_gpio_irq_t)(plic_irq_id - @@ -573,7 +596,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralHmac: { dif_hmac_irq_t irq = (dif_hmac_irq_t)(plic_irq_id - @@ -609,7 +632,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralI2c0: { dif_i2c_irq_t irq = (dif_i2c_irq_t)(plic_irq_id - @@ -645,7 +668,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralI2c1: { dif_i2c_irq_t irq = (dif_i2c_irq_t)(plic_irq_id - @@ -681,7 +704,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralI2c2: { dif_i2c_irq_t irq = (dif_i2c_irq_t)(plic_irq_id - @@ -717,7 +740,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralKeymgr: { dif_keymgr_irq_t irq = (dif_keymgr_irq_t)(plic_irq_id - @@ -740,7 +763,7 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralKmac: { dif_kmac_irq_t irq = (dif_kmac_irq_t)(plic_irq_id - @@ -776,29 +799,6 @@ void ottf_external_isr(uint32_t *exc_info) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - case kTopEarlgreyPlicPeripheralOtbn: { - dif_otbn_irq_t irq = - (dif_otbn_irq_t)(plic_irq_id - - (dif_rv_plic_irq_id_t) - kTopEarlgreyPlicIrqIdOtbnDone); - CHECK(irq == otbn_irq_expected, - "Incorrect otbn IRQ triggered: exp = %d, obs = %d", - otbn_irq_expected, irq); - otbn_irq_serviced = irq; - - dif_otbn_irq_state_snapshot_t snapshot; - CHECK_DIF_OK(dif_otbn_irq_get_state(&otbn, &snapshot)); - CHECK(snapshot == (dif_otbn_irq_state_snapshot_t)(1 << irq), - "Only otbn IRQ %d expected to fire. Actual interrupt " - "status = %x", - irq, snapshot); - - CHECK_DIF_OK(dif_otbn_irq_acknowledge(&otbn, irq)); - break; - } -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL case kTopEarlgreyPlicPeripheralOtpCtrl: { dif_otp_ctrl_irq_t irq = @@ -1253,85 +1253,85 @@ static void peripherals_init(void) { mmio_region_t base_addr; #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR); + CHECK_DIF_OK(dif_acc_init(base_addr, &acc)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR); CHECK_DIF_OK(dif_adc_ctrl_init(base_addr, &adc_ctrl_aon)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR); CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR); CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR); CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR); CHECK_DIF_OK(dif_edn_init(base_addr, &edn0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR); CHECK_DIF_OK(dif_edn_init(base_addr, &edn1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR); CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR); CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR); CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C0_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C1_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_I2C2_BASE_ADDR); CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR); CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR); CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR); - CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL base_addr = mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR); CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); @@ -1411,67 +1411,67 @@ static void peripherals_init(void) { */ static void peripheral_irqs_clear(void) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge_all(&adc_ctrl_aon)); + CHECK_DIF_OK(dif_acc_irq_acknowledge_all(&acc)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler)); + CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge_all(&adc_ctrl_aon)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon)); + CHECK_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng)); + CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_entropy_src_irq_acknowledge_all(&entropy_src)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_flash_ctrl_irq_acknowledge_all(&flash_ctrl)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_hmac_irq_acknowledge_all(&hmac)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c0)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c1)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c2)); -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_keymgr_irq_acknowledge_all(&keymgr)); + CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c2)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac)); + CHECK_DIF_OK(dif_keymgr_irq_acknowledge_all(&keymgr)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn)); + CHECK_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL @@ -1538,31 +1538,36 @@ static void peripheral_irqs_clear(void) { */ static void peripheral_irqs_enable(void) { #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + dif_acc_irq_state_snapshot_t acc_irqs = + (dif_acc_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL dif_adc_ctrl_irq_state_snapshot_t adc_ctrl_irqs = (dif_adc_ctrl_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL dif_alert_handler_irq_state_snapshot_t alert_handler_irqs = (dif_alert_handler_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL dif_csrng_irq_state_snapshot_t csrng_irqs = (dif_csrng_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL dif_edn_irq_state_snapshot_t edn_irqs = (dif_edn_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL dif_entropy_src_irq_state_snapshot_t entropy_src_irqs = (dif_entropy_src_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL // Note: this peripheral contains status interrupts that are asserted by // default. Therefore, not all interrupts are enabled here, since that // would interfere with this test. Instead, these interrupts are enabled on @@ -1571,36 +1576,31 @@ static void peripheral_irqs_enable(void) { (dif_flash_ctrl_irq_state_snapshot_t)0xfffffffc; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL dif_gpio_irq_state_snapshot_t gpio_irqs = (dif_gpio_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL dif_hmac_irq_state_snapshot_t hmac_irqs = (dif_hmac_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL dif_i2c_irq_state_snapshot_t i2c_irqs = (dif_i2c_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL dif_keymgr_irq_state_snapshot_t keymgr_irqs = (dif_keymgr_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL dif_kmac_irq_state_snapshot_t kmac_irqs = (dif_kmac_irq_state_snapshot_t)0xffffffff; #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - dif_otbn_irq_state_snapshot_t otbn_irqs = - (dif_otbn_irq_state_snapshot_t)0xffffffff; -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL dif_otp_ctrl_irq_state_snapshot_t otp_ctrl_irqs = (dif_otp_ctrl_irq_state_snapshot_t)0xffffffff; @@ -1656,63 +1656,63 @@ static void peripheral_irqs_enable(void) { #endif #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_adc_ctrl_irq_restore_all(&adc_ctrl_aon, &adc_ctrl_irqs)); + CHECK_DIF_OK(dif_acc_irq_restore_all(&acc, &acc_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_adc_ctrl_irq_restore_all(&adc_ctrl_aon, &adc_ctrl_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_alert_handler_irq_restore_all(&alert_handler, &alert_handler_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_csrng_irq_restore_all(&csrng, &csrng_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_restore_all(&edn0, &edn_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_edn_irq_restore_all(&edn1, &edn_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_entropy_src_irq_restore_all(&entropy_src, &entropy_src_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_flash_ctrl_irq_restore_all(&flash_ctrl, &flash_ctrl_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_gpio_irq_restore_all(&gpio, &gpio_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_hmac_irq_restore_all(&hmac, &hmac_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c0, &i2c_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c1, &i2c_irqs)); #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c2, &i2c_irqs)); -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_keymgr_irq_restore_all(&keymgr, &keymgr_irqs)); + CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c2, &i2c_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_kmac_irq_restore_all(&kmac, &kmac_irqs)); + CHECK_DIF_OK(dif_keymgr_irq_restore_all(&keymgr, &keymgr_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - CHECK_DIF_OK(dif_otbn_irq_restore_all(&otbn, &otbn_irqs)); + CHECK_DIF_OK(dif_kmac_irq_restore_all(&kmac, &kmac_irqs)); #endif #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL @@ -1794,6 +1794,21 @@ static void peripheral_irqs_trigger(void) { (void)status_default_mask; #if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopEarlgreyPlicPeripheralAcc; + for (dif_acc_irq_t irq = kDifAccIrqDone; irq <= kDifAccIrqDone; + ++irq) { + acc_irq_expected = irq; + LOG_INFO("Triggering acc IRQ %d.", irq); + CHECK_DIF_OK(dif_acc_irq_force(&acc, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(acc_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from acc is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralAdcCtrlAon; status_default_mask = 0x0; for (dif_adc_ctrl_irq_t irq = kDifAdcCtrlIrqMatchPending; irq <= kDifAdcCtrlIrqMatchPending; @@ -1817,7 +1832,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralAlertHandler; for (dif_alert_handler_irq_t irq = kDifAlertHandlerIrqClassa; irq <= kDifAlertHandlerIrqClassd; ++irq) { @@ -1832,7 +1847,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference // from the logging facility. // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. @@ -1854,7 +1869,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralCsrng; for (dif_csrng_irq_t irq = kDifCsrngIrqCsCmdReqDone; irq <= kDifCsrngIrqCsFatalErr; ++irq) { @@ -1869,7 +1884,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralEdn0; for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; irq <= kDifEdnIrqEdnFatalErr; ++irq) { @@ -1884,7 +1899,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralEdn1; for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; irq <= kDifEdnIrqEdnFatalErr; ++irq) { @@ -1899,7 +1914,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralEntropySrc; for (dif_entropy_src_irq_t irq = kDifEntropySrcIrqEsEntropyValid; irq <= kDifEntropySrcIrqEsFatalErr; ++irq) { @@ -1914,7 +1929,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralFlashCtrl; status_default_mask = 0x3; for (dif_flash_ctrl_irq_t irq = kDifFlashCtrlIrqProgEmpty; irq <= kDifFlashCtrlIrqCorrErr; @@ -1938,7 +1953,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralGpio; for (dif_gpio_irq_t irq = kDifGpioIrqGpio0; irq <= kDifGpioIrqGpio31; ++irq) { @@ -1953,7 +1968,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralHmac; status_default_mask = 0x0; for (dif_hmac_irq_t irq = kDifHmacIrqHmacDone; irq <= kDifHmacIrqHmacErr; @@ -1977,7 +1992,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralI2c0; status_default_mask = 0x0; for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; @@ -2001,7 +2016,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralI2c1; status_default_mask = 0x0; for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; @@ -2025,7 +2040,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralI2c2; status_default_mask = 0x0; for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; @@ -2049,7 +2064,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralKeymgr; for (dif_keymgr_irq_t irq = kDifKeymgrIrqOpDone; irq <= kDifKeymgrIrqOpDone; ++irq) { @@ -2064,7 +2079,7 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL peripheral_expected = kTopEarlgreyPlicPeripheralKmac; status_default_mask = 0x0; for (dif_kmac_irq_t irq = kDifKmacIrqKmacDone; irq <= kDifKmacIrqKmacErr; @@ -2088,21 +2103,6 @@ static void peripheral_irqs_trigger(void) { } #endif -#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL - peripheral_expected = kTopEarlgreyPlicPeripheralOtbn; - for (dif_otbn_irq_t irq = kDifOtbnIrqDone; irq <= kDifOtbnIrqDone; - ++irq) { - otbn_irq_expected = irq; - LOG_INFO("Triggering otbn IRQ %d.", irq); - CHECK_DIF_OK(dif_otbn_irq_force(&otbn, irq, true)); - - // This avoids a race where *irq_serviced is read before - // entering the ISR. - IBEX_SPIN_FOR(otbn_irq_serviced == irq, 1); - LOG_INFO("IRQ %d from otbn is serviced.", irq); - } -#endif - #if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL // Skip OTP_CTRL in boot stage owner since ROM_EXT configures all accesses // to OTP_CTRL and AST to be illegal. diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index ab30fd000b2..5c170e13b4b 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c @@ -59,13 +59,13 @@ const top_earlgrey_alert_peripheral_t [kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert] = kTopEarlgreyAlertPeripheralFlashCtrl, [kTopEarlgreyAlertIdRvDmFatalFault] = kTopEarlgreyAlertPeripheralRvDm, [kTopEarlgreyAlertIdRvPlicFatalFault] = kTopEarlgreyAlertPeripheralRvPlic, + [kTopEarlgreyAlertIdAccFatal] = kTopEarlgreyAlertPeripheralAcc, + [kTopEarlgreyAlertIdAccRecov] = kTopEarlgreyAlertPeripheralAcc, [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes, [kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes, [kTopEarlgreyAlertIdHmacFatalFault] = kTopEarlgreyAlertPeripheralHmac, [kTopEarlgreyAlertIdKmacRecovOperationErr] = kTopEarlgreyAlertPeripheralKmac, [kTopEarlgreyAlertIdKmacFatalFaultErr] = kTopEarlgreyAlertPeripheralKmac, - [kTopEarlgreyAlertIdOtbnFatal] = kTopEarlgreyAlertPeripheralOtbn, - [kTopEarlgreyAlertIdOtbnRecov] = kTopEarlgreyAlertPeripheralOtbn, [kTopEarlgreyAlertIdKeymgrRecovOperationErr] = kTopEarlgreyAlertPeripheralKeymgr, [kTopEarlgreyAlertIdKeymgrFatalFaultErr] = kTopEarlgreyAlertPeripheralKeymgr, [kTopEarlgreyAlertIdCsrngRecovAlert] = kTopEarlgreyAlertPeripheralCsrng, @@ -258,13 +258,13 @@ const top_earlgrey_plic_peripheral_t [kTopEarlgreyPlicIrqIdFlashCtrlRdLvl] = kTopEarlgreyPlicPeripheralFlashCtrl, [kTopEarlgreyPlicIrqIdFlashCtrlOpDone] = kTopEarlgreyPlicPeripheralFlashCtrl, [kTopEarlgreyPlicIrqIdFlashCtrlCorrErr] = kTopEarlgreyPlicPeripheralFlashCtrl, + [kTopEarlgreyPlicIrqIdAccDone] = kTopEarlgreyPlicPeripheralAcc, [kTopEarlgreyPlicIrqIdHmacHmacDone] = kTopEarlgreyPlicPeripheralHmac, [kTopEarlgreyPlicIrqIdHmacFifoEmpty] = kTopEarlgreyPlicPeripheralHmac, [kTopEarlgreyPlicIrqIdHmacHmacErr] = kTopEarlgreyPlicPeripheralHmac, [kTopEarlgreyPlicIrqIdKmacKmacDone] = kTopEarlgreyPlicPeripheralKmac, [kTopEarlgreyPlicIrqIdKmacFifoEmpty] = kTopEarlgreyPlicPeripheralKmac, [kTopEarlgreyPlicIrqIdKmacKmacErr] = kTopEarlgreyPlicPeripheralKmac, - [kTopEarlgreyPlicIrqIdOtbnDone] = kTopEarlgreyPlicPeripheralOtbn, [kTopEarlgreyPlicIrqIdKeymgrOpDone] = kTopEarlgreyPlicPeripheralKeymgr, [kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone] = kTopEarlgreyPlicPeripheralCsrng, [kTopEarlgreyPlicIrqIdCsrngCsEntropyReq] = kTopEarlgreyPlicPeripheralCsrng, diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 2f50f49def1..05ceb4ac71f 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -678,6 +678,24 @@ extern "C" { */ #define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000u +/** + * Peripheral base address for acc in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_ACC_BASE_ADDR 0x41300000u + +/** + * Peripheral size for acc in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_ACC_BASE_ADDR and + * `TOP_EARLGREY_ACC_BASE_ADDR + TOP_EARLGREY_ACC_SIZE_BYTES`. + */ +#define TOP_EARLGREY_ACC_SIZE_BYTES 0x20000u + /** * Peripheral base address for aes in top earlgrey. * @@ -732,24 +750,6 @@ extern "C" { */ #define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000u -/** - * Peripheral base address for otbn in top earlgrey. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_EARLGREY_OTBN_BASE_ADDR 0x41300000u - -/** - * Peripheral size for otbn in top earlgrey. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_OTBN_BASE_ADDR and - * `TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES`. - */ -#define TOP_EARLGREY_OTBN_SIZE_BYTES 0x20000u - /** * Peripheral base address for keymgr in top earlgrey. * @@ -966,9 +966,9 @@ typedef enum top_earlgrey_plic_peripheral { kTopEarlgreyPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */ kTopEarlgreyPlicPeripheralSensorCtrlAon = 21, /**< sensor_ctrl_aon */ kTopEarlgreyPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */ - kTopEarlgreyPlicPeripheralHmac = 23, /**< hmac */ - kTopEarlgreyPlicPeripheralKmac = 24, /**< kmac */ - kTopEarlgreyPlicPeripheralOtbn = 25, /**< otbn */ + kTopEarlgreyPlicPeripheralAcc = 23, /**< acc */ + kTopEarlgreyPlicPeripheralHmac = 24, /**< hmac */ + kTopEarlgreyPlicPeripheralKmac = 25, /**< kmac */ kTopEarlgreyPlicPeripheralKeymgr = 26, /**< keymgr */ kTopEarlgreyPlicPeripheralCsrng = 27, /**< csrng */ kTopEarlgreyPlicPeripheralEntropySrc = 28, /**< entropy_src */ @@ -1150,13 +1150,13 @@ typedef enum top_earlgrey_plic_irq_id { kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 163, /**< flash_ctrl_rd_lvl */ kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 164, /**< flash_ctrl_op_done */ kTopEarlgreyPlicIrqIdFlashCtrlCorrErr = 165, /**< flash_ctrl_corr_err */ - kTopEarlgreyPlicIrqIdHmacHmacDone = 166, /**< hmac_hmac_done */ - kTopEarlgreyPlicIrqIdHmacFifoEmpty = 167, /**< hmac_fifo_empty */ - kTopEarlgreyPlicIrqIdHmacHmacErr = 168, /**< hmac_hmac_err */ - kTopEarlgreyPlicIrqIdKmacKmacDone = 169, /**< kmac_kmac_done */ - kTopEarlgreyPlicIrqIdKmacFifoEmpty = 170, /**< kmac_fifo_empty */ - kTopEarlgreyPlicIrqIdKmacKmacErr = 171, /**< kmac_kmac_err */ - kTopEarlgreyPlicIrqIdOtbnDone = 172, /**< otbn_done */ + kTopEarlgreyPlicIrqIdAccDone = 166, /**< acc_done */ + kTopEarlgreyPlicIrqIdHmacHmacDone = 167, /**< hmac_hmac_done */ + kTopEarlgreyPlicIrqIdHmacFifoEmpty = 168, /**< hmac_fifo_empty */ + kTopEarlgreyPlicIrqIdHmacHmacErr = 169, /**< hmac_hmac_err */ + kTopEarlgreyPlicIrqIdKmacKmacDone = 170, /**< kmac_kmac_done */ + kTopEarlgreyPlicIrqIdKmacFifoEmpty = 171, /**< kmac_fifo_empty */ + kTopEarlgreyPlicIrqIdKmacKmacErr = 172, /**< kmac_kmac_err */ kTopEarlgreyPlicIrqIdKeymgrOpDone = 173, /**< keymgr_op_done */ kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 174, /**< csrng_cs_cmd_req_done */ kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 175, /**< csrng_cs_entropy_req */ @@ -1231,10 +1231,10 @@ typedef enum top_earlgrey_alert_peripheral { kTopEarlgreyAlertPeripheralFlashCtrl = 27, /**< flash_ctrl */ kTopEarlgreyAlertPeripheralRvDm = 28, /**< rv_dm */ kTopEarlgreyAlertPeripheralRvPlic = 29, /**< rv_plic */ - kTopEarlgreyAlertPeripheralAes = 30, /**< aes */ - kTopEarlgreyAlertPeripheralHmac = 31, /**< hmac */ - kTopEarlgreyAlertPeripheralKmac = 32, /**< kmac */ - kTopEarlgreyAlertPeripheralOtbn = 33, /**< otbn */ + kTopEarlgreyAlertPeripheralAcc = 30, /**< acc */ + kTopEarlgreyAlertPeripheralAes = 31, /**< aes */ + kTopEarlgreyAlertPeripheralHmac = 32, /**< hmac */ + kTopEarlgreyAlertPeripheralKmac = 33, /**< kmac */ kTopEarlgreyAlertPeripheralKeymgr = 34, /**< keymgr */ kTopEarlgreyAlertPeripheralCsrng = 35, /**< csrng */ kTopEarlgreyAlertPeripheralEntropySrc = 36, /**< entropy_src */ @@ -1295,13 +1295,13 @@ typedef enum top_earlgrey_alert_id { kTopEarlgreyAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */ kTopEarlgreyAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */ kTopEarlgreyAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */ - kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */ - kTopEarlgreyAlertIdAesFatalFault = 43, /**< aes_fatal_fault */ - kTopEarlgreyAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */ - kTopEarlgreyAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */ - kTopEarlgreyAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */ - kTopEarlgreyAlertIdOtbnFatal = 47, /**< otbn_fatal */ - kTopEarlgreyAlertIdOtbnRecov = 48, /**< otbn_recov */ + kTopEarlgreyAlertIdAccFatal = 42, /**< acc_fatal */ + kTopEarlgreyAlertIdAccRecov = 43, /**< acc_recov */ + kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 44, /**< aes_recov_ctrl_update_err */ + kTopEarlgreyAlertIdAesFatalFault = 45, /**< aes_fatal_fault */ + kTopEarlgreyAlertIdHmacFatalFault = 46, /**< hmac_fatal_fault */ + kTopEarlgreyAlertIdKmacRecovOperationErr = 47, /**< kmac_recov_operation_err */ + kTopEarlgreyAlertIdKmacFatalFaultErr = 48, /**< kmac_fatal_fault_err */ kTopEarlgreyAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */ kTopEarlgreyAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */ kTopEarlgreyAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */ @@ -1732,10 +1732,10 @@ typedef enum top_earlgrey_gateable_clocks { * but the clock manager is in control of whether the clock actually is stopped. */ typedef enum top_earlgrey_hintable_clocks { - kTopEarlgreyHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */ - kTopEarlgreyHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */ - kTopEarlgreyHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */ - kTopEarlgreyHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */ + kTopEarlgreyHintableClocksMainAcc = 0, /**< Clock clk_main_acc in group trans */ + kTopEarlgreyHintableClocksMainAes = 1, /**< Clock clk_main_aes in group trans */ + kTopEarlgreyHintableClocksMainHmac = 2, /**< Clock clk_main_hmac in group trans */ + kTopEarlgreyHintableClocksMainKmac = 3, /**< Clock clk_main_kmac in group trans */ kTopEarlgreyHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */ } top_earlgrey_hintable_clocks_t; diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index ba34aff1b9e..eefe7d0d3f2 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h @@ -678,6 +678,23 @@ * `TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES`. */ #define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000 +/** + * Peripheral base address for acc in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_ACC_BASE_ADDR 0x41300000 + +/** + * Peripheral size for acc in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_ACC_BASE_ADDR and + * `TOP_EARLGREY_ACC_BASE_ADDR + TOP_EARLGREY_ACC_SIZE_BYTES`. + */ +#define TOP_EARLGREY_ACC_SIZE_BYTES 0x20000 /** * Peripheral base address for aes in top earlgrey. * @@ -729,23 +746,6 @@ * `TOP_EARLGREY_KMAC_BASE_ADDR + TOP_EARLGREY_KMAC_SIZE_BYTES`. */ #define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000 -/** - * Peripheral base address for otbn in top earlgrey. - * - * This should be used with #mmio_region_from_addr to access the memory-mapped - * registers associated with the peripheral (usually via a DIF). - */ -#define TOP_EARLGREY_OTBN_BASE_ADDR 0x41300000 - -/** - * Peripheral size for otbn in top earlgrey. - * - * This is the size (in bytes) of the peripheral's reserved memory area. All - * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_OTBN_BASE_ADDR and - * `TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES`. - */ -#define TOP_EARLGREY_OTBN_SIZE_BYTES 0x20000 /** * Peripheral base address for keymgr in top earlgrey. * diff --git a/hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson b/hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson index 1e180dcfe42..6562bca1dde 100644 --- a/hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson +++ b/hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson @@ -17,7 +17,7 @@ "{proj_root}/hw/ip/keymgr/syn/keymgr_syn_cfg.hjson", "{proj_root}/hw/ip/kmac/syn/kmac_syn_cfg.hjson", "{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_syn_cfg.hjson", - "{proj_root}/hw/ip/otbn/syn/otbn_syn_cfg.hjson", + "{proj_root}/hw/ip/acc/syn/acc_syn_cfg.hjson", "{proj_root}/hw/top_earlgrey/ip_autogen/rv_core_ibex/syn/rv_core_ibex_syn_cfg.hjson", "{proj_root}/hw/top_earlgrey/ip_autogen/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson", // Top-level synthesis flows. diff --git a/hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson b/hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson index fd7eddef7e0..c60b0f32698 100644 --- a/hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson +++ b/hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson @@ -18,7 +18,7 @@ "{proj_root}/hw/ip/keymgr/syn/keymgr_gtech_syn_cfg.hjson", "{proj_root}/hw/ip/kmac/syn/kmac_gtech_syn_cfg.hjson", "{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_gtech_syn_cfg.hjson", - "{proj_root}/hw/ip/otbn/syn/otbn_gtech_syn_cfg.hjson", + "{proj_root}/hw/ip/acc/syn/acc_gtech_syn_cfg.hjson", "{proj_root}/hw/top_earlgrey/ip_autogen/rv_core_ibex/syn/rv_core_ibex_gtech_syn_cfg.hjson", "{proj_root}/hw/top_earlgrey/ip_autogen/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson", // Top-level GTECH synthesis flows. diff --git a/hw/top_earlgrey/templates/chiplevel.sv.tpl b/hw/top_earlgrey/templates/chiplevel.sv.tpl index 736b5508f1b..c68a22f23e9 100644 --- a/hw/top_earlgrey/templates/chiplevel.sv.tpl +++ b/hw/top_earlgrey/templates/chiplevel.sv.tpl @@ -1146,9 +1146,9 @@ module chip_${top["name"]}_${target["name"]} #( .SecAesStartTriggerDelay(0), .SecAesAllowForcingMasks(1'b1), .CsrngSBoxImpl(aes_pkg::SBoxImplLut), - .OtbnRegFile(otbn_pkg::RegFileFPGA), - .SecOtbnMuteUrnd(1'b0), - .SecOtbnSkipUrndReseedAtStart(1'b0), + .AccRegFile(acc_pkg::RegFileFPGA), + .SecAccMuteUrnd(1'b0), + .SecAccSkipUrndReseedAtStart(1'b0), .OtpMacroMemInitFile(OtpMacroMemInitFile), .RvCoreIbexPipeLine(1), .SramCtrlRetAonInstrExec(0), @@ -1173,8 +1173,8 @@ module chip_${top["name"]}_${target["name"]} #( .SramCtrlRetAonInstrExec(0), .EntropySrcStub(1'b1), .CsrngSBoxImpl(aes_pkg::SBoxImplLut), - .OtbnRegFile(otbn_pkg::RegFileFPGA), - .OtbnStub(1'b1), + .AccRegFile(acc_pkg::RegFileFPGA), + .AccStub(1'b1), .OtpMacroMemInitFile(OtpMacroMemInitFile), .RvCoreIbexPipeLine(1), % endif @@ -1305,7 +1305,7 @@ module chip_${top["name"]}_${target["name"]} #( // AES - 00 - 0 // HMAC - 01 - 1 - not implemented on CW305 // KMAC - 10 - 2 - not implemented on CW305 - // OTBN - 11 - 3 - not implemented on CW305 + // ACC - 11 - 3 - not implemented on CW305 // // GPIO9 is used for gating the selected capture trigger in software. Alternatively, GPIO8 // can be used to implement a less precise but fully software-controlled capture trigger @@ -1324,7 +1324,7 @@ module chip_${top["name"]}_${target["name"]} #( 2'b00: trigger_sel = clkmgr_pkg::HintMainAes; 2'b01: trigger_sel = clkmgr_pkg::HintMainHmac; 2'b10: trigger_sel = clkmgr_pkg::HintMainKmac; - 2'b11: trigger_sel = clkmgr_pkg::HintMainOtbn; + 2'b11: trigger_sel = clkmgr_pkg::HintMainAcc; default: trigger_sel = clkmgr_pkg::HintMainAes; endcase; end diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index 22c3d768efa..fd32c808986 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -27,7 +27,7 @@ filesets: - lowrisc:ip:edn - lowrisc:ip:hmac - lowrisc:ip:kmac - - lowrisc:ip:otbn + - lowrisc:ip:acc - lowrisc:prim:ram_1p_scr - lowrisc:prim:flash - lowrisc:ip:sram_ctrl diff --git a/hw/top_englishbreakfast/dv/verilator/verilator_sim_cfg.hjson b/hw/top_englishbreakfast/dv/verilator/verilator_sim_cfg.hjson index 710bc7cf44b..2e72587b4d1 100644 --- a/hw/top_englishbreakfast/dv/verilator/verilator_sim_cfg.hjson +++ b/hw/top_englishbreakfast/dv/verilator/verilator_sim_cfg.hjson @@ -56,7 +56,7 @@ // needed as a run time switch to Verilator. '''{eval_cmd} \ opts=; \ - types=(rom flash otbn otp); \ + types=(rom flash acc otp); \ exts=(scr.39.vmem elf elf vmem); \ images=`echo {sw_images}`; \ for image in $images; do \ @@ -80,7 +80,7 @@ // to know what type of image is it: // - 0 for Boot ROM, // - 1 for SW test (loaded in flash), - // - 2 for OTBN test, + // - 2 for ACC test, // - 3 for OTP. // This allows an arbitrary number of SW images to be supplied to the TB. // @@ -135,8 +135,8 @@ sw_images: ["//sw/device/tests:crt_test:1"] } { - name: otbn_smoketest_rtl - sw_images: ["//sw/device/tests:otbn_smoketest:1"] + name: acc_smoketest_rtl + sw_images: ["//sw/device/tests:acc_smoketest:1"] } { name: otp_ctrl_smoketest diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/doc/theory_of_operation.md b/hw/top_englishbreakfast/ip_autogen/clkmgr/doc/theory_of_operation.md index 61f684d57d4..7dee2124e07 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/doc/theory_of_operation.md +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/doc/theory_of_operation.md @@ -19,7 +19,7 @@ The table shows the group name, the modules that belong to each group, and wheth | Group | Frequencies | Modules | Software | Wait for Interrupt | | ------------- | ------------------------------ | -------------------------------------------------------------- | -------------- | ------------------ | | Power-up | 100~200KHz, 24MHz | Clock Manager, Power Manager, Reset Manager, Pinmux | No | No | -| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Otbn | Yes (1) | Yes (2) | +| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Acc | Yes (1) | Yes (2) | | Infrastructural | 24MHz, ~100MHz | Fabric, Fabric gaskets (iopmp), Memories | No | Yes (3) | | Security | 24MHz, ~100MHz | Alert handler, Entropy, Life cycle, Plic, Sensors | No | No | | Peripheral | 24MHz, 48MHz, 96MHz | I2c, Spi, Uart, Usb, others | Yes | Yes | @@ -170,7 +170,7 @@ Note, the power manager's request to turn off clocks supersedes all other local This means even if a particular clock is turned on by the clock manager (for example a transactional unit that is ongoing or a peripheral that is enabled), the power manager requests will still turn clocks on / off at the root. This makes it software's responsibility to ensure low power entry requests (which can only be initiated by software) do not conflict with any ongoing activities controlled by software. -For example, software should ensure that Aes / Otbn activities have completed before initializing a low power entry process. +For example, software should ensure that Aes / Acc activities have completed before initializing a low power entry process. ### Clock Division diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/README.md b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/README.md index 7018a0c5c2e..033754641fc 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/README.md +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/README.md @@ -57,7 +57,7 @@ All common types and methods defined at the package level can be found in PeriIo, PeriUsb } peri_e; - typedef enum int {TransAes, TransHmac, TransKmac, TransOtbn} trans_e; + typedef enum int {TransAes, TransHmac, TransKmac, TransAcc} trans_e; ``` ### TL_agent diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el index ca5f99828dd..326e1d3c68c 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el @@ -24,7 +24,7 @@ INSTANCE: tb.dut.u_clk_main_kmac_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "2301929872 1660332954" -INSTANCE: tb.dut.u_clk_main_otbn_trans.u_idle_cnt +INSTANCE: tb.dut.u_clk_main_acc_trans.u_idle_cnt ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." Toggle step_i "net step_i[3:0]" CHECKSUM: "953655365 3155586170" diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el index 85e292d7a9f..761e9fac2e7 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el @@ -25,7 +25,7 @@ INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3274445021" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") CHECKSUM: "2972535896 3554514034" @@ -47,7 +47,7 @@ Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" CHECKSUM: "2972535896 3554514034" -INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_acc_val ANNOTATION: "VC_COV_UNR" Branch 0 "3759852512" "wr_en" (1) "wr_en 0" ANNOTATION: "VC_COV_UNR" diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv index 6807809aec3..520c511f26c 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv @@ -68,10 +68,10 @@ class clkmgr_smoke_vseq extends clkmgr_base_vseq; uvm_reg_field value_bit; } trans_descriptor_t; trans_descriptor_t trans_descriptors[NUM_TRANS] = '{ + '{TransAcc, ral.clk_hints.clk_main_acc_hint, ral.clk_hints_status.clk_main_acc_val}, '{TransAes, ral.clk_hints.clk_main_aes_hint, ral.clk_hints_status.clk_main_aes_val}, '{TransHmac, ral.clk_hints.clk_main_hmac_hint, ral.clk_hints_status.clk_main_hmac_val}, - '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val}, - '{TransOtbn, ral.clk_hints.clk_main_otbn_hint, ral.clk_hints_status.clk_main_otbn_val} + '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val} }; idle = 0; // Changes in idle take at least 10 cycles to stick. diff --git a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/tb.sv b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/tb.sv index 9130eb33857..1fa1d966e37 100644 --- a/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/tb.sv +++ b/hw/top_englishbreakfast/ip_autogen/clkmgr/dv/tb.sv @@ -113,7 +113,7 @@ module tb; reg2hw.clk_enables.clk_io_div2_peri_en.q, reg2hw.clk_enables.clk_io_div4_peri_en.q}), .clk_hints({ - reg2hw.clk_hints.clk_main_otbn_hint.q, + reg2hw.clk_hints.clk_main_acc_hint.q, reg2hw.clk_hints.clk_main_kmac_hint.q, reg2hw.clk_hints.clk_main_hmac_hint.q, reg2hw.clk_hints.clk_main_aes_hint.q}) diff --git a/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv b/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv index 991e68e2961..6f1c52e325f 100644 --- a/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv +++ b/hw/top_englishbreakfast/rtl/autogen/chip_englishbreakfast_cw305.sv @@ -1054,7 +1054,7 @@ module chip_englishbreakfast_cw305 #( // AES - 00 - 0 // HMAC - 01 - 1 - not implemented on CW305 // KMAC - 10 - 2 - not implemented on CW305 - // OTBN - 11 - 3 - not implemented on CW305 + // ACC - 11 - 3 - not implemented on CW305 // // GPIO9 is used for gating the selected capture trigger in software. Alternatively, GPIO8 // can be used to implement a less precise but fully software-controlled capture trigger diff --git a/quality/licenses.hjson b/quality/licenses.hjson index fa9158de3c7..6d752c5bd5a 100644 --- a/quality/licenses.hjson +++ b/quality/licenses.hjson @@ -75,7 +75,7 @@ Copyright lowRISC contributors (OpenTitan project). Copyright zeroRISC Inc. Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of - "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" + "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" (https://eprint.iacr.org/2025/2028). Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -92,7 +92,7 @@ Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of - "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" + "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" (https://eprint.iacr.org/2025/2028). Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -118,7 +118,7 @@ ''' Copyright zeroRISC Inc. Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of - "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" + "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" (https://eprint.iacr.org/2025/2028). Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -134,7 +134,7 @@ Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of - "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" + "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" (https://eprint.iacr.org/2025/2028). Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. Licensed under the Apache License, Version 2.0, see LICENSE for details. @@ -192,21 +192,21 @@ // Other Licences, "util/wavegen/LICENSE.wavedrom", - "sw/otbn/crypto/LICENSE.tiny_sha3", + "sw/acc/crypto/LICENSE.tiny_sha3", // Site Assets "site/**/assets/scss/**", "site/landing/static/js/tiny-slider.js", // MdBook assets (MPL licensed) "site/book-theme/*", // Code taken from Chromium, so covered by the BSD licence - "sw/otbn/crypto/modexp.s", - "sw/otbn/crypto/montmul.s", - "sw/otbn/crypto/p256.s", - "sw/otbn/crypto/rsa_verify.s", - "sw/otbn/crypto/handwritten/rsa_verify_3072.s", - "sw/otbn/crypto/sha512.s", + "sw/acc/crypto/modexp.s", + "sw/acc/crypto/montmul.s", + "sw/acc/crypto/p256.s", + "sw/acc/crypto/rsa_verify.s", + "sw/acc/crypto/handwritten/rsa_verify_3072.s", + "sw/acc/crypto/sha512.s", // Code based on tiny_sha3 - "sw/otbn/crypto/sha3_shake.s", + "sw/acc/crypto/sha3_shake.s", // Mersenne Twister PRNG "sw/device/sca/lib/prng.c", // SPHINCS+ known-answer test data @@ -216,6 +216,10 @@ "hw/ip/aes/pre_sca/alma/cpp/verilator_tb_aes_sbox.cpp", "hw/ip/aes/pre_sca/alma/cpp/verilator_tb_aes_sub_bytes.cpp", "hw/ip/kmac/pre_sca/alma/cpp/verilator_tb_keccak_2share.cpp", + // Existing __init__ from ACC + "hw/ip/acc/dv/rig/rig/__init__.py", + "hw/ip/acc/dv/rig/rig/gens/__init__.py", + "hw/ip/acc/util/docs/__init__.py", // Code contributed by mlkem-native authors "sw/device/lib/crypto/impl/mlkem.c", "sw/device/lib/crypto/include/mlkem.h", diff --git a/rules/otbn.bzl b/rules/acc.bzl similarity index 83% rename from rules/otbn.bzl rename to rules/acc.bzl index 5926e90751c..8c433443f4c 100644 --- a/rules/otbn.bzl +++ b/rules/acc.bzl @@ -8,9 +8,9 @@ load("//rules:rv.bzl", "rv_rule") load("@rules_cc//cc:find_cc_toolchain.bzl", "find_cc_toolchain") -def _otbn_assemble_sources(ctx, additional_srcs = []): +def _acc_assemble_sources(ctx, additional_srcs = []): """Helper function that, in the provided context, adds an action to the - context that invokes the otbn assember (otbn_as.py), producing a + context that invokes the acc assember (acc_as.py), producing a corresponding object file by assembling the provided src files. Returns an object file that will be generated by these actions. """ @@ -34,7 +34,7 @@ def _otbn_assemble_sources(ctx, additional_srcs = []): ctx.actions.run( outputs = [obj], inputs = depset( - direct = files + [ctx.executable._otbn_as], + direct = files + [ctx.executable._acc_as], transitive = [cc_toolchain.all_files], ), env = { @@ -42,14 +42,14 @@ def _otbn_assemble_sources(ctx, additional_srcs = []): "RV32_TOOL_GCC": ctx.executable._riscv32_gcc.path, }, arguments = copts + ["-o", obj.path] + paths + ctx.attr.args, - executable = ctx.executable._otbn_as, + executable = ctx.executable._acc_as, ) return obj -def _otbn_library(ctx): - """Produces an object file used as a dependency for otbn binaries.""" - obj = _otbn_assemble_sources(ctx) +def _acc_library(ctx): + """Produces an object file used as a dependency for acc binaries.""" + obj = _acc_assemble_sources(ctx) return [ DefaultInfo( @@ -58,28 +58,28 @@ def _otbn_library(ctx): ), ] -def _otbn_binary(ctx, additional_srcs = []): - """The build process for otbn resources currently invokes - `//hw/ip/otbn/util/otbn_{as,ld,...}.py` to build the otbn resource. - These programs are python scripts which translate otbn special +def _acc_binary(ctx, additional_srcs = []): + """The build process for acc resources currently invokes + `//hw/ip/acc/util/acc_{as,ld,...}.py` to build the acc resource. + These programs are python scripts which translate acc special instructions into the proper opcode sequences and _then_ invoke the normal `rv32-{as,ld,...}` programs to produce the resource. These "native" - otbn resources are the `otbn_objs` and `elf` output groups. + acc resources are the `acc_objs` and `elf` output groups. - In order to make the otbn resource useful to the main CPU, the - otbn resource needs to be included as a blob of data that the main - CPU can dump into the otbn `imem` area and ask otbn to execute it. - `util/otbn-build.py` does this with some objcopy-fu, emitting + In order to make the acc resource useful to the main CPU, the + acc resource needs to be included as a blob of data that the main + CPU can dump into the acc `imem` area and ask acc to execute it. + `util/acc-build.py` does this with some objcopy-fu, emitting `foo.rv32embed.o`. Bazel's `cc_*` rules really want dependency objects expressed as archives rather than raw object files, so I've modified - `otbn-build` to also emit an archive file. + `acc-build` to also emit an archive file. - _Morally_, the otbn resource is a data dependency. However the + _Morally_, the acc resource is a data dependency. However the practical meaning of a `data` dependency in bazel is a file made - available at runtime, which is not how we're using the otbn resource. + available at runtime, which is not how we're using the acc resource. The closest analog is something like `cc_embed_data`, which is like a data dependency that needs to be linked into the main program. - We achieve by having `otbn_build.py` emit a conventional RV32I library + We achieve by having `acc_build.py` emit a conventional RV32I library that other rules can depend on in their `deps`. """ binary = getattr(ctx.attr, "binary", None) @@ -93,8 +93,8 @@ def _otbn_binary(ctx, additional_srcs = []): cc_toolchain = find_cc_toolchain(ctx) - # Run the otbn assembler on source files to produce an object (.o) file. - obj = _otbn_assemble_sources(ctx, additional_srcs) + # Run the acc assembler on source files to produce an object (.o) file. + obj = _acc_assemble_sources(ctx, additional_srcs) # Declare output files. elf = ctx.actions.declare_file(ctx.attr.name + ".elf") @@ -103,14 +103,14 @@ def _otbn_binary(ctx, additional_srcs = []): deps = [f for dep in ctx.attr.deps for f in dep.files.to_list()] - # Run the otbn_build.py script to link object files from the sources and + # Run the acc_build.py script to link object files from the sources and # dependencies. ctx.actions.run( outputs = [elf, rv32embed, archive], inputs = ([obj] + deps + cc_toolchain.all_files.to_list() + - ctx.files._otbn_data + + ctx.files._acc_data + [ctx.executable._wrapper]), env = { "RV32_TOOL_AS": ctx.executable._riscv32_as.path, @@ -139,7 +139,7 @@ def _otbn_binary(ctx, additional_srcs = []): return [ DefaultInfo(files = depset(outputs), data_runfiles = ctx.runfiles(files = outputs)), OutputGroupInfo( - otbn_objs = depset([obj] + deps), + acc_objs = depset([obj] + deps), elf = depset([elf]), rv32embed = depset([rv32embed]), archive = depset([archive]), @@ -162,7 +162,7 @@ def _otbn_binary(ctx, additional_srcs = []): ] def _run_sim_test(ctx, exp, dexp, pqc, stats, testcase = None, additional_srcs = []): - providers = _otbn_binary(ctx, additional_srcs) + providers = _acc_binary(ctx, additional_srcs) # Extract the output .elf file from the output group. elf = providers[1].elf.to_list()[0] @@ -185,7 +185,7 @@ def _run_sim_test(ctx, exp, dexp, pqc, stats, testcase = None, additional_srcs = if stats: flag_content += "--stats " - # Create a simple script that runs the OTBN test wrapper on the .elf file + # Create a simple script that runs the ACC test wrapper on the .elf file # using the provided simulator path. sim_test_wrapper = ctx.executable._sim_test_wrapper simulator = ctx.executable._simulator @@ -204,17 +204,17 @@ def _run_sim_test(ctx, exp, dexp, pqc, stats, testcase = None, additional_srcs = providers[1], ] -def _otbn_sim_test(ctx): - """This rule is for standalone OTBN unit tests, which are run on the host - via the OTBN simulator. +def _acc_sim_test(ctx): + """This rule is for standalone ACC unit tests, which are run on the host + via the ACC simulator. - It first generates binaries using the same method as otbn_binary, then runs + It first generates binaries using the same method as acc_binary, then runs them on the simulator. Tests are expected to count failures in the w0 register; the test checks that w0=0 to determine if the test passed. """ return _run_sim_test(ctx, ctx.file.exp, ctx.file.dexp, ctx.attr.pqc, ctx.attr.stats, testcase = ctx.file.testcase) -def otbn_sim_test_suite(name, tests, **kwargs): +def acc_sim_test_suite(name, tests, **kwargs): def testname(target): target = target.rsplit("/", 1)[-1] target = target.rsplit(":", 1)[-1] @@ -224,7 +224,7 @@ def otbn_sim_test_suite(name, tests, **kwargs): tests = {testname(t): t for t in tests} for test_name, testcase in tests.items(): - otbn_sim_test(name = test_name, testcase = testcase, **kwargs) + acc_sim_test(name = test_name, testcase = testcase, **kwargs) # manual test_suite to group all individual testcases tags = kwargs.get("tags", []) + ["manual"] @@ -234,9 +234,9 @@ def otbn_sim_test_suite(name, tests, **kwargs): tags = tags, ) -def _otbn_autogen_sim_test_impl(ctx): +def _acc_autogen_sim_test_impl(ctx): """ - Automatically generate test data for OTBN simulator tests. + Automatically generate test data for ACC simulator tests. This infrastructure can be used to generate tests using a known-good implementation. Note that tests with the same testgen script and seed value @@ -245,7 +245,7 @@ def _otbn_autogen_sim_test_impl(ctx): Uses the provided generation script to generate a .s file with input values for DMEM (.data section) and a .exp file with expected register values after - the test. Then, runs the OTBN simulator to check this test's results. + the test. Then, runs the ACC simulator to check this test's results. Test data generation scripts should take two mandatory arguments: the data file path and the expected-values file path. They should also accept a seed @@ -265,7 +265,7 @@ def _otbn_autogen_sim_test_impl(ctx): return _run_sim_test(ctx, exp, dexp, ctx.attr.pqc, ctx.attr.stats, additional_srcs = [data]) -def _otbn_consttime_test_impl(ctx): +def _acc_consttime_test_impl(ctx): """This rule checks if a program or subroutine is constant-time. There are some limitations to this check; see the Python script's @@ -275,7 +275,7 @@ def _otbn_consttime_test_impl(ctx): time; that is, the check can produce false negatives but never false positives. - This rule expects one dependency of an otbn_binary or otbn_sim_test type, + This rule expects one dependency of an acc_binary or acc_sim_test type, which should provide exactly one `.elf` file. """ @@ -307,8 +307,8 @@ def _otbn_consttime_test_impl(ctx): runfiles = runfiles.merge(ctx.attr._checker[DefaultInfo].default_runfiles) return [DefaultInfo(runfiles = runfiles)] -def _otbn_insn_count_range(ctx): - """This rule gets min/max possible instruction counts for an OTBN program. +def _acc_insn_count_range(ctx): + """This rule gets min/max possible instruction counts for an ACC program. """ # Extract the .elf file to check from the dependency list. @@ -328,8 +328,8 @@ def _otbn_insn_count_range(ctx): runfiles = ctx.runfiles(files = ([out])) return [DefaultInfo(files = depset([out]), runfiles = runfiles)] -otbn_library = rv_rule( - implementation = _otbn_library, +acc_library = rv_rule( + implementation = _acc_library, attrs = { "srcs": attr.label_list(allow_files = True), "args": attr.string_list(), @@ -346,8 +346,8 @@ otbn_library = rv_rule( executable = True, cfg = "exec", ), - "_otbn_as": attr.label( - default = "//hw/ip/otbn/util:otbn_as", + "_acc_as": attr.label( + default = "//hw/ip/acc/util:acc_as", executable = True, cfg = "exec", ), @@ -357,8 +357,8 @@ otbn_library = rv_rule( incompatible_use_toolchain_transition = True, ) -otbn_binary = rv_rule( - implementation = _otbn_binary, +acc_binary = rv_rule( + implementation = _acc_binary, attrs = { "srcs": attr.label_list(allow_files = True), "deps": attr.label_list(providers = [DefaultInfo]), @@ -394,17 +394,17 @@ otbn_binary = rv_rule( executable = True, cfg = "exec", ), - "_otbn_as": attr.label( - default = "//hw/ip/otbn/util:otbn_as", + "_acc_as": attr.label( + default = "//hw/ip/acc/util:acc_as", executable = True, cfg = "exec", ), - "_otbn_data": attr.label( - default = "//hw/ip/otbn/data:all_files", + "_acc_data": attr.label( + default = "//hw/ip/acc/data:all_files", allow_files = True, ), "_wrapper": attr.label( - default = "//util:otbn_build", + default = "//util:acc_build", executable = True, cfg = "exec", ), @@ -414,8 +414,8 @@ otbn_binary = rv_rule( incompatible_use_toolchain_transition = True, ) -otbn_sim_test = rv_rule( - implementation = _otbn_sim_test, +acc_sim_test = rv_rule( + implementation = _acc_sim_test, test = True, attrs = { "srcs": attr.label_list(allow_files = True), @@ -457,27 +457,27 @@ otbn_sim_test = rv_rule( executable = True, cfg = "exec", ), - "_otbn_as": attr.label( - default = "//hw/ip/otbn/util:otbn_as", + "_acc_as": attr.label( + default = "//hw/ip/acc/util:acc_as", executable = True, cfg = "exec", ), - "_otbn_data": attr.label( - default = "//hw/ip/otbn/data:all_files", + "_acc_data": attr.label( + default = "//hw/ip/acc/data:all_files", allow_files = True, ), "_simulator": attr.label( - default = "//hw/ip/otbn/dv/otbnsim:standalone", + default = "//hw/ip/acc/dv/accsim:standalone", executable = True, cfg = "exec", ), "_sim_test_wrapper": attr.label( - default = "//hw/ip/otbn/util:otbn_sim_test", + default = "//hw/ip/acc/util:acc_sim_test", executable = True, cfg = "exec", ), "_wrapper": attr.label( - default = "//util:otbn_build", + default = "//util:acc_build", executable = True, cfg = "exec", ), @@ -487,8 +487,8 @@ otbn_sim_test = rv_rule( incompatible_use_toolchain_transition = True, ) -otbn_autogen_sim_test = rv_rule( - implementation = _otbn_autogen_sim_test_impl, +acc_autogen_sim_test = rv_rule( + implementation = _acc_autogen_sim_test_impl, test = True, attrs = { "srcs": attr.label_list(allow_files = True), @@ -533,27 +533,27 @@ otbn_autogen_sim_test = rv_rule( cfg = "exec", ), "seed": attr.int(mandatory = True), - "_otbn_as": attr.label( - default = "//hw/ip/otbn/util:otbn_as", + "_acc_as": attr.label( + default = "//hw/ip/acc/util:acc_as", executable = True, cfg = "exec", ), - "_otbn_data": attr.label( - default = "//hw/ip/otbn/data:all_files", + "_acc_data": attr.label( + default = "//hw/ip/acc/data:all_files", allow_files = True, ), "_simulator": attr.label( - default = "//hw/ip/otbn/dv/otbnsim:standalone", + default = "//hw/ip/acc/dv/accsim:standalone", executable = True, cfg = "exec", ), "_sim_test_wrapper": attr.label( - default = "//hw/ip/otbn/util:otbn_sim_test", + default = "//hw/ip/acc/util:acc_sim_test", executable = True, cfg = "exec", ), "_wrapper": attr.label( - default = "//util:otbn_build", + default = "//util:acc_build", executable = True, cfg = "exec", ), @@ -563,8 +563,8 @@ otbn_autogen_sim_test = rv_rule( incompatible_use_toolchain_transition = True, ) -otbn_consttime_test = rule( - implementation = _otbn_consttime_test_impl, +acc_consttime_test = rule( + implementation = _acc_consttime_test_impl, test = True, attrs = { "srcs": attr.label_list(allow_files = True), @@ -574,19 +574,19 @@ otbn_consttime_test = rule( "secrets": attr.string_list(), "initial_constants": attr.string_list(), "_checker": attr.label( - default = "//hw/ip/otbn/util:check_const_time", + default = "//hw/ip/acc/util:check_const_time", executable = True, cfg = "exec", ), }, ) -otbn_insn_count_range = rule( - implementation = _otbn_insn_count_range, +acc_insn_count_range = rule( + implementation = _acc_insn_count_range, attrs = { "deps": attr.label_list(providers = [OutputGroupInfo]), "_counter": attr.label( - default = "//hw/ip/otbn/util:get_instruction_count_range.py", + default = "//hw/ip/acc/util:get_instruction_count_range.py", allow_single_file = True, ), }, diff --git a/rules/autogen.bzl b/rules/autogen.bzl index 9c90436b52d..7b20a224068 100644 --- a/rules/autogen.bzl +++ b/rules/autogen.bzl @@ -721,9 +721,9 @@ autogen_stamp_include = rule( attrs = stamp_attr(-1, "//rules:stamp_flag"), ) -def _autogen_otbn_insn_count_header(ctx): +def _autogen_acc_insn_count_header(ctx): """This rule generates a header containing min/max instruciton counts for - each mode of a top-level OTBN program. + each mode of a top-level ACC program. """ # Fetch paths and declare files we'll need. @@ -767,14 +767,14 @@ def _autogen_otbn_insn_count_header(ctx): ), ] -autogen_otbn_insn_count_header = rule( - implementation = _autogen_otbn_insn_count_header, +autogen_acc_insn_count_header = rule( + implementation = _autogen_acc_insn_count_header, attrs = { "deps": attr.label_list(providers = [OutputGroupInfo]), "template": attr.label(mandatory = True, allow_single_file = [".tpl"]), "hjson": attr.label(mandatory = True, allow_single_file = [".hjson"]), "_generator": attr.label( - default = "//hw/ip/otbn/util:gen_instruction_count_header", + default = "//hw/ip/acc/util:gen_instruction_count_header", executable = True, cfg = "exec", ), diff --git a/sw/README.md b/sw/README.md index 1cf70d02159..6b04ecb112d 100644 --- a/sw/README.md +++ b/sw/README.md @@ -6,7 +6,7 @@ More description and information can be found within the [Reference Manual](../u There are three major parts to the OpenTitan software stack: * The _device_ software, which runs on the primary core within the OpenTitan platform chip. -* The _otbn_ software, which runs on the OTBN cryptographic co-processor within the OpenTitan platform chip. +* The _acc_ software, which runs on the ACC cryptographic co-processor within the OpenTitan platform chip. * The _host_ software, which is run on a host device and interacts with an OpenTitan device. We use the term "image" to denote a complete, standalone executable which has been prepared for the OpenTitan platform chip. @@ -24,16 +24,16 @@ The device software is split into two parts: Device software must be written in C, Assembly, or Rust. -# OTBN Software +# ACC Software -This software runs on the OTBN cryptographic co-processor within the OpenTitan platform chip. -You can find all the OTBN software in the `sw/otbn` directory of the repository. +This software runs on the ACC cryptographic co-processor within the OpenTitan platform chip. +You can find all the ACC software in the `sw/acc` directory of the repository. -This software consists of a number of hand-written assembly routines which can be run on the OTBN co-processor. +This software consists of a number of hand-written assembly routines which can be run on the ACC co-processor. -Normally, this software can not be run on its own, and the main processor has to set up the data and instructions for the OTBN co-processor before it triggers the start of execution. +Normally, this software can not be run on its own, and the main processor has to set up the data and instructions for the ACC co-processor before it triggers the start of execution. -OTBN Software must only be written in Assembly. +ACC Software must only be written in Assembly. # Host Software diff --git a/sw/otbn/code-snippets/BUILD b/sw/acc/code-snippets/BUILD similarity index 84% rename from sw/otbn/code-snippets/BUILD rename to sw/acc/code-snippets/BUILD index 654c437f929..998da9ffd17 100644 --- a/sw/otbn/code-snippets/BUILD +++ b/sw/acc/code-snippets/BUILD @@ -2,67 +2,67 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_binary") +load("//rules:acc.bzl", "acc_binary") package(default_visibility = ["//visibility:public"]) -otbn_binary( +acc_binary( name = "barrett384", srcs = [ "barrett384.s", ], ) -otbn_binary( +acc_binary( name = "err_test", srcs = [ "err_test.s", ], ) -otbn_binary( +acc_binary( name = "loop", srcs = [ "loop.s", ], ) -otbn_binary( +acc_binary( name = "mul256", srcs = [ "mul256.s", ], ) -otbn_binary( +acc_binary( name = "mul384", srcs = [ "mul384.s", ], ) -otbn_binary( +acc_binary( name = "pseudo-ops", srcs = [ "pseudo-ops.s", ], ) -otbn_binary( +acc_binary( name = "solinas384", srcs = [ "solinas384.s", ], ) -otbn_binary( +acc_binary( name = "randomness", srcs = [ "randomness.s", ], ) -otbn_binary( +acc_binary( name = "calc_montgomery_consts", srcs = [ "calc_montgomery_consts.s", diff --git a/sw/otbn/code-snippets/README.md b/sw/acc/code-snippets/README.md similarity index 90% rename from sw/otbn/code-snippets/README.md rename to sw/acc/code-snippets/README.md index 531caf5b73e..62b95459e74 100644 --- a/sw/otbn/code-snippets/README.md +++ b/sw/acc/code-snippets/README.md @@ -1,10 +1,10 @@ -# OTBN Code Snippets +# ACC Code Snippets This directory contains some code snippets that give examples of how -to do various tasks in OTBN code. +to do various tasks in ACC code. - `modexp.s`: An example of how to do modular exponentiation. -- `pseudo-ops.s`: An example of the pseudo-operations supported by the OTBN ISA. +- `pseudo-ops.s`: An example of the pseudo-operations supported by the ACC ISA. - `mul256.s`: An example of a 256x256 bit multiply using the MULQACC instruction. - `mul384.s`: An example of a 384x384 bit multiply using the MULQACC diff --git a/sw/otbn/code-snippets/barrett384.s b/sw/acc/code-snippets/barrett384.s similarity index 100% rename from sw/otbn/code-snippets/barrett384.s rename to sw/acc/code-snippets/barrett384.s diff --git a/sw/otbn/code-snippets/calc_montgomery_consts.s b/sw/acc/code-snippets/calc_montgomery_consts.s similarity index 100% rename from sw/otbn/code-snippets/calc_montgomery_consts.s rename to sw/acc/code-snippets/calc_montgomery_consts.s diff --git a/sw/otbn/code-snippets/err_test.s b/sw/acc/code-snippets/err_test.s similarity index 100% rename from sw/otbn/code-snippets/err_test.s rename to sw/acc/code-snippets/err_test.s diff --git a/sw/otbn/code-snippets/loop.s b/sw/acc/code-snippets/loop.s similarity index 94% rename from sw/otbn/code-snippets/loop.s rename to sw/acc/code-snippets/loop.s index 77a65517276..59cf048b31d 100644 --- a/sw/otbn/code-snippets/loop.s +++ b/sw/acc/code-snippets/loop.s @@ -2,7 +2,7 @@ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ /* SPDX-License-Identifier: Apache-2.0 */ /* - An example of how hardware loops work in OTBN + An example of how hardware loops work in ACC */ .section .text.start diff --git a/sw/otbn/code-snippets/mul256.s b/sw/acc/code-snippets/mul256.s similarity index 100% rename from sw/otbn/code-snippets/mul256.s rename to sw/acc/code-snippets/mul256.s diff --git a/sw/otbn/code-snippets/mul384.s b/sw/acc/code-snippets/mul384.s similarity index 100% rename from sw/otbn/code-snippets/mul384.s rename to sw/acc/code-snippets/mul384.s diff --git a/sw/otbn/code-snippets/pseudo-ops.s b/sw/acc/code-snippets/pseudo-ops.s similarity index 93% rename from sw/otbn/code-snippets/pseudo-ops.s rename to sw/acc/code-snippets/pseudo-ops.s index 7691a1b863d..752c148c80f 100644 --- a/sw/otbn/code-snippets/pseudo-ops.s +++ b/sw/acc/code-snippets/pseudo-ops.s @@ -2,7 +2,7 @@ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ /* SPDX-License-Identifier: Apache-2.0 */ /* - An example of the pseudo-operations supported by the OTBN ISA + An example of the pseudo-operations supported by the ACC ISA */ .section .text.start diff --git a/sw/otbn/code-snippets/randomness.s b/sw/acc/code-snippets/randomness.s similarity index 97% rename from sw/otbn/code-snippets/randomness.s rename to sw/acc/code-snippets/randomness.s index 1db6f8ebac6..689dfa505a9 100644 --- a/sw/otbn/code-snippets/randomness.s +++ b/sw/acc/code-snippets/randomness.s @@ -2,7 +2,7 @@ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ /* SPDX-License-Identifier: Apache-2.0 */ -/* Test access to randomness from OTBN. */ +/* Test access to randomness from ACC. */ .section .text.start /* Test entry point, no arguments need to be passed in nor results returned. */ @@ -32,7 +32,7 @@ main: * are equal. In rare cases, this could happen and the test should be * re-executed. * - The randomness prefetch is an optimization to hide unknown and highly - * variable latency from the EDN. This, plus the fact that OTBN software + * variable latency from the EDN. This, plus the fact that ACC software * cannot measure its own execution time, makes it impossible to automate * a test for RND_PREFETCH. The instruction is kept nonetheless to help * debugging with waveforms. diff --git a/sw/otbn/code-snippets/solinas384.s b/sw/acc/code-snippets/solinas384.s similarity index 100% rename from sw/otbn/code-snippets/solinas384.s rename to sw/acc/code-snippets/solinas384.s diff --git a/sw/otbn/crypto/BUILD b/sw/acc/crypto/BUILD similarity index 88% rename from sw/otbn/crypto/BUILD rename to sw/acc/crypto/BUILD index 36eae6eba60..6d1b2b62bdb 100644 --- a/sw/otbn/crypto/BUILD +++ b/sw/acc/crypto/BUILD @@ -6,11 +6,11 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_binary", "otbn_library") +load("//rules:acc.bzl", "acc_binary", "acc_library") package(default_visibility = ["//visibility:public"]) -otbn_binary( +acc_binary( name = "boot", srcs = [ "boot.s", @@ -23,21 +23,21 @@ otbn_binary( ], ) -otbn_library( +acc_library( name = "ed25519", srcs = [ "ed25519.s", ], ) -otbn_library( +acc_library( name = "ed25519_scalar", srcs = [ "ed25519_scalar.s", ], ) -otbn_binary( +acc_binary( name = "run_ed25519", srcs = [ "run_ed25519.s", @@ -52,105 +52,105 @@ otbn_binary( ], ) -otbn_library( +acc_library( name = "div", srcs = [ "div.s", ], ) -otbn_library( +acc_library( name = "field25519", srcs = [ "field25519.s", ], ) -otbn_library( +acc_library( name = "gcd", srcs = [ "gcd.s", ], ) -otbn_library( +acc_library( name = "lcm", srcs = [ "lcm.s", ], ) -otbn_library( +acc_library( name = "modexp", srcs = [ "modexp.s", ], ) -otbn_library( +acc_library( name = "modinv", srcs = [ "modinv.s", ], ) -otbn_library( +acc_library( name = "montmul", srcs = [ "montmul.s", ], ) -otbn_library( +acc_library( name = "mul", srcs = [ "mul.s", ], ) -otbn_library( +acc_library( name = "p256_shared_key", srcs = [ "p256_shared_key.s", ], ) -otbn_library( +acc_library( name = "p256_base", srcs = [ "p256_base.s", ], ) -otbn_library( +acc_library( name = "p256_isoncurve", srcs = [ "p256_isoncurve.s", ], ) -otbn_library( +acc_library( name = "p256_isoncurve_proj", srcs = [ "p256_isoncurve_proj.s", ], ) -otbn_library( +acc_library( name = "p256_sign", srcs = [ "p256_sign.s", ], ) -otbn_library( +acc_library( name = "p256_verify", srcs = [ "p256_verify.s", ], ) -otbn_binary( +acc_binary( name = "run_p256", srcs = [ "run_p256.s", @@ -165,105 +165,105 @@ otbn_binary( ], ) -otbn_library( +acc_library( name = "p384_base", srcs = [ "p384_base.s", ], ) -otbn_library( +acc_library( name = "p384_a2b", srcs = [ "p384_a2b.s", ], ) -otbn_library( +acc_library( name = "p384_b2a", srcs = [ "p384_b2a.s", ], ) -otbn_library( +acc_library( name = "p384_isoncurve", srcs = [ "p384_isoncurve.s", ], ) -otbn_library( +acc_library( name = "p384_isoncurve_proj", srcs = [ "p384_isoncurve_proj.s", ], ) -otbn_library( +acc_library( name = "p384_sign", srcs = [ "p384_sign.s", ], ) -otbn_library( +acc_library( name = "p384_internal_mult", srcs = [ "p384_internal_mult.s", ], ) -otbn_library( +acc_library( name = "p384_keygen", srcs = [ "p384_keygen.s", ], ) -otbn_library( +acc_library( name = "p384_keygen_from_seed", srcs = [ "p384_keygen_from_seed.s", ], ) -otbn_library( +acc_library( name = "p384_base_mult", srcs = [ "p384_base_mult.s", ], ) -otbn_library( +acc_library( name = "p384_modinv", srcs = [ "p384_modinv.s", ], ) -otbn_library( +acc_library( name = "p384_scalar_mult", srcs = [ "p384_scalar_mult.s", ], ) -otbn_library( +acc_library( name = "p384_verify", srcs = [ "p384_verify.s", ], ) -otbn_library( +acc_library( name = "primality", srcs = [ "primality.s", ], ) -otbn_binary( +acc_binary( name = "rsa", srcs = [ "rsa.s", @@ -276,7 +276,7 @@ otbn_binary( ], ) -otbn_binary( +acc_binary( name = "run_rsa_modexp", srcs = [ "run_rsa_modexp.s", @@ -289,14 +289,14 @@ otbn_binary( ], ) -otbn_library( +acc_library( name = "rsa_keygen", srcs = [ "rsa_keygen.s", ], ) -otbn_binary( +acc_binary( name = "run_rsa_keygen", srcs = [ "run_rsa_keygen.s", @@ -313,7 +313,7 @@ otbn_binary( ], ) -otbn_binary( +acc_binary( name = "p256_ecdsa_sca", srcs = [ "p256_ecdsa_sca.s", @@ -326,7 +326,7 @@ otbn_binary( ], ) -otbn_binary( +acc_binary( name = "p256_key_from_seed_sca", srcs = [ "p256_key_from_seed_sca.s", @@ -337,7 +337,7 @@ otbn_binary( ], ) -otbn_binary( +acc_binary( name = "p256_mod_inv_sca", srcs = [ "p256_mod_inv_sca.s", @@ -348,7 +348,7 @@ otbn_binary( ], ) -otbn_binary( +acc_binary( name = "p384_ecdsa_sca", srcs = [ "p384_ecdsa_sca.s", @@ -362,7 +362,7 @@ otbn_binary( ], ) -otbn_binary( +acc_binary( name = "run_p384", srcs = [ "run_p384.s", @@ -384,14 +384,14 @@ otbn_binary( ], ) -otbn_library( +acc_library( name = "sha256", srcs = [ "sha256.s", ], ) -otbn_binary( +acc_binary( name = "run_sha256", srcs = [ "run_sha256.s", @@ -401,28 +401,28 @@ otbn_binary( ], ) -otbn_library( +acc_library( name = "sha512", srcs = [ "sha512.s", ], ) -otbn_library( +acc_library( name = "sha512_interface", srcs = [ "sha512_interface.s", ], ) -otbn_library( +acc_library( name = "sha512_padding", srcs = [ "sha512_padding.s", ], ) -otbn_binary( +acc_binary( name = "run_sha512", srcs = [ "run_sha512.s", @@ -432,28 +432,28 @@ otbn_binary( ], ) -otbn_library( +acc_library( name = "sha512_compact", srcs = [ "sha512_compact.s", ], ) -otbn_library( +acc_library( name = "sha3_shake", srcs = [ "sha3_shake.s", ], ) -otbn_library( +acc_library( name = "x25519", srcs = [ "x25519.s", ], ) -otbn_binary( +acc_binary( name = "x25519_sideload", srcs = [ "x25519_sideload.s", diff --git a/sw/otbn/crypto/LICENSE.dcrypto b/sw/acc/crypto/LICENSE.dcrypto similarity index 100% rename from sw/otbn/crypto/LICENSE.dcrypto rename to sw/acc/crypto/LICENSE.dcrypto diff --git a/sw/otbn/crypto/LICENSE.tiny_sha3 b/sw/acc/crypto/LICENSE.tiny_sha3 similarity index 100% rename from sw/otbn/crypto/LICENSE.tiny_sha3 rename to sw/acc/crypto/LICENSE.tiny_sha3 diff --git a/sw/otbn/crypto/boot.s b/sw/acc/crypto/boot.s similarity index 97% rename from sw/otbn/crypto/boot.s rename to sw/acc/crypto/boot.s index 5ce726e7571..893779e9d45 100644 --- a/sw/otbn/crypto/boot.s +++ b/sw/acc/crypto/boot.s @@ -3,7 +3,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ /** - * Unified boot-services OTBN program. + * Unified boot-services ACC program. * * During the boot process, this program should remain loaded. This binary has * the following modes: @@ -30,7 +30,7 @@ * * Of course, in the first stage there is no previous stage signing key and no * certificate, so Ibex should skip the `MODE_ATTESTATION_ENDORSE` step. Ibex - * may clear IMEM/DMEM if it needs to run a different OTBN routine (e.g. + * may clear IMEM/DMEM if it needs to run a different ACC routine (e.g. * signature verification for ownership transfer), but doing so will wipe any * saved keys. This binary is designed so that it should not need to be * cleared and re-loaded on a normal boot. @@ -40,7 +40,7 @@ * 186-5 requirement that the seed comes from a DRBG (other FIPS documents say * it is permissible to XOR DRBG output with implementation-specific values, so * the key manager seed is effectively ignored for FIPS compliance). The saved - * signing key is stored in OTBN's scratchpad memory, which is not accessible + * signing key is stored in ACC's scratchpad memory, which is not accessible * to Ibex over the bus. */ @@ -51,7 +51,7 @@ * Call the same utility with the same arguments and a higher -m to generate * additional value(s) without changing the others or sacrificing mutual HD. * - * TODO(#17727): in some places the OTBN assembler support for .equ directives + * TODO(#17727): in some places the ACC assembler support for .equ directives * is lacking, so they cannot be used in bignum instructions or pseudo-ops such * as `li`. If support is added, we could use 32-bit values here instead of * 11-bit. diff --git a/sw/otbn/crypto/div.s b/sw/acc/crypto/div.s similarity index 100% rename from sw/otbn/crypto/div.s rename to sw/acc/crypto/div.s diff --git a/sw/otbn/crypto/ed25519.s b/sw/acc/crypto/ed25519.s similarity index 99% rename from sw/otbn/crypto/ed25519.s rename to sw/acc/crypto/ed25519.s index 56b6cd34669..155bb4a294a 100644 --- a/sw/otbn/crypto/ed25519.s +++ b/sw/acc/crypto/ed25519.s @@ -48,7 +48,7 @@ * Returns SUCCESS or FAILURE. * * This routine follows RFC 8032, section 5.1.7, but because SHA-512 is not in - * the same OTBN program we have to slightly rearrange the order of operations. + * the same ACC program we have to slightly rearrange the order of operations. * In particular, we assume that Ibex computes step 2 (computation of k = * SHA2-512(dom2(F,C) || R_ || A_ || PH(M)), where R_ and A_ are the encoded * values of curve points from the signature and public key respectively). This diff --git a/sw/otbn/crypto/ed25519_scalar.s b/sw/acc/crypto/ed25519_scalar.s similarity index 98% rename from sw/otbn/crypto/ed25519_scalar.s rename to sw/acc/crypto/ed25519_scalar.s index b4bd460592b..3cdaafb0b67 100644 --- a/sw/otbn/crypto/ed25519_scalar.s +++ b/sw/acc/crypto/ed25519_scalar.s @@ -91,7 +91,7 @@ sc_init: * https://gist.github.com/jadephilipoom/f70e740fbe885bf8b040374eca27a456 * * Note that the proof covers only the algorithm; it doesn't have the exact - * instructions or a machine model of OTBN. The algorithm definition and the + * instructions or a machine model of ACC. The algorithm definition and the * proven specification are reproduced below: * * Definition sc_reduce (x : N) := @@ -208,7 +208,7 @@ sc_reduce: /* Compute r = (x - r2) mod 2^512. Note that the conditional addition in HACS is consistent with the - default behavior of subtraction underflow in OTBN, so there is nothing + default behavior of subtraction underflow in ACC, so there is nothing extra to do here. Additionally, because we know that (x - r2) < 2^256, it holds that: r = (x - r2) mod 2^512 = (x - r2) mod 2^256 diff --git a/sw/otbn/crypto/field25519.s b/sw/acc/crypto/field25519.s similarity index 100% rename from sw/otbn/crypto/field25519.s rename to sw/acc/crypto/field25519.s diff --git a/sw/otbn/crypto/gcd.s b/sw/acc/crypto/gcd.s similarity index 100% rename from sw/otbn/crypto/gcd.s rename to sw/acc/crypto/gcd.s diff --git a/sw/otbn/crypto/handwritten/README.md b/sw/acc/crypto/handwritten/README.md similarity index 100% rename from sw/otbn/crypto/handwritten/README.md rename to sw/acc/crypto/handwritten/README.md diff --git a/sw/otbn/crypto/handwritten/rsa_verify_3072.s b/sw/acc/crypto/handwritten/rsa_verify_3072.s similarity index 100% rename from sw/otbn/crypto/handwritten/rsa_verify_3072.s rename to sw/acc/crypto/handwritten/rsa_verify_3072.s diff --git a/sw/otbn/crypto/lcm.s b/sw/acc/crypto/lcm.s similarity index 100% rename from sw/otbn/crypto/lcm.s rename to sw/acc/crypto/lcm.s diff --git a/sw/otbn/crypto/mldsa/BUILD b/sw/acc/crypto/mldsa/BUILD similarity index 90% rename from sw/otbn/crypto/mldsa/BUILD rename to sw/acc/crypto/mldsa/BUILD index 88cfe734fa9..ccb905105a1 100644 --- a/sw/otbn/crypto/mldsa/BUILD +++ b/sw/acc/crypto/mldsa/BUILD @@ -4,7 +4,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_binary", "otbn_library") +load("//rules:acc.bzl", "acc_binary", "acc_library") package(default_visibility = ["//visibility:public"]) @@ -14,42 +14,42 @@ NAME_BY_SEC_LEVEL = { 5: "mldsa87", } -otbn_library( +acc_library( name = "kmac_send_msg", srcs = [ "kmac_send_msg.s", ], ) -otbn_library( +acc_library( name = "ntt", srcs = [ "ntt.s", ], ) -otbn_library( +acc_library( name = "intt", srcs = [ "intt.s", ], ) -otbn_library( +acc_library( name = "poly_pointwise", srcs = [ "poly_pointwise.s", ], ) -otbn_library( +acc_library( name = "poly_add", srcs = [ "poly_add.s", ], ) -otbn_library( +acc_library( name = "poly_sub", srcs = [ "poly_sub.s", @@ -57,7 +57,7 @@ otbn_library( ) [ - otbn_library( + acc_library( name = name + "_keypair", srcs = [ "mldsa_keypair.s", @@ -70,7 +70,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_verify", srcs = [ "mldsa_verify.s", @@ -83,7 +83,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_poly", srcs = [ "poly.s", @@ -96,7 +96,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_rounding", srcs = [ "rounding.s", @@ -109,7 +109,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_sign", srcs = [ "mldsa_sign.s", @@ -122,7 +122,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_consts", srcs = [ "mldsa_consts.s", diff --git a/sw/otbn/crypto/mldsa/intt.s b/sw/acc/crypto/mldsa/intt.s similarity index 99% rename from sw/otbn/crypto/mldsa/intt.s rename to sw/acc/crypto/mldsa/intt.s index 4ab2c5f8232..ba532adff7d 100644 --- a/sw/otbn/crypto/mldsa/intt.s +++ b/sw/acc/crypto/mldsa/intt.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/kmac_send_msg.s b/sw/acc/crypto/mldsa/kmac_send_msg.s similarity index 98% rename from sw/otbn/crypto/mldsa/kmac_send_msg.s rename to sw/acc/crypto/mldsa/kmac_send_msg.s index e67659f2a8b..1cb428ea842 100644 --- a/sw/otbn/crypto/mldsa/kmac_send_msg.s +++ b/sw/acc/crypto/mldsa/kmac_send_msg.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/mldsa_consts.s b/sw/acc/crypto/mldsa/mldsa_consts.s similarity index 99% rename from sw/otbn/crypto/mldsa/mldsa_consts.s rename to sw/acc/crypto/mldsa/mldsa_consts.s index 1201b435d3d..4e8d358a3de 100644 --- a/sw/otbn/crypto/mldsa/mldsa_consts.s +++ b/sw/acc/crypto/mldsa/mldsa_consts.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/mldsa_keypair.s b/sw/acc/crypto/mldsa/mldsa_keypair.s similarity index 99% rename from sw/otbn/crypto/mldsa/mldsa_keypair.s rename to sw/acc/crypto/mldsa/mldsa_keypair.s index 1ceca7b78f0..d9253a361d8 100644 --- a/sw/otbn/crypto/mldsa/mldsa_keypair.s +++ b/sw/acc/crypto/mldsa/mldsa_keypair.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/mldsa_sign.s b/sw/acc/crypto/mldsa/mldsa_sign.s similarity index 99% rename from sw/otbn/crypto/mldsa/mldsa_sign.s rename to sw/acc/crypto/mldsa/mldsa_sign.s index c4f0eb4a436..a7815d32b74 100644 --- a/sw/otbn/crypto/mldsa/mldsa_sign.s +++ b/sw/acc/crypto/mldsa/mldsa_sign.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/mldsa_verify.s b/sw/acc/crypto/mldsa/mldsa_verify.s similarity index 99% rename from sw/otbn/crypto/mldsa/mldsa_verify.s rename to sw/acc/crypto/mldsa/mldsa_verify.s index 38d3175aad9..82d822da8aa 100644 --- a/sw/otbn/crypto/mldsa/mldsa_verify.s +++ b/sw/acc/crypto/mldsa/mldsa_verify.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/ntt.s b/sw/acc/crypto/mldsa/ntt.s similarity index 99% rename from sw/otbn/crypto/mldsa/ntt.s rename to sw/acc/crypto/mldsa/ntt.s index 5594cf0677f..27e36095819 100644 --- a/sw/otbn/crypto/mldsa/ntt.s +++ b/sw/acc/crypto/mldsa/ntt.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/poly.s b/sw/acc/crypto/mldsa/poly.s similarity index 100% rename from sw/otbn/crypto/mldsa/poly.s rename to sw/acc/crypto/mldsa/poly.s diff --git a/sw/otbn/crypto/mldsa/poly_add.s b/sw/acc/crypto/mldsa/poly_add.s similarity index 97% rename from sw/otbn/crypto/mldsa/poly_add.s rename to sw/acc/crypto/mldsa/poly_add.s index 257adf373f6..ea5f814e1b9 100644 --- a/sw/otbn/crypto/mldsa/poly_add.s +++ b/sw/acc/crypto/mldsa/poly_add.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/poly_pointwise.s b/sw/acc/crypto/mldsa/poly_pointwise.s similarity index 98% rename from sw/otbn/crypto/mldsa/poly_pointwise.s rename to sw/acc/crypto/mldsa/poly_pointwise.s index 8dc81a2915c..7652df45e87 100644 --- a/sw/otbn/crypto/mldsa/poly_pointwise.s +++ b/sw/acc/crypto/mldsa/poly_pointwise.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/poly_sub.s b/sw/acc/crypto/mldsa/poly_sub.s similarity index 97% rename from sw/otbn/crypto/mldsa/poly_sub.s rename to sw/acc/crypto/mldsa/poly_sub.s index d61a0f6af02..385c135b088 100644 --- a/sw/otbn/crypto/mldsa/poly_sub.s +++ b/sw/acc/crypto/mldsa/poly_sub.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mldsa/rounding.s b/sw/acc/crypto/mldsa/rounding.s similarity index 100% rename from sw/otbn/crypto/mldsa/rounding.s rename to sw/acc/crypto/mldsa/rounding.s diff --git a/sw/otbn/crypto/mlkem/BUILD b/sw/acc/crypto/mlkem/BUILD similarity index 90% rename from sw/otbn/crypto/mlkem/BUILD rename to sw/acc/crypto/mlkem/BUILD index 8a549ab4c64..ff58f48a27f 100644 --- a/sw/otbn/crypto/mlkem/BUILD +++ b/sw/acc/crypto/mlkem/BUILD @@ -4,7 +4,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_binary", "otbn_library") +load("//rules:acc.bzl", "acc_binary", "acc_library") package(default_visibility = ["//visibility:public"]) @@ -14,28 +14,28 @@ NAME_BY_SEC_LEVEL = { 4: "mlkem1024", } -otbn_library( +acc_library( name = "ntt", srcs = [ "ntt.s", ], ) -otbn_library( +acc_library( name = "intt", srcs = [ "intt.s", ], ) -otbn_library( +acc_library( name = "basemul", srcs = [ "basemul.s", ], ) -otbn_library( +acc_library( name = "cbd", srcs = [ "cbd.s", @@ -43,7 +43,7 @@ otbn_library( ) [ - otbn_library( + acc_library( name = name + "_poly", srcs = [ "poly.s", @@ -55,7 +55,7 @@ otbn_library( for sec_level, name in NAME_BY_SEC_LEVEL.items() ] -otbn_library( +acc_library( name = "poly_gen_matrix", srcs = [ "poly_gen_matrix.s", @@ -63,7 +63,7 @@ otbn_library( ) [ - otbn_library( + acc_library( name = name + "_pack_ciphertext", srcs = [ "pack_ciphertext.s", @@ -76,7 +76,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_pack_keys", srcs = [ "pack_keys.s", @@ -89,7 +89,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_keypair", srcs = [ "mlkem_keypair.s", @@ -102,7 +102,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_encap", srcs = [ "mlkem_encap.s", @@ -115,7 +115,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_decap", srcs = [ "mlkem_decap.s", @@ -128,7 +128,7 @@ otbn_library( ] [ - otbn_library( + acc_library( name = name + "_consts", srcs = [ "mlkem_consts.s", @@ -140,7 +140,7 @@ otbn_library( for sec_level, name in NAME_BY_SEC_LEVEL.items() ] -otbn_library( +acc_library( name = "kmac_send_msg", srcs = [ "kmac_send_msg.s", diff --git a/sw/otbn/crypto/mlkem/basemul.s b/sw/acc/crypto/mlkem/basemul.s similarity index 99% rename from sw/otbn/crypto/mlkem/basemul.s rename to sw/acc/crypto/mlkem/basemul.s index 32e8db8216e..f2486c2fb24 100644 --- a/sw/otbn/crypto/mlkem/basemul.s +++ b/sw/acc/crypto/mlkem/basemul.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/cbd.s b/sw/acc/crypto/mlkem/cbd.s similarity index 100% rename from sw/otbn/crypto/mlkem/cbd.s rename to sw/acc/crypto/mlkem/cbd.s diff --git a/sw/otbn/crypto/mlkem/intt.s b/sw/acc/crypto/mlkem/intt.s similarity index 99% rename from sw/otbn/crypto/mlkem/intt.s rename to sw/acc/crypto/mlkem/intt.s index 09b2600b20f..ff9d6d8a117 100644 --- a/sw/otbn/crypto/mlkem/intt.s +++ b/sw/acc/crypto/mlkem/intt.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/kmac_send_msg.s b/sw/acc/crypto/mlkem/kmac_send_msg.s similarity index 98% rename from sw/otbn/crypto/mlkem/kmac_send_msg.s rename to sw/acc/crypto/mlkem/kmac_send_msg.s index ac0f9a0d459..06705225309 100644 --- a/sw/otbn/crypto/mlkem/kmac_send_msg.s +++ b/sw/acc/crypto/mlkem/kmac_send_msg.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/mlkem_consts.s b/sw/acc/crypto/mlkem/mlkem_consts.s similarity index 99% rename from sw/otbn/crypto/mlkem/mlkem_consts.s rename to sw/acc/crypto/mlkem/mlkem_consts.s index c4e60931f0c..538fb82504b 100644 --- a/sw/otbn/crypto/mlkem/mlkem_consts.s +++ b/sw/acc/crypto/mlkem/mlkem_consts.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/mlkem_decap.s b/sw/acc/crypto/mlkem/mlkem_decap.s similarity index 99% rename from sw/otbn/crypto/mlkem/mlkem_decap.s rename to sw/acc/crypto/mlkem/mlkem_decap.s index e878727f2be..1722cb1687b 100644 --- a/sw/otbn/crypto/mlkem/mlkem_decap.s +++ b/sw/acc/crypto/mlkem/mlkem_decap.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/mlkem_encap.s b/sw/acc/crypto/mlkem/mlkem_encap.s similarity index 99% rename from sw/otbn/crypto/mlkem/mlkem_encap.s rename to sw/acc/crypto/mlkem/mlkem_encap.s index dd4fb7a9fe3..3ed96aa1450 100644 --- a/sw/otbn/crypto/mlkem/mlkem_encap.s +++ b/sw/acc/crypto/mlkem/mlkem_encap.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/mlkem_keypair.s b/sw/acc/crypto/mlkem/mlkem_keypair.s similarity index 99% rename from sw/otbn/crypto/mlkem/mlkem_keypair.s rename to sw/acc/crypto/mlkem/mlkem_keypair.s index b7bfd8161b7..2a7b8121ac1 100644 --- a/sw/otbn/crypto/mlkem/mlkem_keypair.s +++ b/sw/acc/crypto/mlkem/mlkem_keypair.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/ntt.s b/sw/acc/crypto/mlkem/ntt.s similarity index 99% rename from sw/otbn/crypto/mlkem/ntt.s rename to sw/acc/crypto/mlkem/ntt.s index dc2a2d0093d..2ba5e64fadc 100644 --- a/sw/otbn/crypto/mlkem/ntt.s +++ b/sw/acc/crypto/mlkem/ntt.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/pack_ciphertext.s b/sw/acc/crypto/mlkem/pack_ciphertext.s similarity index 99% rename from sw/otbn/crypto/mlkem/pack_ciphertext.s rename to sw/acc/crypto/mlkem/pack_ciphertext.s index 507d5df7c6b..e682f9d8b9d 100644 --- a/sw/otbn/crypto/mlkem/pack_ciphertext.s +++ b/sw/acc/crypto/mlkem/pack_ciphertext.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/pack_keys.s b/sw/acc/crypto/mlkem/pack_keys.s similarity index 99% rename from sw/otbn/crypto/mlkem/pack_keys.s rename to sw/acc/crypto/mlkem/pack_keys.s index e4cdc484816..832a8fc9ae7 100644 --- a/sw/otbn/crypto/mlkem/pack_keys.s +++ b/sw/acc/crypto/mlkem/pack_keys.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/poly.s b/sw/acc/crypto/mlkem/poly.s similarity index 99% rename from sw/otbn/crypto/mlkem/poly.s rename to sw/acc/crypto/mlkem/poly.s index 36e5cfb3f0c..fd2993a1e0a 100644 --- a/sw/otbn/crypto/mlkem/poly.s +++ b/sw/acc/crypto/mlkem/poly.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/mlkem/poly_gen_matrix.s b/sw/acc/crypto/mlkem/poly_gen_matrix.s similarity index 99% rename from sw/otbn/crypto/mlkem/poly_gen_matrix.s rename to sw/acc/crypto/mlkem/poly_gen_matrix.s index bda68f1e801..24da9e22f6f 100644 --- a/sw/otbn/crypto/mlkem/poly_gen_matrix.s +++ b/sw/acc/crypto/mlkem/poly_gen_matrix.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/modexp.s b/sw/acc/crypto/modexp.s similarity index 100% rename from sw/otbn/crypto/modexp.s rename to sw/acc/crypto/modexp.s diff --git a/sw/otbn/crypto/modinv.s b/sw/acc/crypto/modinv.s similarity index 100% rename from sw/otbn/crypto/modinv.s rename to sw/acc/crypto/modinv.s diff --git a/sw/otbn/crypto/montmul.s b/sw/acc/crypto/montmul.s similarity index 100% rename from sw/otbn/crypto/montmul.s rename to sw/acc/crypto/montmul.s diff --git a/sw/otbn/crypto/mul.s b/sw/acc/crypto/mul.s similarity index 100% rename from sw/otbn/crypto/mul.s rename to sw/acc/crypto/mul.s diff --git a/sw/otbn/crypto/p256_base.s b/sw/acc/crypto/p256_base.s similarity index 99% rename from sw/otbn/crypto/p256_base.s rename to sw/acc/crypto/p256_base.s index 807643eb2eb..b6096325128 100644 --- a/sw/otbn/crypto/p256_base.s +++ b/sw/acc/crypto/p256_base.s @@ -40,7 +40,7 @@ * Trigger a fault if the FG0.Z flag is 1. * * If the flag is 1, then this routine will trigger an `ILLEGAL_INSN` error and - * abort the OTBN program. If the flag is 0, the routine will essentially do + * abort the ACC program. If the flag is 0, the routine will essentially do * nothing. * * NOTE: Be careful when calling this routine that the FG0.Z flag is not @@ -81,7 +81,7 @@ trigger_fault_if_fg0_z: * Trigger a fault if the FG0.Z flag is 0. * * If the flag is 0, then this routine will trigger an `ILLEGAL_INSN` error and - * abort the OTBN program. If the flag is 1, the routine will essentially do + * abort the ACC program. If the flag is 1, the routine will essentially do * nothing. * * NOTE: Be careful when calling this routine that the FG0.Z flag is not @@ -148,7 +148,7 @@ trigger_fault_if_fg0_not_z: * sufficient (although potentially not necessary): * b * (b^2k mod m) + mu <= b^(k+1) * - * For OTBN with a 256-bit modulus, we have b=2^256 and k=1, so this is: + * For ACC with a 256-bit modulus, we have b=2^256 and k=1, so this is: * 2^256 * (2^512 mod m) + mu <= 2^512 * * Flags: Flags have no meaning beyond the scope of this subroutine. @@ -411,7 +411,7 @@ mod_mul_320x128: * modulus p = 2^256 - 2^224 + 2^192 + 2^96 - 1. * * This code has been proven correct in Coq here against a simplified model of - * OTBN (simplified in the sense of only including the instructions and + * ACC (simplified in the sense of only including the instructions and * functionality that this code uses): * https://gist.github.com/jadephilipoom/5c1910fd355f730238c99ce620aed98a * @@ -1670,7 +1670,7 @@ p256_random_scalar: bn.wsrr w17, RND /* XOR with bits from URND, just in case there's any vulnerability in EDN - that lets the attacker recover bits before they reach OTBN. */ + that lets the attacker recover bits before they reach ACC. */ bn.wsrr w20, URND bn.xor w15, w15, w20 bn.wsrr w20, URND diff --git a/sw/otbn/crypto/p256_ecdsa_sca.s b/sw/acc/crypto/p256_ecdsa_sca.s similarity index 97% rename from sw/otbn/crypto/p256_ecdsa_sca.s rename to sw/acc/crypto/p256_ecdsa_sca.s index 3de53836079..e9f75ed781e 100644 --- a/sw/otbn/crypto/p256_ecdsa_sca.s +++ b/sw/acc/crypto/p256_ecdsa_sca.s @@ -5,7 +5,7 @@ /** * Elliptic curve P-256 ECDSA * - * Uses OTBN ECC P-256 lib to perform an ECDSA operations. + * Uses ACC ECC P-256 lib to perform an ECDSA operations. */ .section .text.start @@ -78,7 +78,7 @@ k1: .globl msg .balign 32 msg: - /* msg = "Hello OTBN."*/ + /* msg = "Hello ACC."*/ /* msg = 0x06d71207...4456fd21 */ /* Note: Byte order in a word is little-endian */ .word 0x4456fd21 diff --git a/sw/otbn/crypto/p256_isoncurve.s b/sw/acc/crypto/p256_isoncurve.s similarity index 100% rename from sw/otbn/crypto/p256_isoncurve.s rename to sw/acc/crypto/p256_isoncurve.s diff --git a/sw/otbn/crypto/p256_isoncurve_proj.s b/sw/acc/crypto/p256_isoncurve_proj.s similarity index 100% rename from sw/otbn/crypto/p256_isoncurve_proj.s rename to sw/acc/crypto/p256_isoncurve_proj.s diff --git a/sw/otbn/crypto/p256_key_from_seed_sca.s b/sw/acc/crypto/p256_key_from_seed_sca.s similarity index 100% rename from sw/otbn/crypto/p256_key_from_seed_sca.s rename to sw/acc/crypto/p256_key_from_seed_sca.s diff --git a/sw/otbn/crypto/p256_mod_inv_sca.s b/sw/acc/crypto/p256_mod_inv_sca.s similarity index 100% rename from sw/otbn/crypto/p256_mod_inv_sca.s rename to sw/acc/crypto/p256_mod_inv_sca.s diff --git a/sw/otbn/crypto/p256_shared_key.s b/sw/acc/crypto/p256_shared_key.s similarity index 100% rename from sw/otbn/crypto/p256_shared_key.s rename to sw/acc/crypto/p256_shared_key.s diff --git a/sw/otbn/crypto/p256_sign.s b/sw/acc/crypto/p256_sign.s similarity index 100% rename from sw/otbn/crypto/p256_sign.s rename to sw/acc/crypto/p256_sign.s diff --git a/sw/otbn/crypto/p256_verify.s b/sw/acc/crypto/p256_verify.s similarity index 100% rename from sw/otbn/crypto/p256_verify.s rename to sw/acc/crypto/p256_verify.s diff --git a/sw/otbn/crypto/p384_a2b.s b/sw/acc/crypto/p384_a2b.s similarity index 100% rename from sw/otbn/crypto/p384_a2b.s rename to sw/acc/crypto/p384_a2b.s diff --git a/sw/otbn/crypto/p384_b2a.s b/sw/acc/crypto/p384_b2a.s similarity index 100% rename from sw/otbn/crypto/p384_b2a.s rename to sw/acc/crypto/p384_b2a.s diff --git a/sw/otbn/crypto/p384_base.s b/sw/acc/crypto/p384_base.s similarity index 100% rename from sw/otbn/crypto/p384_base.s rename to sw/acc/crypto/p384_base.s diff --git a/sw/otbn/crypto/p384_base_mult.s b/sw/acc/crypto/p384_base_mult.s similarity index 100% rename from sw/otbn/crypto/p384_base_mult.s rename to sw/acc/crypto/p384_base_mult.s diff --git a/sw/otbn/crypto/p384_curve_point_valid.s b/sw/acc/crypto/p384_curve_point_valid.s similarity index 100% rename from sw/otbn/crypto/p384_curve_point_valid.s rename to sw/acc/crypto/p384_curve_point_valid.s diff --git a/sw/otbn/crypto/p384_ecdsa_sca.s b/sw/acc/crypto/p384_ecdsa_sca.s similarity index 96% rename from sw/otbn/crypto/p384_ecdsa_sca.s rename to sw/acc/crypto/p384_ecdsa_sca.s index ba0c2a8e94b..61eee8b1545 100644 --- a/sw/otbn/crypto/p384_ecdsa_sca.s +++ b/sw/acc/crypto/p384_ecdsa_sca.s @@ -5,7 +5,7 @@ /** * Elliptic curve P-384 ECDSA * - * Uses OTBN ECC P-384 lib to perform an ECDSA operations. + * Uses ACC ECC P-384 lib to perform an ECDSA operations. */ .section .text.start diff --git a/sw/otbn/crypto/p384_internal_mult.s b/sw/acc/crypto/p384_internal_mult.s similarity index 100% rename from sw/otbn/crypto/p384_internal_mult.s rename to sw/acc/crypto/p384_internal_mult.s diff --git a/sw/otbn/crypto/p384_isoncurve.s b/sw/acc/crypto/p384_isoncurve.s similarity index 98% rename from sw/otbn/crypto/p384_isoncurve.s rename to sw/acc/crypto/p384_isoncurve.s index 25150d8c104..20b9efa5469 100644 --- a/sw/otbn/crypto/p384_isoncurve.s +++ b/sw/acc/crypto/p384_isoncurve.s @@ -24,7 +24,7 @@ * Trigger a fault if the FG0.Z flag is 0. * * If the flag is 0, then this routine will trigger an `ILLEGAL_INSN` error and - * abort the OTBN program. If the flag is 1, the routine will essentially do + * abort the ACC program. If the flag is 1, the routine will essentially do * nothing. * * NOTE: Be careful when calling this routine that the FG0.Z flag is not @@ -344,7 +344,7 @@ p384_check_public_key: /** * If the flag is 0, then this routine will sets `ok` to false and end the - * execution of the OTBN program. If the flag is 1, the routine will + * execution of the ACC program. If the flag is 1, the routine will * essentially do nothing. * * @param[in] FG0.Z: boolean indicating fault condition diff --git a/sw/otbn/crypto/p384_isoncurve_proj.s b/sw/acc/crypto/p384_isoncurve_proj.s similarity index 100% rename from sw/otbn/crypto/p384_isoncurve_proj.s rename to sw/acc/crypto/p384_isoncurve_proj.s diff --git a/sw/otbn/crypto/p384_keygen.s b/sw/acc/crypto/p384_keygen.s similarity index 99% rename from sw/otbn/crypto/p384_keygen.s rename to sw/acc/crypto/p384_keygen.s index f5678062111..f81b1697d58 100644 --- a/sw/otbn/crypto/p384_keygen.s +++ b/sw/acc/crypto/p384_keygen.s @@ -70,7 +70,7 @@ p384_random_scalar: bn.wsrr w9, RND /* XOR with bits from URND, just in case there's any vulnerability in EDN - that lets the attacker recover bits before they reach OTBN. */ + that lets the attacker recover bits before they reach ACC. */ bn.wsrr w5, URND bn.xor w6, w6, w5 bn.wsrr w5, URND diff --git a/sw/otbn/crypto/p384_keygen_from_seed.s b/sw/acc/crypto/p384_keygen_from_seed.s similarity index 100% rename from sw/otbn/crypto/p384_keygen_from_seed.s rename to sw/acc/crypto/p384_keygen_from_seed.s diff --git a/sw/otbn/crypto/p384_modinv.s b/sw/acc/crypto/p384_modinv.s similarity index 100% rename from sw/otbn/crypto/p384_modinv.s rename to sw/acc/crypto/p384_modinv.s diff --git a/sw/otbn/crypto/p384_scalar_mult.s b/sw/acc/crypto/p384_scalar_mult.s similarity index 100% rename from sw/otbn/crypto/p384_scalar_mult.s rename to sw/acc/crypto/p384_scalar_mult.s diff --git a/sw/otbn/crypto/p384_sign.s b/sw/acc/crypto/p384_sign.s similarity index 100% rename from sw/otbn/crypto/p384_sign.s rename to sw/acc/crypto/p384_sign.s diff --git a/sw/otbn/crypto/p384_verify.s b/sw/acc/crypto/p384_verify.s similarity index 100% rename from sw/otbn/crypto/p384_verify.s rename to sw/acc/crypto/p384_verify.s diff --git a/sw/otbn/crypto/primality.s b/sw/acc/crypto/primality.s similarity index 99% rename from sw/otbn/crypto/primality.s rename to sw/acc/crypto/primality.s index 020e5aa0d47..0382c3d644c 100644 --- a/sw/otbn/crypto/primality.s +++ b/sw/acc/crypto/primality.s @@ -60,7 +60,7 @@ miller_rabin: andi x2, x2, 1 /* Skip the rest of the loop if w is composite (x2 == 0). We can't exit - loops early in OTBN, but we can jump past the loop body to speed up + loops early in ACC, but we can jump past the loop body to speed up computation. */ beq x2, x0, _miller_rabin_loop_end diff --git a/sw/otbn/crypto/rsa.s b/sw/acc/crypto/rsa.s similarity index 100% rename from sw/otbn/crypto/rsa.s rename to sw/acc/crypto/rsa.s diff --git a/sw/otbn/crypto/rsa_keygen.s b/sw/acc/crypto/rsa_keygen.s similarity index 99% rename from sw/otbn/crypto/rsa_keygen.s rename to sw/acc/crypto/rsa_keygen.s index 1cb6c978ce9..13a46d35ddc 100644 --- a/sw/otbn/crypto/rsa_keygen.s +++ b/sw/acc/crypto/rsa_keygen.s @@ -1485,7 +1485,7 @@ generate_p: _generate_p_retry: /* Check if the attempt counter is nonzero. Otherwise, trigger an error that - immediately aborts the OTBN program. */ + immediately aborts the ACC program. */ bne x4, x0, _generate_p_counter_nonzero unimp @@ -1557,7 +1557,7 @@ generate_q: _generate_q_retry: /* Check if the attempt counter is nonzero. Otherwise, trigger an error that - immediately aborts the OTBN program. */ + immediately aborts the ACC program. */ bne x4, x0, _generate_q_counter_nonzero unimp diff --git a/sw/otbn/crypto/run_ed25519.s b/sw/acc/crypto/run_ed25519.s similarity index 98% rename from sw/otbn/crypto/run_ed25519.s rename to sw/acc/crypto/run_ed25519.s index cd0687f046c..38fe611271c 100644 --- a/sw/otbn/crypto/run_ed25519.s +++ b/sw/acc/crypto/run_ed25519.s @@ -20,7 +20,7 @@ * Call the same utility with the same arguments and a higher -m to generate * additional value(s) without changing the others or sacrificing mutual HD. * - * TODO(#17727): in some places the OTBN assembler support for .equ directives + * TODO(#17727): in some places the ACC assembler support for .equ directives * is lacking, so they cannot be used in bignum instructions or pseudo-ops such * as `li`. If support is added, we could use 32-bit values here instead of * 11-bit. diff --git a/sw/otbn/crypto/run_p256.s b/sw/acc/crypto/run_p256.s similarity index 99% rename from sw/otbn/crypto/run_p256.s rename to sw/acc/crypto/run_p256.s index 4fd8bb75630..3199efa5e1a 100644 --- a/sw/otbn/crypto/run_p256.s +++ b/sw/acc/crypto/run_p256.s @@ -28,7 +28,7 @@ * Call the same utility with the same arguments and a higher -m to generate * additional value(s) without changing the others or sacrificing mutual HD. * - * TODO(#17727): in some places the OTBN assembler support for .equ directives + * TODO(#17727): in some places the ACC assembler support for .equ directives * is lacking, so they cannot be used in bignum instructions or pseudo-ops such * as `li`. If support is added, we could use 32-bit values here instead of * 11-bit. diff --git a/sw/otbn/crypto/run_p384.s b/sw/acc/crypto/run_p384.s similarity index 99% rename from sw/otbn/crypto/run_p384.s rename to sw/acc/crypto/run_p384.s index 59df06cad4d..9659dd8deb0 100644 --- a/sw/otbn/crypto/run_p384.s +++ b/sw/acc/crypto/run_p384.s @@ -27,7 +27,7 @@ * Call the same utility with the same arguments and a higher -m to generate * additional value(s) without changing the others or sacrificing mutual HD. * - * TODO(#17727): in some places the OTBN assembler support for .equ directives + * TODO(#17727): in some places the ACC assembler support for .equ directives * is lacking, so they cannot be used in bignum instructions or pseudo-ops such * as `li`. If support is added, we could use 32-bit values here instead of * 11-bit. diff --git a/sw/otbn/crypto/run_rsa_keygen.s b/sw/acc/crypto/run_rsa_keygen.s similarity index 98% rename from sw/otbn/crypto/run_rsa_keygen.s rename to sw/acc/crypto/run_rsa_keygen.s index 89a8ff7ed80..95c81673064 100644 --- a/sw/otbn/crypto/run_rsa_keygen.s +++ b/sw/acc/crypto/run_rsa_keygen.s @@ -21,7 +21,7 @@ * Call the same utility with the same arguments and a higher -m to generate * additional value(s) without changing the others or sacrificing mutual HD. * - * TODO(#17727): in some places the OTBN assembler support for .equ directives + * TODO(#17727): in some places the ACC assembler support for .equ directives * is lacking, so they cannot be used in bignum instructions or pseudo-ops such * as `li`. If support is added, we could use 32-bit values here instead of * 11-bit. diff --git a/sw/otbn/crypto/run_rsa_modexp.s b/sw/acc/crypto/run_rsa_modexp.s similarity index 99% rename from sw/otbn/crypto/run_rsa_modexp.s rename to sw/acc/crypto/run_rsa_modexp.s index 1dd8e601c8d..d65c2878ac7 100644 --- a/sw/otbn/crypto/run_rsa_modexp.s +++ b/sw/acc/crypto/run_rsa_modexp.s @@ -29,7 +29,7 @@ * Call the same utility with the same arguments and a higher -m to generate * additional value(s) without changing the others or sacrificing mutual HD. * - * TODO(#17727): in some places the OTBN assembler support for .equ directives + * TODO(#17727): in some places the ACC assembler support for .equ directives * is lacking, so they cannot be used in bignum instructions or pseudo-ops such * as `li`. If support is added, we could use 32-bit values here instead of * 11-bit. diff --git a/sw/otbn/crypto/run_sha256.s b/sw/acc/crypto/run_sha256.s similarity index 100% rename from sw/otbn/crypto/run_sha256.s rename to sw/acc/crypto/run_sha256.s diff --git a/sw/otbn/crypto/run_sha512.s b/sw/acc/crypto/run_sha512.s similarity index 100% rename from sw/otbn/crypto/run_sha512.s rename to sw/acc/crypto/run_sha512.s diff --git a/sw/otbn/crypto/sha256.s b/sw/acc/crypto/sha256.s similarity index 99% rename from sw/otbn/crypto/sha256.s rename to sw/acc/crypto/sha256.s index abf18389c9b..3d720380f5f 100644 --- a/sw/otbn/crypto/sha256.s +++ b/sw/acc/crypto/sha256.s @@ -84,7 +84,7 @@ sha256: * Flip the bytes in each 32-bit word of a 256-bit value. * * This is useful for big-endian/little-endian conversions. FIPS 180-4 uses - * big-endian integer representation, and OTBN uses little-endian. + * big-endian integer representation, and ACC uses little-endian. * * This routine runs in constant time. * diff --git a/sw/otbn/crypto/sha3_shake.s b/sw/acc/crypto/sha3_shake.s similarity index 100% rename from sw/otbn/crypto/sha3_shake.s rename to sw/acc/crypto/sha3_shake.s diff --git a/sw/otbn/crypto/sha512.s b/sw/acc/crypto/sha512.s similarity index 100% rename from sw/otbn/crypto/sha512.s rename to sw/acc/crypto/sha512.s diff --git a/sw/otbn/crypto/sha512_compact.s b/sw/acc/crypto/sha512_compact.s similarity index 100% rename from sw/otbn/crypto/sha512_compact.s rename to sw/acc/crypto/sha512_compact.s diff --git a/sw/otbn/crypto/sha512_interface.s b/sw/acc/crypto/sha512_interface.s similarity index 99% rename from sw/otbn/crypto/sha512_interface.s rename to sw/acc/crypto/sha512_interface.s index 692d3b96586..9f4f30278a3 100644 --- a/sw/otbn/crypto/sha512_interface.s +++ b/sw/acc/crypto/sha512_interface.s @@ -7,7 +7,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ /** - * The purpose of this library is to give *other OTBN code* (primarily Ed25519) + * The purpose of this library is to give *other ACC code* (primarily Ed25519) * a clean way to call SHA-512. It is not intended for use directly from Ibex. */ .globl sha512_oneshot diff --git a/sw/otbn/crypto/sha512_padding.s b/sw/acc/crypto/sha512_padding.s similarity index 98% rename from sw/otbn/crypto/sha512_padding.s rename to sw/acc/crypto/sha512_padding.s index f2776d9bd90..591dc72235b 100644 --- a/sw/otbn/crypto/sha512_padding.s +++ b/sw/acc/crypto/sha512_padding.s @@ -68,7 +68,7 @@ sha512_pad_message: srl x2, x2, x3 _sha512_pad_message_skip_load: - /* Set the first (least significant, because OTBN is little-endian) padding + /* Set the first (least significant, because ACC is little-endian) padding byte to 0x80, and fill remainder of word with zeroes. dmem[x21] = x2 ^ (0x80 << (8 * x20) */ slli x3, x20, 3 diff --git a/sw/otbn/crypto/tests/BUILD b/sw/acc/crypto/tests/BUILD similarity index 59% rename from sw/otbn/crypto/tests/BUILD rename to sw/acc/crypto/tests/BUILD index eacee958564..16be5ea4b84 100644 --- a/sw/otbn/crypto/tests/BUILD +++ b/sw/acc/crypto/tests/BUILD @@ -3,43 +3,43 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_consttime_test", "otbn_library", "otbn_sim_test", "otbn_sim_test_suite") +load("//rules:acc.bzl", "acc_consttime_test", "acc_library", "acc_sim_test", "acc_sim_test_suite") package(default_visibility = ["//visibility:public"]) -otbn_sim_test( +acc_sim_test( name = "ed25519_encode_decode_test", srcs = [ "ed25519_encode_decode_test.s", ], exp = "ed25519_encode_decode_test.exp", deps = [ - "//sw/otbn/crypto:ed25519", - "//sw/otbn/crypto:ed25519_scalar", - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:sha512_compact", - "//sw/otbn/crypto:sha512_interface", - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:ed25519", + "//sw/acc/crypto:ed25519_scalar", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:sha512_compact", + "//sw/acc/crypto:sha512_interface", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_sim_test( +acc_sim_test( name = "ed25519_ext_add_test", srcs = [ "ed25519_ext_add_test.s", ], exp = "ed25519_ext_add_test.exp", deps = [ - "//sw/otbn/crypto:ed25519", - "//sw/otbn/crypto:ed25519_scalar", - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:sha512_compact", - "//sw/otbn/crypto:sha512_interface", - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:ed25519", + "//sw/acc/crypto:ed25519_scalar", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:sha512_compact", + "//sw/acc/crypto:sha512_interface", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_consttime_test( +acc_consttime_test( name = "ed25519_ext_add_consttime", subroutine = "ext_add", deps = [ @@ -47,115 +47,115 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "ed25519_ext_scmul_test", srcs = [ "ed25519_ext_scmul_test.s", ], exp = "ed25519_ext_scmul_test.exp", deps = [ - "//sw/otbn/crypto:ed25519", - "//sw/otbn/crypto:ed25519_scalar", - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:sha512_compact", - "//sw/otbn/crypto:sha512_interface", - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:ed25519", + "//sw/acc/crypto:ed25519_scalar", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:sha512_compact", + "//sw/acc/crypto:sha512_interface", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_sim_test( +acc_sim_test( name = "ed25519_scalar_test", srcs = [ "ed25519_scalar_test.s", ], exp = "ed25519_scalar_test.exp", deps = [ - "//sw/otbn/crypto:ed25519_scalar", + "//sw/acc/crypto:ed25519_scalar", ], ) -otbn_sim_test( +acc_sim_test( name = "ed25519_sign_prehashed_test", srcs = [ "ed25519_sign_prehashed_test.s", ], dexp = "ed25519_sign_prehashed_test.dexp", deps = [ - "//sw/otbn/crypto:ed25519", - "//sw/otbn/crypto:ed25519_scalar", - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:sha512_compact", - "//sw/otbn/crypto:sha512_interface", - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:ed25519", + "//sw/acc/crypto:ed25519_scalar", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:sha512_compact", + "//sw/acc/crypto:sha512_interface", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_sim_test( +acc_sim_test( name = "ed25519_verify_test", srcs = [ "ed25519_verify_test.s", ], exp = "ed25519_verify_test.exp", deps = [ - "//sw/otbn/crypto:ed25519", - "//sw/otbn/crypto:ed25519_scalar", - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:sha512_compact", - "//sw/otbn/crypto:sha512_interface", - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:ed25519", + "//sw/acc/crypto:ed25519_scalar", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:sha512_compact", + "//sw/acc/crypto:sha512_interface", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_sim_test( +acc_sim_test( name = "ed25519_verify_test2", srcs = [ "ed25519_verify_test2.s", ], exp = "ed25519_verify_test2.exp", deps = [ - "//sw/otbn/crypto:ed25519", - "//sw/otbn/crypto:ed25519_scalar", - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:sha512_compact", - "//sw/otbn/crypto:sha512_interface", - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:ed25519", + "//sw/acc/crypto:ed25519_scalar", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:sha512_compact", + "//sw/acc/crypto:sha512_interface", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_sim_test( +acc_sim_test( name = "div_large_test", srcs = [ "div_large_test.s", ], exp = "div_large_test.exp", deps = [ - "//sw/otbn/crypto:div", + "//sw/acc/crypto:div", ], ) -otbn_sim_test( +acc_sim_test( name = "div_medium_test", srcs = [ "div_medium_test.s", ], exp = "div_medium_test.exp", deps = [ - "//sw/otbn/crypto:div", + "//sw/acc/crypto:div", ], ) -otbn_sim_test( +acc_sim_test( name = "div_small_test", srcs = [ "div_small_test.s", ], exp = "div_small_test.exp", deps = [ - "//sw/otbn/crypto:div", + "//sw/acc/crypto:div", ], ) -otbn_consttime_test( +acc_consttime_test( name = "div_consttime", # All secrets are stored in DMEM; timing is permitted to depend on the # number of limbs. @@ -166,18 +166,18 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "mod_test", srcs = [ "mod_test.s", ], exp = "mod_test.exp", deps = [ - "//sw/otbn/crypto:div", + "//sw/acc/crypto:div", ], ) -otbn_consttime_test( +acc_consttime_test( name = "mod_consttime", # All secrets are stored in DMEM; timing is permitted to depend on the # number of limbs. @@ -188,18 +188,18 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "field25519_test", srcs = [ "field25519_test.s", ], exp = "field25519_test.exp", deps = [ - "//sw/otbn/crypto:field25519", + "//sw/acc/crypto:field25519", ], ) -otbn_consttime_test( +acc_consttime_test( name = "field25519_fe_inv_consttime", subroutine = "fe_inv", deps = [ @@ -207,7 +207,7 @@ otbn_consttime_test( ], ) -otbn_consttime_test( +acc_consttime_test( name = "field25519_fe_mul_consttime", subroutine = "fe_mul", deps = [ @@ -215,7 +215,7 @@ otbn_consttime_test( ], ) -otbn_consttime_test( +acc_consttime_test( name = "field25519_fe_square_consttime", subroutine = "fe_square", deps = [ @@ -223,29 +223,29 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "gcd_small_test", srcs = [ "gcd_small_test.s", ], exp = "gcd_small_test.exp", deps = [ - "//sw/otbn/crypto:gcd", + "//sw/acc/crypto:gcd", ], ) -otbn_sim_test( +acc_sim_test( name = "gcd_large_test", srcs = [ "gcd_large_test.s", ], exp = "gcd_large_test.exp", deps = [ - "//sw/otbn/crypto:gcd", + "//sw/acc/crypto:gcd", ], ) -otbn_consttime_test( +acc_consttime_test( name = "gcd_consttime", # All inputs are in DMEM; no registers are secret. secrets = ["dmem"], @@ -255,21 +255,21 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "lcm_test", srcs = [ "lcm_test.s", ], exp = "lcm_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:mul", ], ) -otbn_consttime_test( +acc_consttime_test( name = "lcm_consttime", # All inputs are in DMEM; no registers are secret. secrets = ["dmem"], @@ -279,18 +279,18 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "mul_test", srcs = [ "mul_test.s", ], dexp = "mul_test.dexp", deps = [ - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:mul", ], ) -otbn_consttime_test( +acc_consttime_test( name = "mul_consttime", # All inputs are in DMEM; no registers are secret. secrets = ["dmem"], @@ -300,18 +300,18 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "mul256_test", srcs = [ "mul256_test.s", ], dexp = "mul256_test.dexp", deps = [ - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:mul", ], ) -otbn_consttime_test( +acc_consttime_test( name = "mul256_consttime", # All inputs are in DMEM; no registers are secret. secrets = ["dmem"], @@ -321,91 +321,91 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "p256_base_mult_test", srcs = [ "p256_base_mult_test.s", ], exp = "p256_base_mult_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_scalar_remask_test", srcs = [ "p256_scalar_remask_test.s", ], exp = "p256_scalar_remask_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_consttime_test( +acc_consttime_test( name = "p256_base_mult_consttime", subroutine = "p256_base_mult", deps = [ - "//sw/otbn/crypto:run_p256", + "//sw/acc/crypto:run_p256", ], ) -otbn_consttime_test( +acc_consttime_test( name = "p256_isoncurve_consttime", subroutine = "p256_isoncurve", deps = [ - "//sw/otbn/crypto:run_p256", + "//sw/acc/crypto:run_p256", ], ) -otbn_consttime_test( +acc_consttime_test( name = "p256_key_from_seed_consttime", subroutine = "p256_key_from_seed", deps = [ - "//sw/otbn/crypto:run_p256", + "//sw/acc/crypto:run_p256", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_key_from_seed_test", srcs = [ "p256_key_from_seed_test.s", ], exp = "p256_key_from_seed_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_mul_modp_test", srcs = [ "p256_mul_modp_test.s", ], exp = "p256_mul_modp_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_consttime_test( +acc_consttime_test( name = "p256_proj_add_consttime", subroutine = "proj_add", deps = [ - "//sw/otbn/crypto:run_p256", + "//sw/acc/crypto:run_p256", ], ) -otbn_consttime_test( +acc_consttime_test( name = "p256_shared_key_consttime", subroutine = "p256_shared_key", deps = [ - "//sw/otbn/crypto:run_p256", + "//sw/acc/crypto:run_p256", ], ) @@ -415,146 +415,146 @@ otbn_consttime_test( # mark DMEM non-secret, and the constant-time checker doesn't currently have # the ability to track different DMEM regions separately. # -# otbn_consttime_test( +# acc_consttime_test( # name = "p256_sign_consttime", # deps = [ -# "//sw/otbn/crypto:run_p256" +# "//sw/acc/crypto:run_p256" # ], # subroutine = "p256_sign", # ) -otbn_sim_test( +acc_sim_test( name = "p256_ecdsa_sign_test", srcs = [ "p256_ecdsa_sign_test.s", ], exp = "p256_ecdsa_sign_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", - "//sw/otbn/crypto:p256_sign", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_sign", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_ecdsa_verify_test", srcs = [ "p256_ecdsa_verify_test.s", ], exp = "p256_ecdsa_verify_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", - "//sw/otbn/crypto:p256_verify", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_verify", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_isoncurve_test", srcs = [ "p256_isoncurve_test.s", ], exp = "p256_isoncurve_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_isoncurve_proj_test", srcs = [ "p256_isoncurve_proj_test.s", ], exp = "p256_isoncurve_proj_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", - "//sw/otbn/crypto:p256_isoncurve_proj", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_isoncurve_proj", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_proj_add_test", srcs = [ "p256_proj_add_test.s", ], exp = "p256_proj_add_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_proj_double_test", srcs = [ "p256_proj_double_test.s", ], exp = "p256_proj_double_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_scalar_mult_test", srcs = [ "p256_scalar_mult_test.s", ], exp = "p256_scalar_mult_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_ecdh_shared_key_test", srcs = [ "p256_ecdh_shared_key_test.s", ], exp = "p256_ecdh_shared_key_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", - "//sw/otbn/crypto:p256_isoncurve_proj", - "//sw/otbn/crypto:p256_shared_key", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_isoncurve_proj", + "//sw/acc/crypto:p256_shared_key", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_arithmetic_to_boolean_test", srcs = [ "p256_arithmetic_to_boolean_test.s", ], exp = "p256_arithmetic_to_boolean_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", - "//sw/otbn/crypto:p256_isoncurve_proj", - "//sw/otbn/crypto:p256_shared_key", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_isoncurve_proj", + "//sw/acc/crypto:p256_shared_key", ], ) -otbn_sim_test( +acc_sim_test( name = "p256_arithmetic_to_boolean_mod_test", srcs = [ "p256_arithmetic_to_boolean_mod_test.s", ], exp = "p256_arithmetic_to_boolean_mod_test.exp", deps = [ - "//sw/otbn/crypto:p256_base", - "//sw/otbn/crypto:p256_isoncurve", - "//sw/otbn/crypto:p256_isoncurve_proj", - "//sw/otbn/crypto:p256_shared_key", + "//sw/acc/crypto:p256_base", + "//sw/acc/crypto:p256_isoncurve", + "//sw/acc/crypto:p256_isoncurve_proj", + "//sw/acc/crypto:p256_shared_key", ], ) -otbn_sim_test_suite( +acc_sim_test_suite( name = "p256_test", - binary = "//sw/otbn/crypto:run_p256", + binary = "//sw/acc/crypto:run_p256", tests = [ "p256_check_public_key_not_on_curve.hjson", "p256_check_public_key_valid.hjson", @@ -565,225 +565,225 @@ otbn_sim_test_suite( ], ) -otbn_sim_test( +acc_sim_test( name = "p384_scalar_remask_test", srcs = [ "p384_scalar_remask_test.s", ], exp = "p384_scalar_remask_test.exp", deps = [ - "//sw/otbn/crypto:p384_base", + "//sw/acc/crypto:p384_base", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_base_mult_test", srcs = [ "p384_base_mult_test.s", ], testcase = "p384_base_mult_test.hjson", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_base_mult", - "//sw/otbn/crypto:p384_internal_mult", - "//sw/otbn/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_base_mult", + "//sw/acc/crypto:p384_internal_mult", + "//sw/acc/crypto:p384_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_base_mult_checked_test", srcs = [ "p384_base_mult_checked_test.s", ], exp = "p384_base_mult_checked_test.exp", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_base_mult", - "//sw/otbn/crypto:p384_internal_mult", - "//sw/otbn/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_base_mult", + "//sw/acc/crypto:p384_internal_mult", + "//sw/acc/crypto:p384_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_boolean_to_arithmetic_test", srcs = [ "p384_boolean_to_arithmetic_test.s", ], exp = "p384_boolean_to_arithmetic_test.exp", deps = [ - "//sw/otbn/crypto:p384_b2a", + "//sw/acc/crypto:p384_b2a", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_arithmetic_to_boolean_test", srcs = [ "p384_arithmetic_to_boolean_test.s", ], exp = "p384_arithmetic_to_boolean_test.exp", deps = [ - "//sw/otbn/crypto:p384_a2b", - "//sw/otbn/crypto:p384_base", + "//sw/acc/crypto:p384_a2b", + "//sw/acc/crypto:p384_base", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_arithmetic_to_boolean_mod_test", srcs = [ "p384_arithmetic_to_boolean_mod_test.s", ], exp = "p384_arithmetic_to_boolean_mod_test.exp", deps = [ - "//sw/otbn/crypto:p384_a2b", - "//sw/otbn/crypto:p384_base", + "//sw/acc/crypto:p384_a2b", + "//sw/acc/crypto:p384_base", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_ecdh_shared_key_test", srcs = [ "p384_ecdh_shared_key_test.s", ], exp = "p384_ecdh_shared_key_test.exp", deps = [ - "//sw/otbn/crypto:p384_a2b", - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_internal_mult", - "//sw/otbn/crypto:p384_isoncurve", - "//sw/otbn/crypto:p384_isoncurve_proj", - "//sw/otbn/crypto:p384_scalar_mult", + "//sw/acc/crypto:p384_a2b", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_internal_mult", + "//sw/acc/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_isoncurve_proj", + "//sw/acc/crypto:p384_scalar_mult", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_ecdsa_sign_test", srcs = [ "p384_ecdsa_sign_test.s", ], testcase = "p384_ecdsa_sign_test.hjson", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_internal_mult", - "//sw/otbn/crypto:p384_isoncurve", - "//sw/otbn/crypto:p384_modinv", - "//sw/otbn/crypto:p384_sign", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_internal_mult", + "//sw/acc/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_modinv", + "//sw/acc/crypto:p384_sign", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_ecdsa_verify_test", srcs = [ "p384_ecdsa_verify_test.s", ], testcase = "p384_ecdsa_verify_test.hjson", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_isoncurve", - "//sw/otbn/crypto:p384_modinv", - "//sw/otbn/crypto:p384_verify", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_modinv", + "//sw/acc/crypto:p384_verify", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_isoncurve_test", srcs = [ "p384_isoncurve_test.s", ], testcase = "p384_isoncurve_test.hjson", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_isoncurve_proj_test", srcs = [ "p384_isoncurve_proj_test.s", ], testcase = "p384_isoncurve_proj_test.hjson", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_isoncurve", - "//sw/otbn/crypto:p384_isoncurve_proj", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_isoncurve_proj", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_curve_point_valid_test", srcs = [ "p384_curve_point_valid_test.s", ], testcase = "p384_curve_point_valid_test.hjson", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_isoncurve", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_keygen_test", srcs = [ "p384_keygen_test.s", ], exp = "p384_keygen_test.exp", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_keygen", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_keygen_from_seed_test", srcs = [ "p384_keygen_from_seed_test.s", ], exp = "p384_keygen_from_seed_test.exp", deps = [ - "//sw/otbn/crypto:p384_b2a", - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_keygen_from_seed", + "//sw/acc/crypto:p384_b2a", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_keygen_from_seed", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_proj_add_test", srcs = [ "p384_proj_add_test.s", ], exp = "p384_proj_add_test.exp", deps = [ - "//sw/otbn/crypto:p384_base", + "//sw/acc/crypto:p384_base", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_scalar_mult_test", srcs = [ "p384_scalar_mult_test.s", ], exp = "p384_scalar_mult_test.exp", deps = [ - "//sw/otbn/crypto:p384_base", - "//sw/otbn/crypto:p384_internal_mult", - "//sw/otbn/crypto:p384_isoncurve", - "//sw/otbn/crypto:p384_isoncurve_proj", - "//sw/otbn/crypto:p384_scalar_mult", + "//sw/acc/crypto:p384_base", + "//sw/acc/crypto:p384_internal_mult", + "//sw/acc/crypto:p384_isoncurve", + "//sw/acc/crypto:p384_isoncurve_proj", + "//sw/acc/crypto:p384_scalar_mult", ], ) -otbn_sim_test( +acc_sim_test( name = "p384_mulmod448x128_test", srcs = [ "p384_mulmod448x128_test.s", ], exp = "p384_mulmod448x128_test.exp", deps = [ - "//sw/otbn/crypto:p384_base", + "//sw/acc/crypto:p384_base", ], ) -otbn_consttime_test( +acc_consttime_test( name = "p384_base_mult_consttime", subroutine = "p384_base_mult", deps = [ @@ -791,7 +791,7 @@ otbn_consttime_test( ], ) -otbn_consttime_test( +acc_consttime_test( name = "p384_scalar_mult_consttime", ignore = [ "trigger_fault_if_fg0_not_z", @@ -802,7 +802,7 @@ otbn_consttime_test( ], ) -otbn_consttime_test( +acc_consttime_test( name = "p384_mulmod_p_consttime", subroutine = "p384_mulmod_p", deps = [ @@ -810,7 +810,7 @@ otbn_consttime_test( ], ) -otbn_consttime_test( +acc_consttime_test( name = "p384_mulmod_n_consttime", subroutine = "p384_mulmod_n", deps = [ @@ -824,7 +824,7 @@ otbn_consttime_test( # mark DMEM non-secret, and the constant-time checker doesn't currently have # the ability to track different DMEM regions separately. # -# otbn_consttime_test( +# acc_consttime_test( # name = "p384_sign_consttime", # deps = [ # ":p384_ecdsa_sign_test" @@ -832,7 +832,7 @@ otbn_consttime_test( # subroutine = "p384_sign", # ) -otbn_consttime_test( +acc_consttime_test( name = "proj_add_p384_consttime", initial_constants = [ "x22:10", @@ -846,14 +846,14 @@ otbn_consttime_test( ], ) -otbn_library( +acc_library( name = "fake_primality", srcs = [ "fake_primality.s", ], ) -otbn_sim_test( +acc_sim_test( name = "primality_test", timeout = "long", srcs = [ @@ -861,12 +861,12 @@ otbn_sim_test( ], exp = "primality_test.exp", deps = [ - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:primality", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:primality", ], ) -otbn_sim_test( +acc_sim_test( name = "primality_test_witness_test", timeout = "long", srcs = [ @@ -874,12 +874,12 @@ otbn_sim_test( ], exp = "primality_test_witness_test.exp", deps = [ - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:primality", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:primality", ], ) -otbn_sim_test( +acc_sim_test( name = "primality_test_witness_negative_test", timeout = "long", srcs = [ @@ -887,12 +887,12 @@ otbn_sim_test( ], exp = "primality_test_witness_negative_test.exp", deps = [ - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:primality", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:primality", ], ) -otbn_sim_test( +acc_sim_test( name = "primality_negative_test", timeout = "long", srcs = [ @@ -901,13 +901,13 @@ otbn_sim_test( exp = "primality_negative_test.exp", tags = ["nightly"], # slow, do not run in CI deps = [ - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:primality", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:primality", ], ) # Miller-Rabin with 1024-bit primes (as in RSA-2048). -otbn_consttime_test( +acc_consttime_test( name = "miller_rabin_consttime_1024", # 4 limbs, x30 = n and x31 = n -1 initial_constants = [ @@ -924,7 +924,7 @@ otbn_consttime_test( ) # Miller-Rabin with 1536-bit primes (as in RSA-3072). -otbn_consttime_test( +acc_consttime_test( name = "miller_rabin_consttime_1536", # 6 limbs, x30 = n and x31 = n -1 initial_constants = [ @@ -941,7 +941,7 @@ otbn_consttime_test( ) # Miller-Rabin with 2048-bit primes (as in RSA-4096). -otbn_consttime_test( +acc_consttime_test( name = "miller_rabin_consttime_2048", # 8 limbs, x30 = n and x31 = n -1 initial_constants = [ @@ -957,43 +957,43 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "modinv_f4_test", srcs = [ "modinv_f4_test.s", ], exp = "modinv_f4_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "modinv_test", srcs = [ "modinv_test.s", ], exp = "modinv_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_consttime_test( +acc_consttime_test( name = "modinv_f4_consttime_test", initial_constants = [ "x20:20", @@ -1008,25 +1008,25 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_f4_test", srcs = [ "relprime_f4_test.s", ], exp = "relprime_f4_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_consttime_test( +acc_consttime_test( name = "relprime_f4_consttime_test", # All secrets are stored in DMEM; timing is permitted to depend on the # number of limbs. @@ -1037,140 +1037,140 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_small_primes_multiple_of_3_test", srcs = [ "relprime_small_primes_multiple_of_3_test.s", ], exp = "relprime_small_primes_multiple_of_3_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_small_primes_multiple_of_5_test", srcs = [ "relprime_small_primes_multiple_of_5_test.s", ], exp = "relprime_small_primes_multiple_of_5_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_small_primes_multiple_of_7_test", srcs = [ "relprime_small_primes_multiple_of_7_test.s", ], exp = "relprime_small_primes_multiple_of_7_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_small_primes_multiple_of_11_test", srcs = [ "relprime_small_primes_multiple_of_11_test.s", ], exp = "relprime_small_primes_multiple_of_11_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_small_primes_multiple_of_17_test", srcs = [ "relprime_small_primes_multiple_of_17_test.s", ], exp = "relprime_small_primes_multiple_of_17_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_small_primes_multiple_of_31_test", srcs = [ "relprime_small_primes_multiple_of_31_test.s", ], exp = "relprime_small_primes_multiple_of_31_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "relprime_small_primes_negative_test", srcs = [ "relprime_small_primes_negative_test.s", ], exp = "relprime_small_primes_negative_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_library( +acc_library( name = "rsa_keygen_checkpq_test_data", srcs = [ "rsa_keygen_checkpq_test_data.s", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_keygen_checkp_good_test", timeout = "long", # runs a primality test srcs = [ @@ -1180,18 +1180,18 @@ otbn_sim_test( tags = ["nightly"], # slow, do not run in CI deps = [ ":rsa_keygen_checkpq_test_data", - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_keygen_checkp_not_relprime_test", srcs = [ "rsa_keygen_checkp_not_relprime_test.s", @@ -1200,17 +1200,17 @@ otbn_sim_test( deps = [ ":fake_primality", ":rsa_keygen_checkpq_test_data", - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_keygen_checkp_not_prime_test", timeout = "long", # runs a primality test srcs = [ @@ -1219,18 +1219,18 @@ otbn_sim_test( exp = "rsa_keygen_checkp_not_prime_test.exp", deps = [ ":rsa_keygen_checkpq_test_data", - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_keygen_checkq_good_test", timeout = "long", # runs a primality test srcs = [ @@ -1240,18 +1240,18 @@ otbn_sim_test( tags = ["nightly"], # slow, do not run in CI deps = [ ":rsa_keygen_checkpq_test_data", - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_keygen_checkq_not_prime_test", timeout = "long", # runs a primality test srcs = [ @@ -1260,18 +1260,18 @@ otbn_sim_test( exp = "rsa_keygen_checkq_not_prime_test.exp", deps = [ ":rsa_keygen_checkpq_test_data", - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_keygen_checkq_not_relprime_test", srcs = [ "rsa_keygen_checkq_not_relprime_test.s", @@ -1280,17 +1280,17 @@ otbn_sim_test( deps = [ ":fake_primality", ":rsa_keygen_checkpq_test_data", - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_keygen_checkq_too_close_test", srcs = [ "rsa_keygen_checkq_too_close_test.s", @@ -1299,17 +1299,17 @@ otbn_sim_test( deps = [ ":fake_primality", ":rsa_keygen_checkpq_test_data", - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_check_key_recover_d_from_crt_test", timeout = "long", srcs = [ @@ -1317,18 +1317,18 @@ otbn_sim_test( ], dexp = "rsa_check_key_recover_d_from_crt_test.dexp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:gcd", - "//sw/otbn/crypto:lcm", - "//sw/otbn/crypto:modinv", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", - "//sw/otbn/crypto:primality", - "//sw/otbn/crypto:rsa_keygen", + "//sw/acc/crypto:div", + "//sw/acc/crypto:gcd", + "//sw/acc/crypto:lcm", + "//sw/acc/crypto:modinv", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", + "//sw/acc/crypto:primality", + "//sw/acc/crypto:rsa_keygen", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_1024_dec_test", timeout = "long", srcs = [ @@ -1336,14 +1336,14 @@ otbn_sim_test( ], exp = "rsa_1024_dec_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_1024_dec_crt_test", timeout = "long", srcs = [ @@ -1351,28 +1351,28 @@ otbn_sim_test( ], exp = "rsa_1024_dec_crt_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_1024_enc_test", srcs = [ "rsa_1024_enc_test.s", ], exp = "rsa_1024_enc_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_2048_dec_test", timeout = "eternal", srcs = [ @@ -1381,14 +1381,14 @@ otbn_sim_test( exp = "rsa_2048_dec_test.exp", tags = ["nightly"], # slow, do not run in CI deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_2048_dec_crt_test", timeout = "eternal", srcs = [ @@ -1396,28 +1396,28 @@ otbn_sim_test( ], exp = "rsa_2048_dec_crt_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_2048_enc_test", srcs = [ "rsa_2048_enc_test.s", ], exp = "rsa_2048_enc_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_3072_dec_test", timeout = "eternal", srcs = [ @@ -1426,14 +1426,14 @@ otbn_sim_test( exp = "rsa_3072_dec_test.exp", tags = ["nightly"], # slow, do not run in CI deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_3072_dec_crt_test", timeout = "eternal", srcs = [ @@ -1442,42 +1442,42 @@ otbn_sim_test( exp = "rsa_3072_dec_crt_test.exp", tags = ["nightly"], # slow, do not run in CI deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_3072_enc_test", srcs = [ "rsa_3072_enc_test.s", ], exp = "rsa_3072_enc_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_4096_enc_test", srcs = [ "rsa_4096_enc_test.s", ], exp = "rsa_4096_enc_test.exp", deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_4096_dec_test", timeout = "eternal", srcs = [ @@ -1486,14 +1486,14 @@ otbn_sim_test( exp = "rsa_4096_dec_test.exp", tags = ["nightly"], # slow, do not run in CI deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "rsa_4096_dec_crt_test", timeout = "eternal", srcs = [ @@ -1502,25 +1502,25 @@ otbn_sim_test( exp = "rsa_4096_dec_crt_test.exp", tags = ["nightly"], # slow, do not run in CI deps = [ - "//sw/otbn/crypto:div", - "//sw/otbn/crypto:modexp", - "//sw/otbn/crypto:montmul", - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:div", + "//sw/acc/crypto:modexp", + "//sw/acc/crypto:montmul", + "//sw/acc/crypto:mul", ], ) -otbn_sim_test( +acc_sim_test( name = "sha256_test", srcs = [ "sha256_test.s", ], exp = "sha256_test.exp", deps = [ - "//sw/otbn/crypto:sha256", + "//sw/acc/crypto:sha256", ], ) -otbn_consttime_test( +acc_consttime_test( name = "sha256_consttime", # All secrets are stored in DMEM; timing is permitted to depend on the # number of message chunks. @@ -1531,99 +1531,99 @@ otbn_consttime_test( ], ) -otbn_sim_test( +acc_sim_test( name = "sha512_test", srcs = [ "sha512_test.s", ], exp = "sha512_test.exp", deps = [ - "//sw/otbn/crypto:sha512", + "//sw/acc/crypto:sha512", ], ) -otbn_sim_test( +acc_sim_test( name = "sha512_compact_test", srcs = [ "sha512_compact_test.s", ], exp = "sha512_compact_test.exp", deps = [ - "//sw/otbn/crypto:sha512_compact", + "//sw/acc/crypto:sha512_compact", ], ) -otbn_sim_test( +acc_sim_test( name = "sha512_padding_test", srcs = [ "sha512_padding_test.s", ], exp = "sha512_padding_test.exp", deps = [ - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_sim_test( +acc_sim_test( name = "sha512_interface_test", srcs = [ "sha512_interface_test.s", ], exp = "sha512_interface_test.exp", deps = [ - "//sw/otbn/crypto:sha512_compact", - "//sw/otbn/crypto:sha512_interface", - "//sw/otbn/crypto:sha512_padding", + "//sw/acc/crypto:sha512_compact", + "//sw/acc/crypto:sha512_interface", + "//sw/acc/crypto:sha512_padding", ], ) -otbn_sim_test( +acc_sim_test( name = "sha384_test", srcs = [ "sha384_test.s", ], exp = "sha384_test.exp", deps = [ - "//sw/otbn/crypto:sha512", + "//sw/acc/crypto:sha512", ], ) -otbn_sim_test( +acc_sim_test( name = "sha3_shake_test", srcs = [ "sha3_shake_test.s", ], exp = "sha3_shake_test.exp", deps = [ - "//sw/otbn/crypto:sha3_shake", + "//sw/acc/crypto:sha3_shake", ], ) -otbn_sim_test( +acc_sim_test( name = "x25519_test1", srcs = [ "x25519_test1.s", ], exp = "x25519_test1.exp", deps = [ - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:x25519", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:x25519", ], ) -otbn_sim_test( +acc_sim_test( name = "x25519_test2", srcs = [ "x25519_test2.s", ], exp = "x25519_test2.exp", deps = [ - "//sw/otbn/crypto:field25519", - "//sw/otbn/crypto:x25519", + "//sw/acc/crypto:field25519", + "//sw/acc/crypto:x25519", ], ) -otbn_consttime_test( +acc_consttime_test( name = "x25519_consttime", subroutine = "X25519", deps = [ @@ -1631,9 +1631,9 @@ otbn_consttime_test( ], ) -otbn_sim_test_suite( +acc_sim_test_suite( name = "boot_test", - binary = "//sw/otbn/crypto:boot", + binary = "//sw/acc/crypto:boot", tests = [ "boot_key_endorse_valid.hjson", "boot_key_save_valid.hjson", diff --git a/sw/otbn/crypto/tests/boot_key_endorse_valid.hjson b/sw/acc/crypto/tests/boot_key_endorse_valid.hjson similarity index 100% rename from sw/otbn/crypto/tests/boot_key_endorse_valid.hjson rename to sw/acc/crypto/tests/boot_key_endorse_valid.hjson diff --git a/sw/otbn/crypto/tests/boot_key_save_valid.hjson b/sw/acc/crypto/tests/boot_key_save_valid.hjson similarity index 100% rename from sw/otbn/crypto/tests/boot_key_save_valid.hjson rename to sw/acc/crypto/tests/boot_key_save_valid.hjson diff --git a/sw/otbn/crypto/tests/boot_keygen_valid.hjson b/sw/acc/crypto/tests/boot_keygen_valid.hjson similarity index 100% rename from sw/otbn/crypto/tests/boot_keygen_valid.hjson rename to sw/acc/crypto/tests/boot_keygen_valid.hjson diff --git a/sw/otbn/crypto/tests/boot_mode_invalid.hjson b/sw/acc/crypto/tests/boot_mode_invalid.hjson similarity index 100% rename from sw/otbn/crypto/tests/boot_mode_invalid.hjson rename to sw/acc/crypto/tests/boot_mode_invalid.hjson diff --git a/sw/otbn/crypto/tests/boot_sigverify_valid.hjson b/sw/acc/crypto/tests/boot_sigverify_valid.hjson similarity index 100% rename from sw/otbn/crypto/tests/boot_sigverify_valid.hjson rename to sw/acc/crypto/tests/boot_sigverify_valid.hjson diff --git a/sw/otbn/crypto/tests/div_large_test.exp b/sw/acc/crypto/tests/div_large_test.exp similarity index 100% rename from sw/otbn/crypto/tests/div_large_test.exp rename to sw/acc/crypto/tests/div_large_test.exp diff --git a/sw/otbn/crypto/tests/div_large_test.s b/sw/acc/crypto/tests/div_large_test.s similarity index 99% rename from sw/otbn/crypto/tests/div_large_test.s rename to sw/acc/crypto/tests/div_large_test.s index 86d233dea0f..228c486b6c8 100644 --- a/sw/otbn/crypto/tests/div_large_test.s +++ b/sw/acc/crypto/tests/div_large_test.s @@ -3,7 +3,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ /** - * Standalone test for OTBN bignum division. + * Standalone test for ACC bignum division. */ .section .text.start diff --git a/sw/otbn/crypto/tests/div_medium_test.exp b/sw/acc/crypto/tests/div_medium_test.exp similarity index 100% rename from sw/otbn/crypto/tests/div_medium_test.exp rename to sw/acc/crypto/tests/div_medium_test.exp diff --git a/sw/otbn/crypto/tests/div_medium_test.s b/sw/acc/crypto/tests/div_medium_test.s similarity index 97% rename from sw/otbn/crypto/tests/div_medium_test.s rename to sw/acc/crypto/tests/div_medium_test.s index 3a31da0f531..78fb55aa378 100644 --- a/sw/otbn/crypto/tests/div_medium_test.s +++ b/sw/acc/crypto/tests/div_medium_test.s @@ -3,7 +3,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ /** - * Standalone test for OTBN bignum division. + * Standalone test for ACC bignum division. */ .section .text.start diff --git a/sw/otbn/crypto/tests/div_small_test.exp b/sw/acc/crypto/tests/div_small_test.exp similarity index 100% rename from sw/otbn/crypto/tests/div_small_test.exp rename to sw/acc/crypto/tests/div_small_test.exp diff --git a/sw/otbn/crypto/tests/div_small_test.s b/sw/acc/crypto/tests/div_small_test.s similarity index 96% rename from sw/otbn/crypto/tests/div_small_test.s rename to sw/acc/crypto/tests/div_small_test.s index 97a55a4fa4e..26e13fc99d8 100644 --- a/sw/otbn/crypto/tests/div_small_test.s +++ b/sw/acc/crypto/tests/div_small_test.s @@ -3,7 +3,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ /** - * Standalone test for OTBN bignum division. + * Standalone test for ACC bignum division. */ .section .text.start diff --git a/sw/otbn/crypto/tests/ed25519_encode_decode_test.exp b/sw/acc/crypto/tests/ed25519_encode_decode_test.exp similarity index 100% rename from sw/otbn/crypto/tests/ed25519_encode_decode_test.exp rename to sw/acc/crypto/tests/ed25519_encode_decode_test.exp diff --git a/sw/otbn/crypto/tests/ed25519_encode_decode_test.s b/sw/acc/crypto/tests/ed25519_encode_decode_test.s similarity index 100% rename from sw/otbn/crypto/tests/ed25519_encode_decode_test.s rename to sw/acc/crypto/tests/ed25519_encode_decode_test.s diff --git a/sw/otbn/crypto/tests/ed25519_ext_add_test.exp b/sw/acc/crypto/tests/ed25519_ext_add_test.exp similarity index 100% rename from sw/otbn/crypto/tests/ed25519_ext_add_test.exp rename to sw/acc/crypto/tests/ed25519_ext_add_test.exp diff --git a/sw/otbn/crypto/tests/ed25519_ext_add_test.s b/sw/acc/crypto/tests/ed25519_ext_add_test.s similarity index 100% rename from sw/otbn/crypto/tests/ed25519_ext_add_test.s rename to sw/acc/crypto/tests/ed25519_ext_add_test.s diff --git a/sw/otbn/crypto/tests/ed25519_ext_scmul_test.exp b/sw/acc/crypto/tests/ed25519_ext_scmul_test.exp similarity index 100% rename from sw/otbn/crypto/tests/ed25519_ext_scmul_test.exp rename to sw/acc/crypto/tests/ed25519_ext_scmul_test.exp diff --git a/sw/otbn/crypto/tests/ed25519_ext_scmul_test.s b/sw/acc/crypto/tests/ed25519_ext_scmul_test.s similarity index 100% rename from sw/otbn/crypto/tests/ed25519_ext_scmul_test.s rename to sw/acc/crypto/tests/ed25519_ext_scmul_test.s diff --git a/sw/otbn/crypto/tests/ed25519_scalar_test.exp b/sw/acc/crypto/tests/ed25519_scalar_test.exp similarity index 100% rename from sw/otbn/crypto/tests/ed25519_scalar_test.exp rename to sw/acc/crypto/tests/ed25519_scalar_test.exp diff --git a/sw/otbn/crypto/tests/ed25519_scalar_test.s b/sw/acc/crypto/tests/ed25519_scalar_test.s similarity index 100% rename from sw/otbn/crypto/tests/ed25519_scalar_test.s rename to sw/acc/crypto/tests/ed25519_scalar_test.s diff --git a/sw/otbn/crypto/tests/ed25519_sign_prehashed_test.dexp b/sw/acc/crypto/tests/ed25519_sign_prehashed_test.dexp similarity index 100% rename from sw/otbn/crypto/tests/ed25519_sign_prehashed_test.dexp rename to sw/acc/crypto/tests/ed25519_sign_prehashed_test.dexp diff --git a/sw/otbn/crypto/tests/ed25519_sign_prehashed_test.s b/sw/acc/crypto/tests/ed25519_sign_prehashed_test.s similarity index 100% rename from sw/otbn/crypto/tests/ed25519_sign_prehashed_test.s rename to sw/acc/crypto/tests/ed25519_sign_prehashed_test.s diff --git a/sw/otbn/crypto/tests/ed25519_verify_test.exp b/sw/acc/crypto/tests/ed25519_verify_test.exp similarity index 100% rename from sw/otbn/crypto/tests/ed25519_verify_test.exp rename to sw/acc/crypto/tests/ed25519_verify_test.exp diff --git a/sw/otbn/crypto/tests/ed25519_verify_test.s b/sw/acc/crypto/tests/ed25519_verify_test.s similarity index 100% rename from sw/otbn/crypto/tests/ed25519_verify_test.s rename to sw/acc/crypto/tests/ed25519_verify_test.s diff --git a/sw/otbn/crypto/tests/ed25519_verify_test2.exp b/sw/acc/crypto/tests/ed25519_verify_test2.exp similarity index 100% rename from sw/otbn/crypto/tests/ed25519_verify_test2.exp rename to sw/acc/crypto/tests/ed25519_verify_test2.exp diff --git a/sw/otbn/crypto/tests/ed25519_verify_test2.s b/sw/acc/crypto/tests/ed25519_verify_test2.s similarity index 100% rename from sw/otbn/crypto/tests/ed25519_verify_test2.s rename to sw/acc/crypto/tests/ed25519_verify_test2.s diff --git a/sw/otbn/crypto/tests/fake_primality.s b/sw/acc/crypto/tests/fake_primality.s similarity index 100% rename from sw/otbn/crypto/tests/fake_primality.s rename to sw/acc/crypto/tests/fake_primality.s diff --git a/sw/otbn/crypto/tests/field25519_test.exp b/sw/acc/crypto/tests/field25519_test.exp similarity index 100% rename from sw/otbn/crypto/tests/field25519_test.exp rename to sw/acc/crypto/tests/field25519_test.exp diff --git a/sw/otbn/crypto/tests/field25519_test.s b/sw/acc/crypto/tests/field25519_test.s similarity index 100% rename from sw/otbn/crypto/tests/field25519_test.s rename to sw/acc/crypto/tests/field25519_test.s diff --git a/sw/otbn/crypto/tests/gcd_large_test.exp b/sw/acc/crypto/tests/gcd_large_test.exp similarity index 100% rename from sw/otbn/crypto/tests/gcd_large_test.exp rename to sw/acc/crypto/tests/gcd_large_test.exp diff --git a/sw/otbn/crypto/tests/gcd_large_test.s b/sw/acc/crypto/tests/gcd_large_test.s similarity index 100% rename from sw/otbn/crypto/tests/gcd_large_test.s rename to sw/acc/crypto/tests/gcd_large_test.s diff --git a/sw/otbn/crypto/tests/gcd_small_test.exp b/sw/acc/crypto/tests/gcd_small_test.exp similarity index 100% rename from sw/otbn/crypto/tests/gcd_small_test.exp rename to sw/acc/crypto/tests/gcd_small_test.exp diff --git a/sw/otbn/crypto/tests/gcd_small_test.s b/sw/acc/crypto/tests/gcd_small_test.s similarity index 100% rename from sw/otbn/crypto/tests/gcd_small_test.s rename to sw/acc/crypto/tests/gcd_small_test.s diff --git a/sw/otbn/crypto/tests/generated/BUILD b/sw/acc/crypto/tests/generated/BUILD similarity index 76% rename from sw/otbn/crypto/tests/generated/BUILD rename to sw/acc/crypto/tests/generated/BUILD index 62e4bcd7894..3a46a6009f4 100644 --- a/sw/otbn/crypto/tests/generated/BUILD +++ b/sw/acc/crypto/tests/generated/BUILD @@ -4,7 +4,7 @@ load("@ot_python_deps//:requirements.bzl", "requirement") load("@rules_python//python:defs.bzl", "py_binary") -load("//rules:otbn.bzl", "otbn_autogen_sim_test") +load("//rules:acc.bzl", "acc_autogen_sim_test") package(default_visibility = ["//visibility:public"]) @@ -12,10 +12,10 @@ py_binary( name = "mul_testgen", srcs = ["mul_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", ], ) @@ -23,13 +23,13 @@ py_binary( # for the same seed every time, because Bazel always builds "hermetically" and # therefore cannot generate any actually random values at build time. [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = "mul_test" + str(i), srcs = ["mul_test.s"], seed = i, testgen = ":mul_testgen", deps = [ - "//sw/otbn/crypto:mul", + "//sw/acc/crypto:mul", ], ) for i in range(10) @@ -40,22 +40,22 @@ py_binary( name = "sha3_testgen", srcs = ["sha3_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("pycryptodome"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = "sha3_test" + str(i), srcs = ["sha3_py_test.s"], seed = i, testgen = ":sha3_testgen", deps = [ - "//sw/otbn/crypto:sha3_shake", + "//sw/acc/crypto:sha3_shake", ], ) for i in range(10) @@ -66,22 +66,22 @@ py_binary( name = "shake_testgen", srcs = ["shake_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("pycryptodome"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = "shake_test" + str(i), srcs = ["shake_py_test.s"], seed = i, testgen = ":shake_testgen", deps = [ - "//sw/otbn/crypto:sha3_shake", + "//sw/acc/crypto:sha3_shake", ], ) for i in range(10) diff --git a/sw/otbn/crypto/tests/generated/mul_test.s b/sw/acc/crypto/tests/generated/mul_test.s similarity index 100% rename from sw/otbn/crypto/tests/generated/mul_test.s rename to sw/acc/crypto/tests/generated/mul_test.s diff --git a/sw/otbn/crypto/tests/generated/mul_testgen.py b/sw/acc/crypto/tests/generated/mul_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/generated/mul_testgen.py rename to sw/acc/crypto/tests/generated/mul_testgen.py diff --git a/sw/otbn/crypto/tests/generated/sha3_py_test.s b/sw/acc/crypto/tests/generated/sha3_py_test.s similarity index 100% rename from sw/otbn/crypto/tests/generated/sha3_py_test.s rename to sw/acc/crypto/tests/generated/sha3_py_test.s diff --git a/sw/otbn/crypto/tests/generated/sha3_testgen.py b/sw/acc/crypto/tests/generated/sha3_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/generated/sha3_testgen.py rename to sw/acc/crypto/tests/generated/sha3_testgen.py diff --git a/sw/otbn/crypto/tests/generated/shake_py_test.s b/sw/acc/crypto/tests/generated/shake_py_test.s similarity index 100% rename from sw/otbn/crypto/tests/generated/shake_py_test.s rename to sw/acc/crypto/tests/generated/shake_py_test.s diff --git a/sw/otbn/crypto/tests/generated/shake_testgen.py b/sw/acc/crypto/tests/generated/shake_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/generated/shake_testgen.py rename to sw/acc/crypto/tests/generated/shake_testgen.py diff --git a/sw/otbn/crypto/tests/lcm_test.exp b/sw/acc/crypto/tests/lcm_test.exp similarity index 100% rename from sw/otbn/crypto/tests/lcm_test.exp rename to sw/acc/crypto/tests/lcm_test.exp diff --git a/sw/otbn/crypto/tests/lcm_test.s b/sw/acc/crypto/tests/lcm_test.s similarity index 100% rename from sw/otbn/crypto/tests/lcm_test.s rename to sw/acc/crypto/tests/lcm_test.s diff --git a/sw/otbn/crypto/tests/mldsa/BUILD b/sw/acc/crypto/tests/mldsa/BUILD similarity index 59% rename from sw/otbn/crypto/tests/mldsa/BUILD rename to sw/acc/crypto/tests/mldsa/BUILD index e1632418616..b79bcc7684f 100644 --- a/sw/otbn/crypto/tests/mldsa/BUILD +++ b/sw/acc/crypto/tests/mldsa/BUILD @@ -5,13 +5,13 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028) # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. load("@ot_python_deps//:requirements.bzl", "requirement") load("@rules_python//python:defs.bzl", "py_binary") -load("//rules:otbn.bzl", "otbn_autogen_sim_test", "otbn_binary", "otbn_consttime_test", "otbn_library", "otbn_sim_test") +load("//rules:acc.bzl", "acc_autogen_sim_test", "acc_binary", "acc_consttime_test", "acc_library", "acc_sim_test") package(default_visibility = ["//visibility:public"]) @@ -36,16 +36,16 @@ py_binary( name = "mldsa_keypair_testgen", srcs = ["mldsa_keypair_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("dilithium-py"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = params + "_keypair_test" + str(i), srcs = ["mldsa_keypair_test.s"], copts = [ @@ -57,15 +57,15 @@ py_binary( testgen = ":mldsa_keypair_testgen", testgen_args = [params], deps = [ - "//sw/otbn/crypto/mldsa:intt", - "//sw/otbn/crypto/mldsa:kmac_send_msg", - "//sw/otbn/crypto/mldsa:" + params + "_consts", - "//sw/otbn/crypto/mldsa:" + params + "_keypair", - "//sw/otbn/crypto/mldsa:" + params + "_poly", - "//sw/otbn/crypto/mldsa:" + params + "_rounding", - "//sw/otbn/crypto/mldsa:ntt", - "//sw/otbn/crypto/mldsa:poly_add", - "//sw/otbn/crypto/mldsa:poly_pointwise", + "//sw/acc/crypto/mldsa:intt", + "//sw/acc/crypto/mldsa:kmac_send_msg", + "//sw/acc/crypto/mldsa:" + params + "_consts", + "//sw/acc/crypto/mldsa:" + params + "_keypair", + "//sw/acc/crypto/mldsa:" + params + "_poly", + "//sw/acc/crypto/mldsa:" + params + "_rounding", + "//sw/acc/crypto/mldsa:ntt", + "//sw/acc/crypto/mldsa:poly_add", + "//sw/acc/crypto/mldsa:poly_pointwise", ], ) for i in range(NTESTS) @@ -77,16 +77,16 @@ py_binary( name = "mldsa_sign_testgen", srcs = ["mldsa_sign_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("dilithium-py"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = params + "_sign_test" + str(i), timeout = "long", srcs = ["mldsa_sign_test.s"], @@ -99,16 +99,16 @@ py_binary( testgen = ":mldsa_sign_testgen", testgen_args = [params], deps = [ - "//sw/otbn/crypto/mldsa:intt", - "//sw/otbn/crypto/mldsa:kmac_send_msg", - "//sw/otbn/crypto/mldsa:" + params + "_consts", - "//sw/otbn/crypto/mldsa:" + params + "_poly", - "//sw/otbn/crypto/mldsa:" + params + "_rounding", - "//sw/otbn/crypto/mldsa:" + params + "_sign", - "//sw/otbn/crypto/mldsa:ntt", - "//sw/otbn/crypto/mldsa:poly_add", - "//sw/otbn/crypto/mldsa:poly_pointwise", - "//sw/otbn/crypto/mldsa:poly_sub", + "//sw/acc/crypto/mldsa:intt", + "//sw/acc/crypto/mldsa:kmac_send_msg", + "//sw/acc/crypto/mldsa:" + params + "_consts", + "//sw/acc/crypto/mldsa:" + params + "_poly", + "//sw/acc/crypto/mldsa:" + params + "_rounding", + "//sw/acc/crypto/mldsa:" + params + "_sign", + "//sw/acc/crypto/mldsa:ntt", + "//sw/acc/crypto/mldsa:poly_add", + "//sw/acc/crypto/mldsa:poly_pointwise", + "//sw/acc/crypto/mldsa:poly_sub", ], ) for i in range(NTESTS) @@ -120,16 +120,16 @@ py_binary( name = "mldsa_verify_testgen", srcs = ["mldsa_verify_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("dilithium-py"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = params + "_verify_test" + str(i), srcs = ["mldsa_verify_test.s"], copts = [ @@ -141,16 +141,16 @@ py_binary( testgen = ":mldsa_verify_testgen", testgen_args = [params], deps = [ - "//sw/otbn/crypto/mldsa:intt", - "//sw/otbn/crypto/mldsa:kmac_send_msg", - "//sw/otbn/crypto/mldsa:" + params + "_consts", - "//sw/otbn/crypto/mldsa:" + params + "_poly", - "//sw/otbn/crypto/mldsa:" + params + "_rounding", - "//sw/otbn/crypto/mldsa:" + params + "_verify", - "//sw/otbn/crypto/mldsa:ntt", - "//sw/otbn/crypto/mldsa:poly_add", - "//sw/otbn/crypto/mldsa:poly_pointwise", - "//sw/otbn/crypto/mldsa:poly_sub", + "//sw/acc/crypto/mldsa:intt", + "//sw/acc/crypto/mldsa:kmac_send_msg", + "//sw/acc/crypto/mldsa:" + params + "_consts", + "//sw/acc/crypto/mldsa:" + params + "_poly", + "//sw/acc/crypto/mldsa:" + params + "_rounding", + "//sw/acc/crypto/mldsa:" + params + "_verify", + "//sw/acc/crypto/mldsa:ntt", + "//sw/acc/crypto/mldsa:poly_add", + "//sw/acc/crypto/mldsa:poly_pointwise", + "//sw/acc/crypto/mldsa:poly_sub", ], ) for i in range(NTESTS) @@ -158,7 +158,7 @@ py_binary( ] [ - otbn_sim_test( + acc_sim_test( name = params + "_poly_make_hint_test", srcs = [ "poly_make_hint_test.s", @@ -169,16 +169,16 @@ py_binary( dexp = "poly_make_hint_test.dexp", pqc = True, deps = [ - "//sw/otbn/crypto/mldsa:kmac_send_msg", - "//sw/otbn/crypto/mldsa:" + params + "_consts", - "//sw/otbn/crypto/mldsa:" + params + "_poly", - "//sw/otbn/crypto/mldsa:" + params + "_rounding", + "//sw/acc/crypto/mldsa:kmac_send_msg", + "//sw/acc/crypto/mldsa:" + params + "_consts", + "//sw/acc/crypto/mldsa:" + params + "_poly", + "//sw/acc/crypto/mldsa:" + params + "_rounding", ], ) for params in MLDSA_PARAMS ] -otbn_sim_test( +acc_sim_test( name = "poly_uniform_test", srcs = [ "poly_uniform_test.s", @@ -191,14 +191,14 @@ otbn_sim_test( dexp = "poly_uniform_test.dexp", pqc = True, deps = [ - "//sw/otbn/crypto/mldsa:kmac_send_msg", - "//sw/otbn/crypto/mldsa:mldsa44_consts", - "//sw/otbn/crypto/mldsa:mldsa44_poly", - "//sw/otbn/crypto/mldsa:mldsa44_rounding", + "//sw/acc/crypto/mldsa:kmac_send_msg", + "//sw/acc/crypto/mldsa:mldsa44_consts", + "//sw/acc/crypto/mldsa:mldsa44_poly", + "//sw/acc/crypto/mldsa:mldsa44_rounding", ], ) -otbn_sim_test( +acc_sim_test( name = "poly_uniform_postprocess_test", srcs = [ "poly_uniform_postprocess_test.s", @@ -211,9 +211,9 @@ otbn_sim_test( dexp = "poly_uniform_postprocess_test.dexp", pqc = True, deps = [ - "//sw/otbn/crypto/mldsa:kmac_send_msg", - "//sw/otbn/crypto/mldsa:mldsa44_consts", - "//sw/otbn/crypto/mldsa:mldsa44_poly", - "//sw/otbn/crypto/mldsa:mldsa44_rounding", + "//sw/acc/crypto/mldsa:kmac_send_msg", + "//sw/acc/crypto/mldsa:mldsa44_consts", + "//sw/acc/crypto/mldsa:mldsa44_poly", + "//sw/acc/crypto/mldsa:mldsa44_rounding", ], ) diff --git a/sw/otbn/crypto/tests/mldsa/mldsa_keypair_test.s b/sw/acc/crypto/tests/mldsa/mldsa_keypair_test.s similarity index 98% rename from sw/otbn/crypto/tests/mldsa/mldsa_keypair_test.s rename to sw/acc/crypto/tests/mldsa/mldsa_keypair_test.s index 3cfbb053b57..d6444556394 100644 --- a/sw/otbn/crypto/tests/mldsa/mldsa_keypair_test.s +++ b/sw/acc/crypto/tests/mldsa/mldsa_keypair_test.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/tests/mldsa/mldsa_keypair_testgen.py b/sw/acc/crypto/tests/mldsa/mldsa_keypair_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/mldsa/mldsa_keypair_testgen.py rename to sw/acc/crypto/tests/mldsa/mldsa_keypair_testgen.py diff --git a/sw/otbn/crypto/tests/mldsa/mldsa_sign_test.s b/sw/acc/crypto/tests/mldsa/mldsa_sign_test.s similarity index 98% rename from sw/otbn/crypto/tests/mldsa/mldsa_sign_test.s rename to sw/acc/crypto/tests/mldsa/mldsa_sign_test.s index 0ad3255022d..5d484d5f732 100644 --- a/sw/otbn/crypto/tests/mldsa/mldsa_sign_test.s +++ b/sw/acc/crypto/tests/mldsa/mldsa_sign_test.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/tests/mldsa/mldsa_sign_testgen.py b/sw/acc/crypto/tests/mldsa/mldsa_sign_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/mldsa/mldsa_sign_testgen.py rename to sw/acc/crypto/tests/mldsa/mldsa_sign_testgen.py diff --git a/sw/otbn/crypto/tests/mldsa/mldsa_verify_test.s b/sw/acc/crypto/tests/mldsa/mldsa_verify_test.s similarity index 98% rename from sw/otbn/crypto/tests/mldsa/mldsa_verify_test.s rename to sw/acc/crypto/tests/mldsa/mldsa_verify_test.s index 0e29d7cd533..c018553d4b3 100644 --- a/sw/otbn/crypto/tests/mldsa/mldsa_verify_test.s +++ b/sw/acc/crypto/tests/mldsa/mldsa_verify_test.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/tests/mldsa/mldsa_verify_testgen.py b/sw/acc/crypto/tests/mldsa/mldsa_verify_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/mldsa/mldsa_verify_testgen.py rename to sw/acc/crypto/tests/mldsa/mldsa_verify_testgen.py diff --git a/sw/otbn/crypto/tests/mldsa/poly_make_hint_test.dexp b/sw/acc/crypto/tests/mldsa/poly_make_hint_test.dexp similarity index 100% rename from sw/otbn/crypto/tests/mldsa/poly_make_hint_test.dexp rename to sw/acc/crypto/tests/mldsa/poly_make_hint_test.dexp diff --git a/sw/otbn/crypto/tests/mldsa/poly_make_hint_test.s b/sw/acc/crypto/tests/mldsa/poly_make_hint_test.s similarity index 100% rename from sw/otbn/crypto/tests/mldsa/poly_make_hint_test.s rename to sw/acc/crypto/tests/mldsa/poly_make_hint_test.s diff --git a/sw/otbn/crypto/tests/mldsa/poly_uniform_postprocess_test.dexp b/sw/acc/crypto/tests/mldsa/poly_uniform_postprocess_test.dexp similarity index 100% rename from sw/otbn/crypto/tests/mldsa/poly_uniform_postprocess_test.dexp rename to sw/acc/crypto/tests/mldsa/poly_uniform_postprocess_test.dexp diff --git a/sw/otbn/crypto/tests/mldsa/poly_uniform_postprocess_test.s b/sw/acc/crypto/tests/mldsa/poly_uniform_postprocess_test.s similarity index 100% rename from sw/otbn/crypto/tests/mldsa/poly_uniform_postprocess_test.s rename to sw/acc/crypto/tests/mldsa/poly_uniform_postprocess_test.s diff --git a/sw/otbn/crypto/tests/mldsa/poly_uniform_test.dexp b/sw/acc/crypto/tests/mldsa/poly_uniform_test.dexp similarity index 100% rename from sw/otbn/crypto/tests/mldsa/poly_uniform_test.dexp rename to sw/acc/crypto/tests/mldsa/poly_uniform_test.dexp diff --git a/sw/otbn/crypto/tests/mldsa/poly_uniform_test.s b/sw/acc/crypto/tests/mldsa/poly_uniform_test.s similarity index 100% rename from sw/otbn/crypto/tests/mldsa/poly_uniform_test.s rename to sw/acc/crypto/tests/mldsa/poly_uniform_test.s diff --git a/sw/otbn/crypto/tests/mlkem/BUILD b/sw/acc/crypto/tests/mlkem/BUILD similarity index 51% rename from sw/otbn/crypto/tests/mlkem/BUILD rename to sw/acc/crypto/tests/mlkem/BUILD index 9ab72623110..54867abe246 100644 --- a/sw/otbn/crypto/tests/mlkem/BUILD +++ b/sw/acc/crypto/tests/mlkem/BUILD @@ -2,14 +2,14 @@ # Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). # Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. # Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of -# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" +# "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" # (https://eprint.iacr.org/2025/2028). # Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 load("@ot_python_deps//:requirements.bzl", "requirement") -load("//rules:otbn.bzl", "otbn_autogen_sim_test", "otbn_binary", "otbn_consttime_test", "otbn_library", "otbn_sim_test") +load("//rules:acc.bzl", "acc_autogen_sim_test", "acc_binary", "acc_consttime_test", "acc_library", "acc_sim_test") package(default_visibility = ["//visibility:public"]) @@ -28,16 +28,16 @@ py_binary( name = "mlkem_keypair_testgen", srcs = ["mlkem_keypair_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("kyber-py"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = params + "_keypair_test" + str(i), srcs = ["mlkem_keypair_test.s"], copts = [ @@ -49,15 +49,15 @@ py_binary( testgen = ":mlkem_keypair_testgen", testgen_args = [params], deps = [ - "//sw/otbn/crypto/mlkem:basemul", - "//sw/otbn/crypto/mlkem:cbd", - "//sw/otbn/crypto/mlkem:kmac_send_msg", - "//sw/otbn/crypto/mlkem:" + params + "_consts", - "//sw/otbn/crypto/mlkem:" + params + "_keypair", - "//sw/otbn/crypto/mlkem:" + params + "_pack_keys", - "//sw/otbn/crypto/mlkem:" + params + "_poly", - "//sw/otbn/crypto/mlkem:ntt", - "//sw/otbn/crypto/mlkem:poly_gen_matrix", + "//sw/acc/crypto/mlkem:basemul", + "//sw/acc/crypto/mlkem:cbd", + "//sw/acc/crypto/mlkem:kmac_send_msg", + "//sw/acc/crypto/mlkem:" + params + "_consts", + "//sw/acc/crypto/mlkem:" + params + "_keypair", + "//sw/acc/crypto/mlkem:" + params + "_pack_keys", + "//sw/acc/crypto/mlkem:" + params + "_poly", + "//sw/acc/crypto/mlkem:ntt", + "//sw/acc/crypto/mlkem:poly_gen_matrix", ], ) for i in range(NTESTS) @@ -69,16 +69,16 @@ py_binary( name = "mlkem_encap_testgen", srcs = ["mlkem_encap_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("kyber-py"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = params + "_encap_test" + str(i), srcs = ["mlkem_encap_test.s"], copts = [ @@ -90,17 +90,17 @@ py_binary( testgen = ":mlkem_encap_testgen", testgen_args = [params], deps = [ - "//sw/otbn/crypto/mlkem:basemul", - "//sw/otbn/crypto/mlkem:cbd", - "//sw/otbn/crypto/mlkem:intt", - "//sw/otbn/crypto/mlkem:kmac_send_msg", - "//sw/otbn/crypto/mlkem:" + params + "_consts", - "//sw/otbn/crypto/mlkem:" + params + "_encap", - "//sw/otbn/crypto/mlkem:" + params + "_pack_ciphertext", - "//sw/otbn/crypto/mlkem:" + params + "_pack_keys", - "//sw/otbn/crypto/mlkem:" + params + "_poly", - "//sw/otbn/crypto/mlkem:ntt", - "//sw/otbn/crypto/mlkem:poly_gen_matrix", + "//sw/acc/crypto/mlkem:basemul", + "//sw/acc/crypto/mlkem:cbd", + "//sw/acc/crypto/mlkem:intt", + "//sw/acc/crypto/mlkem:kmac_send_msg", + "//sw/acc/crypto/mlkem:" + params + "_consts", + "//sw/acc/crypto/mlkem:" + params + "_encap", + "//sw/acc/crypto/mlkem:" + params + "_pack_ciphertext", + "//sw/acc/crypto/mlkem:" + params + "_pack_keys", + "//sw/acc/crypto/mlkem:" + params + "_poly", + "//sw/acc/crypto/mlkem:ntt", + "//sw/acc/crypto/mlkem:poly_gen_matrix", ], ) for i in range(NTESTS) @@ -112,16 +112,16 @@ py_binary( name = "mlkem_decap_testgen", srcs = ["mlkem_decap_testgen.py"], imports = [ - "../../../../../hw/ip/otbn/util", + "../../../../../hw/ip/acc/util", ], deps = [ - "//hw/ip/otbn/util/shared:testgen", + "//hw/ip/acc/util/shared:testgen", requirement("kyber-py"), ], ) [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = params + "_decap_test" + str(i), srcs = ["mlkem_decap_test.s"], copts = [ @@ -133,18 +133,18 @@ py_binary( testgen = ":mlkem_decap_testgen", testgen_args = [params], deps = [ - "//sw/otbn/crypto/mlkem:basemul", - "//sw/otbn/crypto/mlkem:cbd", - "//sw/otbn/crypto/mlkem:intt", - "//sw/otbn/crypto/mlkem:kmac_send_msg", - "//sw/otbn/crypto/mlkem:" + params + "_consts", - "//sw/otbn/crypto/mlkem:" + params + "_decap", - "//sw/otbn/crypto/mlkem:" + params + "_encap", - "//sw/otbn/crypto/mlkem:" + params + "_pack_ciphertext", - "//sw/otbn/crypto/mlkem:" + params + "_pack_keys", - "//sw/otbn/crypto/mlkem:" + params + "_poly", - "//sw/otbn/crypto/mlkem:ntt", - "//sw/otbn/crypto/mlkem:poly_gen_matrix", + "//sw/acc/crypto/mlkem:basemul", + "//sw/acc/crypto/mlkem:cbd", + "//sw/acc/crypto/mlkem:intt", + "//sw/acc/crypto/mlkem:kmac_send_msg", + "//sw/acc/crypto/mlkem:" + params + "_consts", + "//sw/acc/crypto/mlkem:" + params + "_decap", + "//sw/acc/crypto/mlkem:" + params + "_encap", + "//sw/acc/crypto/mlkem:" + params + "_pack_ciphertext", + "//sw/acc/crypto/mlkem:" + params + "_pack_keys", + "//sw/acc/crypto/mlkem:" + params + "_poly", + "//sw/acc/crypto/mlkem:ntt", + "//sw/acc/crypto/mlkem:poly_gen_matrix", ], ) for i in range(NTESTS) @@ -152,7 +152,7 @@ py_binary( ] [ - otbn_autogen_sim_test( + acc_autogen_sim_test( name = params + "_false_decap_test" + str(i), srcs = ["mlkem_decap_test.s"], copts = [ @@ -167,18 +167,18 @@ py_binary( params, ], deps = [ - "//sw/otbn/crypto/mlkem:basemul", - "//sw/otbn/crypto/mlkem:cbd", - "//sw/otbn/crypto/mlkem:intt", - "//sw/otbn/crypto/mlkem:kmac_send_msg", - "//sw/otbn/crypto/mlkem:" + params + "_consts", - "//sw/otbn/crypto/mlkem:" + params + "_decap", - "//sw/otbn/crypto/mlkem:" + params + "_encap", - "//sw/otbn/crypto/mlkem:" + params + "_pack_ciphertext", - "//sw/otbn/crypto/mlkem:" + params + "_pack_keys", - "//sw/otbn/crypto/mlkem:" + params + "_poly", - "//sw/otbn/crypto/mlkem:ntt", - "//sw/otbn/crypto/mlkem:poly_gen_matrix", + "//sw/acc/crypto/mlkem:basemul", + "//sw/acc/crypto/mlkem:cbd", + "//sw/acc/crypto/mlkem:intt", + "//sw/acc/crypto/mlkem:kmac_send_msg", + "//sw/acc/crypto/mlkem:" + params + "_consts", + "//sw/acc/crypto/mlkem:" + params + "_decap", + "//sw/acc/crypto/mlkem:" + params + "_encap", + "//sw/acc/crypto/mlkem:" + params + "_pack_ciphertext", + "//sw/acc/crypto/mlkem:" + params + "_pack_keys", + "//sw/acc/crypto/mlkem:" + params + "_poly", + "//sw/acc/crypto/mlkem:ntt", + "//sw/acc/crypto/mlkem:poly_gen_matrix", ], ) for i in range(NTESTS) diff --git a/sw/otbn/crypto/tests/mlkem/mlkem_decap_test.s b/sw/acc/crypto/tests/mlkem/mlkem_decap_test.s similarity index 98% rename from sw/otbn/crypto/tests/mlkem/mlkem_decap_test.s rename to sw/acc/crypto/tests/mlkem/mlkem_decap_test.s index c4ce4720ec1..da85e9b030c 100644 --- a/sw/otbn/crypto/tests/mlkem/mlkem_decap_test.s +++ b/sw/acc/crypto/tests/mlkem/mlkem_decap_test.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/tests/mlkem/mlkem_decap_testgen.py b/sw/acc/crypto/tests/mlkem/mlkem_decap_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/mlkem/mlkem_decap_testgen.py rename to sw/acc/crypto/tests/mlkem/mlkem_decap_testgen.py diff --git a/sw/otbn/crypto/tests/mlkem/mlkem_encap_test.s b/sw/acc/crypto/tests/mlkem/mlkem_encap_test.s similarity index 98% rename from sw/otbn/crypto/tests/mlkem/mlkem_encap_test.s rename to sw/acc/crypto/tests/mlkem/mlkem_encap_test.s index af785f59a62..6e2bcaaa31d 100644 --- a/sw/otbn/crypto/tests/mlkem/mlkem_encap_test.s +++ b/sw/acc/crypto/tests/mlkem/mlkem_encap_test.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/tests/mlkem/mlkem_encap_testgen.py b/sw/acc/crypto/tests/mlkem/mlkem_encap_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/mlkem/mlkem_encap_testgen.py rename to sw/acc/crypto/tests/mlkem/mlkem_encap_testgen.py diff --git a/sw/otbn/crypto/tests/mlkem/mlkem_false_decap_test.s b/sw/acc/crypto/tests/mlkem/mlkem_false_decap_test.s similarity index 99% rename from sw/otbn/crypto/tests/mlkem/mlkem_false_decap_test.s rename to sw/acc/crypto/tests/mlkem/mlkem_false_decap_test.s index feb8573f0b8..5dbfc7c1d8a 100644 --- a/sw/otbn/crypto/tests/mlkem/mlkem_false_decap_test.s +++ b/sw/acc/crypto/tests/mlkem/mlkem_false_decap_test.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/tests/mlkem/mlkem_keypair_test.s b/sw/acc/crypto/tests/mlkem/mlkem_keypair_test.s similarity index 98% rename from sw/otbn/crypto/tests/mlkem/mlkem_keypair_test.s rename to sw/acc/crypto/tests/mlkem/mlkem_keypair_test.s index e095bdd199a..1b4cc3c519d 100644 --- a/sw/otbn/crypto/tests/mlkem/mlkem_keypair_test.s +++ b/sw/acc/crypto/tests/mlkem/mlkem_keypair_test.s @@ -2,7 +2,7 @@ /* Modified by Authors of "Towards ML-KEM & ML-DSA on OpenTitan" (https://eprint.iacr.org/2024/1192). */ /* Copyright "Towards ML-KEM & ML-DSA on OpenTitan" Authors. */ /* Modified by Ruben Niederhagen and Hoang Nguyen Hien Pham - authors of */ -/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for OTBN" */ +/* "Improving ML-KEM & ML-DSA on OpenTitan - Efficient Multiplication Vector Instructions for ACC" */ /* (https://eprint.iacr.org/2025/2028). */ /* Copyright Ruben Niederhagen and Hoang Nguyen Hien Pham. */ /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ diff --git a/sw/otbn/crypto/tests/mlkem/mlkem_keypair_testgen.py b/sw/acc/crypto/tests/mlkem/mlkem_keypair_testgen.py similarity index 100% rename from sw/otbn/crypto/tests/mlkem/mlkem_keypair_testgen.py rename to sw/acc/crypto/tests/mlkem/mlkem_keypair_testgen.py diff --git a/sw/otbn/crypto/tests/mod_test.exp b/sw/acc/crypto/tests/mod_test.exp similarity index 100% rename from sw/otbn/crypto/tests/mod_test.exp rename to sw/acc/crypto/tests/mod_test.exp diff --git a/sw/otbn/crypto/tests/mod_test.s b/sw/acc/crypto/tests/mod_test.s similarity index 99% rename from sw/otbn/crypto/tests/mod_test.s rename to sw/acc/crypto/tests/mod_test.s index 445fd23b4c5..684138c0eb7 100644 --- a/sw/otbn/crypto/tests/mod_test.s +++ b/sw/acc/crypto/tests/mod_test.s @@ -3,7 +3,7 @@ /* SPDX-License-Identifier: Apache-2.0 */ /** - * Standalone test for OTBN bignum division. + * Standalone test for ACC bignum division. */ .section .text.start diff --git a/sw/otbn/crypto/tests/modinv_f4_test.exp b/sw/acc/crypto/tests/modinv_f4_test.exp similarity index 100% rename from sw/otbn/crypto/tests/modinv_f4_test.exp rename to sw/acc/crypto/tests/modinv_f4_test.exp diff --git a/sw/otbn/crypto/tests/modinv_f4_test.s b/sw/acc/crypto/tests/modinv_f4_test.s similarity index 100% rename from sw/otbn/crypto/tests/modinv_f4_test.s rename to sw/acc/crypto/tests/modinv_f4_test.s diff --git a/sw/otbn/crypto/tests/modinv_test.exp b/sw/acc/crypto/tests/modinv_test.exp similarity index 100% rename from sw/otbn/crypto/tests/modinv_test.exp rename to sw/acc/crypto/tests/modinv_test.exp diff --git a/sw/otbn/crypto/tests/modinv_test.s b/sw/acc/crypto/tests/modinv_test.s similarity index 100% rename from sw/otbn/crypto/tests/modinv_test.s rename to sw/acc/crypto/tests/modinv_test.s diff --git a/sw/otbn/crypto/tests/mul256_test.dexp b/sw/acc/crypto/tests/mul256_test.dexp similarity index 100% rename from sw/otbn/crypto/tests/mul256_test.dexp rename to sw/acc/crypto/tests/mul256_test.dexp diff --git a/sw/otbn/crypto/tests/mul256_test.s b/sw/acc/crypto/tests/mul256_test.s similarity index 100% rename from sw/otbn/crypto/tests/mul256_test.s rename to sw/acc/crypto/tests/mul256_test.s diff --git a/sw/otbn/crypto/tests/mul_test.dexp b/sw/acc/crypto/tests/mul_test.dexp similarity index 100% rename from sw/otbn/crypto/tests/mul_test.dexp rename to sw/acc/crypto/tests/mul_test.dexp diff --git a/sw/otbn/crypto/tests/mul_test.s b/sw/acc/crypto/tests/mul_test.s similarity index 100% rename from sw/otbn/crypto/tests/mul_test.s rename to sw/acc/crypto/tests/mul_test.s diff --git a/sw/otbn/crypto/tests/p256_arithmetic_to_boolean_mod_test.exp b/sw/acc/crypto/tests/p256_arithmetic_to_boolean_mod_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_arithmetic_to_boolean_mod_test.exp rename to sw/acc/crypto/tests/p256_arithmetic_to_boolean_mod_test.exp diff --git a/sw/otbn/crypto/tests/p256_arithmetic_to_boolean_mod_test.s b/sw/acc/crypto/tests/p256_arithmetic_to_boolean_mod_test.s similarity index 95% rename from sw/otbn/crypto/tests/p256_arithmetic_to_boolean_mod_test.s rename to sw/acc/crypto/tests/p256_arithmetic_to_boolean_mod_test.s index 82f37fe1afc..b498474ae41 100644 --- a/sw/otbn/crypto/tests/p256_arithmetic_to_boolean_mod_test.s +++ b/sw/acc/crypto/tests/p256_arithmetic_to_boolean_mod_test.s @@ -5,7 +5,7 @@ /** * Standalone elliptic curve P-256 arithmetic-to-boolean masking test * - * Uses OTBN ECC P-256 lib to perform arithmetic-to-boolean conversion of + * Uses ACC ECC P-256 lib to perform arithmetic-to-boolean conversion of * a given masked curve value with a random mask. Afterwards it unmasks the * result and compares it with the initial value from DMEM. */ diff --git a/sw/otbn/crypto/tests/p256_arithmetic_to_boolean_test.exp b/sw/acc/crypto/tests/p256_arithmetic_to_boolean_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_arithmetic_to_boolean_test.exp rename to sw/acc/crypto/tests/p256_arithmetic_to_boolean_test.exp diff --git a/sw/otbn/crypto/tests/p256_arithmetic_to_boolean_test.s b/sw/acc/crypto/tests/p256_arithmetic_to_boolean_test.s similarity index 96% rename from sw/otbn/crypto/tests/p256_arithmetic_to_boolean_test.s rename to sw/acc/crypto/tests/p256_arithmetic_to_boolean_test.s index dc224f414cb..188711734df 100644 --- a/sw/otbn/crypto/tests/p256_arithmetic_to_boolean_test.s +++ b/sw/acc/crypto/tests/p256_arithmetic_to_boolean_test.s @@ -5,7 +5,7 @@ /** * Standalone 257-bit arithmetic-to-boolean masking test * - * Uses OTBN ECC P-256 lib to perform arithmetic-to-boolean conversion of + * Uses ACC ECC P-256 lib to perform arithmetic-to-boolean conversion of * a given masked 257-bit value with a random mask. Afterwards it unmasks the * result and compares it with the initial value from DMEM. */ diff --git a/sw/otbn/crypto/tests/p256_base_mult_test.exp b/sw/acc/crypto/tests/p256_base_mult_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_base_mult_test.exp rename to sw/acc/crypto/tests/p256_base_mult_test.exp diff --git a/sw/otbn/crypto/tests/p256_base_mult_test.s b/sw/acc/crypto/tests/p256_base_mult_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_base_mult_test.s rename to sw/acc/crypto/tests/p256_base_mult_test.s diff --git a/sw/otbn/crypto/tests/p256_check_public_key_not_on_curve.hjson b/sw/acc/crypto/tests/p256_check_public_key_not_on_curve.hjson similarity index 100% rename from sw/otbn/crypto/tests/p256_check_public_key_not_on_curve.hjson rename to sw/acc/crypto/tests/p256_check_public_key_not_on_curve.hjson diff --git a/sw/otbn/crypto/tests/p256_check_public_key_valid.hjson b/sw/acc/crypto/tests/p256_check_public_key_valid.hjson similarity index 100% rename from sw/otbn/crypto/tests/p256_check_public_key_valid.hjson rename to sw/acc/crypto/tests/p256_check_public_key_valid.hjson diff --git a/sw/otbn/crypto/tests/p256_check_public_key_x_too_large.hjson b/sw/acc/crypto/tests/p256_check_public_key_x_too_large.hjson similarity index 100% rename from sw/otbn/crypto/tests/p256_check_public_key_x_too_large.hjson rename to sw/acc/crypto/tests/p256_check_public_key_x_too_large.hjson diff --git a/sw/otbn/crypto/tests/p256_check_public_key_y_too_large.hjson b/sw/acc/crypto/tests/p256_check_public_key_y_too_large.hjson similarity index 100% rename from sw/otbn/crypto/tests/p256_check_public_key_y_too_large.hjson rename to sw/acc/crypto/tests/p256_check_public_key_y_too_large.hjson diff --git a/sw/otbn/crypto/tests/p256_ecdh_shared_key_test.exp b/sw/acc/crypto/tests/p256_ecdh_shared_key_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_ecdh_shared_key_test.exp rename to sw/acc/crypto/tests/p256_ecdh_shared_key_test.exp diff --git a/sw/otbn/crypto/tests/p256_ecdh_shared_key_test.s b/sw/acc/crypto/tests/p256_ecdh_shared_key_test.s similarity index 96% rename from sw/otbn/crypto/tests/p256_ecdh_shared_key_test.s rename to sw/acc/crypto/tests/p256_ecdh_shared_key_test.s index 71fee6c83ba..9ba45da5986 100644 --- a/sw/otbn/crypto/tests/p256_ecdh_shared_key_test.s +++ b/sw/acc/crypto/tests/p256_ecdh_shared_key_test.s @@ -5,7 +5,7 @@ /** * Standalone elliptic curve P-256 ECDH shared key generation test * - * Uses OTBN ECC P-256 lib to perform a scalar multiplication with a valid + * Uses ACC ECC P-256 lib to perform a scalar multiplication with a valid * example curve point and an example scalar. Both scalar and coordinates of * the curve point are contained in the .data section below. * The x coordinate of the resulting curve point is masked arithmetically diff --git a/sw/otbn/crypto/tests/p256_ecdsa_sign_test.exp b/sw/acc/crypto/tests/p256_ecdsa_sign_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_ecdsa_sign_test.exp rename to sw/acc/crypto/tests/p256_ecdsa_sign_test.exp diff --git a/sw/otbn/crypto/tests/p256_ecdsa_sign_test.s b/sw/acc/crypto/tests/p256_ecdsa_sign_test.s similarity index 96% rename from sw/otbn/crypto/tests/p256_ecdsa_sign_test.s rename to sw/acc/crypto/tests/p256_ecdsa_sign_test.s index baa80806e30..20fc10133fb 100644 --- a/sw/otbn/crypto/tests/p256_ecdsa_sign_test.s +++ b/sw/acc/crypto/tests/p256_ecdsa_sign_test.s @@ -5,10 +5,10 @@ /** * Standalone elliptic curve P-256 ECDSA sign test * - * Uses OTBN ECC P-256 lib to perform an ECDSA signing operation. + * Uses ACC ECC P-256 lib to perform an ECDSA signing operation. * An example message digest, the private signing key and a random value k are * provided in the .data section below. Note that this test does not yet use - * OTBN's entropy interface as a source for the random value in the ECDSA + * ACC's entropy interface as a source for the random value in the ECDSA * operation. * * Resulting R and S of the signature are copied to the wide registers. See diff --git a/sw/otbn/crypto/tests/p256_ecdsa_verify_test.exp b/sw/acc/crypto/tests/p256_ecdsa_verify_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_ecdsa_verify_test.exp rename to sw/acc/crypto/tests/p256_ecdsa_verify_test.exp diff --git a/sw/otbn/crypto/tests/p256_ecdsa_verify_test.s b/sw/acc/crypto/tests/p256_ecdsa_verify_test.s similarity index 96% rename from sw/otbn/crypto/tests/p256_ecdsa_verify_test.s rename to sw/acc/crypto/tests/p256_ecdsa_verify_test.s index 92e78adfd2d..a407ea9596a 100644 --- a/sw/otbn/crypto/tests/p256_ecdsa_verify_test.s +++ b/sw/acc/crypto/tests/p256_ecdsa_verify_test.s @@ -5,7 +5,7 @@ /** * Standalone elliptic curve P-256 ECDSA signature verification test * - * Uses OTBN ECC P-256 lib to perform an ECDSA signature verification. + * Uses ACC ECC P-256 lib to perform an ECDSA signature verification. * Coordinates of the public key, the message digest and R and S of the * signature are provided in the .data section below. * diff --git a/sw/otbn/crypto/tests/p256_isoncurve_proj_test.exp b/sw/acc/crypto/tests/p256_isoncurve_proj_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_isoncurve_proj_test.exp rename to sw/acc/crypto/tests/p256_isoncurve_proj_test.exp diff --git a/sw/otbn/crypto/tests/p256_isoncurve_proj_test.s b/sw/acc/crypto/tests/p256_isoncurve_proj_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_isoncurve_proj_test.s rename to sw/acc/crypto/tests/p256_isoncurve_proj_test.s diff --git a/sw/otbn/crypto/tests/p256_isoncurve_test.exp b/sw/acc/crypto/tests/p256_isoncurve_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_isoncurve_test.exp rename to sw/acc/crypto/tests/p256_isoncurve_test.exp diff --git a/sw/otbn/crypto/tests/p256_isoncurve_test.s b/sw/acc/crypto/tests/p256_isoncurve_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_isoncurve_test.s rename to sw/acc/crypto/tests/p256_isoncurve_test.s diff --git a/sw/otbn/crypto/tests/p256_isoncurve_valid.hjson b/sw/acc/crypto/tests/p256_isoncurve_valid.hjson similarity index 100% rename from sw/otbn/crypto/tests/p256_isoncurve_valid.hjson rename to sw/acc/crypto/tests/p256_isoncurve_valid.hjson diff --git a/sw/otbn/crypto/tests/p256_key_from_seed_test.exp b/sw/acc/crypto/tests/p256_key_from_seed_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_key_from_seed_test.exp rename to sw/acc/crypto/tests/p256_key_from_seed_test.exp diff --git a/sw/otbn/crypto/tests/p256_key_from_seed_test.s b/sw/acc/crypto/tests/p256_key_from_seed_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_key_from_seed_test.s rename to sw/acc/crypto/tests/p256_key_from_seed_test.s diff --git a/sw/otbn/crypto/tests/p256_keygen_valid.hjson b/sw/acc/crypto/tests/p256_keygen_valid.hjson similarity index 100% rename from sw/otbn/crypto/tests/p256_keygen_valid.hjson rename to sw/acc/crypto/tests/p256_keygen_valid.hjson diff --git a/sw/otbn/crypto/tests/p256_mul_modp_test.exp b/sw/acc/crypto/tests/p256_mul_modp_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_mul_modp_test.exp rename to sw/acc/crypto/tests/p256_mul_modp_test.exp diff --git a/sw/otbn/crypto/tests/p256_mul_modp_test.s b/sw/acc/crypto/tests/p256_mul_modp_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_mul_modp_test.s rename to sw/acc/crypto/tests/p256_mul_modp_test.s diff --git a/sw/otbn/crypto/tests/p256_proj_add_test.exp b/sw/acc/crypto/tests/p256_proj_add_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_proj_add_test.exp rename to sw/acc/crypto/tests/p256_proj_add_test.exp diff --git a/sw/otbn/crypto/tests/p256_proj_add_test.s b/sw/acc/crypto/tests/p256_proj_add_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_proj_add_test.s rename to sw/acc/crypto/tests/p256_proj_add_test.s diff --git a/sw/otbn/crypto/tests/p256_proj_double_test.exp b/sw/acc/crypto/tests/p256_proj_double_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_proj_double_test.exp rename to sw/acc/crypto/tests/p256_proj_double_test.exp diff --git a/sw/otbn/crypto/tests/p256_proj_double_test.s b/sw/acc/crypto/tests/p256_proj_double_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_proj_double_test.s rename to sw/acc/crypto/tests/p256_proj_double_test.s diff --git a/sw/otbn/crypto/tests/p256_scalar_mult_test.exp b/sw/acc/crypto/tests/p256_scalar_mult_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_scalar_mult_test.exp rename to sw/acc/crypto/tests/p256_scalar_mult_test.exp diff --git a/sw/otbn/crypto/tests/p256_scalar_mult_test.s b/sw/acc/crypto/tests/p256_scalar_mult_test.s similarity index 96% rename from sw/otbn/crypto/tests/p256_scalar_mult_test.s rename to sw/acc/crypto/tests/p256_scalar_mult_test.s index 7804331403f..f34eea736a6 100644 --- a/sw/otbn/crypto/tests/p256_scalar_mult_test.s +++ b/sw/acc/crypto/tests/p256_scalar_mult_test.s @@ -5,7 +5,7 @@ /** * Standalone elliptic curve P-256 scalar multiplication test * - * Uses OTBN ECC P-256 lib to perform a scalar multiplication with a valid + * Uses ACC ECC P-256 lib to perform a scalar multiplication with a valid * example curve point and an example scalar. Both scalar and coordinates of * the curve point are contained in the .data section below. * diff --git a/sw/otbn/crypto/tests/p256_scalar_remask_test.exp b/sw/acc/crypto/tests/p256_scalar_remask_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p256_scalar_remask_test.exp rename to sw/acc/crypto/tests/p256_scalar_remask_test.exp diff --git a/sw/otbn/crypto/tests/p256_scalar_remask_test.s b/sw/acc/crypto/tests/p256_scalar_remask_test.s similarity index 100% rename from sw/otbn/crypto/tests/p256_scalar_remask_test.s rename to sw/acc/crypto/tests/p256_scalar_remask_test.s diff --git a/sw/otbn/crypto/tests/p384_arithmetic_to_boolean_mod_test.exp b/sw/acc/crypto/tests/p384_arithmetic_to_boolean_mod_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_arithmetic_to_boolean_mod_test.exp rename to sw/acc/crypto/tests/p384_arithmetic_to_boolean_mod_test.exp diff --git a/sw/otbn/crypto/tests/p384_arithmetic_to_boolean_mod_test.s b/sw/acc/crypto/tests/p384_arithmetic_to_boolean_mod_test.s similarity index 97% rename from sw/otbn/crypto/tests/p384_arithmetic_to_boolean_mod_test.s rename to sw/acc/crypto/tests/p384_arithmetic_to_boolean_mod_test.s index 2c23e5cc547..9877eaf598a 100644 --- a/sw/otbn/crypto/tests/p384_arithmetic_to_boolean_mod_test.s +++ b/sw/acc/crypto/tests/p384_arithmetic_to_boolean_mod_test.s @@ -5,7 +5,7 @@ /** * Standalone elliptic curve P-384 arithmetic-to-boolean masking test * - * Uses OTBN ECC P-384 lib to perform arithmetic-to-boolean conversion of + * Uses ACC ECC P-384 lib to perform arithmetic-to-boolean conversion of * a given masked curve value with a random mask. Afterwards it unmasks the * result and compares it with the initial value from DMEM. */ diff --git a/sw/otbn/crypto/tests/p384_arithmetic_to_boolean_test.exp b/sw/acc/crypto/tests/p384_arithmetic_to_boolean_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_arithmetic_to_boolean_test.exp rename to sw/acc/crypto/tests/p384_arithmetic_to_boolean_test.exp diff --git a/sw/otbn/crypto/tests/p384_arithmetic_to_boolean_test.s b/sw/acc/crypto/tests/p384_arithmetic_to_boolean_test.s similarity index 96% rename from sw/otbn/crypto/tests/p384_arithmetic_to_boolean_test.s rename to sw/acc/crypto/tests/p384_arithmetic_to_boolean_test.s index 2af2cc3946a..fc278e4cc8a 100644 --- a/sw/otbn/crypto/tests/p384_arithmetic_to_boolean_test.s +++ b/sw/acc/crypto/tests/p384_arithmetic_to_boolean_test.s @@ -5,7 +5,7 @@ /** * Standalone 385-bit arithmetic-to-boolean masking test * - * Uses OTBN ECC P-384 lib to perform arithmetic-to-boolean conversion of + * Uses ACC ECC P-384 lib to perform arithmetic-to-boolean conversion of * a given masked 385-bit value with a random mask. Afterwards it unmasks the * result and compares it with the initial value from DMEM. */ diff --git a/sw/otbn/crypto/tests/p384_base_mult_checked_test.exp b/sw/acc/crypto/tests/p384_base_mult_checked_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_base_mult_checked_test.exp rename to sw/acc/crypto/tests/p384_base_mult_checked_test.exp diff --git a/sw/otbn/crypto/tests/p384_base_mult_checked_test.s b/sw/acc/crypto/tests/p384_base_mult_checked_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_base_mult_checked_test.s rename to sw/acc/crypto/tests/p384_base_mult_checked_test.s diff --git a/sw/otbn/crypto/tests/p384_base_mult_test.hjson b/sw/acc/crypto/tests/p384_base_mult_test.hjson similarity index 100% rename from sw/otbn/crypto/tests/p384_base_mult_test.hjson rename to sw/acc/crypto/tests/p384_base_mult_test.hjson diff --git a/sw/otbn/crypto/tests/p384_base_mult_test.s b/sw/acc/crypto/tests/p384_base_mult_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_base_mult_test.s rename to sw/acc/crypto/tests/p384_base_mult_test.s diff --git a/sw/otbn/crypto/tests/p384_boolean_to_arithmetic_test.exp b/sw/acc/crypto/tests/p384_boolean_to_arithmetic_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_boolean_to_arithmetic_test.exp rename to sw/acc/crypto/tests/p384_boolean_to_arithmetic_test.exp diff --git a/sw/otbn/crypto/tests/p384_boolean_to_arithmetic_test.s b/sw/acc/crypto/tests/p384_boolean_to_arithmetic_test.s similarity index 96% rename from sw/otbn/crypto/tests/p384_boolean_to_arithmetic_test.s rename to sw/acc/crypto/tests/p384_boolean_to_arithmetic_test.s index 6878ae8b1f2..e985b5306af 100644 --- a/sw/otbn/crypto/tests/p384_boolean_to_arithmetic_test.s +++ b/sw/acc/crypto/tests/p384_boolean_to_arithmetic_test.s @@ -5,7 +5,7 @@ /** * Standalone 384-bit boolean-to-arithmetic masking test * - * Uses OTBN ECC P-384 lib to perform arithmetic-to-boolean conversion of + * Uses ACC ECC P-384 lib to perform arithmetic-to-boolean conversion of * a given masked 384-bit value with a random mask. Afterwards it unmasks the * result and compares it with the initial value from DMEM. */ diff --git a/sw/otbn/crypto/tests/p384_curve_point_valid_test.exp b/sw/acc/crypto/tests/p384_curve_point_valid_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_curve_point_valid_test.exp rename to sw/acc/crypto/tests/p384_curve_point_valid_test.exp diff --git a/sw/otbn/crypto/tests/p384_curve_point_valid_test.hjson b/sw/acc/crypto/tests/p384_curve_point_valid_test.hjson similarity index 100% rename from sw/otbn/crypto/tests/p384_curve_point_valid_test.hjson rename to sw/acc/crypto/tests/p384_curve_point_valid_test.hjson diff --git a/sw/otbn/crypto/tests/p384_curve_point_valid_test.s b/sw/acc/crypto/tests/p384_curve_point_valid_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_curve_point_valid_test.s rename to sw/acc/crypto/tests/p384_curve_point_valid_test.s diff --git a/sw/otbn/crypto/tests/p384_ecdh_shared_key_test.exp b/sw/acc/crypto/tests/p384_ecdh_shared_key_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_ecdh_shared_key_test.exp rename to sw/acc/crypto/tests/p384_ecdh_shared_key_test.exp diff --git a/sw/otbn/crypto/tests/p384_ecdh_shared_key_test.s b/sw/acc/crypto/tests/p384_ecdh_shared_key_test.s similarity index 97% rename from sw/otbn/crypto/tests/p384_ecdh_shared_key_test.s rename to sw/acc/crypto/tests/p384_ecdh_shared_key_test.s index 02ca716d013..ade6db0dd02 100644 --- a/sw/otbn/crypto/tests/p384_ecdh_shared_key_test.s +++ b/sw/acc/crypto/tests/p384_ecdh_shared_key_test.s @@ -5,7 +5,7 @@ /** * Standalone elliptic curve P-384 ECDH shared key generation test * - * Uses OTBN ECC P-384 lib to perform a scalar multiplication with a valid + * Uses ACC ECC P-384 lib to perform a scalar multiplication with a valid * example curve point and an example scalar. Both scalar and coordinates of * the curve point are contained in the .data section below. * The x coordinate of the resulting curve point is masked arithmetically diff --git a/sw/otbn/crypto/tests/p384_ecdsa_sign_test.exp b/sw/acc/crypto/tests/p384_ecdsa_sign_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_ecdsa_sign_test.exp rename to sw/acc/crypto/tests/p384_ecdsa_sign_test.exp diff --git a/sw/otbn/crypto/tests/p384_ecdsa_sign_test.hjson b/sw/acc/crypto/tests/p384_ecdsa_sign_test.hjson similarity index 100% rename from sw/otbn/crypto/tests/p384_ecdsa_sign_test.hjson rename to sw/acc/crypto/tests/p384_ecdsa_sign_test.hjson diff --git a/sw/otbn/crypto/tests/p384_ecdsa_sign_test.s b/sw/acc/crypto/tests/p384_ecdsa_sign_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_ecdsa_sign_test.s rename to sw/acc/crypto/tests/p384_ecdsa_sign_test.s diff --git a/sw/otbn/crypto/tests/p384_ecdsa_verify_test.hjson b/sw/acc/crypto/tests/p384_ecdsa_verify_test.hjson similarity index 100% rename from sw/otbn/crypto/tests/p384_ecdsa_verify_test.hjson rename to sw/acc/crypto/tests/p384_ecdsa_verify_test.hjson diff --git a/sw/otbn/crypto/tests/p384_ecdsa_verify_test.s b/sw/acc/crypto/tests/p384_ecdsa_verify_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_ecdsa_verify_test.s rename to sw/acc/crypto/tests/p384_ecdsa_verify_test.s diff --git a/sw/otbn/crypto/tests/p384_isoncurve_proj_test.hjson b/sw/acc/crypto/tests/p384_isoncurve_proj_test.hjson similarity index 100% rename from sw/otbn/crypto/tests/p384_isoncurve_proj_test.hjson rename to sw/acc/crypto/tests/p384_isoncurve_proj_test.hjson diff --git a/sw/otbn/crypto/tests/p384_isoncurve_proj_test.s b/sw/acc/crypto/tests/p384_isoncurve_proj_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_isoncurve_proj_test.s rename to sw/acc/crypto/tests/p384_isoncurve_proj_test.s diff --git a/sw/otbn/crypto/tests/p384_isoncurve_test.hjson b/sw/acc/crypto/tests/p384_isoncurve_test.hjson similarity index 100% rename from sw/otbn/crypto/tests/p384_isoncurve_test.hjson rename to sw/acc/crypto/tests/p384_isoncurve_test.hjson diff --git a/sw/otbn/crypto/tests/p384_isoncurve_test.s b/sw/acc/crypto/tests/p384_isoncurve_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_isoncurve_test.s rename to sw/acc/crypto/tests/p384_isoncurve_test.s diff --git a/sw/otbn/crypto/tests/p384_keygen_from_seed_test.exp b/sw/acc/crypto/tests/p384_keygen_from_seed_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_keygen_from_seed_test.exp rename to sw/acc/crypto/tests/p384_keygen_from_seed_test.exp diff --git a/sw/otbn/crypto/tests/p384_keygen_from_seed_test.s b/sw/acc/crypto/tests/p384_keygen_from_seed_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_keygen_from_seed_test.s rename to sw/acc/crypto/tests/p384_keygen_from_seed_test.s diff --git a/sw/otbn/crypto/tests/p384_keygen_test.exp b/sw/acc/crypto/tests/p384_keygen_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_keygen_test.exp rename to sw/acc/crypto/tests/p384_keygen_test.exp diff --git a/sw/otbn/crypto/tests/p384_keygen_test.s b/sw/acc/crypto/tests/p384_keygen_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_keygen_test.s rename to sw/acc/crypto/tests/p384_keygen_test.s diff --git a/sw/otbn/crypto/tests/p384_mulmod448x128_test.exp b/sw/acc/crypto/tests/p384_mulmod448x128_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_mulmod448x128_test.exp rename to sw/acc/crypto/tests/p384_mulmod448x128_test.exp diff --git a/sw/otbn/crypto/tests/p384_mulmod448x128_test.s b/sw/acc/crypto/tests/p384_mulmod448x128_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_mulmod448x128_test.s rename to sw/acc/crypto/tests/p384_mulmod448x128_test.s diff --git a/sw/otbn/crypto/tests/p384_proj_add_test.exp b/sw/acc/crypto/tests/p384_proj_add_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_proj_add_test.exp rename to sw/acc/crypto/tests/p384_proj_add_test.exp diff --git a/sw/otbn/crypto/tests/p384_proj_add_test.s b/sw/acc/crypto/tests/p384_proj_add_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_proj_add_test.s rename to sw/acc/crypto/tests/p384_proj_add_test.s diff --git a/sw/otbn/crypto/tests/p384_scalar_mult_test.exp b/sw/acc/crypto/tests/p384_scalar_mult_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_scalar_mult_test.exp rename to sw/acc/crypto/tests/p384_scalar_mult_test.exp diff --git a/sw/otbn/crypto/tests/p384_scalar_mult_test.s b/sw/acc/crypto/tests/p384_scalar_mult_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_scalar_mult_test.s rename to sw/acc/crypto/tests/p384_scalar_mult_test.s diff --git a/sw/otbn/crypto/tests/p384_scalar_remask_test.exp b/sw/acc/crypto/tests/p384_scalar_remask_test.exp similarity index 100% rename from sw/otbn/crypto/tests/p384_scalar_remask_test.exp rename to sw/acc/crypto/tests/p384_scalar_remask_test.exp diff --git a/sw/otbn/crypto/tests/p384_scalar_remask_test.s b/sw/acc/crypto/tests/p384_scalar_remask_test.s similarity index 100% rename from sw/otbn/crypto/tests/p384_scalar_remask_test.s rename to sw/acc/crypto/tests/p384_scalar_remask_test.s diff --git a/sw/otbn/crypto/tests/primality_negative_test.exp b/sw/acc/crypto/tests/primality_negative_test.exp similarity index 100% rename from sw/otbn/crypto/tests/primality_negative_test.exp rename to sw/acc/crypto/tests/primality_negative_test.exp diff --git a/sw/otbn/crypto/tests/primality_negative_test.s b/sw/acc/crypto/tests/primality_negative_test.s similarity index 100% rename from sw/otbn/crypto/tests/primality_negative_test.s rename to sw/acc/crypto/tests/primality_negative_test.s diff --git a/sw/otbn/crypto/tests/primality_test.exp b/sw/acc/crypto/tests/primality_test.exp similarity index 100% rename from sw/otbn/crypto/tests/primality_test.exp rename to sw/acc/crypto/tests/primality_test.exp diff --git a/sw/otbn/crypto/tests/primality_test.s b/sw/acc/crypto/tests/primality_test.s similarity index 100% rename from sw/otbn/crypto/tests/primality_test.s rename to sw/acc/crypto/tests/primality_test.s diff --git a/sw/otbn/crypto/tests/primality_test_witness_negative_test.exp b/sw/acc/crypto/tests/primality_test_witness_negative_test.exp similarity index 100% rename from sw/otbn/crypto/tests/primality_test_witness_negative_test.exp rename to sw/acc/crypto/tests/primality_test_witness_negative_test.exp diff --git a/sw/otbn/crypto/tests/primality_test_witness_negative_test.s b/sw/acc/crypto/tests/primality_test_witness_negative_test.s similarity index 100% rename from sw/otbn/crypto/tests/primality_test_witness_negative_test.s rename to sw/acc/crypto/tests/primality_test_witness_negative_test.s diff --git a/sw/otbn/crypto/tests/primality_test_witness_test.exp b/sw/acc/crypto/tests/primality_test_witness_test.exp similarity index 100% rename from sw/otbn/crypto/tests/primality_test_witness_test.exp rename to sw/acc/crypto/tests/primality_test_witness_test.exp diff --git a/sw/otbn/crypto/tests/primality_test_witness_test.s b/sw/acc/crypto/tests/primality_test_witness_test.s similarity index 100% rename from sw/otbn/crypto/tests/primality_test_witness_test.s rename to sw/acc/crypto/tests/primality_test_witness_test.s diff --git a/sw/otbn/crypto/tests/relprime_f4_test.exp b/sw/acc/crypto/tests/relprime_f4_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_f4_test.exp rename to sw/acc/crypto/tests/relprime_f4_test.exp diff --git a/sw/otbn/crypto/tests/relprime_f4_test.s b/sw/acc/crypto/tests/relprime_f4_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_f4_test.s rename to sw/acc/crypto/tests/relprime_f4_test.s diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_11_test.exp b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_11_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_11_test.exp rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_11_test.exp diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_11_test.s b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_11_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_11_test.s rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_11_test.s diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_17_test.exp b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_17_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_17_test.exp rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_17_test.exp diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_17_test.s b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_17_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_17_test.s rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_17_test.s diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_31_test.exp b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_31_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_31_test.exp rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_31_test.exp diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_31_test.s b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_31_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_31_test.s rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_31_test.s diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_3_test.exp b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_3_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_3_test.exp rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_3_test.exp diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_3_test.s b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_3_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_3_test.s rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_3_test.s diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_5_test.exp b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_5_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_5_test.exp rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_5_test.exp diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_5_test.s b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_5_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_5_test.s rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_5_test.s diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_7_test.exp b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_7_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_7_test.exp rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_7_test.exp diff --git a/sw/otbn/crypto/tests/relprime_small_primes_multiple_of_7_test.s b/sw/acc/crypto/tests/relprime_small_primes_multiple_of_7_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_multiple_of_7_test.s rename to sw/acc/crypto/tests/relprime_small_primes_multiple_of_7_test.s diff --git a/sw/otbn/crypto/tests/relprime_small_primes_negative_test.exp b/sw/acc/crypto/tests/relprime_small_primes_negative_test.exp similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_negative_test.exp rename to sw/acc/crypto/tests/relprime_small_primes_negative_test.exp diff --git a/sw/otbn/crypto/tests/relprime_small_primes_negative_test.s b/sw/acc/crypto/tests/relprime_small_primes_negative_test.s similarity index 100% rename from sw/otbn/crypto/tests/relprime_small_primes_negative_test.s rename to sw/acc/crypto/tests/relprime_small_primes_negative_test.s diff --git a/sw/otbn/crypto/tests/rsa_1024_dec_crt_test.exp b/sw/acc/crypto/tests/rsa_1024_dec_crt_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_1024_dec_crt_test.exp rename to sw/acc/crypto/tests/rsa_1024_dec_crt_test.exp diff --git a/sw/otbn/crypto/tests/rsa_1024_dec_crt_test.s b/sw/acc/crypto/tests/rsa_1024_dec_crt_test.s similarity index 97% rename from sw/otbn/crypto/tests/rsa_1024_dec_crt_test.s rename to sw/acc/crypto/tests/rsa_1024_dec_crt_test.s index 8e546a3d167..5fe76beecc0 100644 --- a/sw/otbn/crypto/tests/rsa_1024_dec_crt_test.s +++ b/sw/acc/crypto/tests/rsa_1024_dec_crt_test.s @@ -7,7 +7,7 @@ /** * Standalone RSA 1024 decrypt using CRT * - * Uses OTBN modexp bignum lib to decrypt the message from the .data segment + * Uses ACC modexp bignum lib to decrypt the message from the .data segment * in this file with the private key contained in .data segment of this file. * * Copies the decrypted message to wide registers for comparison (starting at diff --git a/sw/otbn/crypto/tests/rsa_1024_dec_test.exp b/sw/acc/crypto/tests/rsa_1024_dec_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_1024_dec_test.exp rename to sw/acc/crypto/tests/rsa_1024_dec_test.exp diff --git a/sw/otbn/crypto/tests/rsa_1024_dec_test.s b/sw/acc/crypto/tests/rsa_1024_dec_test.s similarity index 97% rename from sw/otbn/crypto/tests/rsa_1024_dec_test.s rename to sw/acc/crypto/tests/rsa_1024_dec_test.s index 2f0ea976ebf..6b1ae5f3ef9 100644 --- a/sw/otbn/crypto/tests/rsa_1024_dec_test.s +++ b/sw/acc/crypto/tests/rsa_1024_dec_test.s @@ -8,7 +8,7 @@ /** * Standalone RSA 1024 decrypt * - * Uses OTBN modexp bignum lib to decrypt the message from the .data segment + * Uses ACC modexp bignum lib to decrypt the message from the .data segment * in this file with the private key contained in .data segment of this file. * * Copies the decrypted message to wide registers for comparison (starting at diff --git a/sw/otbn/crypto/tests/rsa_1024_enc_test.exp b/sw/acc/crypto/tests/rsa_1024_enc_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_1024_enc_test.exp rename to sw/acc/crypto/tests/rsa_1024_enc_test.exp diff --git a/sw/otbn/crypto/tests/rsa_1024_enc_test.s b/sw/acc/crypto/tests/rsa_1024_enc_test.s similarity index 96% rename from sw/otbn/crypto/tests/rsa_1024_enc_test.s rename to sw/acc/crypto/tests/rsa_1024_enc_test.s index 9289eec9532..c99a822f80b 100644 --- a/sw/otbn/crypto/tests/rsa_1024_enc_test.s +++ b/sw/acc/crypto/tests/rsa_1024_enc_test.s @@ -8,7 +8,7 @@ /** * Standalone RSA 1024 encrypt * - * Uses OTBN modexp bignum lib to encrypt the message from the .data segment + * Uses ACC modexp bignum lib to encrypt the message from the .data segment * in this file with the public key consisting of e=65537 and modulus from * .data segment in this file. * diff --git a/sw/otbn/crypto/tests/rsa_2048_dec_crt_test.exp b/sw/acc/crypto/tests/rsa_2048_dec_crt_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_2048_dec_crt_test.exp rename to sw/acc/crypto/tests/rsa_2048_dec_crt_test.exp diff --git a/sw/otbn/crypto/tests/rsa_2048_dec_crt_test.s b/sw/acc/crypto/tests/rsa_2048_dec_crt_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_2048_dec_crt_test.s rename to sw/acc/crypto/tests/rsa_2048_dec_crt_test.s diff --git a/sw/otbn/crypto/tests/rsa_2048_dec_test.exp b/sw/acc/crypto/tests/rsa_2048_dec_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_2048_dec_test.exp rename to sw/acc/crypto/tests/rsa_2048_dec_test.exp diff --git a/sw/otbn/crypto/tests/rsa_2048_dec_test.s b/sw/acc/crypto/tests/rsa_2048_dec_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_2048_dec_test.s rename to sw/acc/crypto/tests/rsa_2048_dec_test.s diff --git a/sw/otbn/crypto/tests/rsa_2048_enc_test.exp b/sw/acc/crypto/tests/rsa_2048_enc_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_2048_enc_test.exp rename to sw/acc/crypto/tests/rsa_2048_enc_test.exp diff --git a/sw/otbn/crypto/tests/rsa_2048_enc_test.s b/sw/acc/crypto/tests/rsa_2048_enc_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_2048_enc_test.s rename to sw/acc/crypto/tests/rsa_2048_enc_test.s diff --git a/sw/otbn/crypto/tests/rsa_3072_dec_crt_test.exp b/sw/acc/crypto/tests/rsa_3072_dec_crt_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_3072_dec_crt_test.exp rename to sw/acc/crypto/tests/rsa_3072_dec_crt_test.exp diff --git a/sw/otbn/crypto/tests/rsa_3072_dec_crt_test.s b/sw/acc/crypto/tests/rsa_3072_dec_crt_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_3072_dec_crt_test.s rename to sw/acc/crypto/tests/rsa_3072_dec_crt_test.s diff --git a/sw/otbn/crypto/tests/rsa_3072_dec_test.exp b/sw/acc/crypto/tests/rsa_3072_dec_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_3072_dec_test.exp rename to sw/acc/crypto/tests/rsa_3072_dec_test.exp diff --git a/sw/otbn/crypto/tests/rsa_3072_dec_test.s b/sw/acc/crypto/tests/rsa_3072_dec_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_3072_dec_test.s rename to sw/acc/crypto/tests/rsa_3072_dec_test.s diff --git a/sw/otbn/crypto/tests/rsa_3072_enc_test.exp b/sw/acc/crypto/tests/rsa_3072_enc_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_3072_enc_test.exp rename to sw/acc/crypto/tests/rsa_3072_enc_test.exp diff --git a/sw/otbn/crypto/tests/rsa_3072_enc_test.s b/sw/acc/crypto/tests/rsa_3072_enc_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_3072_enc_test.s rename to sw/acc/crypto/tests/rsa_3072_enc_test.s diff --git a/sw/otbn/crypto/tests/rsa_4096_dec_crt_test.exp b/sw/acc/crypto/tests/rsa_4096_dec_crt_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_4096_dec_crt_test.exp rename to sw/acc/crypto/tests/rsa_4096_dec_crt_test.exp diff --git a/sw/otbn/crypto/tests/rsa_4096_dec_crt_test.s b/sw/acc/crypto/tests/rsa_4096_dec_crt_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_4096_dec_crt_test.s rename to sw/acc/crypto/tests/rsa_4096_dec_crt_test.s diff --git a/sw/otbn/crypto/tests/rsa_4096_dec_test.exp b/sw/acc/crypto/tests/rsa_4096_dec_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_4096_dec_test.exp rename to sw/acc/crypto/tests/rsa_4096_dec_test.exp diff --git a/sw/otbn/crypto/tests/rsa_4096_dec_test.s b/sw/acc/crypto/tests/rsa_4096_dec_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_4096_dec_test.s rename to sw/acc/crypto/tests/rsa_4096_dec_test.s diff --git a/sw/otbn/crypto/tests/rsa_4096_enc_test.exp b/sw/acc/crypto/tests/rsa_4096_enc_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_4096_enc_test.exp rename to sw/acc/crypto/tests/rsa_4096_enc_test.exp diff --git a/sw/otbn/crypto/tests/rsa_4096_enc_test.s b/sw/acc/crypto/tests/rsa_4096_enc_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_4096_enc_test.s rename to sw/acc/crypto/tests/rsa_4096_enc_test.s diff --git a/sw/otbn/crypto/tests/rsa_check_key_recover_d_from_crt_test.dexp b/sw/acc/crypto/tests/rsa_check_key_recover_d_from_crt_test.dexp similarity index 100% rename from sw/otbn/crypto/tests/rsa_check_key_recover_d_from_crt_test.dexp rename to sw/acc/crypto/tests/rsa_check_key_recover_d_from_crt_test.dexp diff --git a/sw/otbn/crypto/tests/rsa_check_key_recover_d_from_crt_test.s b/sw/acc/crypto/tests/rsa_check_key_recover_d_from_crt_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_check_key_recover_d_from_crt_test.s rename to sw/acc/crypto/tests/rsa_check_key_recover_d_from_crt_test.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkp_good_test.exp b/sw/acc/crypto/tests/rsa_keygen_checkp_good_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkp_good_test.exp rename to sw/acc/crypto/tests/rsa_keygen_checkp_good_test.exp diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkp_good_test.s b/sw/acc/crypto/tests/rsa_keygen_checkp_good_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkp_good_test.s rename to sw/acc/crypto/tests/rsa_keygen_checkp_good_test.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkp_not_prime_test.exp b/sw/acc/crypto/tests/rsa_keygen_checkp_not_prime_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkp_not_prime_test.exp rename to sw/acc/crypto/tests/rsa_keygen_checkp_not_prime_test.exp diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkp_not_prime_test.s b/sw/acc/crypto/tests/rsa_keygen_checkp_not_prime_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkp_not_prime_test.s rename to sw/acc/crypto/tests/rsa_keygen_checkp_not_prime_test.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkp_not_relprime_test.exp b/sw/acc/crypto/tests/rsa_keygen_checkp_not_relprime_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkp_not_relprime_test.exp rename to sw/acc/crypto/tests/rsa_keygen_checkp_not_relprime_test.exp diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkp_not_relprime_test.s b/sw/acc/crypto/tests/rsa_keygen_checkp_not_relprime_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkp_not_relprime_test.s rename to sw/acc/crypto/tests/rsa_keygen_checkp_not_relprime_test.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkpq_test_data.s b/sw/acc/crypto/tests/rsa_keygen_checkpq_test_data.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkpq_test_data.s rename to sw/acc/crypto/tests/rsa_keygen_checkpq_test_data.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_good_test.exp b/sw/acc/crypto/tests/rsa_keygen_checkq_good_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_good_test.exp rename to sw/acc/crypto/tests/rsa_keygen_checkq_good_test.exp diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_good_test.s b/sw/acc/crypto/tests/rsa_keygen_checkq_good_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_good_test.s rename to sw/acc/crypto/tests/rsa_keygen_checkq_good_test.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_not_prime_test.exp b/sw/acc/crypto/tests/rsa_keygen_checkq_not_prime_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_not_prime_test.exp rename to sw/acc/crypto/tests/rsa_keygen_checkq_not_prime_test.exp diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_not_prime_test.s b/sw/acc/crypto/tests/rsa_keygen_checkq_not_prime_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_not_prime_test.s rename to sw/acc/crypto/tests/rsa_keygen_checkq_not_prime_test.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_not_relprime_test.exp b/sw/acc/crypto/tests/rsa_keygen_checkq_not_relprime_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_not_relprime_test.exp rename to sw/acc/crypto/tests/rsa_keygen_checkq_not_relprime_test.exp diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_not_relprime_test.s b/sw/acc/crypto/tests/rsa_keygen_checkq_not_relprime_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_not_relprime_test.s rename to sw/acc/crypto/tests/rsa_keygen_checkq_not_relprime_test.s diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_too_close_test.exp b/sw/acc/crypto/tests/rsa_keygen_checkq_too_close_test.exp similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_too_close_test.exp rename to sw/acc/crypto/tests/rsa_keygen_checkq_too_close_test.exp diff --git a/sw/otbn/crypto/tests/rsa_keygen_checkq_too_close_test.s b/sw/acc/crypto/tests/rsa_keygen_checkq_too_close_test.s similarity index 100% rename from sw/otbn/crypto/tests/rsa_keygen_checkq_too_close_test.s rename to sw/acc/crypto/tests/rsa_keygen_checkq_too_close_test.s diff --git a/sw/otbn/crypto/tests/sha256_test.exp b/sw/acc/crypto/tests/sha256_test.exp similarity index 100% rename from sw/otbn/crypto/tests/sha256_test.exp rename to sw/acc/crypto/tests/sha256_test.exp diff --git a/sw/otbn/crypto/tests/sha256_test.s b/sw/acc/crypto/tests/sha256_test.s similarity index 100% rename from sw/otbn/crypto/tests/sha256_test.s rename to sw/acc/crypto/tests/sha256_test.s diff --git a/sw/otbn/crypto/tests/sha384_test.exp b/sw/acc/crypto/tests/sha384_test.exp similarity index 100% rename from sw/otbn/crypto/tests/sha384_test.exp rename to sw/acc/crypto/tests/sha384_test.exp diff --git a/sw/otbn/crypto/tests/sha384_test.s b/sw/acc/crypto/tests/sha384_test.s similarity index 100% rename from sw/otbn/crypto/tests/sha384_test.s rename to sw/acc/crypto/tests/sha384_test.s diff --git a/sw/otbn/crypto/tests/sha3_shake_test.exp b/sw/acc/crypto/tests/sha3_shake_test.exp similarity index 100% rename from sw/otbn/crypto/tests/sha3_shake_test.exp rename to sw/acc/crypto/tests/sha3_shake_test.exp diff --git a/sw/otbn/crypto/tests/sha3_shake_test.s b/sw/acc/crypto/tests/sha3_shake_test.s similarity index 100% rename from sw/otbn/crypto/tests/sha3_shake_test.s rename to sw/acc/crypto/tests/sha3_shake_test.s diff --git a/sw/otbn/crypto/tests/sha512_compact_test.exp b/sw/acc/crypto/tests/sha512_compact_test.exp similarity index 100% rename from sw/otbn/crypto/tests/sha512_compact_test.exp rename to sw/acc/crypto/tests/sha512_compact_test.exp diff --git a/sw/otbn/crypto/tests/sha512_compact_test.s b/sw/acc/crypto/tests/sha512_compact_test.s similarity index 100% rename from sw/otbn/crypto/tests/sha512_compact_test.s rename to sw/acc/crypto/tests/sha512_compact_test.s diff --git a/sw/otbn/crypto/tests/sha512_interface_test.exp b/sw/acc/crypto/tests/sha512_interface_test.exp similarity index 97% rename from sw/otbn/crypto/tests/sha512_interface_test.exp rename to sw/acc/crypto/tests/sha512_interface_test.exp index 161974d1ebe..f55b9ca56ba 100644 --- a/sw/otbn/crypto/tests/sha512_interface_test.exp +++ b/sw/acc/crypto/tests/sha512_interface_test.exp @@ -10,6 +10,6 @@ w3 = 0x09e94b875be5965e5426ddb6ee29d3c73a43b5c4de991b33e4f700499e281d50 w4 = 0x189088b6adae9972a17f9febc679778f3f14fc1428f7f48cda13e3da759b958e w5 = 0x09e94b875be5965e5426ddb6ee29d3c73a43b5c4de991b33e4f700499e281d50 -# Test 4: Ed25519ph +# Test 4: Ed25519ph w6 = 0x2c698c6dc15fa0d4f96a7ab08824ad082367f97a21b9bbfc2384d8d0e0d99836 w7 = 0x1fe7cde1508df386751f6e837a637fb92dc19b087833c32e05a3cc909e7b5f0d diff --git a/sw/otbn/crypto/tests/sha512_interface_test.s b/sw/acc/crypto/tests/sha512_interface_test.s similarity index 100% rename from sw/otbn/crypto/tests/sha512_interface_test.s rename to sw/acc/crypto/tests/sha512_interface_test.s diff --git a/sw/otbn/crypto/tests/sha512_padding_test.exp b/sw/acc/crypto/tests/sha512_padding_test.exp similarity index 100% rename from sw/otbn/crypto/tests/sha512_padding_test.exp rename to sw/acc/crypto/tests/sha512_padding_test.exp diff --git a/sw/otbn/crypto/tests/sha512_padding_test.s b/sw/acc/crypto/tests/sha512_padding_test.s similarity index 100% rename from sw/otbn/crypto/tests/sha512_padding_test.s rename to sw/acc/crypto/tests/sha512_padding_test.s diff --git a/sw/otbn/crypto/tests/sha512_test.exp b/sw/acc/crypto/tests/sha512_test.exp similarity index 100% rename from sw/otbn/crypto/tests/sha512_test.exp rename to sw/acc/crypto/tests/sha512_test.exp diff --git a/sw/otbn/crypto/tests/sha512_test.s b/sw/acc/crypto/tests/sha512_test.s similarity index 100% rename from sw/otbn/crypto/tests/sha512_test.s rename to sw/acc/crypto/tests/sha512_test.s diff --git a/sw/otbn/crypto/tests/x25519_test1.exp b/sw/acc/crypto/tests/x25519_test1.exp similarity index 100% rename from sw/otbn/crypto/tests/x25519_test1.exp rename to sw/acc/crypto/tests/x25519_test1.exp diff --git a/sw/otbn/crypto/tests/x25519_test1.s b/sw/acc/crypto/tests/x25519_test1.s similarity index 100% rename from sw/otbn/crypto/tests/x25519_test1.s rename to sw/acc/crypto/tests/x25519_test1.s diff --git a/sw/otbn/crypto/tests/x25519_test2.exp b/sw/acc/crypto/tests/x25519_test2.exp similarity index 100% rename from sw/otbn/crypto/tests/x25519_test2.exp rename to sw/acc/crypto/tests/x25519_test2.exp diff --git a/sw/otbn/crypto/tests/x25519_test2.s b/sw/acc/crypto/tests/x25519_test2.s similarity index 100% rename from sw/otbn/crypto/tests/x25519_test2.s rename to sw/acc/crypto/tests/x25519_test2.s diff --git a/sw/otbn/crypto/x25519.s b/sw/acc/crypto/x25519.s similarity index 99% rename from sw/otbn/crypto/x25519.s rename to sw/acc/crypto/x25519.s index 0a104057f1d..1bbebedfcd6 100644 --- a/sw/otbn/crypto/x25519.s +++ b/sw/acc/crypto/x25519.s @@ -79,7 +79,7 @@ X25519: jal x1, scalar_mult /* Since the scalar multiplication routine has already reduced its result - modulo p and OTBN is little-endian, encoding the result is a no-op. */ + modulo p and ACC is little-endian, encoding the result is a no-op. */ ret diff --git a/sw/otbn/crypto/x25519_sideload.s b/sw/acc/crypto/x25519_sideload.s similarity index 100% rename from sw/otbn/crypto/x25519_sideload.s rename to sw/acc/crypto/x25519_sideload.s diff --git a/sw/device/lib/crypto/drivers/BUILD b/sw/device/lib/crypto/drivers/BUILD index 7a58f2d6eea..4877839d92e 100644 --- a/sw/device/lib/crypto/drivers/BUILD +++ b/sw/device/lib/crypto/drivers/BUILD @@ -199,13 +199,13 @@ opentitan_test( deps = [ ":entropy", ":entropy_kat", - "//hw/top:dt_otbn", + "//hw/top:dt_acc", "//sw/device/lib/base:macros", "//sw/device/lib/base:memory", - "//sw/device/lib/dif:otbn", + "//sw/device/lib/dif:acc", "//sw/device/lib/testing/test_framework:check", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/device/tests:otbn_randomness_impl", + "//sw/device/tests:acc_randomness_impl", ], ) @@ -272,13 +272,13 @@ opentitan_test( ) cc_library( - name = "otbn", - srcs = ["otbn.c"], - hdrs = ["otbn.h"], + name = "acc", + srcs = ["acc.c"], + hdrs = ["acc.h"], deps = [ ":entropy", - "//hw/top:dt_otbn", - "//hw/top:otbn_c_regs", + "//hw/top:acc_c_regs", + "//hw/top:dt_acc", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:bitfield", "//sw/device/lib/base:crc32", diff --git a/sw/device/lib/crypto/drivers/otbn.c b/sw/device/lib/crypto/drivers/acc.c similarity index 57% rename from sw/device/lib/crypto/drivers/otbn.c rename to sw/device/lib/crypto/drivers/acc.c index 89e2cb32c6d..dcd9deb6267 100644 --- a/sw/device/lib/crypto/drivers/otbn.c +++ b/sw/device/lib/crypto/drivers/acc.c @@ -3,9 +3,9 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" -#include "hw/top/dt/dt_otbn.h" +#include "hw/top/dt/dt_acc.h" #include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/bitfield.h" #include "sw/device/lib/base/crc32.h" @@ -15,57 +15,57 @@ #include "sw/device/lib/base/status.h" #include "sw/device/lib/crypto/impl/status.h" -#include "hw/top/otbn_regs.h" // Generated. +#include "hw/top/acc_regs.h" // Generated. // Module ID for status codes. #define MODULE_ID MAKE_MODULE_ID('d', 'b', 'n') -static const dt_otbn_t kOtbnDt = kDtOtbn; +static const dt_acc_t kAccDt = kDtAcc; -static inline uint32_t otbn_base(void) { - return dt_otbn_primary_reg_block(kOtbnDt); +static inline uint32_t acc_base(void) { + return dt_acc_primary_reg_block(kAccDt); } enum { /** * DMEM size in bytes. */ - kOtbnDMemSizeBytes = OTBN_DMEM_SIZE_BYTES, + kAccDMemSizeBytes = ACC_DMEM_SIZE_BYTES, /** * IMEM size in bytes. */ - kOtbnIMemSizeBytes = OTBN_IMEM_SIZE_BYTES, + kAccIMemSizeBytes = ACC_IMEM_SIZE_BYTES, /** * ERR_BITS register value in the case of no errors. * - * Although some parts of the ERR_BITS register are marked reserved, the OTBN + * Although some parts of the ERR_BITS register are marked reserved, the ACC * documentation explicitly guarantees that ERR_BITS is zero for a successful * execution: - * https://opentitan.org/book/hw/ip/otbn/doc/theory_of_operation.html#software-execution-design-details + * https://opentitan.org/book/hw/ip/acc/doc/theory_of_operation.html#software-execution-design-details */ - kOtbnErrBitsNoError = 0, + kAccErrBitsNoError = 0, }; /** - * OTBN commands + * ACC commands */ -typedef enum otbn_cmd { - kOtbnCmdExecute = 0xd8, - kOtbnCmdSecWipeDmem = 0xc3, - kOtbnCmdSecWipeImem = 0x1e, -} otbn_cmd_t; +typedef enum acc_cmd { + kAccCmdExecute = 0xd8, + kAccCmdSecWipeDmem = 0xc3, + kAccCmdSecWipeImem = 0x1e, +} acc_cmd_t; /** - * OTBN status + * ACC status */ -typedef enum otbn_status { - kOtbnStatusIdle = 0x00, - kOtbnStatusBusyExecute = 0x01, - kOtbnStatusBusySecWipeDmem = 0x02, - kOtbnStatusBusySecWipeImem = 0x03, - kOtbnStatusBusySecWipeInt = 0x04, - kOtbnStatusLocked = 0xFF, -} otbn_status_t; +typedef enum acc_status { + kAccStatusIdle = 0x00, + kAccStatusBusyExecute = 0x01, + kAccStatusBusySecWipeDmem = 0x02, + kAccStatusBusySecWipeImem = 0x03, + kAccStatusBusySecWipeInt = 0x04, + kAccStatusLocked = 0xFF, +} acc_status_t; /** * Ensures that a memory access fits within the given memory size. @@ -99,7 +99,7 @@ static status_t check_offset_len(uint32_t offset_bytes, size_t num_words, * Update a checksum value with a given DMEM write. * * Calculates the checksum stream according to: - * https://opentitan.org/book/hw/ip/otbn/doc/theory_of_operation.html#memory-load-integrity + * https://opentitan.org/book/hw/ip/acc/doc/theory_of_operation.html#memory-load-integrity * * This means each write is a 48b value, where the most significant two bytes * indicate the location and the least significant four bytes are the 32-bit @@ -111,7 +111,7 @@ static status_t check_offset_len(uint32_t offset_bytes, size_t num_words, * - The next 5b are zero * - The next 10b are the word-index of the address in memory * - * The 48b value is read by OTBN in little-endian order, so we accumulate it to + * The 48b value is read by ACC in little-endian order, so we accumulate it to * the checksum with least significant bytes first. * * @param checksum Checksum value (updated in-place). @@ -131,17 +131,17 @@ static void update_checksum_for_write(uint32_t *checksum, uint32_t addr, crc32_add8(checksum, prefix_bytes[1]); } -status_t otbn_dmem_write(size_t num_words, const uint32_t *src, - otbn_addr_t dest) { +status_t acc_dmem_write(size_t num_words, const uint32_t *src, + acc_addr_t dest) { // Check that the write fits in DMEM. - HARDENED_TRY(check_offset_len(dest, num_words, kOtbnDMemSizeBytes)); + HARDENED_TRY(check_offset_len(dest, num_words, kAccDMemSizeBytes)); // Calculate the base offset for DMEM. - uint32_t dmem_addr = otbn_base() + OTBN_DMEM_REG_OFFSET; + uint32_t dmem_addr = acc_base() + ACC_DMEM_REG_OFFSET; - // Read the initial checksum value from OTBN. - uint32_t checksum = launder32(otbn_load_checksum_get()); - HARDENED_CHECK_EQ(checksum, otbn_load_checksum_get()); + // Read the initial checksum value from ACC. + uint32_t checksum = launder32(acc_load_checksum_get()); + HARDENED_CHECK_EQ(checksum, acc_load_checksum_get()); // Invert the checksum to match the internal representation. checksum ^= UINT32_MAX; @@ -183,23 +183,23 @@ status_t otbn_dmem_write(size_t num_words, const uint32_t *src, } RANDOM_ORDER_HARDENED_CHECK_DONE(iter); - // Ensure the checksum updated the same way here and on OTBN. - if (launder32(checksum) != otbn_load_checksum_get()) { + // Ensure the checksum updated the same way here and on ACC. + if (launder32(checksum) != acc_load_checksum_get()) { return OTCRYPTO_FATAL_ERR; } - HARDENED_CHECK_EQ(checksum, otbn_load_checksum_get()); + HARDENED_CHECK_EQ(checksum, acc_load_checksum_get()); return OTCRYPTO_OK; } -status_t otbn_dmem_set(size_t num_words, const uint32_t src, otbn_addr_t dest) { - HARDENED_TRY(check_offset_len(dest, num_words, kOtbnDMemSizeBytes)); +status_t acc_dmem_set(size_t num_words, const uint32_t src, acc_addr_t dest) { + HARDENED_TRY(check_offset_len(dest, num_words, kAccDMemSizeBytes)); // No need to randomize here, since all the values are the same. size_t i = 0; - const uint32_t kBase = otbn_base(); + const uint32_t kBase = acc_base(); for (; launder32(i) < num_words; ++i) { - abs_mmio_write32(kBase + OTBN_DMEM_REG_OFFSET + dest + i * sizeof(uint32_t), + abs_mmio_write32(kBase + ACC_DMEM_REG_OFFSET + dest + i * sizeof(uint32_t), src); HARDENED_CHECK_LT(i, num_words); } @@ -207,13 +207,13 @@ status_t otbn_dmem_set(size_t num_words, const uint32_t src, otbn_addr_t dest) { return OTCRYPTO_OK; } -status_t otbn_dmem_read(size_t num_words, otbn_addr_t src, uint32_t *dest) { - HARDENED_TRY(check_offset_len(src, num_words, kOtbnDMemSizeBytes)); +status_t acc_dmem_read(size_t num_words, acc_addr_t src, uint32_t *dest) { + HARDENED_TRY(check_offset_len(src, num_words, kAccDMemSizeBytes)); size_t i = 0; - const uint32_t kBase = otbn_base(); + const uint32_t kBase = acc_base(); for (; launder32(i) < num_words; ++i) { - dest[i] = abs_mmio_read32(kBase + OTBN_DMEM_REG_OFFSET + src + + dest[i] = abs_mmio_read32(kBase + ACC_DMEM_REG_OFFSET + src + i * sizeof(uint32_t)); } HARDENED_CHECK_EQ(i, num_words); @@ -221,100 +221,100 @@ status_t otbn_dmem_read(size_t num_words, otbn_addr_t src, uint32_t *dest) { return OTCRYPTO_OK; } -status_t otbn_assert_idle(void) { - uint32_t status = launder32(~(uint32_t)kOtbnStatusIdle); +status_t acc_assert_idle(void) { + uint32_t status = launder32(~(uint32_t)kAccStatusIdle); status_t res = (status_t){ .value = (int32_t)launder32((uint32_t)OTCRYPTO_OK.value ^ status)}; - status = abs_mmio_read32(otbn_base() + OTBN_STATUS_REG_OFFSET); + status = abs_mmio_read32(acc_base() + ACC_STATUS_REG_OFFSET); res.value ^= ~status; if (launder32(OT_UNSIGNED(res.value)) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(res.value, kHardenedBoolTrue); - HARDENED_CHECK_EQ(abs_mmio_read32(otbn_base() + OTBN_STATUS_REG_OFFSET), - kOtbnStatusIdle); + HARDENED_CHECK_EQ(abs_mmio_read32(acc_base() + ACC_STATUS_REG_OFFSET), + kAccStatusIdle); return res; } return OTCRYPTO_ASYNC_INCOMPLETE; } -status_t otbn_execute(void) { - // Ensure OTBN is idle before attempting to run a command. - HARDENED_TRY(otbn_assert_idle()); +status_t acc_execute(void) { + // Ensure ACC is idle before attempting to run a command. + HARDENED_TRY(acc_assert_idle()); - abs_mmio_write32(otbn_base() + OTBN_CMD_REG_OFFSET, kOtbnCmdExecute); + abs_mmio_write32(acc_base() + ACC_CMD_REG_OFFSET, kAccCmdExecute); return OTCRYPTO_OK; } -status_t otbn_busy_wait_for_done(void) { +status_t acc_busy_wait_for_done(void) { uint32_t status = launder32(UINT32_MAX); - const uint32_t kBase = otbn_base(); + const uint32_t kBase = acc_base(); status_t res = (status_t){ .value = (int32_t)launder32((uint32_t)kHardenedBoolTrue ^ status)}; do { - status = abs_mmio_read32(kBase + OTBN_STATUS_REG_OFFSET); - } while (launder32(status) != kOtbnStatusIdle && - launder32(status) != kOtbnStatusLocked); + status = abs_mmio_read32(kBase + ACC_STATUS_REG_OFFSET); + } while (launder32(status) != kAccStatusIdle && + launder32(status) != kAccStatusLocked); res.value ^= ~status; - uint32_t err_bits = otbn_err_bits_get(); + uint32_t err_bits = acc_err_bits_get(); if (launder32(OT_UNSIGNED(res.value)) == kHardenedBoolTrue && - launder32(err_bits) == kOtbnErrBitsNoError) { + launder32(err_bits) == kAccErrBitsNoError) { HARDENED_CHECK_EQ(res.value, kHardenedBoolTrue); - err_bits = otbn_err_bits_get(); - HARDENED_CHECK_EQ(err_bits, kOtbnErrBitsNoError); - HARDENED_CHECK_EQ(abs_mmio_read32(kBase + OTBN_STATUS_REG_OFFSET), - kOtbnStatusIdle); + err_bits = acc_err_bits_get(); + HARDENED_CHECK_EQ(err_bits, kAccErrBitsNoError); + HARDENED_CHECK_EQ(abs_mmio_read32(kBase + ACC_STATUS_REG_OFFSET), + kAccStatusIdle); return res; } - // If OTBN is idle (not locked), then return a recoverable error. - if (launder32(status) == kOtbnStatusIdle) { - HARDENED_CHECK_EQ(status, kOtbnStatusIdle); + // If ACC is idle (not locked), then return a recoverable error. + if (launder32(status) == kAccStatusIdle) { + HARDENED_CHECK_EQ(status, kAccStatusIdle); return OTCRYPTO_RECOV_ERR; } - // OTBN is locked; return a fatal error. - HARDENED_CHECK_EQ(status, kOtbnStatusLocked); + // ACC is locked; return a fatal error. + HARDENED_CHECK_EQ(status, kAccStatusLocked); return OTCRYPTO_FATAL_ERR; } -uint32_t otbn_err_bits_get(void) { - return abs_mmio_read32(otbn_base() + OTBN_ERR_BITS_REG_OFFSET); +uint32_t acc_err_bits_get(void) { + return abs_mmio_read32(acc_base() + ACC_ERR_BITS_REG_OFFSET); } -uint32_t otbn_load_checksum_get(void) { - return abs_mmio_read32(otbn_base() + OTBN_LOAD_CHECKSUM_REG_OFFSET); +uint32_t acc_load_checksum_get(void) { + return abs_mmio_read32(acc_base() + ACC_LOAD_CHECKSUM_REG_OFFSET); } -void otbn_load_checksum_reset(void) { - abs_mmio_write32(otbn_base() + OTBN_LOAD_CHECKSUM_REG_OFFSET, 0); +void acc_load_checksum_reset(void) { + abs_mmio_write32(acc_base() + ACC_LOAD_CHECKSUM_REG_OFFSET, 0); } -uint32_t otbn_instruction_count_get(void) { - return abs_mmio_read32(otbn_base() + OTBN_INSN_CNT_REG_OFFSET); +uint32_t acc_instruction_count_get(void) { + return abs_mmio_read32(acc_base() + ACC_INSN_CNT_REG_OFFSET); } -status_t otbn_imem_sec_wipe(void) { - HARDENED_TRY(otbn_assert_idle()); - abs_mmio_write32(otbn_base() + OTBN_CMD_REG_OFFSET, kOtbnCmdSecWipeImem); - HARDENED_TRY(otbn_busy_wait_for_done()); +status_t acc_imem_sec_wipe(void) { + HARDENED_TRY(acc_assert_idle()); + abs_mmio_write32(acc_base() + ACC_CMD_REG_OFFSET, kAccCmdSecWipeImem); + HARDENED_TRY(acc_busy_wait_for_done()); return OTCRYPTO_OK; } -status_t otbn_dmem_sec_wipe(void) { - HARDENED_TRY(otbn_assert_idle()); - abs_mmio_write32(otbn_base() + OTBN_CMD_REG_OFFSET, kOtbnCmdSecWipeDmem); - HARDENED_TRY(otbn_busy_wait_for_done()); +status_t acc_dmem_sec_wipe(void) { + HARDENED_TRY(acc_assert_idle()); + abs_mmio_write32(acc_base() + ACC_CMD_REG_OFFSET, kAccCmdSecWipeDmem); + HARDENED_TRY(acc_busy_wait_for_done()); return OTCRYPTO_OK; } -void otbn_dmem_sec_wipe_nofail(void) { - abs_mmio_write32(otbn_base() + OTBN_CMD_REG_OFFSET, kOtbnCmdSecWipeDmem); +void acc_dmem_sec_wipe_nofail(void) { + abs_mmio_write32(acc_base() + ACC_CMD_REG_OFFSET, kAccCmdSecWipeDmem); } -status_t otbn_set_ctrl_software_errs_fatal(bool enable) { - // Ensure OTBN is idle (otherwise CTRL writes will be ignored). - HARDENED_TRY(otbn_assert_idle()); +status_t acc_set_ctrl_software_errs_fatal(bool enable) { + // Ensure ACC is idle (otherwise CTRL writes will be ignored). + HARDENED_TRY(acc_assert_idle()); // Only one bit in the CTRL register so no need to read current value. uint32_t new_ctrl; @@ -325,24 +325,24 @@ status_t otbn_set_ctrl_software_errs_fatal(bool enable) { new_ctrl = 0; } - abs_mmio_write32(otbn_base() + OTBN_CTRL_REG_OFFSET, new_ctrl); + abs_mmio_write32(acc_base() + ACC_CTRL_REG_OFFSET, new_ctrl); return OTCRYPTO_OK; } /** - * Checks if the OTBN application's IMEM and DMEM address parameters are valid. + * Checks if the ACC application's IMEM and DMEM address parameters are valid. * * This function checks the following properties: * - IMEM and DMEM ranges must not be "backwards" in memory, with the end * address coming before the start address. * - The IMEM range must be non-empty. * - * @param app the OTBN application to check + * @param app the ACC application to check * @return `OTCRYPTO_OK` if checks pass, otherwise `OTCRYPTO_BAD_ARGS`. */ OT_WARN_UNUSED_RESULT -static status_t check_app_address_ranges(const otbn_app_t *app) { +static status_t check_app_address_ranges(const acc_app_t *app) { // IMEM must not be backwards or empty. if (app->imem_end <= app->imem_start) { return OTCRYPTO_BAD_ARGS; @@ -358,34 +358,34 @@ static status_t check_app_address_ranges(const otbn_app_t *app) { return OTCRYPTO_OK; } -status_t otbn_load_app(const otbn_app_t app) { +status_t acc_load_app(const acc_app_t app) { HARDENED_TRY(check_app_address_ranges(&app)); - // Ensure OTBN is idle. - HARDENED_TRY(otbn_assert_idle()); + // Ensure ACC is idle. + HARDENED_TRY(acc_assert_idle()); const size_t imem_num_words = (size_t)(app.imem_end - app.imem_start); const size_t data_num_words = (size_t)(app.dmem_data_end - app.dmem_data_start); // Wipe the memories and reset the checksum register. - HARDENED_TRY(otbn_imem_sec_wipe()); - HARDENED_TRY(otbn_dmem_sec_wipe()); - otbn_load_checksum_reset(); + HARDENED_TRY(acc_imem_sec_wipe()); + HARDENED_TRY(acc_dmem_sec_wipe()); + acc_load_checksum_reset(); // Reset the LOAD_CHECKSUM register. - abs_mmio_write32(otbn_base() + OTBN_LOAD_CHECKSUM_REG_OFFSET, 0); + abs_mmio_write32(acc_base() + ACC_LOAD_CHECKSUM_REG_OFFSET, 0); // Ensure that the IMEM section fits in IMEM and the data section fits in // DMEM. HARDENED_TRY(check_offset_len(app.dmem_data_start_addr, data_num_words, - kOtbnDMemSizeBytes)); + kAccDMemSizeBytes)); - // Write to IMEM. Always starts at zero on the OTBN side. - otbn_addr_t imem_offset = 0; + // Write to IMEM. Always starts at zero on the ACC side. + acc_addr_t imem_offset = 0; HARDENED_TRY( - check_offset_len(imem_offset, imem_num_words, kOtbnIMemSizeBytes)); - uint32_t imem_start_addr = otbn_base() + OTBN_IMEM_REG_OFFSET + imem_offset; + check_offset_len(imem_offset, imem_num_words, kAccIMemSizeBytes)); + uint32_t imem_start_addr = acc_base() + ACC_IMEM_REG_OFFSET + imem_offset; uint32_t i = 0; for (; launder32(i) < imem_num_words; i++) { HARDENED_CHECK_LT(i, imem_num_words); @@ -394,10 +394,10 @@ status_t otbn_load_app(const otbn_app_t app) { HARDENED_CHECK_EQ(i, imem_num_words); // Write the data portion to DMEM. - otbn_addr_t data_offset = app.dmem_data_start_addr; + acc_addr_t data_offset = app.dmem_data_start_addr; HARDENED_TRY( - check_offset_len(data_offset, data_num_words, kOtbnDMemSizeBytes)); - uint32_t data_start_addr = otbn_base() + OTBN_DMEM_REG_OFFSET + data_offset; + check_offset_len(data_offset, data_num_words, kAccDMemSizeBytes)); + uint32_t data_start_addr = acc_base() + ACC_DMEM_REG_OFFSET + data_offset; i = 0; for (; launder32(i) < data_num_words; i++) { HARDENED_CHECK_LT(i, data_num_words); @@ -408,7 +408,7 @@ status_t otbn_load_app(const otbn_app_t app) { // Ensure that the checksum matches expectations. uint32_t checksum = - abs_mmio_read32(otbn_base() + OTBN_LOAD_CHECKSUM_REG_OFFSET); + abs_mmio_read32(acc_base() + ACC_LOAD_CHECKSUM_REG_OFFSET); if (launder32(checksum) != app.checksum) { return OTCRYPTO_FATAL_ERR; } diff --git a/sw/device/lib/crypto/drivers/otbn.h b/sw/device/lib/crypto/drivers/acc.h similarity index 53% rename from sw/device/lib/crypto/drivers/otbn.h rename to sw/device/lib/crypto/drivers/acc.h index da32122bab2..b2a23c6e7fa 100644 --- a/sw/device/lib/crypto/drivers/otbn.h +++ b/sw/device/lib/crypto/drivers/acc.h @@ -3,8 +3,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_SW_DEVICE_LIB_CRYPTO_DRIVERS_OTBN_H_ -#define OPENTITAN_SW_DEVICE_LIB_CRYPTO_DRIVERS_OTBN_H_ +#ifndef OPENTITAN_SW_DEVICE_LIB_CRYPTO_DRIVERS_ACC_H_ +#define OPENTITAN_SW_DEVICE_LIB_CRYPTO_DRIVERS_ACC_H_ #include #include @@ -17,43 +17,43 @@ extern "C" { #endif /** - * Constants related to OTBN wide words + * Constants related to ACC wide words */ enum { - /* Length of an OTBN wide word in bits */ - kOtbnWideWordNumBits = 256, - /* Length of an OTBN wide word in bytes */ - kOtbnWideWordNumBytes = kOtbnWideWordNumBits / 8, - /* Length of an OTBN wide word in words */ - kOtbnWideWordNumWords = kOtbnWideWordNumBytes / sizeof(uint32_t), + /* Length of an ACC wide word in bits */ + kAccWideWordNumBits = 256, + /* Length of an ACC wide word in bytes */ + kAccWideWordNumBytes = kAccWideWordNumBits / 8, + /* Length of an ACC wide word in words */ + kAccWideWordNumWords = kAccWideWordNumBytes / sizeof(uint32_t), }; /** - * The address of an OTBN symbol as seen by OTBN. + * The address of an ACC symbol as seen by ACC. * - * Use `OTBN_DECLARE_SYMBOL_ADDR()` together with `OTBN_ADDR_T_INIT()` to + * Use `ACC_DECLARE_SYMBOL_ADDR()` together with `ACC_ADDR_T_INIT()` to * initialize this type. */ -typedef uint32_t otbn_addr_t; +typedef uint32_t acc_addr_t; /** - * Information about an embedded OTBN application image. + * Information about an embedded ACC application image. * * All pointers reference data in the normal CPU address space. - * uint32_t values are addresses in the OTBN address space. + * uint32_t values are addresses in the ACC address space. * - * Use `OTBN_DECLARE_APP_SYMBOLS()` together with `OTBN_APP_T_INIT()` to + * Use `ACC_DECLARE_APP_SYMBOLS()` together with `ACC_APP_T_INIT()` to * initialize this structure. */ -typedef struct otbn_app { +typedef struct acc_app { /** - * Start of OTBN instruction memory in the embedded program. + * Start of ACC instruction memory in the embedded program. * * This pointer references Ibex's memory. */ const uint32_t *imem_start; /** - * The first word after OTBN instruction memory in the embedded program. + * The first word after ACC instruction memory in the embedded program. * * This pointer references Ibex's memory. * @@ -61,16 +61,16 @@ typedef struct otbn_app { */ const uint32_t *imem_end; /** - * Start of initialized OTBN data in the embedded program. + * Start of initialized ACC data in the embedded program. * * This pointer references Ibex's memory. * * Data in between `dmem_data_start` and `dmem_data_end` will be copied to - * OTBN at app load time. + * ACC at app load time. */ const uint32_t *dmem_data_start; /** - * The first word after initialized OTBN data in the embedded program. + * The first word after initialized ACC data in the embedded program. * * This pointer references Ibex's memory. * @@ -78,12 +78,12 @@ typedef struct otbn_app { */ const uint32_t *dmem_data_end; /** - * Start of initialized data section in OTBN's DMEM. + * Start of initialized data section in ACC's DMEM. * - * This pointer references OTBN's memory and is used to copy data at app load + * This pointer references ACC's memory and is used to copy data at app load * time. */ - const otbn_addr_t dmem_data_start_addr; + const acc_addr_t dmem_data_start_addr; /** * Application checksum. * @@ -91,47 +91,47 @@ typedef struct otbn_app { * of DMEM. */ const uint32_t checksum; -} otbn_app_t; +} acc_app_t; /** - * Generate the prefix to add to an OTBN symbol name used on the Ibex side + * Generate the prefix to add to an ACC symbol name used on the Ibex side * * The result is a pointer to Ibex's rodata that should be used to initialise * memory for that symbol. * - * This is needed by the OTBN driver to support DMEM/IMEM ranges but - * application code shouldn't need to use this. Use the `otbn_addr_t` type and + * This is needed by the ACC driver to support DMEM/IMEM ranges but + * application code shouldn't need to use this. Use the `acc_addr_t` type and * supporting macros instead. */ -#define OTBN_SYMBOL_PTR(app_name, sym) _otbn_local_app_##app_name##_##sym +#define ACC_SYMBOL_PTR(app_name, sym) _acc_local_app_##app_name##_##sym /** - * Generate the prefix to add to an OTBN symbol name used on the OTBN side + * Generate the prefix to add to an ACC symbol name used on the ACC side * * The result is a pointer whose integer value is the address by which the - * symbol should be accessed in OTBN memory. + * symbol should be accessed in ACC memory. * - * This is an internal macro used in `OTBN_DECLARE_SYMBOL_ADDR` and - * `OTBN_ADDR_T_INIT` but application code shouldn't need to use it directly. + * This is an internal macro used in `ACC_DECLARE_SYMBOL_ADDR` and + * `ACC_ADDR_T_INIT` but application code shouldn't need to use it directly. */ -#define OTBN_SYMBOL_ADDR(app_name, sym) _otbn_remote_app_##app_name##_##sym +#define ACC_SYMBOL_ADDR(app_name, sym) _acc_remote_app_##app_name##_##sym /** - * Makes a symbol in the OTBN application image available. + * Makes a symbol in the ACC application image available. * - * This is needed by the OTBN driver to support DMEM/IMEM ranges but - * application code shouldn't need to use this. To get access to OTBN - * addresses, use `OTBN_DECLARE_SYMBOL_ADDR` instead. + * This is needed by the ACC driver to support DMEM/IMEM ranges but + * application code shouldn't need to use this. To get access to ACC + * addresses, use `ACC_DECLARE_SYMBOL_ADDR` instead. */ -#define OTBN_DECLARE_SYMBOL_PTR(app_name, symbol_name) \ - extern const uint32_t OTBN_SYMBOL_PTR(app_name, symbol_name)[] +#define ACC_DECLARE_SYMBOL_PTR(app_name, symbol_name) \ + extern const uint32_t ACC_SYMBOL_PTR(app_name, symbol_name)[] /** - * Makes the OTBN address of a symbol in the OTBN application available. + * Makes the ACC address of a symbol in the ACC application available. * * Symbols are typically function or data pointers, i.e. labels in assembly - * code. Unlike OTBN_DECLARE_SYMBOL_PTR, this will work for symbols in the .bss - * section (which exist on the OTBN side, even though they don't have backing + * code. Unlike ACC_DECLARE_SYMBOL_PTR, this will work for symbols in the .bss + * section (which exist on the ACC side, even though they don't have backing * data on Ibex). * * Use this macro instead of manually declaring the symbols as symbol names @@ -140,11 +140,11 @@ typedef struct otbn_app { * @param app_name Name of the application the function is contained in. * @param symbol_name Name of the symbol (function, label). */ -#define OTBN_DECLARE_SYMBOL_ADDR(app_name, symbol_name) \ - extern const uint32_t OTBN_SYMBOL_ADDR(app_name, symbol_name)[] +#define ACC_DECLARE_SYMBOL_ADDR(app_name, symbol_name) \ + extern const uint32_t ACC_SYMBOL_ADDR(app_name, symbol_name)[] /** - * Makes an embedded OTBN application image available for use. + * Makes an embedded ACC application image available for use. * * Make symbols available that indicate the start and the end of instruction * and data memory regions, as they are stored in the device memory. @@ -155,39 +155,39 @@ typedef struct otbn_app { * @param app_name Name of the application to load, which is typically the * name of the main (assembly) source file. */ -#define OTBN_DECLARE_APP_SYMBOLS(app_name) \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _imem_start); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _imem_end); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _dmem_data_start); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _dmem_data_end); \ - OTBN_DECLARE_SYMBOL_ADDR(app_name, _dmem_data_start); \ - OTBN_DECLARE_SYMBOL_ADDR(app_name, _checksum) +#define ACC_DECLARE_APP_SYMBOLS(app_name) \ + ACC_DECLARE_SYMBOL_PTR(app_name, _imem_start); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _imem_end); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _dmem_data_start); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _dmem_data_end); \ + ACC_DECLARE_SYMBOL_ADDR(app_name, _dmem_data_start); \ + ACC_DECLARE_SYMBOL_ADDR(app_name, _checksum) /** - * Initializes the OTBN application information structure. + * Initializes the ACC application information structure. * * After making all required symbols from the application image available - * through `OTBN_DECLARE_APP_SYMBOLS()`, use this macro to initialize an - * `otbn_app_t` struct with those symbols. + * through `ACC_DECLARE_APP_SYMBOLS()`, use this macro to initialize an + * `acc_app_t` struct with those symbols. * * @param app_name Name of the application to load. - * @see OTBN_DECLARE_APP_SYMBOLS() + * @see ACC_DECLARE_APP_SYMBOLS() */ -#define OTBN_APP_T_INIT(app_name) \ - ((otbn_app_t){ \ - .imem_start = OTBN_SYMBOL_PTR(app_name, _imem_start), \ - .imem_end = OTBN_SYMBOL_PTR(app_name, _imem_end), \ - .dmem_data_start = OTBN_SYMBOL_PTR(app_name, _dmem_data_start), \ - .dmem_data_end = OTBN_SYMBOL_PTR(app_name, _dmem_data_end), \ - .dmem_data_start_addr = OTBN_ADDR_T_INIT(app_name, _dmem_data_start), \ - .checksum = OTBN_ADDR_T_INIT(app_name, _checksum), \ +#define ACC_APP_T_INIT(app_name) \ + ((acc_app_t){ \ + .imem_start = ACC_SYMBOL_PTR(app_name, _imem_start), \ + .imem_end = ACC_SYMBOL_PTR(app_name, _imem_end), \ + .dmem_data_start = ACC_SYMBOL_PTR(app_name, _dmem_data_start), \ + .dmem_data_end = ACC_SYMBOL_PTR(app_name, _dmem_data_end), \ + .dmem_data_start_addr = ACC_ADDR_T_INIT(app_name, _dmem_data_start), \ + .checksum = ACC_ADDR_T_INIT(app_name, _checksum), \ }) /** - * Initializes an `otbn_addr_t`. + * Initializes an `acc_addr_t`. */ -#define OTBN_ADDR_T_INIT(app_name, symbol_name) \ - ((uint32_t)OTBN_SYMBOL_ADDR(app_name, symbol_name)) +#define ACC_ADDR_T_INIT(app_name, symbol_name) \ + ((uint32_t)ACC_SYMBOL_ADDR(app_name, symbol_name)) /** * Variant of HARDENED_TRY that wipes DMEM before returning. @@ -199,22 +199,22 @@ typedef struct otbn_app { * @param expr_ An expression that evaluates to a `status_t`. */ #ifndef OT_DISABLE_HARDENING -#define OTBN_WIPE_IF_ERROR(expr_) \ +#define ACC_WIPE_IF_ERROR(expr_) \ do { \ status_t status_ = expr_; \ if (launder32(OT_UNSIGNED(status_.value)) != kHardenedBoolTrue) { \ - otbn_dmem_sec_wipe_nofail(); \ + acc_dmem_sec_wipe_nofail(); \ return (status_t){ \ .value = (int32_t)(OT_UNSIGNED(status_.value) | 0x80000000)}; \ } \ HARDENED_CHECK_EQ(status_.value, kHardenedBoolTrue); \ } while (false) #else // OT_DISABLE_HARDENING -#define OTBN_WIPE_IF_ERROR(expr_) \ +#define ACC_WIPE_IF_ERROR(expr_) \ do { \ status_t status_ = expr_; \ if (status_.value != kHardenedBoolTrue) { \ - otbn_dmem_sec_wipe_nofail(); \ + acc_dmem_sec_wipe_nofail(); \ return (status_t){ \ .value = (int32_t)(OT_UNSIGNED(status_.value) | 0x80000000)}; \ } \ @@ -225,41 +225,41 @@ typedef struct otbn_app { * Checks that a provided operation completed with a valid instuction count. * * @param operation_ The operation performed, used to reference autogenerated - * constants created by `autogen_otbn_insn_count_header`. + * constants created by `autogen_acc_insn_count_header`. */ #ifndef OT_DISABLE_HARDENING -#define OTBN_CHECK_INSN_COUNT(min_count_, max_count_) \ +#define ACC_CHECK_INSN_COUNT(min_count_, max_count_) \ do { \ - uint32_t insn_count = otbn_instruction_count_get(); \ + uint32_t insn_count = acc_instruction_count_get(); \ if (insn_count < min_count_ || insn_count > max_count_) { \ - otbn_dmem_sec_wipe_nofail(); \ + acc_dmem_sec_wipe_nofail(); \ return OTCRYPTO_FATAL_ERR; \ } \ HARDENED_CHECK_GE(insn_count, min_count_); \ HARDENED_CHECK_LE(insn_count, max_count_); \ } while (false) #else // OT_DISABLE_HARDENING -#define OTBN_CHECK_INSN_COUNT(min_count_, max_count_) \ +#define ACC_CHECK_INSN_COUNT(min_count_, max_count_) \ do { \ - uint32_t insn_count = otbn_instruction_count_get(); \ + uint32_t insn_count = acc_instruction_count_get(); \ if (insn_count < min_count_ || insn_count > max_count_) { \ - otbn_dmem_sec_wipe_nofail(); \ + acc_dmem_sec_wipe_nofail(); \ return OTCRYPTO_FATAL_ERR; \ } \ } while (false) #endif // OT_DISABLE_HARDENING /** - * Write to OTBN's data memory (DMEM) + * Write to ACC's data memory (DMEM) * * Only 32b-aligned 32b word accesses are allowed. If `dest` is not * word-aligned or if the length and offset exceed the DMEM size, this function * will return an error. * - * Automatically checks that OTBN's LOAD_CHECKSUM register updates as expected + * Automatically checks that ACC's LOAD_CHECKSUM register updates as expected * for consistency. * - * The caller must ensure OTBN is idle before calling this function. + * The caller must ensure ACC is idle before calling this function. * * @param num_words Length of the data in 32-bit words. * @param src The main memory location to copy from. @@ -267,17 +267,16 @@ typedef struct otbn_app { * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_dmem_write(size_t num_words, const uint32_t *src, - otbn_addr_t dest); +status_t acc_dmem_write(size_t num_words, const uint32_t *src, acc_addr_t dest); /** - * Set a range of OTBN's data memory (DMEM) to a particular value. + * Set a range of ACC's data memory (DMEM) to a particular value. * * Only 32b-aligned 32b word accesses are allowed. If `dest` is not * word-aligned or if the length and offset exceed the DMEM size, this function * will return an error. * - * The caller must ensure OTBN is idle before calling this function. + * The caller must ensure ACC is idle before calling this function. * * @param num_words Length of the range to set in 32-bit words. * @param src The value to set each word in DMEM to. @@ -285,16 +284,16 @@ status_t otbn_dmem_write(size_t num_words, const uint32_t *src, * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_dmem_set(size_t num_words, const uint32_t src, otbn_addr_t dest); +status_t acc_dmem_set(size_t num_words, const uint32_t src, acc_addr_t dest); /** - * Read from OTBN's data memory (DMEM) + * Read from ACC's data memory (DMEM) * * Only 32b-aligned 32b word accesses are allowed. If `src` is not word-aligned * or if the length and offset exceed the DMEM size, this function will return * an error. * - * The caller must ensure OTBN is idle before calling this function. + * The caller must ensure ACC is idle before calling this function. * * @param num_words Length of the data in 32-bit words. * @param src The DMEM location to copy from. @@ -302,152 +301,152 @@ status_t otbn_dmem_set(size_t num_words, const uint32_t src, otbn_addr_t dest); * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_dmem_read(size_t num_words, otbn_addr_t src, uint32_t *dest); +status_t acc_dmem_read(size_t num_words, acc_addr_t src, uint32_t *dest); /** - * Ensures OTBN is idle. + * Ensures ACC is idle. * - * If OTBN is busy or locked, this function will return + * If ACC is busy or locked, this function will return * `OTCRYPTO_ASYNC_INCOMPLETE`; otherwise it will return `OTCRYPTO_OK`. * * @return Result of the operation. */ -status_t otbn_assert_idle(void); +status_t acc_assert_idle(void); /** - * Start the execution of the application loaded into OTBN. + * Start the execution of the application loaded into ACC. * - * This function returns an error if called when OTBN is not idle. + * This function returns an error if called when ACC is not idle. * * The caller is responsible for initializing the entropy complex before - * calling this function, even if the RND register is not being used. OTBN + * calling this function, even if the RND register is not being used. ACC * still consumes randomness for the secure wipe of its internal state before * exiting the program, and will lock if entropy is unavailable. * * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_execute(void); +status_t acc_execute(void); /** - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * - * If OTBN is or becomes locked, an error will occur. + * If ACC is or becomes locked, an error will occur. * * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_busy_wait_for_done(void); +status_t acc_busy_wait_for_done(void); /** * Get the error bits set by the device if the operation failed. * - * @return The contents of OTBN's ERR_BITS register. + * @return The contents of ACC's ERR_BITS register. */ -uint32_t otbn_err_bits_get(void); +uint32_t acc_err_bits_get(void); /** - * Read OTBN's instruction count register. + * Read ACC's instruction count register. * - * OTBN automatically calculates how many instructions are executed in a given + * ACC automatically calculates how many instructions are executed in a given * program and writes the result to this register. Software can read it to * verify that instructions were not unexpectedly skipped or added (for * instance, due to fault injection attacks). * - * Note that the OTBN hardware resets the instruction count register to 0 when + * Note that the ACC hardware resets the instruction count register to 0 when * the EXECUTE command is issued, so there is no need for software to reset the * counter between programs. * * @return count the value from the instruction count register */ -uint32_t otbn_instruction_count_get(void); +uint32_t acc_instruction_count_get(void); /** - * Get the checksum value of loaded data from OTBN. + * Get the checksum value of loaded data from ACC. * - * @return The contents of OTBN's LOAD_CHECKSUM register. + * @return The contents of ACC's LOAD_CHECKSUM register. */ -uint32_t otbn_load_checksum_get(void); +uint32_t acc_load_checksum_get(void); /** - * Reset the value of OTBN's LOAD_CHECKSUM register. + * Reset the value of ACC's LOAD_CHECKSUM register. * * Sets the checksum value to all-zero. */ -void otbn_load_checksum_reset(void); +void acc_load_checksum_reset(void); /** * Wipe IMEM securely. * - * This function returns an error if called when OTBN is not idle, and blocks + * This function returns an error if called when ACC is not idle, and blocks * until the secure wipe is complete. * * The caller is responsible for initializing the entropy complex before * calling this function, since it consumes randomness. If entropy is not - * available, OTBN will lock itself. + * available, ACC will lock itself. * * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_imem_sec_wipe(void); +status_t acc_imem_sec_wipe(void); /** * Wipe DMEM securely. * - * This function returns an error if called when OTBN is not idle, and blocks + * This function returns an error if called when ACC is not idle, and blocks * until the secure wipe is complete. * * The caller is responsible for initializing the entropy complex before * calling this function, since it consumes randomness. If entropy is not - * available, OTBN will lock itself. + * available, ACC will lock itself. * * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_dmem_sec_wipe(void); +status_t acc_dmem_sec_wipe(void); /** - * Variant of otbn_dmem_sec_wipe that does not error or block. + * Variant of acc_dmem_sec_wipe that does not error or block. * * Intended for cases where another operation has failed and we want to wipe * DMEM before returning the error code up the stack. */ -void otbn_dmem_sec_wipe_nofail(void); +void acc_dmem_sec_wipe_nofail(void); /** * Sets the software errors are fatal bit in the control register. * * When set any software error becomes a fatal error. The bit can only be - * changed when the OTBN status is IDLE. + * changed when the ACC status is IDLE. * - * This function returns an error if called when OTBN is not idle. + * This function returns an error if called when ACC is not idle. * * @param enable Enable or disable whether software errors are fatal. * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_set_ctrl_software_errs_fatal(bool enable); +status_t acc_set_ctrl_software_errs_fatal(bool enable); /** - * (Re-)loads the provided application into OTBN. + * (Re-)loads the provided application into ACC. * * Load the application image with both instruction and data segments into - * OTBN. + * ACC. * - * This function will return an error if called when OTBN is not idle. + * This function will return an error if called when ACC is not idle. * - * Because this function uses the OTBN secure wipe functionality before - * loading, it will lock OTBN if the entropy complex is not initialized. + * Because this function uses the ACC secure wipe functionality before + * loading, it will lock ACC if the entropy complex is not initialized. * * @param ctx The context object. - * @param app The application to load into OTBN. + * @param app The application to load into ACC. * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -status_t otbn_load_app(const otbn_app_t app); +status_t acc_load_app(const acc_app_t app); #ifdef __cplusplus } #endif -#endif // OPENTITAN_SW_DEVICE_LIB_CRYPTO_DRIVERS_OTBN_H_ +#endif // OPENTITAN_SW_DEVICE_LIB_CRYPTO_DRIVERS_ACC_H_ diff --git a/sw/device/lib/crypto/drivers/entropy_test.c b/sw/device/lib/crypto/drivers/entropy_test.c index bf78d103a83..ad2581fa43d 100644 --- a/sw/device/lib/crypto/drivers/entropy_test.c +++ b/sw/device/lib/crypto/drivers/entropy_test.c @@ -4,15 +4,15 @@ // SPDX-License-Identifier: Apache-2.0 #include "sw/device/lib/crypto/drivers/entropy.h" -#include "hw/top/dt/dt_otbn.h" +#include "hw/top/dt/dt_acc.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/status.h" #include "sw/device/lib/crypto/drivers/entropy_kat.h" -#include "sw/device/lib/dif/dif_otbn.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #define MODULE_ID MAKE_MODULE_ID('e', 'n', 't') @@ -26,11 +26,11 @@ static status_t entropy_complex_init_test(void) { TRY(entropy_complex_check()); // The following test requests entropy from both EDN0 and EDN1. - dif_otbn_t otbn; - TRY(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + dif_acc_t acc; + TRY(dif_acc_init_from_dt(kDtAcc, &acc)); - otbn_randomness_test_start(&otbn, /*iters=*/0); - TRY_CHECK(otbn_randomness_test_end(&otbn, /*skip_otbn_don_check=*/false)); + acc_randomness_test_start(&acc, /*iters=*/0); + TRY_CHECK(acc_randomness_test_end(&acc, /*skip_acc_don_check=*/false)); return OK_STATUS(); } diff --git a/sw/device/lib/crypto/drivers/keymgr.c b/sw/device/lib/crypto/drivers/keymgr.c index 01fcc7dcfb0..1b16a25d8ff 100644 --- a/sw/device/lib/crypto/drivers/keymgr.c +++ b/sw/device/lib/crypto/drivers/keymgr.c @@ -136,7 +136,7 @@ static status_t keymgr_wait_until_done(void) { * The CDI select bit is always set to false for this driver (i.e. Sealing * CDI). The driver does not support attestation CDI. * - * @param dest (NONE, AES, OTBN, or KMAC) + * @param dest (NONE, AES, ACC, or KMAC) * @param operation (GENERATE_SW or GENERATE_HW) */ #define WRITE_CTRL(dest, operation) \ @@ -156,7 +156,7 @@ static status_t keymgr_wait_until_done(void) { /** * Verify the control register of the key manager. * - * @param dest (NONE, AES, OTBN, or KMAC) + * @param dest (NONE, AES, ACC, or KMAC) * @param operation (GENERATE_SW or GENERATE_HW) */ #define VERIFY_CTRL(dest, operation) \ @@ -238,19 +238,19 @@ status_t keymgr_generate_key_kmac(keymgr_diversification_t diversification) { return OTCRYPTO_OK; } -status_t keymgr_generate_key_otbn(keymgr_diversification_t diversification) { +status_t keymgr_generate_key_acc(keymgr_diversification_t diversification) { // Ensure that the entropy complex has been initialized and keymgr is idle. HARDENED_TRY(entropy_complex_check()); HARDENED_TRY(keymgr_is_idle()); - // Set the control register to generate an OTBN key. - WRITE_CTRL(OTBN, GENERATE_HW); + // Set the control register to generate an ACC key. + WRITE_CTRL(ACC, GENERATE_HW); // Start the operation and wait for it to complete. keymgr_start(diversification); HARDENED_TRY(keymgr_wait_until_done()); // Check the control register. - VERIFY_CTRL(OTBN, GENERATE_HW); + VERIFY_CTRL(ACC, GENERATE_HW); return OTCRYPTO_OK; } @@ -260,7 +260,7 @@ status_t keymgr_generate_key_otbn(keymgr_diversification_t diversification) { * The `slot` parameter should be one of: * - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_AES * - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_KMAC - * - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_OTBN + * - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_ACC * * @param slot Value to write to the SIDELOAD_CLEAR register. */ @@ -302,6 +302,6 @@ status_t keymgr_sideload_clear_kmac(void) { return keymgr_sideload_clear(KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_KMAC); } -status_t keymgr_sideload_clear_otbn(void) { - return keymgr_sideload_clear(KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_OTBN); +status_t keymgr_sideload_clear_acc(void) { + return keymgr_sideload_clear(KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_ACC); } diff --git a/sw/device/lib/crypto/drivers/keymgr.h b/sw/device/lib/crypto/drivers/keymgr.h index 923009bb716..8ba577f4209 100644 --- a/sw/device/lib/crypto/drivers/keymgr.h +++ b/sw/device/lib/crypto/drivers/keymgr.h @@ -89,16 +89,16 @@ status_t keymgr_generate_key_kmac( const keymgr_diversification_t diversification); /** - * Derive a key manager key for the OTBN block. + * Derive a key manager key for the ACC block. * - * Calls the key manager to sideload a key into the OTBN hardware block and + * Calls the key manager to sideload a key into the ACC hardware block and * waits until the operation is complete before returning. * * @param diversification Diversification input for the key derivation. * @return OK or error. */ OT_WARN_UNUSED_RESULT -status_t keymgr_generate_key_otbn( +status_t keymgr_generate_key_acc( const keymgr_diversification_t diversification); /** @@ -118,12 +118,12 @@ OT_WARN_UNUSED_RESULT status_t keymgr_sideload_clear_kmac(void); /** - * Clear the sideloaded OTBN key. + * Clear the sideloaded ACC key. * * @return OK or error. */ OT_WARN_UNUSED_RESULT -status_t keymgr_sideload_clear_otbn(void); +status_t keymgr_sideload_clear_acc(void); #ifdef __cplusplus } diff --git a/sw/device/lib/crypto/drivers/keymgr_test.c b/sw/device/lib/crypto/drivers/keymgr_test.c index 49e4cc94bea..a5151d1a363 100644 --- a/sw/device/lib/crypto/drivers/keymgr_test.c +++ b/sw/device/lib/crypto/drivers/keymgr_test.c @@ -83,13 +83,13 @@ status_t kmac_basic_test(void) { } /** - * Test generating a single sideloaded OTBN key. + * Test generating a single sideloaded ACC key. * * This test just checks that the key generation process finished without * errors, without actually attempting to use the key. */ -status_t otbn_basic_test(void) { - return keymgr_generate_key_otbn(kTestDiversification); +status_t acc_basic_test(void) { + return keymgr_generate_key_acc(kTestDiversification); } /** @@ -200,7 +200,7 @@ bool test_main(void) { EXECUTE_TEST(result, sw_keys_change_version_test); EXECUTE_TEST(result, aes_basic_test); EXECUTE_TEST(result, kmac_basic_test); - EXECUTE_TEST(result, otbn_basic_test); + EXECUTE_TEST(result, acc_basic_test); return status_ok(result); } diff --git a/sw/device/lib/crypto/impl/ecc/BUILD b/sw/device/lib/crypto/impl/ecc/BUILD index cabe04b2002..3bd4ed6a059 100644 --- a/sw/device/lib/crypto/impl/ecc/BUILD +++ b/sw/device/lib/crypto/impl/ecc/BUILD @@ -9,7 +9,7 @@ package(default_visibility = ["//visibility:public"]) load("//rules/opentitan:defs.bzl", "OPENTITAN_CPU") -load("//rules:autogen.bzl", "autogen_otbn_insn_count_header") +load("//rules:autogen.bzl", "autogen_acc_insn_count_header") cc_library( name = "p256", @@ -18,12 +18,12 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":p256_insn_counts", + "//sw/acc/crypto:run_p256", "//sw/device/lib/base:hardened", "//sw/device/lib/base:hardened_memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:rv_core_ibex", "//sw/device/lib/crypto/impl:status", - "//sw/otbn/crypto:run_p256", ], ) @@ -34,12 +34,12 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":p384_insn_counts", + "//sw/acc/crypto:run_p384", "//sw/device/lib/base:hardened", "//sw/device/lib/base:hardened_memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:rv_core_ibex", "//sw/device/lib/crypto/impl:status", - "//sw/otbn/crypto:run_p384", ], ) @@ -50,38 +50,38 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":ed25519_insn_counts", + "//sw/acc/crypto:run_ed25519", "//sw/device/lib/base:hardened", "//sw/device/lib/base:hardened_memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:rv_core_ibex", "//sw/device/lib/crypto/impl:status", - "//sw/otbn/crypto:run_ed25519", ], ) -autogen_otbn_insn_count_header( +autogen_acc_insn_count_header( name = "p256_insn_counts", hjson = "p256_modes.hjson", template = "p256_insn_counts.h.tpl", deps = [ - "//sw/otbn/crypto:run_p256", + "//sw/acc/crypto:run_p256", ], ) -autogen_otbn_insn_count_header( +autogen_acc_insn_count_header( name = "p384_insn_counts", hjson = "p384_modes.hjson", template = "p384_insn_counts.h.tpl", deps = [ - "//sw/otbn/crypto:run_p384", + "//sw/acc/crypto:run_p384", ], ) -autogen_otbn_insn_count_header( +autogen_acc_insn_count_header( name = "ed25519_insn_counts", hjson = "ed25519_modes.hjson", template = "ed25519_insn_counts.h.tpl", deps = [ - "//sw/otbn/crypto:run_ed25519", + "//sw/acc/crypto:run_ed25519", ], ) diff --git a/sw/device/lib/crypto/impl/ecc/ed25519.c b/sw/device/lib/crypto/impl/ecc/ed25519.c index 59351ac2fee..b10752017d6 100644 --- a/sw/device/lib/crypto/impl/ecc/ed25519.c +++ b/sw/device/lib/crypto/impl/ecc/ed25519.c @@ -9,58 +9,58 @@ // Module ID for status codes. #define MODULE_ID MAKE_MODULE_ID('e', '2', 'r') -// Declare the OTBN app. -OTBN_DECLARE_APP_SYMBOLS(run_ed25519); // The OTBN Ed25519 app. -static const otbn_app_t kOtbnAppEd25519 = OTBN_APP_T_INIT(run_ed25519); +// Declare the ACC app. +ACC_DECLARE_APP_SYMBOLS(run_ed25519); // The ACC Ed25519 app. +static const acc_app_t kAccAppEd25519 = ACC_APP_T_INIT(run_ed25519); // Declare offsets for input and output buffers. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_mode); // Mode of operation.. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_message); // Message. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_sig_R); // R signature point. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_sig_S); // S signature scalar. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_hash_h); // Secret key hash h. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_hash_k); // Pre-computed hash k. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_ctx); // Context string. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_ctx_len); // Context length. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_public_key); // Public key. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_verify_result); // Verify result. - -static const otbn_addr_t kOtbnVarEd25519Mode = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_mode); -static const otbn_addr_t kOtbnVarEd25519Message = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_message); -static const otbn_addr_t kOtbnVarEd25519SigR = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_sig_R); -static const otbn_addr_t kOtbnVarEd25519SigS = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_sig_S); -static const otbn_addr_t kOtbnVarEd25519HashH = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_hash_h); -static const otbn_addr_t kOtbnVarEd25519HashK = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_hash_k); -static const otbn_addr_t kOtbnVarEd25519Ctx = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_ctx); -static const otbn_addr_t kOtbnVarEd25519CtxLen = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_ctx_len); -static const otbn_addr_t kOtbnVarEd25519PublicKey = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_public_key); -static const otbn_addr_t kOtbnVarEd25519VerifyResult = - OTBN_ADDR_T_INIT(run_ed25519, ed25519_verify_result); +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_mode); // Mode of operation.. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_message); // Message. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_sig_R); // R signature point. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_sig_S); // S signature scalar. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_hash_h); // Secret key hash h. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_hash_k); // Pre-computed hash k. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_ctx); // Context string. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_ctx_len); // Context length. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_public_key); // Public key. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ed25519_verify_result); // Verify result. + +static const acc_addr_t kAccVarEd25519Mode = + ACC_ADDR_T_INIT(run_ed25519, ed25519_mode); +static const acc_addr_t kAccVarEd25519Message = + ACC_ADDR_T_INIT(run_ed25519, ed25519_message); +static const acc_addr_t kAccVarEd25519SigR = + ACC_ADDR_T_INIT(run_ed25519, ed25519_sig_R); +static const acc_addr_t kAccVarEd25519SigS = + ACC_ADDR_T_INIT(run_ed25519, ed25519_sig_S); +static const acc_addr_t kAccVarEd25519HashH = + ACC_ADDR_T_INIT(run_ed25519, ed25519_hash_h); +static const acc_addr_t kAccVarEd25519HashK = + ACC_ADDR_T_INIT(run_ed25519, ed25519_hash_k); +static const acc_addr_t kAccVarEd25519Ctx = + ACC_ADDR_T_INIT(run_ed25519, ed25519_ctx); +static const acc_addr_t kAccVarEd25519CtxLen = + ACC_ADDR_T_INIT(run_ed25519, ed25519_ctx_len); +static const acc_addr_t kAccVarEd25519PublicKey = + ACC_ADDR_T_INIT(run_ed25519, ed25519_public_key); +static const acc_addr_t kAccVarEd25519VerifyResult = + ACC_ADDR_T_INIT(run_ed25519, ed25519_verify_result); // Declare mode constants. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, ED25519_MODE_SIGN); // Ed25519 signing. -OTBN_DECLARE_SYMBOL_ADDR(run_ed25519, - ED25519_MODE_VERIFY); // Ed25519 verification. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, ED25519_MODE_SIGN); // Ed25519 signing. +ACC_DECLARE_SYMBOL_ADDR(run_ed25519, + ED25519_MODE_VERIFY); // Ed25519 verification. -static const uint32_t kOtbnEd25519ModeSign = - OTBN_ADDR_T_INIT(run_ed25519, ED25519_MODE_SIGN); -static const uint32_t kOtbnEd25519ModeVerify = - OTBN_ADDR_T_INIT(run_ed25519, ED25519_MODE_VERIFY); +static const uint32_t kAccEd25519ModeSign = + ACC_ADDR_T_INIT(run_ed25519, ED25519_MODE_SIGN); +static const uint32_t kAccEd25519ModeVerify = + ACC_ADDR_T_INIT(run_ed25519, ED25519_MODE_VERIFY); enum { /* * Mode is represented by a single word. */ - kOtbnEd25519ModeWords = 1, + kAccEd25519ModeWords = 1, }; /** @@ -79,10 +79,10 @@ static status_t set_context(const uint32_t context[kEd25519ContextWords], HARDENED_CHECK_LE(context_length, kEd25519ContextWords); // Write the full context string. - HARDENED_TRY(otbn_dmem_write(context_length, context, kOtbnVarEd25519Ctx)); + HARDENED_TRY(acc_dmem_write(context_length, context, kAccVarEd25519Ctx)); // Set the context length. - return otbn_dmem_write(1, &context_length, kOtbnVarEd25519CtxLen); + return acc_dmem_write(1, &context_length, kAccVarEd25519CtxLen); } status_t ed25519_sign_start( @@ -90,45 +90,44 @@ status_t ed25519_sign_start( const uint32_t hash_h[kEd25519HashWords], const uint32_t context[kEd25519ContextWords], const uint32_t context_length) { - // Load the Ed25519 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppEd25519)); + // Load the Ed25519 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppEd25519)); // Set mode so start() will jump into signing. - uint32_t mode = kOtbnEd25519ModeSign; - HARDENED_TRY( - otbn_dmem_write(kOtbnEd25519ModeWords, &mode, kOtbnVarEd25519Mode)); + uint32_t mode = kAccEd25519ModeSign; + HARDENED_TRY(acc_dmem_write(kAccEd25519ModeWords, &mode, kAccVarEd25519Mode)); // Set the precomputed private key hash h. HARDENED_TRY( - otbn_dmem_write(kEd25519PreHashWords, hash_h, kOtbnVarEd25519HashH)); + acc_dmem_write(kEd25519PreHashWords, hash_h, kAccVarEd25519HashH)); // Set the context string. HARDENED_TRY(set_context(context, context_length)); // Set the pre-hashed message. - HARDENED_TRY(otbn_dmem_write(kEd25519HashWords, prehashed_message, - kOtbnVarEd25519Message)); + HARDENED_TRY(acc_dmem_write(kEd25519HashWords, prehashed_message, + kAccVarEd25519Message)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t ed25519_sign_finalize(ed25519_signature_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kEd25519SignMinInstructionCount, - kEd25519SignMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kEd25519SignMinInstructionCount, + kEd25519SignMaxInstructionCount); - // Read signature R out of OTBN dmem. - HARDENED_TRY(otbn_dmem_read(8, kOtbnVarEd25519SigR, result->r)); + // Read signature R out of ACC dmem. + HARDENED_TRY(acc_dmem_read(8, kAccVarEd25519SigR, result->r)); - // Read signature S out of OTBN dmem. - HARDENED_TRY(otbn_dmem_read(8, kOtbnVarEd25519SigS, result->s)); + // Read signature S out of ACC dmem. + HARDENED_TRY(acc_dmem_read(8, kAccVarEd25519SigS, result->s)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t ed25519_verify_start( @@ -138,55 +137,53 @@ status_t ed25519_verify_start( const uint32_t context[kEd25519ContextWords], const uint32_t context_length) { // Load the P-256 app and set up data pointers - HARDENED_TRY(otbn_load_app(kOtbnAppEd25519)); + HARDENED_TRY(acc_load_app(kAccAppEd25519)); // Set mode so start() will jump into verifying. - uint32_t mode = kOtbnEd25519ModeVerify; - HARDENED_TRY( - otbn_dmem_write(kOtbnEd25519ModeWords, &mode, kOtbnVarEd25519Mode)); + uint32_t mode = kAccEd25519ModeVerify; + HARDENED_TRY(acc_dmem_write(kAccEd25519ModeWords, &mode, kAccVarEd25519Mode)); // Set the pre-hashed message to the provided digest. - HARDENED_TRY(otbn_dmem_write(kEd25519HashWords, prehashed_message, - kOtbnVarEd25519Message)); + HARDENED_TRY(acc_dmem_write(kEd25519HashWords, prehashed_message, + kAccVarEd25519Message)); // Set the precomputed hash value k. - HARDENED_TRY( - otbn_dmem_write(kEd25519HashWords, hash_k, kOtbnVarEd25519HashK)); + HARDENED_TRY(acc_dmem_write(kEd25519HashWords, hash_k, kAccVarEd25519HashK)); // Set the context string. HARDENED_TRY(set_context(context, context_length)); // Set the signature R. HARDENED_TRY( - otbn_dmem_write(kEd25519PointWords, signature->r, kOtbnVarEd25519SigR)); + acc_dmem_write(kEd25519PointWords, signature->r, kAccVarEd25519SigR)); // Set the signature S. HARDENED_TRY( - otbn_dmem_write(kEd25519ScalarWords, signature->s, kOtbnVarEd25519SigS)); + acc_dmem_write(kEd25519ScalarWords, signature->s, kAccVarEd25519SigS)); // Set the public key. - HARDENED_TRY(otbn_dmem_write(kEd25519PointWords, public_key->data, - kOtbnVarEd25519PublicKey)); + HARDENED_TRY(acc_dmem_write(kEd25519PointWords, public_key->data, + kAccVarEd25519PublicKey)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t ed25519_verify_finalize(const ed25519_signature_t *signature, hardened_bool_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kEd25519VerifyMinInstructionCount, - kEd25519VerifyMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kEd25519VerifyMinInstructionCount, + kEd25519VerifyMaxInstructionCount); - // Read verification result out of OTBN dmem. + // Read verification result out of ACC dmem. uint32_t verify_result; - HARDENED_TRY(otbn_dmem_read(1, kOtbnVarEd25519VerifyResult, &verify_result)); + HARDENED_TRY(acc_dmem_read(1, kAccVarEd25519VerifyResult, &verify_result)); // Wipe DMEM. - HARDENED_TRY(otbn_dmem_sec_wipe()); + HARDENED_TRY(acc_dmem_sec_wipe()); // Return a result based on the read value. *result = kHardenedBoolFalse; diff --git a/sw/device/lib/crypto/impl/ecc/ed25519.h b/sw/device/lib/crypto/impl/ecc/ed25519.h index 2278b6b0ca0..9e85a475719 100644 --- a/sw/device/lib/crypto/impl/ecc/ed25519.h +++ b/sw/device/lib/crypto/impl/ecc/ed25519.h @@ -9,7 +9,7 @@ #include #include "sw/device/lib/base/hardened.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #ifdef __cplusplus extern "C" { @@ -135,9 +135,9 @@ typedef struct ed25519_signature { ; /** - * Start an async Ed25519ph signature generation operation on OTBN. + * Start an async Ed25519ph signature generation operation on ACC. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param prehashed_message Prehashed (SHA-512) message to sign. * @param hash_h SHA-512 hash of the Ed25519 private key to sign with. @@ -153,11 +153,11 @@ status_t ed25519_sign_start( const uint32_t context_length); /** - * Finish an async Ed25519 signature generation operation on OTBN. + * Finish an async Ed25519 signature generation operation on ACC. * * See the documentation of `p256_ecdsa_sign` for details. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] result Buffer in which to store the generated signature. * @return Result of the operation (OK or error). @@ -166,7 +166,7 @@ OT_WARN_UNUSED_RESULT status_t ed25519_sign_finalize(ed25519_signature_t *result); /** - * Start an async Ed25519 signature verification operation on OTBN. + * Start an async Ed25519 signature verification operation on ACC. * * This function expects the scalar value k as computed in RFC 8032 section * 5.2.6 step 2 to be pre-computed and provided as a little-endian value to this @@ -188,7 +188,7 @@ status_t ed25519_verify_start( const uint32_t context_length); /** - * Finish an async Ed25519 signature verification operation on OTBN. + * Finish an async Ed25519 signature verification operation on ACC. * * @param signature Signature to be verified. * @param[out] result Result of verification. diff --git a/sw/device/lib/crypto/impl/ecc/p256.c b/sw/device/lib/crypto/impl/ecc/p256.c index c4896778eea..c3c1abb0b0f 100644 --- a/sw/device/lib/crypto/impl/ecc/p256.c +++ b/sw/device/lib/crypto/impl/ecc/p256.c @@ -10,7 +10,7 @@ #include "sw/device/lib/base/hardened.h" #include "sw/device/lib/base/hardened_memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/ecc/p256_insn_counts.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" @@ -18,62 +18,62 @@ // Module ID for status codes. #define MODULE_ID MAKE_MODULE_ID('p', '2', 'r') -// Declare the OTBN app. -OTBN_DECLARE_APP_SYMBOLS(run_p256); // The OTBN P-256 app. -static const otbn_app_t kOtbnAppP256 = OTBN_APP_T_INIT(run_p256); +// Declare the ACC app. +ACC_DECLARE_APP_SYMBOLS(run_p256); // The ACC P-256 app. +static const acc_app_t kAccAppP256 = ACC_APP_T_INIT(run_p256); // Declare offsets for input and output buffers. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, mode); // Mode of operation. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, msg); // ECDSA message digest. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, r); // ECDSA signature scalar R. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, s); // ECDSA signature scalar S. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, x); // Public key x-coordinate. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, y); // Public key y-coordinate. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, d0_io); // Private key scalar d (share 0). -OTBN_DECLARE_SYMBOL_ADDR(run_p256, d1_io); // Private key scalar d (share 1). -OTBN_DECLARE_SYMBOL_ADDR(run_p256, x_r); // ECDSA verification result. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, ok); // Status code. - -static const otbn_addr_t kOtbnVarMode = OTBN_ADDR_T_INIT(run_p256, mode); -static const otbn_addr_t kOtbnVarMsg = OTBN_ADDR_T_INIT(run_p256, msg); -static const otbn_addr_t kOtbnVarR = OTBN_ADDR_T_INIT(run_p256, r); -static const otbn_addr_t kOtbnVarS = OTBN_ADDR_T_INIT(run_p256, s); -static const otbn_addr_t kOtbnVarX = OTBN_ADDR_T_INIT(run_p256, x); -static const otbn_addr_t kOtbnVarY = OTBN_ADDR_T_INIT(run_p256, y); -static const otbn_addr_t kOtbnVarD0 = OTBN_ADDR_T_INIT(run_p256, d0_io); -static const otbn_addr_t kOtbnVarD1 = OTBN_ADDR_T_INIT(run_p256, d1_io); -static const otbn_addr_t kOtbnVarXr = OTBN_ADDR_T_INIT(run_p256, x_r); -static const otbn_addr_t kOtbnVarOk = OTBN_ADDR_T_INIT(run_p256, ok); +ACC_DECLARE_SYMBOL_ADDR(run_p256, mode); // Mode of operation. +ACC_DECLARE_SYMBOL_ADDR(run_p256, msg); // ECDSA message digest. +ACC_DECLARE_SYMBOL_ADDR(run_p256, r); // ECDSA signature scalar R. +ACC_DECLARE_SYMBOL_ADDR(run_p256, s); // ECDSA signature scalar S. +ACC_DECLARE_SYMBOL_ADDR(run_p256, x); // Public key x-coordinate. +ACC_DECLARE_SYMBOL_ADDR(run_p256, y); // Public key y-coordinate. +ACC_DECLARE_SYMBOL_ADDR(run_p256, d0_io); // Private key scalar d (share 0). +ACC_DECLARE_SYMBOL_ADDR(run_p256, d1_io); // Private key scalar d (share 1). +ACC_DECLARE_SYMBOL_ADDR(run_p256, x_r); // ECDSA verification result. +ACC_DECLARE_SYMBOL_ADDR(run_p256, ok); // Status code. + +static const acc_addr_t kAccVarMode = ACC_ADDR_T_INIT(run_p256, mode); +static const acc_addr_t kAccVarMsg = ACC_ADDR_T_INIT(run_p256, msg); +static const acc_addr_t kAccVarR = ACC_ADDR_T_INIT(run_p256, r); +static const acc_addr_t kAccVarS = ACC_ADDR_T_INIT(run_p256, s); +static const acc_addr_t kAccVarX = ACC_ADDR_T_INIT(run_p256, x); +static const acc_addr_t kAccVarY = ACC_ADDR_T_INIT(run_p256, y); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(run_p256, d0_io); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(run_p256, d1_io); +static const acc_addr_t kAccVarXr = ACC_ADDR_T_INIT(run_p256, x_r); +static const acc_addr_t kAccVarOk = ACC_ADDR_T_INIT(run_p256, ok); // Declare mode constants. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_KEYGEN); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_KEY_CHECK); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIGN); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_VERIFY); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_ECDH); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIDELOAD_KEYGEN); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIDELOAD_SIGN); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIDELOAD_ECDH); -static const uint32_t kOtbnP256ModeKeygen = - OTBN_ADDR_T_INIT(run_p256, MODE_KEYGEN); -static const uint32_t kOtbnP256ModeKeyCheck = - OTBN_ADDR_T_INIT(run_p256, MODE_KEY_CHECK); -static const uint32_t kOtbnP256ModeSign = OTBN_ADDR_T_INIT(run_p256, MODE_SIGN); -static const uint32_t kOtbnP256ModeVerify = - OTBN_ADDR_T_INIT(run_p256, MODE_VERIFY); -static const uint32_t kOtbnP256ModeEcdh = OTBN_ADDR_T_INIT(run_p256, MODE_ECDH); -static const uint32_t kOtbnP256ModeSideloadKeygen = - OTBN_ADDR_T_INIT(run_p256, MODE_SIDELOAD_KEYGEN); -static const uint32_t kOtbnP256ModeSideloadSign = - OTBN_ADDR_T_INIT(run_p256, MODE_SIDELOAD_SIGN); -static const uint32_t kOtbnP256ModeSideloadEcdh = - OTBN_ADDR_T_INIT(run_p256, MODE_SIDELOAD_ECDH); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_KEYGEN); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_KEY_CHECK); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIGN); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_VERIFY); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_ECDH); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIDELOAD_KEYGEN); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIDELOAD_SIGN); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIDELOAD_ECDH); +static const uint32_t kAccP256ModeKeygen = + ACC_ADDR_T_INIT(run_p256, MODE_KEYGEN); +static const uint32_t kAccP256ModeKeyCheck = + ACC_ADDR_T_INIT(run_p256, MODE_KEY_CHECK); +static const uint32_t kAccP256ModeSign = ACC_ADDR_T_INIT(run_p256, MODE_SIGN); +static const uint32_t kAccP256ModeVerify = + ACC_ADDR_T_INIT(run_p256, MODE_VERIFY); +static const uint32_t kAccP256ModeEcdh = ACC_ADDR_T_INIT(run_p256, MODE_ECDH); +static const uint32_t kAccP256ModeSideloadKeygen = + ACC_ADDR_T_INIT(run_p256, MODE_SIDELOAD_KEYGEN); +static const uint32_t kAccP256ModeSideloadSign = + ACC_ADDR_T_INIT(run_p256, MODE_SIDELOAD_SIGN); +static const uint32_t kAccP256ModeSideloadEcdh = + ACC_ADDR_T_INIT(run_p256, MODE_SIDELOAD_ECDH); enum { /* * Mode is represented by a single word. */ - kOtbnP256ModeWords = 1, + kAccP256ModeWords = 1, /** * Number of extra padding words needed for masked scalar shares. * @@ -83,95 +83,95 @@ enum { * The extra outer "% W" ensures that the padding is 0 if (S % W) is 0. */ kMaskedScalarPaddingWords = - (kOtbnWideWordNumWords - - (kP256MaskedScalarShareWords % kOtbnWideWordNumWords)) % - kOtbnWideWordNumWords, + (kAccWideWordNumWords - + (kP256MaskedScalarShareWords % kAccWideWordNumWords)) % + kAccWideWordNumWords, }; OT_WARN_UNUSED_RESULT static status_t p256_masked_scalar_write(const p256_masked_scalar_t *src, - const otbn_addr_t share0_addr, - const otbn_addr_t share1_addr) { - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kP256MaskedScalarShareWords, src->share0, share0_addr)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kP256MaskedScalarShareWords, src->share1, share1_addr)); - - // Write trailing 0s so that OTBN's 256-bit read of the second share does not + const acc_addr_t share0_addr, + const acc_addr_t share1_addr) { + ACC_WIPE_IF_ERROR( + acc_dmem_write(kP256MaskedScalarShareWords, src->share0, share0_addr)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kP256MaskedScalarShareWords, src->share1, share1_addr)); + + // Write trailing 0s so that ACC's 256-bit read of the second share does not // cause an error. - OTBN_WIPE_IF_ERROR(otbn_dmem_set(kMaskedScalarPaddingWords, 0, - share0_addr + kP256MaskedScalarShareBytes)); - return otbn_dmem_set(kMaskedScalarPaddingWords, 0, - share1_addr + kP256MaskedScalarShareBytes); + ACC_WIPE_IF_ERROR(acc_dmem_set(kMaskedScalarPaddingWords, 0, + share0_addr + kP256MaskedScalarShareBytes)); + return acc_dmem_set(kMaskedScalarPaddingWords, 0, + share1_addr + kP256MaskedScalarShareBytes); } status_t p256_keygen_start(void) { - // Load the P-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + // Load the P-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into keygen. - uint32_t mode = kOtbnP256ModeKeygen; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeKeygen; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p256_sideload_keygen_start(void) { - // Load the P-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + // Load the P-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into sideload-keygen. - uint32_t mode = kOtbnP256ModeSideloadKeygen; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeSideloadKeygen; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p256_keygen_finalize(p256_masked_scalar_t *private_key, p256_point_t *public_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP256KeygenMinInstructionCount, - kP256KeygenMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP256KeygenMinInstructionCount, + kP256KeygenMaxInstructionCount); - // Read the masked private key from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256MaskedScalarShareWords, kOtbnVarD0, - private_key->share0)); - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256MaskedScalarShareWords, kOtbnVarD1, - private_key->share1)); + // Read the masked private key from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256MaskedScalarShareWords, kAccVarD0, + private_key->share0)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256MaskedScalarShareWords, kAccVarD1, + private_key->share1)); - // Read the public key from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256CoordWords, kOtbnVarX, public_key->x)); - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256CoordWords, kOtbnVarY, public_key->y)); + // Read the public key from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256CoordWords, kAccVarX, public_key->x)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256CoordWords, kAccVarY, public_key->y)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p256_sideload_keygen_finalize(p256_point_t *public_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP256SideloadKeygenMinInstructionCount, - kP256SideloadKeygenMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP256SideloadKeygenMinInstructionCount, + kP256SideloadKeygenMaxInstructionCount); - // Read the public key from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256CoordWords, kOtbnVarX, public_key->x)); - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256CoordWords, kOtbnVarY, public_key->y)); + // Read the public key from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256CoordWords, kAccVarX, public_key->x)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256CoordWords, kAccVarY, public_key->y)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } /** * Set the message digest for signature generation or verification. * - * OTBN requires the digest in little-endian form, so this routine flips the + * ACC requires the digest in little-endian form, so this routine flips the * bytes. * * @param digest Digest to set (big-endian). @@ -179,7 +179,7 @@ status_t p256_sideload_keygen_finalize(p256_point_t *public_key) { */ OT_WARN_UNUSED_RESULT static status_t set_message_digest(const uint32_t digest[kP256ScalarWords]) { - // Set the message digest. We swap all the bytes so that OTBN can interpret + // Set the message digest. We swap all the bytes so that ACC can interpret // the digest as a little-endian integer, which is a more natural fit for the // architecture than the big-endian form requested by the specification (FIPS // 186-5, section B.2.1). @@ -190,241 +190,241 @@ static status_t set_message_digest(const uint32_t digest[kP256ScalarWords]) { __builtin_bswap32(digest[kP256ScalarWords - 1 - i]); } HARDENED_CHECK_EQ(i, kP256ScalarWords); - return otbn_dmem_write(kP256ScalarWords, digest_little_endian, kOtbnVarMsg); + return acc_dmem_write(kP256ScalarWords, digest_little_endian, kAccVarMsg); } status_t p256_public_key_check_start(p256_point_t *public_key) { - // Load the P-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + // Load the P-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into signing. - uint32_t mode = kOtbnP256ModeKeyCheck; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeKeyCheck; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); // Set the public key x coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->x, kOtbnVarX)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->x, kAccVarX)); // Set the public key y coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->y, kOtbnVarY)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->y, kAccVarY)); - // Start the OTBN routine. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start the ACC routine. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } status_t p256_public_key_check_finalize(hardened_bool_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the status code out of DMEM (false if the public key is invalid) - HARDENED_TRY(otbn_dmem_read(1, kOtbnVarOk, result)); + HARDENED_TRY(acc_dmem_read(1, kAccVarOk, result)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p256_ecdsa_sign_start(const uint32_t digest[kP256ScalarWords], const p256_masked_scalar_t *private_key) { - // Load the P-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + // Load the P-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into signing. - uint32_t mode = kOtbnP256ModeSign; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeSign; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); // Set the message digest. HARDENED_TRY(set_message_digest(digest)); // Set the private key shares. - OTBN_WIPE_IF_ERROR( - p256_masked_scalar_write(private_key, kOtbnVarD0, kOtbnVarD1)); + ACC_WIPE_IF_ERROR( + p256_masked_scalar_write(private_key, kAccVarD0, kAccVarD1)); - // Start the OTBN routine. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start the ACC routine. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } status_t p256_ecdsa_sideload_sign_start( const uint32_t digest[kP256ScalarWords]) { - // Load the P-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + // Load the P-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into sideloaded signing. - uint32_t mode = kOtbnP256ModeSideloadSign; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeSideloadSign; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); // Set the message digest. HARDENED_TRY(set_message_digest(digest)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p256_ecdsa_sign_finalize(p256_ecdsa_signature_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP256SignMinInstructionCount, - kP256SignMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP256SignMinInstructionCount, + kP256SignMaxInstructionCount); - // Read signature R out of OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256ScalarWords, kOtbnVarR, result->r)); + // Read signature R out of ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256ScalarWords, kAccVarR, result->r)); - // Read signature S out of OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP256ScalarWords, kOtbnVarS, result->s)); + // Read signature S out of ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP256ScalarWords, kAccVarS, result->s)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p256_ecdsa_verify_start(const p256_ecdsa_signature_t *signature, const uint32_t digest[kP256ScalarWords], const p256_point_t *public_key) { // Load the P-256 app and set up data pointers - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into verifying. - uint32_t mode = kOtbnP256ModeVerify; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeVerify; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); // Set the message digest. HARDENED_TRY(set_message_digest(digest)); // Set the signature R. - HARDENED_TRY(otbn_dmem_write(kP256ScalarWords, signature->r, kOtbnVarR)); + HARDENED_TRY(acc_dmem_write(kP256ScalarWords, signature->r, kAccVarR)); // Set the signature S. - HARDENED_TRY(otbn_dmem_write(kP256ScalarWords, signature->s, kOtbnVarS)); + HARDENED_TRY(acc_dmem_write(kP256ScalarWords, signature->s, kAccVarS)); // Set the public key x coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->x, kOtbnVarX)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->x, kAccVarX)); // Set the public key y coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->y, kOtbnVarY)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->y, kAccVarY)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p256_ecdsa_verify_finalize(const p256_ecdsa_signature_t *signature, hardened_bool_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the status code out of DMEM (false if basic checks on the validity of // the signature and public key failed). uint32_t ok; - HARDENED_TRY(otbn_dmem_read(1, kOtbnVarOk, &ok)); + HARDENED_TRY(acc_dmem_read(1, kAccVarOk, &ok)); if (launder32(ok) != kHardenedBoolTrue) { return OTCRYPTO_BAD_ARGS; } HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP256VerifyMinInstructionCount, - kP256VerifyMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP256VerifyMinInstructionCount, + kP256VerifyMaxInstructionCount); - // Read x_r (recovered R) out of OTBN dmem. + // Read x_r (recovered R) out of ACC dmem. uint32_t x_r[kP256ScalarWords]; - HARDENED_TRY(otbn_dmem_read(kP256ScalarWords, kOtbnVarXr, x_r)); + HARDENED_TRY(acc_dmem_read(kP256ScalarWords, kAccVarXr, x_r)); *result = hardened_memeq(x_r, signature->r, kP256ScalarWords); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p256_ecdh_start(const p256_masked_scalar_t *private_key, const p256_point_t *public_key) { - // Load the P-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + // Load the P-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into shared-key generation. - uint32_t mode = kOtbnP256ModeEcdh; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeEcdh; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); // Set the public key x coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->x, kOtbnVarX)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->x, kAccVarX)); // Set the public key y coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->y, kOtbnVarY)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->y, kAccVarY)); // Set the private key shares. - OTBN_WIPE_IF_ERROR( - p256_masked_scalar_write(private_key, kOtbnVarD0, kOtbnVarD1)); + ACC_WIPE_IF_ERROR( + p256_masked_scalar_write(private_key, kAccVarD0, kAccVarD1)); - // Start the OTBN routine. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start the ACC routine. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } status_t p256_ecdh_finalize(p256_ecdh_shared_key_t *shared_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the code indicating if the public key is valid. uint32_t ok; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarOk, &ok)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarOk, &ok)); if (launder32(ok) != kHardenedBoolTrue) { return OTCRYPTO_BAD_ARGS; } HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP256EcdhMinInstructionCount, - kP256EcdhMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP256EcdhMinInstructionCount, + kP256EcdhMaxInstructionCount); - // Read the shares of the key from OTBN dmem (at vars x and y). - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP256CoordWords, kOtbnVarX, shared_key->share0)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP256CoordWords, kOtbnVarY, shared_key->share1)); + // Read the shares of the key from ACC dmem (at vars x and y). + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP256CoordWords, kAccVarX, shared_key->share0)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP256CoordWords, kAccVarY, shared_key->share1)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p256_sideload_ecdh_start(const p256_point_t *public_key) { - // Load the P-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP256)); + // Load the P-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP256)); // Set mode so start() will jump into shared-key generation. - uint32_t mode = kOtbnP256ModeSideloadEcdh; - HARDENED_TRY(otbn_dmem_write(kOtbnP256ModeWords, &mode, kOtbnVarMode)); + uint32_t mode = kAccP256ModeSideloadEcdh; + HARDENED_TRY(acc_dmem_write(kAccP256ModeWords, &mode, kAccVarMode)); // Set the public key x coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->x, kOtbnVarX)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->x, kAccVarX)); // Set the public key y coordinate. - HARDENED_TRY(otbn_dmem_write(kP256CoordWords, public_key->y, kOtbnVarY)); + HARDENED_TRY(acc_dmem_write(kP256CoordWords, public_key->y, kAccVarY)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p256_sideload_ecdh_finalize(p256_ecdh_shared_key_t *shared_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the code indicating if the public key is valid. uint32_t ok; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarOk, &ok)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarOk, &ok)); if (launder32(ok) != kHardenedBoolTrue) { return OTCRYPTO_BAD_ARGS; } HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP256SideloadEcdhMinInstructionCount, - kP256SideloadEcdhMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP256SideloadEcdhMinInstructionCount, + kP256SideloadEcdhMaxInstructionCount); - // Read the shares of the key from OTBN dmem (at vars x and y). - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP256CoordWords, kOtbnVarX, shared_key->share0)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP256CoordWords, kOtbnVarY, shared_key->share1)); + // Read the shares of the key from ACC dmem (at vars x and y). + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP256CoordWords, kAccVarX, shared_key->share0)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP256CoordWords, kAccVarY, shared_key->share1)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } diff --git a/sw/device/lib/crypto/impl/ecc/p256.h b/sw/device/lib/crypto/impl/ecc/p256.h index 47c9d21c3dc..6046b27bcc7 100644 --- a/sw/device/lib/crypto/impl/ecc/p256.h +++ b/sw/device/lib/crypto/impl/ecc/p256.h @@ -10,7 +10,7 @@ #include #include "sw/device/lib/base/hardened.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #ifdef __cplusplus extern "C" { @@ -111,11 +111,11 @@ typedef struct p256_ecdh_shared_key { } p256_ecdh_shared_key_t; /** - * Start an async P-256 keypair generation operation on OTBN. + * Start an async P-256 keypair generation operation on ACC. * * Appropriate for both ECDSA and ECDH; the key-generation process is the same. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @return Result of the operation (OK or error). */ @@ -123,9 +123,9 @@ OT_WARN_UNUSED_RESULT status_t p256_keygen_start(void); /** - * Finish an async P-256 keypair generation operation on OTBN. + * Finish an async P-256 keypair generation operation on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] private_key Generated private key. * @param[out] public_key Generated public key. @@ -136,12 +136,12 @@ status_t p256_keygen_finalize(p256_masked_scalar_t *private_key, p256_point_t *public_key); /** - * Start an async P-256 sideloaded keypair generation operation on OTBN. + * Start an async P-256 sideloaded keypair generation operation on ACC. * * Appropriate for both ECDSA and ECDH; the key-generation process is the same. * - * Expects a sideloaded key from keymgr to be already loaded on OTBN. Returns - * an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Expects a sideloaded key from keymgr to be already loaded on ACC. Returns + * an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @return Result of the operation (OK or error). */ @@ -149,10 +149,10 @@ OT_WARN_UNUSED_RESULT status_t p256_sideload_keygen_start(void); /** - * Finish an async P-256 sideloaded keypair generation operation on OTBN. + * Finish an async P-256 sideloaded keypair generation operation on ACC. * * This routine will only read back the public key, instead of both public and - * private as with `p256_ecdsa_keygen_finalize`. Blocks until OTBN is idle. + * private as with `p256_ecdsa_keygen_finalize`. Blocks until ACC is idle. * * @param[out] public_key Public key. * @return Result of the operation (OK or error). @@ -161,9 +161,9 @@ OT_WARN_UNUSED_RESULT status_t p256_sideload_keygen_finalize(p256_point_t *public_key); /** - * Start a P-256 public key on-curve check on OTBN. + * Start a P-256 public key on-curve check on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[in] public_key Generated public key. * @return Result of the operation (OK or error). @@ -172,9 +172,9 @@ OT_WARN_UNUSED_RESULT status_t p256_public_key_check_start(p256_point_t *public_key); /** - * Finish a P-256 public key on-curve check on OTBN. + * Finish a P-256 public key on-curve check on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] reuslt Result of on-curve check. * @return Result of the operation (OK or error). @@ -183,9 +183,9 @@ OT_WARN_UNUSED_RESULT status_t p256_public_key_check_finalize(hardened_bool_t *result); /** - * Start an async ECDSA/P-256 signature generation operation on OTBN. + * Start an async ECDSA/P-256 signature generation operation on ACC. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param digest Digest of the message to sign. * @param private_key Secret key to sign the message with. @@ -196,10 +196,10 @@ status_t p256_ecdsa_sign_start(const uint32_t digest[kP256ScalarWords], const p256_masked_scalar_t *private_key); /** - * Start an async ECDSA/P-256 signature generation operation on OTBN. + * Start an async ECDSA/P-256 signature generation operation on ACC. * - * Expects a sideloaded key from keymgr to be already loaded on OTBN. Returns - * an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Expects a sideloaded key from keymgr to be already loaded on ACC. Returns + * an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param digest Digest of the message to sign. * @return Result of the operation (OK or error). @@ -209,11 +209,11 @@ status_t p256_ecdsa_sideload_sign_start( const uint32_t digest[kP256ScalarWords]); /** - * Finish an async ECDSA/P-256 signature generation operation on OTBN. + * Finish an async ECDSA/P-256 signature generation operation on ACC. * * See the documentation of `p256_ecdsa_sign` for details. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] result Buffer in which to store the generated signature. * @return Result of the operation (OK or error). @@ -222,11 +222,11 @@ OT_WARN_UNUSED_RESULT status_t p256_ecdsa_sign_finalize(p256_ecdsa_signature_t *result); /** - * Start an async ECDSA/P-256 signature verification operation on OTBN. + * Start an async ECDSA/P-256 signature verification operation on ACC. * * See the documentation of `p256_ecdsa_verify` for details. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param signature Signature to be verified. * @param digest Digest of the message to check the signature against. @@ -239,11 +239,11 @@ status_t p256_ecdsa_verify_start(const p256_ecdsa_signature_t *signature, const p256_point_t *public_key); /** - * Finish an async ECDSA/P-256 signature verification operation on OTBN. + * Finish an async ECDSA/P-256 signature verification operation on ACC. * * See the documentation of `p256_ecdsa_verify` for details. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * If the signature is valid, writes `kHardenedBoolTrue` to `result`; * otherwise, writes `kHardenedBoolFalse`. @@ -263,9 +263,9 @@ status_t p256_ecdsa_verify_finalize(const p256_ecdsa_signature_t *signature, hardened_bool_t *result); /** - * Start an async ECDH/P-256 shared key generation operation on OTBN. + * Start an async ECDH/P-256 shared key generation operation on ACC. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key Private key (d). * @param public_key Public key (Q). @@ -276,9 +276,9 @@ status_t p256_ecdh_start(const p256_masked_scalar_t *private_key, const p256_point_t *public_key); /** - * Finish an async ECDH/P-256 shared key generation operation on OTBN. + * Finish an async ECDH/P-256 shared key generation operation on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] shared_key Shared secret key (x-coordinate of d*Q). * @return Result of the operation (OK or error). @@ -287,12 +287,12 @@ OT_WARN_UNUSED_RESULT status_t p256_ecdh_finalize(p256_ecdh_shared_key_t *shared_key); /** - * Start an async ECDH/P-256 shared key generation operation on OTBN. + * Start an async ECDH/P-256 shared key generation operation on ACC. * * Uses a private key generated from a key manager seed. The key manager should - * already have sideloaded the key into OTBN before this operation is called. + * already have sideloaded the key into ACC before this operation is called. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key Public key (Q). * @return Result of the operation (OK or error). @@ -301,12 +301,12 @@ OT_WARN_UNUSED_RESULT status_t p256_sideload_ecdh_start(const p256_point_t *public_key); /** - * Finish an async ECDH/P-256 shared key generation operation on OTBN. + * Finish an async ECDH/P-256 shared key generation operation on ACC. * * Uses a private key generated from a key manager seed. The key manager should - * already have sideloaded the key into OTBN before this operation is called. + * already have sideloaded the key into ACC before this operation is called. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] shared_key Shared secret key (x-coordinate of d*Q). * @return Result of the operation (OK or error). diff --git a/sw/device/lib/crypto/impl/ecc/p384.c b/sw/device/lib/crypto/impl/ecc/p384.c index e0b54766385..35194106ccf 100644 --- a/sw/device/lib/crypto/impl/ecc/p384.c +++ b/sw/device/lib/crypto/impl/ecc/p384.c @@ -10,7 +10,7 @@ #include "sw/device/lib/base/hardened.h" #include "sw/device/lib/base/hardened_memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/ecc/p384_insn_counts.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" @@ -18,54 +18,54 @@ // Module ID for status codes. #define MODULE_ID MAKE_MODULE_ID('p', '3', 'r') -// Declare the OTBN app. -OTBN_DECLARE_APP_SYMBOLS(run_p384); -static const otbn_app_t kOtbnAppP384 = OTBN_APP_T_INIT(run_p384); +// Declare the ACC app. +ACC_DECLARE_APP_SYMBOLS(run_p384); +static const acc_app_t kAccAppP384 = ACC_APP_T_INIT(run_p384); // Declare offsets for input and output buffers. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, mode); // Mode of operation. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, msg); // ECDSA message digest. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, r); // ECDSA signature scalar R. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, s); // ECDSA signature scalar S. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, x); // Public key x-coordinate. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, y); // Public key y-coordinate. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, d0_io); // Private key scalar d (share 0). -OTBN_DECLARE_SYMBOL_ADDR(run_p384, d1_io); // Private key scalar d (share 1). -OTBN_DECLARE_SYMBOL_ADDR(run_p384, x_r); // ECDSA verification result. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, ok); // Status code. - -static const otbn_addr_t kOtbnVarMode = OTBN_ADDR_T_INIT(run_p384, mode); -static const otbn_addr_t kOtbnVarMsg = OTBN_ADDR_T_INIT(run_p384, msg); -static const otbn_addr_t kOtbnVarR = OTBN_ADDR_T_INIT(run_p384, r); -static const otbn_addr_t kOtbnVarS = OTBN_ADDR_T_INIT(run_p384, s); -static const otbn_addr_t kOtbnVarX = OTBN_ADDR_T_INIT(run_p384, x); -static const otbn_addr_t kOtbnVarY = OTBN_ADDR_T_INIT(run_p384, y); -static const otbn_addr_t kOtbnVarD0 = OTBN_ADDR_T_INIT(run_p384, d0_io); -static const otbn_addr_t kOtbnVarD1 = OTBN_ADDR_T_INIT(run_p384, d1_io); -static const otbn_addr_t kOtbnVarXr = OTBN_ADDR_T_INIT(run_p384, x_r); -static const otbn_addr_t kOtbnVarOk = OTBN_ADDR_T_INIT(run_p384, ok); +ACC_DECLARE_SYMBOL_ADDR(run_p384, mode); // Mode of operation. +ACC_DECLARE_SYMBOL_ADDR(run_p384, msg); // ECDSA message digest. +ACC_DECLARE_SYMBOL_ADDR(run_p384, r); // ECDSA signature scalar R. +ACC_DECLARE_SYMBOL_ADDR(run_p384, s); // ECDSA signature scalar S. +ACC_DECLARE_SYMBOL_ADDR(run_p384, x); // Public key x-coordinate. +ACC_DECLARE_SYMBOL_ADDR(run_p384, y); // Public key y-coordinate. +ACC_DECLARE_SYMBOL_ADDR(run_p384, d0_io); // Private key scalar d (share 0). +ACC_DECLARE_SYMBOL_ADDR(run_p384, d1_io); // Private key scalar d (share 1). +ACC_DECLARE_SYMBOL_ADDR(run_p384, x_r); // ECDSA verification result. +ACC_DECLARE_SYMBOL_ADDR(run_p384, ok); // Status code. + +static const acc_addr_t kAccVarMode = ACC_ADDR_T_INIT(run_p384, mode); +static const acc_addr_t kAccVarMsg = ACC_ADDR_T_INIT(run_p384, msg); +static const acc_addr_t kAccVarR = ACC_ADDR_T_INIT(run_p384, r); +static const acc_addr_t kAccVarS = ACC_ADDR_T_INIT(run_p384, s); +static const acc_addr_t kAccVarX = ACC_ADDR_T_INIT(run_p384, x); +static const acc_addr_t kAccVarY = ACC_ADDR_T_INIT(run_p384, y); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(run_p384, d0_io); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(run_p384, d1_io); +static const acc_addr_t kAccVarXr = ACC_ADDR_T_INIT(run_p384, x_r); +static const acc_addr_t kAccVarOk = ACC_ADDR_T_INIT(run_p384, ok); // Declare mode constants. -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_KEYGEN); -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_KEY_CHECK); -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIGN); -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_VERIFY); -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_ECDH); -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIDELOAD_KEYGEN); -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIDELOAD_SIGN); -OTBN_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIDELOAD_ECDH); -static const uint32_t kP384ModeKeygen = OTBN_ADDR_T_INIT(run_p384, MODE_KEYGEN); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_KEYGEN); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_KEY_CHECK); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIGN); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_VERIFY); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_ECDH); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIDELOAD_KEYGEN); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIDELOAD_SIGN); +ACC_DECLARE_SYMBOL_ADDR(run_p384, MODE_SIDELOAD_ECDH); +static const uint32_t kP384ModeKeygen = ACC_ADDR_T_INIT(run_p384, MODE_KEYGEN); static const uint32_t kP384ModeKeyCheck = - OTBN_ADDR_T_INIT(run_p384, MODE_KEY_CHECK); -static const uint32_t kP384ModeSign = OTBN_ADDR_T_INIT(run_p384, MODE_SIGN); -static const uint32_t kP384ModeVerify = OTBN_ADDR_T_INIT(run_p384, MODE_VERIFY); -static const uint32_t kP384ModeEcdh = OTBN_ADDR_T_INIT(run_p384, MODE_ECDH); + ACC_ADDR_T_INIT(run_p384, MODE_KEY_CHECK); +static const uint32_t kP384ModeSign = ACC_ADDR_T_INIT(run_p384, MODE_SIGN); +static const uint32_t kP384ModeVerify = ACC_ADDR_T_INIT(run_p384, MODE_VERIFY); +static const uint32_t kP384ModeEcdh = ACC_ADDR_T_INIT(run_p384, MODE_ECDH); static const uint32_t kP384ModeSideloadKeygen = - OTBN_ADDR_T_INIT(run_p384, MODE_SIDELOAD_KEYGEN); + ACC_ADDR_T_INIT(run_p384, MODE_SIDELOAD_KEYGEN); static const uint32_t kP384ModeSideloadSign = - OTBN_ADDR_T_INIT(run_p384, MODE_SIDELOAD_SIGN); + ACC_ADDR_T_INIT(run_p384, MODE_SIDELOAD_SIGN); static const uint32_t kP384ModeSideloadEcdh = - OTBN_ADDR_T_INIT(run_p384, MODE_SIDELOAD_ECDH); + ACC_ADDR_T_INIT(run_p384, MODE_SIDELOAD_ECDH); enum { /* @@ -81,38 +81,38 @@ enum { * The extra outer "% W" ensures that the padding is 0 if (S % W) is 0. */ kMaskedScalarPaddingWords = - (kOtbnWideWordNumWords - - (kP384MaskedScalarShareWords % kOtbnWideWordNumWords)) % - kOtbnWideWordNumWords, + (kAccWideWordNumWords - + (kP384MaskedScalarShareWords % kAccWideWordNumWords)) % + kAccWideWordNumWords, /** * Number of extra padding words needed for unmasked scalars. */ kScalarPaddingWords = - (kOtbnWideWordNumWords - (kP384ScalarWords % kOtbnWideWordNumWords)) % - kOtbnWideWordNumWords, + (kAccWideWordNumWords - (kP384ScalarWords % kAccWideWordNumWords)) % + kAccWideWordNumWords, /** * Number of extra padding words needed for unmasked coordinates. */ kCoordPaddingWords = - (kOtbnWideWordNumWords - (kP384CoordWords % kOtbnWideWordNumWords)) % - kOtbnWideWordNumWords, + (kAccWideWordNumWords - (kP384CoordWords % kAccWideWordNumWords)) % + kAccWideWordNumWords, }; OT_WARN_UNUSED_RESULT static status_t p384_masked_scalar_write(const p384_masked_scalar_t *src, - const otbn_addr_t share0_addr, - const otbn_addr_t share1_addr) { + const acc_addr_t share0_addr, + const acc_addr_t share1_addr) { HARDENED_TRY( - otbn_dmem_write(kP384MaskedScalarShareWords, src->share0, share0_addr)); + acc_dmem_write(kP384MaskedScalarShareWords, src->share0, share0_addr)); HARDENED_TRY( - otbn_dmem_write(kP384MaskedScalarShareWords, src->share1, share1_addr)); + acc_dmem_write(kP384MaskedScalarShareWords, src->share1, share1_addr)); - // Write trailing 0s so that OTBN's 384-bit read of the second share does not + // Write trailing 0s so that ACC's 384-bit read of the second share does not // cause an error. - HARDENED_TRY(otbn_dmem_set(kMaskedScalarPaddingWords, 0, - share0_addr + kP384MaskedScalarShareBytes)); - return otbn_dmem_set(kMaskedScalarPaddingWords, 0, - share1_addr + kP384MaskedScalarShareBytes); + HARDENED_TRY(acc_dmem_set(kMaskedScalarPaddingWords, 0, + share0_addr + kP384MaskedScalarShareBytes)); + return acc_dmem_set(kMaskedScalarPaddingWords, 0, + share1_addr + kP384MaskedScalarShareBytes); } /** @@ -123,10 +123,10 @@ static status_t p384_masked_scalar_write(const p384_masked_scalar_t *src, */ OT_WARN_UNUSED_RESULT static status_t p384_scalar_write(const uint32_t src[kP384ScalarWords], - const otbn_addr_t addr) { - HARDENED_TRY(otbn_dmem_write(kP384ScalarWords, src, addr)); + const acc_addr_t addr) { + HARDENED_TRY(acc_dmem_write(kP384ScalarWords, src, addr)); - return otbn_dmem_set(kScalarPaddingWords, 0, addr + kP384ScalarBytes); + return acc_dmem_set(kScalarPaddingWords, 0, addr + kP384ScalarBytes); } /** @@ -136,18 +136,17 @@ static status_t p384_scalar_write(const uint32_t src[kP384ScalarWords], */ OT_WARN_UNUSED_RESULT static status_t set_public_key(const p384_point_t *p) { - HARDENED_TRY(otbn_dmem_write(kP384CoordWords, p->x, kOtbnVarX)); - HARDENED_TRY(otbn_dmem_write(kP384CoordWords, p->y, kOtbnVarY)); + HARDENED_TRY(acc_dmem_write(kP384CoordWords, p->x, kAccVarX)); + HARDENED_TRY(acc_dmem_write(kP384CoordWords, p->y, kAccVarY)); - HARDENED_TRY( - otbn_dmem_set(kCoordPaddingWords, 0, kOtbnVarX + kP384CoordBytes)); - return otbn_dmem_set(kCoordPaddingWords, 0, kOtbnVarY + kP384CoordBytes); + HARDENED_TRY(acc_dmem_set(kCoordPaddingWords, 0, kAccVarX + kP384CoordBytes)); + return acc_dmem_set(kCoordPaddingWords, 0, kAccVarY + kP384CoordBytes); } OT_WARN_UNUSED_RESULT static status_t set_message_digest(const uint32_t digest[kP384ScalarWords], - const otbn_addr_t dst) { - // Set the message digest. We swap all the bytes so that OTBN can interpret + const acc_addr_t dst) { + // Set the message digest. We swap all the bytes so that ACC can interpret // the digest as a little-endian integer, which is a more natural fit for the // architecture than the big-endian form requested by the specification (FIPS // 186-5, section B.2.1). @@ -162,290 +161,290 @@ static status_t set_message_digest(const uint32_t digest[kP384ScalarWords], } status_t p384_keygen_start(void) { - // Load the ECDH/P-384 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + // Load the ECDH/P-384 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into keygen. uint32_t mode = kP384ModeKeygen; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p384_keygen_finalize(p384_masked_scalar_t *private_key, p384_point_t *public_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP384KeygenMinInstructionCount, - kP384KeygenMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP384KeygenMinInstructionCount, + kP384KeygenMaxInstructionCount); - // Read the masked private key from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384MaskedScalarShareWords, kOtbnVarD0, - private_key->share0)); - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384MaskedScalarShareWords, kOtbnVarD1, - private_key->share1)); + // Read the masked private key from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384MaskedScalarShareWords, kAccVarD0, + private_key->share0)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384MaskedScalarShareWords, kAccVarD1, + private_key->share1)); - // Read the public key from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384CoordWords, kOtbnVarX, public_key->x)); - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384CoordWords, kOtbnVarY, public_key->y)); + // Read the public key from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384CoordWords, kAccVarX, public_key->x)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384CoordWords, kAccVarY, public_key->y)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p384_sideload_keygen_start(void) { - // Load the ECDH/P-384 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + // Load the ECDH/P-384 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into keygen. uint32_t mode = kP384ModeSideloadKeygen; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p384_sideload_keygen_finalize(p384_point_t *public_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP384SideloadKeygenMinInstructionCount, - kP384SideloadKeygenMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP384SideloadKeygenMinInstructionCount, + kP384SideloadKeygenMaxInstructionCount); - // Read the public key from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384CoordWords, kOtbnVarX, public_key->x)); - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384CoordWords, kOtbnVarY, public_key->y)); + // Read the public key from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384CoordWords, kAccVarX, public_key->x)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384CoordWords, kAccVarY, public_key->y)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p384_public_key_check_start(p384_point_t *public_key) { - // Load the P-384 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + // Load the P-384 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into signing. uint32_t mode = kP384ModeKeyCheck; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); // Set the public key. HARDENED_TRY(set_public_key(public_key)); - // Start the OTBN routine. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start the ACC routine. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } status_t p384_public_key_check_finalize(hardened_bool_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the status code out of DMEM (false if the public key is invalid) - HARDENED_TRY(otbn_dmem_read(1, kOtbnVarOk, result)); + HARDENED_TRY(acc_dmem_read(1, kAccVarOk, result)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p384_ecdsa_sign_start(const uint32_t digest[kP384ScalarWords], const p384_masked_scalar_t *private_key) { - // Load the ECDSA/P-384 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + // Load the ECDSA/P-384 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into sideloaded signing. uint32_t mode = kP384ModeSign; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); // Set the message digest. - HARDENED_TRY(set_message_digest(digest, kOtbnVarMsg)); + HARDENED_TRY(set_message_digest(digest, kAccVarMsg)); // Set the private key shares. - OTBN_WIPE_IF_ERROR( - p384_masked_scalar_write(private_key, kOtbnVarD0, kOtbnVarD1)); + ACC_WIPE_IF_ERROR( + p384_masked_scalar_write(private_key, kAccVarD0, kAccVarD1)); - // Start the OTBN routine. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start the ACC routine. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } status_t p384_ecdsa_sideload_sign_start( const uint32_t digest[kP384ScalarWords]) { - // Load the ECDSA/P-384 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + // Load the ECDSA/P-384 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into sideloaded signing. uint32_t mode = kP384ModeSideloadSign; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); // Set the message digest. - HARDENED_TRY(set_message_digest(digest, kOtbnVarMsg)); + HARDENED_TRY(set_message_digest(digest, kAccVarMsg)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p384_ecdsa_sign_finalize(p384_ecdsa_signature_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP384SignMinInstructionCount, - kP384SignMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP384SignMinInstructionCount, + kP384SignMaxInstructionCount); - // Read signature R out of OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384ScalarWords, kOtbnVarR, result->r)); + // Read signature R out of ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384ScalarWords, kAccVarR, result->r)); - // Read signature S out of OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(kP384ScalarWords, kOtbnVarS, result->s)); + // Read signature S out of ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(kP384ScalarWords, kAccVarS, result->s)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p384_ecdsa_verify_start(const p384_ecdsa_signature_t *signature, const uint32_t digest[kP384ScalarWords], const p384_point_t *public_key) { // Load the ECDSA/P-384 app - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into ECDSA verify. uint32_t mode = kP384ModeVerify; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); // Set the message digest. - HARDENED_TRY(set_message_digest(digest, kOtbnVarMsg)); + HARDENED_TRY(set_message_digest(digest, kAccVarMsg)); // Set the signature R. - HARDENED_TRY(p384_scalar_write(signature->r, kOtbnVarR)); + HARDENED_TRY(p384_scalar_write(signature->r, kAccVarR)); // Set the signature S. - HARDENED_TRY(p384_scalar_write(signature->s, kOtbnVarS)); + HARDENED_TRY(p384_scalar_write(signature->s, kAccVarS)); // Set the public key. HARDENED_TRY(set_public_key(public_key)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p384_ecdsa_verify_finalize(const p384_ecdsa_signature_t *signature, hardened_bool_t *result) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the status code out of DMEM (false if basic checks on the validity of // the signature and public key failed). uint32_t ok; - HARDENED_TRY(otbn_dmem_read(1, kOtbnVarOk, &ok)); + HARDENED_TRY(acc_dmem_read(1, kAccVarOk, &ok)); if (launder32(ok) != kHardenedBoolTrue) { return OTCRYPTO_BAD_ARGS; } HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP384VerifyMinInstructionCount, - kP384VerifyMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP384VerifyMinInstructionCount, + kP384VerifyMaxInstructionCount); - // Read x_r (recovered R) out of OTBN dmem. + // Read x_r (recovered R) out of ACC dmem. uint32_t x_r[kP384ScalarWords]; - HARDENED_TRY(otbn_dmem_read(kP384ScalarWords, kOtbnVarXr, x_r)); + HARDENED_TRY(acc_dmem_read(kP384ScalarWords, kAccVarXr, x_r)); *result = hardened_memeq(x_r, signature->r, kP384ScalarWords); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p384_ecdh_start(const p384_masked_scalar_t *private_key, const p384_point_t *public_key) { - // Load the ECDH/P-384 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + // Load the ECDH/P-384 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into shared-key generation. uint32_t mode = kP384ModeEcdh; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); // Set the public key. HARDENED_TRY(set_public_key(public_key)); // Set the private key shares. - OTBN_WIPE_IF_ERROR( - p384_masked_scalar_write(private_key, kOtbnVarD0, kOtbnVarD1)); + ACC_WIPE_IF_ERROR( + p384_masked_scalar_write(private_key, kAccVarD0, kAccVarD1)); - // Start the OTBN routine. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start the ACC routine. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } status_t p384_ecdh_finalize(p384_ecdh_shared_key_t *shared_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the status code out of DMEM (false if basic checks on the validity of // the signature and public key failed). uint32_t ok; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarOk, &ok)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarOk, &ok)); if (launder32(ok) != kHardenedBoolTrue) { return OTCRYPTO_BAD_ARGS; } HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP384EcdhMinInstructionCount, - kP384EcdhMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP384EcdhMinInstructionCount, + kP384EcdhMaxInstructionCount); - // Read the shares of the key from OTBN dmem (at vars x and y). - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP384CoordWords, kOtbnVarX, shared_key->share0)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP384CoordWords, kOtbnVarY, shared_key->share1)); + // Read the shares of the key from ACC dmem (at vars x and y). + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP384CoordWords, kAccVarX, shared_key->share0)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP384CoordWords, kAccVarY, shared_key->share1)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t p384_sideload_ecdh_start(const p384_point_t *public_key) { - // Load the ECDH/P-384 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppP384)); + // Load the ECDH/P-384 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppP384)); // Set mode so start() will jump into shared-key generation. uint32_t mode = kP384ModeSideloadEcdh; - HARDENED_TRY(otbn_dmem_write(kP384ModeWords, &mode, kOtbnVarMode)); + HARDENED_TRY(acc_dmem_write(kP384ModeWords, &mode, kAccVarMode)); // Set the public key. HARDENED_TRY(set_public_key(public_key)); - // Start the OTBN routine. - return otbn_execute(); + // Start the ACC routine. + return acc_execute(); } status_t p384_sideload_ecdh_finalize(p384_ecdh_shared_key_t *shared_key) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the status code out of DMEM (false if basic checks on the validity of // the signature and public key failed). uint32_t ok; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarOk, &ok)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarOk, &ok)); if (launder32(ok) != kHardenedBoolTrue) { return OTCRYPTO_BAD_ARGS; } HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kP384SideloadEcdhMinInstructionCount, - kP384SideloadEcdhMaxInstructionCount); + ACC_CHECK_INSN_COUNT(kP384SideloadEcdhMinInstructionCount, + kP384SideloadEcdhMaxInstructionCount); - // Read the shares of the key from OTBN dmem (at vars x and y). - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP384CoordWords, kOtbnVarX, shared_key->share0)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kP384CoordWords, kOtbnVarY, shared_key->share1)); + // Read the shares of the key from ACC dmem (at vars x and y). + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP384CoordWords, kAccVarX, shared_key->share0)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kP384CoordWords, kAccVarY, shared_key->share1)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } diff --git a/sw/device/lib/crypto/impl/ecc/p384.h b/sw/device/lib/crypto/impl/ecc/p384.h index f70ab81b316..9c96988f215 100644 --- a/sw/device/lib/crypto/impl/ecc/p384.h +++ b/sw/device/lib/crypto/impl/ecc/p384.h @@ -10,7 +10,7 @@ #include #include "sw/device/lib/base/hardened.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #ifdef __cplusplus extern "C" { @@ -111,11 +111,11 @@ typedef struct p384_ecdh_shared_key { } p384_ecdh_shared_key_t; /** - * Start an async P-384 keypair generation operation on OTBN. + * Start an async P-384 keypair generation operation on ACC. * * Appropriate for both ECDSA and ECDH; the key-generation process is the same. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @return Result of the operation (OK or error). */ @@ -123,9 +123,9 @@ OT_WARN_UNUSED_RESULT status_t p384_keygen_start(void); /** - * Finish an async P-384 keypair generation operation on OTBN. + * Finish an async P-384 keypair generation operation on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] private_key Generated private key. * @param[out] public_key Generated public key. @@ -136,12 +136,12 @@ status_t p384_keygen_finalize(p384_masked_scalar_t *private_key, p384_point_t *public_key); /** - * Start an async P-384 sideloaded keypair generation operation on OTBN. + * Start an async P-384 sideloaded keypair generation operation on ACC. * * Appropriate for both ECDSA and ECDH; the key-generation process is the same. * - * Expects a sideloaded key from keymgr to be already loaded on OTBN. Returns - * an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Expects a sideloaded key from keymgr to be already loaded on ACC. Returns + * an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @return Result of the operation (OK or error). */ @@ -149,10 +149,10 @@ OT_WARN_UNUSED_RESULT status_t p384_sideload_keygen_start(void); /** - * Finish an async P-384 sideloaded keypair generation operation on OTBN. + * Finish an async P-384 sideloaded keypair generation operation on ACC. * * This routine will only read back the public key, instead of both public and - * private as with `p384_ecdsa_keygen_finalize`. Blocks until OTBN is idle. + * private as with `p384_ecdsa_keygen_finalize`. Blocks until ACC is idle. * * @param[out] public_key Public key. * @return Result of the operation (OK or error). @@ -161,9 +161,9 @@ OT_WARN_UNUSED_RESULT status_t p384_sideload_keygen_finalize(p384_point_t *public_key); /** - * Start a P-384 public key on-curve check on OTBN. + * Start a P-384 public key on-curve check on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[in] public_key Generated public key. * @return Result of the operation (OK or error). @@ -172,9 +172,9 @@ OT_WARN_UNUSED_RESULT status_t p384_public_key_check_start(p384_point_t *public_key); /** - * Finish a P-384 public key on-curve check on OTBN. + * Finish a P-384 public key on-curve check on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] reuslt Result of on-curve check. * @return Result of the operation (OK or error). @@ -183,9 +183,9 @@ OT_WARN_UNUSED_RESULT status_t p384_public_key_check_finalize(hardened_bool_t *result); /** - * Start an async ECDSA/P-384 signature generation operation on OTBN. + * Start an async ECDSA/P-384 signature generation operation on ACC. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param digest Digest of the message to sign. * @param private_key Secret key to sign the message with. @@ -196,10 +196,10 @@ status_t p384_ecdsa_sign_start(const uint32_t digest[kP384ScalarWords], const p384_masked_scalar_t *private_key); /** - * Start an async ECDSA/P-384 signature generation operation on OTBN. + * Start an async ECDSA/P-384 signature generation operation on ACC. * - * Expects a sideloaded key from keymgr to be already loaded on OTBN. Returns - * an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Expects a sideloaded key from keymgr to be already loaded on ACC. Returns + * an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param digest Digest of the message to sign. * @return Result of the operation (OK or error). @@ -209,11 +209,11 @@ status_t p384_ecdsa_sideload_sign_start( const uint32_t digest[kP384ScalarWords]); /** - * Finish an async ECDSA/P-384 signature generation operation on OTBN. + * Finish an async ECDSA/P-384 signature generation operation on ACC. * * See the documentation of `p384_ecdsa_sign` for details. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] result Buffer in which to store the generated signature. * @return Result of the operation (OK or error). @@ -222,11 +222,11 @@ OT_WARN_UNUSED_RESULT status_t p384_ecdsa_sign_finalize(p384_ecdsa_signature_t *result); /** - * Start an async ECDSA/P-384 signature verification operation on OTBN. + * Start an async ECDSA/P-384 signature verification operation on ACC. * * See the documentation of `p384_ecdsa_verify` for details. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param signature Signature to be verified. * @param digest Digest of the message to check the signature against. @@ -239,11 +239,11 @@ status_t p384_ecdsa_verify_start(const p384_ecdsa_signature_t *signature, const p384_point_t *public_key); /** - * Finish an async ECDSA/P-384 signature verification operation on OTBN. + * Finish an async ECDSA/P-384 signature verification operation on ACC. * * See the documentation of `p384_ecdsa_verify` for details. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * If the signature is valid, writes `kHardenedBoolTrue` to `result`; * otherwise, writes `kHardenedBoolFalse`. @@ -263,9 +263,9 @@ status_t p384_ecdsa_verify_finalize(const p384_ecdsa_signature_t *signature, hardened_bool_t *result); /** - * Start an async ECDH/P-384 shared key generation operation on OTBN. + * Start an async ECDH/P-384 shared key generation operation on ACC. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key Private key (d). * @param public_key Public key (Q). @@ -276,9 +276,9 @@ status_t p384_ecdh_start(const p384_masked_scalar_t *private_key, const p384_point_t *public_key); /** - * Finish an async ECDH/P-384 shared key generation operation on OTBN. + * Finish an async ECDH/P-384 shared key generation operation on ACC. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] shared_key Shared secret key (x-coordinate of d*Q). * @return Result of the operation (OK or error). @@ -287,12 +287,12 @@ OT_WARN_UNUSED_RESULT status_t p384_ecdh_finalize(p384_ecdh_shared_key_t *shared_key); /** - * Start an async ECDH/P-384 shared key generation operation on OTBN. + * Start an async ECDH/P-384 shared key generation operation on ACC. * * Uses a private key generated from a key manager seed. The key manager should - * already have sideloaded the key into OTBN before this operation is called. + * already have sideloaded the key into ACC before this operation is called. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key Public key (Q). * @return Result of the operation (OK or error). @@ -301,12 +301,12 @@ OT_WARN_UNUSED_RESULT status_t p384_sideload_ecdh_start(const p384_point_t *public_key); /** - * Finish an async ECDH/P-384 shared key generation operation on OTBN. + * Finish an async ECDH/P-384 shared key generation operation on ACC. * * Uses a private key generated from a key manager seed. The key manager should - * already have sideloaded the key into OTBN before this operation is called. + * already have sideloaded the key into ACC before this operation is called. * - * Blocks until OTBN is idle. + * Blocks until ACC is idle. * * @param[out] shared_key Shared secret key (x-coordinate of d*Q). * @return Result of the operation (OK or error). diff --git a/sw/device/lib/crypto/impl/ecc_p256.c b/sw/device/lib/crypto/impl/ecc_p256.c index 06ebe3aa26c..200d6523fb3 100644 --- a/sw/device/lib/crypto/impl/ecc_p256.c +++ b/sw/device/lib/crypto/impl/ecc_p256.c @@ -7,9 +7,9 @@ #include "sw/device/lib/base/hardened.h" #include "sw/device/lib/base/hardened_memory.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" #include "sw/device/lib/crypto/drivers/hmac.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/ecc/p256.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/keyblob.h" @@ -153,7 +153,7 @@ otcrypto_status_t otcrypto_p256_public_key_construct_and_check( otcrypto_unblinded_key_t *public_key, hardened_bool_t *key_valid) { HARDENED_TRY(otcrypto_p256_public_key_construct_and_check_async_start( x, y, public_key, key_valid)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_p256_public_key_construct_and_check_async_finalize(key_valid); } @@ -299,7 +299,7 @@ otcrypto_status_t otcrypto_p256_private_key_deconstruct( otcrypto_status_t otcrypto_ecdsa_p256_keygen( otcrypto_blinded_key_t *private_key, otcrypto_unblinded_key_t *public_key) { HARDENED_TRY(otcrypto_ecdsa_p256_keygen_async_start(private_key)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdsa_p256_keygen_async_finalize(private_key, public_key); } @@ -309,7 +309,7 @@ otcrypto_status_t otcrypto_ecdsa_p256_sign( otcrypto_word32_buf_t signature) { HARDENED_TRY( otcrypto_ecdsa_p256_sign_async_start(private_key, message_digest)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdsa_p256_sign_async_finalize(signature); } @@ -320,7 +320,7 @@ otcrypto_status_t otcrypto_ecdsa_p256_verify( hardened_bool_t *verification_result) { HARDENED_TRY(otcrypto_ecdsa_p256_verify_async_start( public_key, message_digest, signature)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdsa_p256_verify_async_finalize(signature, verification_result); } @@ -351,7 +351,7 @@ otcrypto_status_t otcrypto_ecdsa_p256_sign_verify( otcrypto_status_t otcrypto_ecdh_p256_keygen( otcrypto_blinded_key_t *private_key, otcrypto_unblinded_key_t *public_key) { HARDENED_TRY(otcrypto_ecdh_p256_keygen_async_start(private_key)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdh_p256_keygen_async_finalize(private_key, public_key); } @@ -359,7 +359,7 @@ otcrypto_status_t otcrypto_ecdh_p256(const otcrypto_blinded_key_t *private_key, const otcrypto_unblinded_key_t *public_key, otcrypto_blinded_key_t *shared_secret) { HARDENED_TRY(otcrypto_ecdh_p256_async_start(private_key, public_key)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdh_p256_async_finalize(private_key, shared_secret); } @@ -380,7 +380,7 @@ static status_t internal_p256_keygen_start( if (launder32(private_key->config.hw_backed) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolTrue); - HARDENED_TRY(keyblob_sideload_key_otbn(private_key)); + HARDENED_TRY(keyblob_sideload_key_acc(private_key)); return p256_sideload_keygen_start(); } else if (launder32(private_key->config.hw_backed) == kHardenedBoolFalse) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolFalse); @@ -455,8 +455,8 @@ static status_t internal_p256_keygen_finalize( private_key->checksum = integrity_blinded_checksum(private_key); public_key->checksum = integrity_unblinded_checksum(public_key); - // Clear the OTBN sideload slot (in case the seed was sideloaded). - return keymgr_sideload_clear_otbn(); + // Clear the ACC sideload slot (in case the seed was sideloaded). + return keymgr_sideload_clear_acc(); } otcrypto_status_t otcrypto_ecdsa_p256_keygen_async_finalize( @@ -519,7 +519,7 @@ otcrypto_status_t otcrypto_ecdsa_p256_sign_async_start( } else if (launder32(private_key->config.hw_backed) == kHardenedBoolTrue) { // Load the key and start in sideloaded-key mode. HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolTrue); - HARDENED_TRY(keyblob_sideload_key_otbn(private_key)); + HARDENED_TRY(keyblob_sideload_key_acc(private_key)); HARDENED_TRY(p256_ecdsa_sideload_sign_start(message_digest.data)); } else { // Invalid value for private_key->hw_backed. @@ -572,8 +572,8 @@ otcrypto_status_t otcrypto_ecdsa_p256_sign_async_finalize( // last potentially error-causing line before returning to the caller. HARDENED_TRY(p256_ecdsa_sign_finalize(sig_p256)); - // Clear the OTBN sideload slot (in case the key was sideloaded). - return keymgr_sideload_clear_otbn(); + // Clear the ACC sideload slot (in case the key was sideloaded). + return keymgr_sideload_clear_acc(); } otcrypto_status_t otcrypto_ecdsa_p256_verify_async_start( @@ -711,7 +711,7 @@ otcrypto_status_t otcrypto_ecdh_p256_async_start( if (launder32(private_key->config.hw_backed) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolTrue); - HARDENED_TRY(keyblob_sideload_key_otbn(private_key)); + HARDENED_TRY(keyblob_sideload_key_acc(private_key)); HARDENED_TRY(p256_sideload_ecdh_start(pk)); } else if (launder32(private_key->config.hw_backed) == kHardenedBoolFalse) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolFalse); @@ -782,6 +782,6 @@ otcrypto_status_t otcrypto_ecdh_p256_async_finalize( // Set the checksum. shared_secret->checksum = integrity_blinded_checksum(shared_secret); - // Clear the OTBN sideload slot (in case the seed was sideloaded). - return keymgr_sideload_clear_otbn(); + // Clear the ACC sideload slot (in case the seed was sideloaded). + return keymgr_sideload_clear_acc(); } diff --git a/sw/device/lib/crypto/impl/ecc_p384.c b/sw/device/lib/crypto/impl/ecc_p384.c index 755b5b8e2ef..8d1f95752ab 100644 --- a/sw/device/lib/crypto/impl/ecc_p384.c +++ b/sw/device/lib/crypto/impl/ecc_p384.c @@ -151,7 +151,7 @@ otcrypto_status_t otcrypto_p384_public_key_construct_and_check( otcrypto_unblinded_key_t *public_key, hardened_bool_t *key_valid) { HARDENED_TRY(otcrypto_p384_public_key_construct_and_check_async_start( x, y, public_key, key_valid)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_p384_public_key_construct_and_check_async_finalize(key_valid); } @@ -297,7 +297,7 @@ otcrypto_status_t otcrypto_p384_private_key_deconstruct( otcrypto_status_t otcrypto_ecdsa_p384_keygen( otcrypto_blinded_key_t *private_key, otcrypto_unblinded_key_t *public_key) { HARDENED_TRY(otcrypto_ecdsa_p384_keygen_async_start(private_key)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdsa_p384_keygen_async_finalize(private_key, public_key); } @@ -307,7 +307,7 @@ otcrypto_status_t otcrypto_ecdsa_p384_sign( otcrypto_word32_buf_t signature) { HARDENED_TRY( otcrypto_ecdsa_p384_sign_async_start(private_key, message_digest)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdsa_p384_sign_async_finalize(signature); } @@ -318,7 +318,7 @@ otcrypto_status_t otcrypto_ecdsa_p384_verify( hardened_bool_t *verification_result) { HARDENED_TRY(otcrypto_ecdsa_p384_verify_async_start( public_key, message_digest, signature)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdsa_p384_verify_async_finalize(signature, verification_result); } @@ -349,7 +349,7 @@ otcrypto_status_t otcrypto_ecdsa_p384_sign_verify( otcrypto_status_t otcrypto_ecdh_p384_keygen( otcrypto_blinded_key_t *private_key, otcrypto_unblinded_key_t *public_key) { HARDENED_TRY(otcrypto_ecdh_p384_keygen_async_start(private_key)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdh_p384_keygen_async_finalize(private_key, public_key); } @@ -357,7 +357,7 @@ otcrypto_status_t otcrypto_ecdh_p384(const otcrypto_blinded_key_t *private_key, const otcrypto_unblinded_key_t *public_key, otcrypto_blinded_key_t *shared_secret) { HARDENED_TRY(otcrypto_ecdh_p384_async_start(private_key, public_key)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ecdh_p384_async_finalize(private_key, shared_secret); } @@ -378,7 +378,7 @@ static status_t internal_p384_keygen_start( if (launder32(private_key->config.hw_backed) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolTrue); - HARDENED_TRY(keyblob_sideload_key_otbn(private_key)); + HARDENED_TRY(keyblob_sideload_key_acc(private_key)); return p384_sideload_keygen_start(); } else if (launder32(private_key->config.hw_backed) == kHardenedBoolFalse) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolFalse); @@ -477,8 +477,8 @@ otcrypto_status_t otcrypto_ecdsa_p384_keygen_async_finalize( HARDENED_TRY(internal_p384_keygen_finalize(private_key, public_key)); - // Clear the OTBN sideload slot (in case the seed was sideloaded). - return keymgr_sideload_clear_otbn(); + // Clear the ACC sideload slot (in case the seed was sideloaded). + return keymgr_sideload_clear_acc(); } otcrypto_status_t otcrypto_ecdsa_p384_sign_async_start( @@ -522,7 +522,7 @@ otcrypto_status_t otcrypto_ecdsa_p384_sign_async_start( } else if (launder32(private_key->config.hw_backed) == kHardenedBoolTrue) { // Load the key and start in sideloaded-key mode. HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolTrue); - HARDENED_TRY(keyblob_sideload_key_otbn(private_key)); + HARDENED_TRY(keyblob_sideload_key_acc(private_key)); HARDENED_TRY(p384_ecdsa_sideload_sign_start(message_digest.data)); } else { // Invalid value for private_key->hw_backed. @@ -575,8 +575,8 @@ otcrypto_status_t otcrypto_ecdsa_p384_sign_async_finalize( // last potentially error-causing line before returning to the caller. HARDENED_TRY(p384_ecdsa_sign_finalize(sig_p384)); - // Clear the OTBN sideload slot (in case the key was sideloaded). - return keymgr_sideload_clear_otbn(); + // Clear the ACC sideload slot (in case the key was sideloaded). + return keymgr_sideload_clear_acc(); } otcrypto_status_t otcrypto_ecdsa_p384_verify_async_start( const otcrypto_unblinded_key_t *public_key, @@ -713,7 +713,7 @@ otcrypto_status_t otcrypto_ecdh_p384_async_start( if (launder32(private_key->config.hw_backed) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolTrue); - HARDENED_TRY(keyblob_sideload_key_otbn(private_key)); + HARDENED_TRY(keyblob_sideload_key_acc(private_key)); HARDENED_TRY(p384_sideload_ecdh_start(pk)); } else if (launder32(private_key->config.hw_backed) == kHardenedBoolFalse) { HARDENED_CHECK_EQ(private_key->config.hw_backed, kHardenedBoolFalse); @@ -783,6 +783,6 @@ otcrypto_status_t otcrypto_ecdh_p384_async_finalize( // Set the checksum. shared_secret->checksum = integrity_blinded_checksum(shared_secret); - // Clear the OTBN sideload slot (in case the seed was sideloaded). - return keymgr_sideload_clear_otbn(); + // Clear the ACC sideload slot (in case the seed was sideloaded). + return keymgr_sideload_clear_acc(); } diff --git a/sw/device/lib/crypto/impl/ed25519.c b/sw/device/lib/crypto/impl/ed25519.c index 0d595a344ca..2faf13ba295 100644 --- a/sw/device/lib/crypto/impl/ed25519.c +++ b/sw/device/lib/crypto/impl/ed25519.c @@ -9,8 +9,8 @@ #include "sw/device/lib/crypto/impl/ecc/ed25519.h" #include "sw/device/lib/base/math.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/status.h" #include "sw/device/lib/crypto/include/datatypes.h" @@ -31,7 +31,7 @@ otcrypto_status_t otcrypto_ed25519_sign( otcrypto_eddsa_sign_mode_t sign_mode, otcrypto_word32_buf_t signature) { HARDENED_TRY(otcrypto_ed25519_sign_async_start( private_key, input_message, context, sign_mode, signature)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ed25519_sign_async_finalize(signature); } @@ -42,7 +42,7 @@ otcrypto_status_t otcrypto_ed25519_verify( hardened_bool_t *verification_result) { HARDENED_TRY(otcrypto_ed25519_verify_async_start( public_key, input_message, context, sign_mode, signature)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_ed25519_verify_async_finalize(signature, verification_result); } diff --git a/sw/device/lib/crypto/impl/keyblob.c b/sw/device/lib/crypto/impl/keyblob.c index 3c7d1d969fc..45effe23e99 100644 --- a/sw/device/lib/crypto/impl/keyblob.c +++ b/sw/device/lib/crypto/impl/keyblob.c @@ -278,8 +278,8 @@ status_t keyblob_key_unmask(const otcrypto_blinded_key_t *key, return OTCRYPTO_OK; } -status_t keyblob_sideload_key_otbn(const otcrypto_blinded_key_t *key) { +status_t keyblob_sideload_key_acc(const otcrypto_blinded_key_t *key) { keymgr_diversification_t diversification; HARDENED_TRY(keyblob_to_keymgr_diversification(key, &diversification)); - return keymgr_generate_key_otbn(diversification); + return keymgr_generate_key_acc(diversification); } diff --git a/sw/device/lib/crypto/impl/keyblob.h b/sw/device/lib/crypto/impl/keyblob.h index ad3e86a2834..e34a0e2d7d9 100644 --- a/sw/device/lib/crypto/impl/keyblob.h +++ b/sw/device/lib/crypto/impl/keyblob.h @@ -202,7 +202,7 @@ status_t keyblob_key_unmask(const otcrypto_blinded_key_t *key, size_t unmasked_key_len, uint32_t *unmasked_key); /** - * Calls keymgr to sideload key material into OTBN. + * Calls keymgr to sideload key material into ACC. * * This routine should only ever be called on hardware-backed keys. * @@ -210,7 +210,7 @@ status_t keyblob_key_unmask(const otcrypto_blinded_key_t *key, * @return OK or error. */ OT_WARN_UNUSED_RESULT -status_t keyblob_sideload_key_otbn(const otcrypto_blinded_key_t *key); +status_t keyblob_sideload_key_acc(const otcrypto_blinded_key_t *key); #ifdef __cplusplus } // extern "C" diff --git a/sw/device/lib/crypto/impl/rsa.c b/sw/device/lib/crypto/impl/rsa.c index d5a78514d5b..adc1a4042d9 100644 --- a/sw/device/lib/crypto/impl/rsa.c +++ b/sw/device/lib/crypto/impl/rsa.c @@ -7,8 +7,8 @@ #include "sw/device/lib/base/hardened_memory.h" #include "sw/device/lib/base/math.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/rsa/rsa_datatypes.h" #include "sw/device/lib/crypto/impl/rsa/rsa_encryption.h" @@ -46,7 +46,7 @@ otcrypto_status_t otcrypto_rsa_keygen(otcrypto_rsa_size_t size, otcrypto_unblinded_key_t *public_key, otcrypto_blinded_key_t *private_key) { HARDENED_TRY(otcrypto_rsa_keygen_async_start(size)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_rsa_keygen_async_finalize(public_key, private_key); } @@ -438,7 +438,7 @@ otcrypto_status_t otcrypto_rsa_private_key_construct_and_check( hardened_bool_t *key_valid) { HARDENED_TRY(otcrypto_rsa_private_key_construct_and_check_async_start( p, q, d_p, d_q, i_q, public_key, check_primes, private_key, key_valid)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_rsa_private_key_construct_and_check_async_finalize( public_key, check_primes, private_key, key_valid); } @@ -636,7 +636,7 @@ otcrypto_status_t otcrypto_rsa_keypair_from_cofactor( otcrypto_unblinded_key_t *public_key, otcrypto_blinded_key_t *private_key) { HARDENED_TRY(otcrypto_rsa_keypair_from_cofactor_async_start( size, modulus, e, cofactor_share0, cofactor_share1)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); HARDENED_TRY(otcrypto_rsa_keypair_from_cofactor_async_finalize(public_key, private_key)); @@ -693,7 +693,7 @@ otcrypto_status_t otcrypto_rsa_sign(const otcrypto_blinded_key_t *private_key, otcrypto_word32_buf_t signature) { HARDENED_TRY( otcrypto_rsa_sign_async_start(private_key, message_digest, padding_mode)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_rsa_sign_async_finalize(signature); } @@ -703,7 +703,7 @@ otcrypto_status_t otcrypto_rsa_verify( otcrypto_rsa_padding_t padding_mode, otcrypto_const_word32_buf_t signature, hardened_bool_t *verification_result) { HARDENED_TRY(otcrypto_rsa_verify_async_start(public_key, signature)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_rsa_verify_async_finalize(public_key, message_digest, padding_mode, verification_result); } @@ -714,7 +714,7 @@ otcrypto_status_t otcrypto_rsa_encrypt( otcrypto_const_byte_buf_t label, otcrypto_word32_buf_t ciphertext) { HARDENED_TRY( otcrypto_rsa_encrypt_async_start(public_key, hash_mode, message, label)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_rsa_encrypt_async_finalize(public_key, ciphertext); } @@ -724,7 +724,7 @@ otcrypto_status_t otcrypto_rsa_decrypt( otcrypto_const_word32_buf_t ciphertext, otcrypto_const_byte_buf_t label, otcrypto_byte_buf_t plaintext, size_t *plaintext_bytelen) { HARDENED_TRY(otcrypto_rsa_decrypt_async_start(private_key, ciphertext)); - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); return otcrypto_rsa_decrypt_async_finalize(hash_mode, label, plaintext, plaintext_bytelen); } @@ -1364,7 +1364,7 @@ otcrypto_status_t otcrypto_rsa_decrypt_async_finalize( HARDENED_TRY(entropy_complex_check()); // Call the unified `finalize()` operation, which will infer the RSA size - // from OTBN. + // from ACC. HARDENED_TRY(rsa_decrypt_finalize(hash_mode, label.data, label.len, plaintext.len, plaintext.data, plaintext_bytelen)); diff --git a/sw/device/lib/crypto/impl/rsa/BUILD b/sw/device/lib/crypto/impl/rsa/BUILD index db7656aeb2a..6ec4b88d17c 100644 --- a/sw/device/lib/crypto/impl/rsa/BUILD +++ b/sw/device/lib/crypto/impl/rsa/BUILD @@ -6,7 +6,7 @@ package(default_visibility = ["//visibility:public"]) load("//rules/opentitan:defs.bzl", "OPENTITAN_CPU") -load("//rules:autogen.bzl", "autogen_otbn_insn_count_header") +load("//rules:autogen.bzl", "autogen_acc_insn_count_header") cc_library( name = "rsa_datatypes", @@ -36,12 +36,12 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":rsa_datatypes", + "//sw/acc/crypto:run_rsa_keygen", "//sw/device/lib/base:hardened", "//sw/device/lib/base:hardened_memory", "//sw/device/lib/base:memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:rv_core_ibex", - "//sw/otbn/crypto:run_rsa_keygen", ], ) @@ -53,8 +53,8 @@ cc_library( deps = [ ":rsa_datatypes", ":rsa_modexp_insn_counts", - "//sw/device/lib/crypto/drivers:otbn", - "//sw/otbn/crypto:run_rsa_modexp", + "//sw/acc/crypto:run_rsa_modexp", + "//sw/device/lib/crypto/drivers:acc", ], ) @@ -94,11 +94,11 @@ cc_library( ], ) -autogen_otbn_insn_count_header( +autogen_acc_insn_count_header( name = "rsa_modexp_insn_counts", hjson = "rsa_modexp_modes.hjson", template = "rsa_modexp_insn_counts.h.tpl", deps = [ - "//sw/otbn/crypto:run_rsa_modexp", + "//sw/acc/crypto:run_rsa_modexp", ], ) diff --git a/sw/device/lib/crypto/impl/rsa/rsa_encryption.c b/sw/device/lib/crypto/impl/rsa/rsa_encryption.c index ddc59b60ca0..283fe042902 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_encryption.c +++ b/sw/device/lib/crypto/impl/rsa/rsa_encryption.c @@ -111,7 +111,7 @@ status_t rsa_decrypt_finalize(const otcrypto_hash_mode_t hash_mode, const uint8_t *label, size_t label_bytelen, size_t plaintext_max_bytelen, uint8_t *plaintext, size_t *plaintext_len) { - // Get the result size, failing if the OTBN isn't done. + // Get the result size, failing if the ACC isn't done. size_t num_words; HARDENED_TRY(rsa_modexp_get_result_size(&num_words)); diff --git a/sw/device/lib/crypto/impl/rsa/rsa_encryption.h b/sw/device/lib/crypto/impl/rsa/rsa_encryption.h index 4c4e5ffec3a..2726d85cf39 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_encryption.h +++ b/sw/device/lib/crypto/impl/rsa/rsa_encryption.h @@ -25,7 +25,7 @@ extern "C" { * the hash function indicated by `hash_mode` and a salt the same length as the * hash function output. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key RSA public key. * @param hash_mode Hash function to use for message encoding. @@ -45,7 +45,7 @@ status_t rsa_encrypt_2048_start(const rsa_2048_public_key_t *public_key, * Waits for an RSA-2048 encryption to complete. * * Should be invoked only after a `rsa_encrypt_2048_start` call. Blocks until - * OTBN is done processing. + * ACC is done processing. * * @param[out] ciphertext Encrypted message. * @return Result of the operation (OK or error). @@ -57,7 +57,7 @@ status_t rsa_encrypt_2048_finalize(const rsa_2048_public_key_t *public_key, /** * Start decrypting a message with RSA-2048; returns immediately. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key RSA private key. * @param ciphertext Encrypted message. @@ -71,8 +71,8 @@ status_t rsa_decrypt_2048_start(const rsa_2048_private_key_t *private_key, * Waits for an RSA decryption to complete. * * Should be invoked only after an `rsa_decrypt_{size}_start`, but works for - * any RSA size. Blocks until OTBN is done processing, and then infers the size - * from the OTBN application mode. + * any RSA size. Blocks until ACC is done processing, and then infers the size + * from the ACC application mode. * * The only supported padding mode is OAEP (see IETF RFC 8017, section 7.1.2). * Only fixed-length hash functions (i.e. the SHA-2 or SHA-3 families) are @@ -113,7 +113,7 @@ status_t rsa_decrypt_finalize(const otcrypto_hash_mode_t hash_mode, * the hash function indicated by `hash_mode` and a salt the same length as the * hash function output. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key RSA public key. * @param hash_mode Hash function to use for message encoding. @@ -133,7 +133,7 @@ status_t rsa_encrypt_3072_start(const rsa_3072_public_key_t *public_key, * Waits for an RSA-3072 encryption to complete. * * Should be invoked only after a `rsa_encrypt_3072_start` call. Blocks until - * OTBN is done processing. + * ACC is done processing. * * @param[out] ciphertext Encrypted message. * @return Result of the operation (OK or error). @@ -145,7 +145,7 @@ status_t rsa_encrypt_3072_finalize(const rsa_3072_public_key_t *public_key, /** * Start decrypting a message with RSA-3072; returns immediately. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key RSA private key. * @param ciphertext Encrypted message. @@ -163,7 +163,7 @@ status_t rsa_decrypt_3072_start(const rsa_3072_private_key_t *private_key, * the hash function indicated by `hash_mode` and a salt the same length as the * hash function output. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key RSA public key. * @param hash_mode Hash function to use for message encoding. @@ -183,7 +183,7 @@ status_t rsa_encrypt_4096_start(const rsa_4096_public_key_t *public_key, * Waits for an RSA-4096 encryption to complete. * * Should be invoked only after a `rsa_encrypt_4096_start` call. Blocks until - * OTBN is done processing. + * ACC is done processing. * * @param[out] ciphertext Encrypted message. * @return Result of the operation (OK or error). @@ -195,7 +195,7 @@ status_t rsa_encrypt_4096_finalize(const rsa_4096_public_key_t *public_key, /** * Start decrypting a message with RSA-4096; returns immediately. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key RSA private key. * @param ciphertext Encrypted message. diff --git a/sw/device/lib/crypto/impl/rsa/rsa_keygen.c b/sw/device/lib/crypto/impl/rsa/rsa_keygen.c index b7366042bf3..480cfcbe106 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_keygen.c +++ b/sw/device/lib/crypto/impl/rsa/rsa_keygen.c @@ -7,88 +7,84 @@ #include "sw/device/lib/base/hardened.h" #include "sw/device/lib/base/hardened_memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/rsa/rsa_datatypes.h" // Module ID for status codes. #define MODULE_ID MAKE_MODULE_ID('r', 'k', 'g') -// Declare the OTBN app. -OTBN_DECLARE_APP_SYMBOLS(run_rsa_keygen); -static const otbn_app_t kOtbnAppRsaKeygen = OTBN_APP_T_INIT(run_rsa_keygen); +// Declare the ACC app. +ACC_DECLARE_APP_SYMBOLS(run_rsa_keygen); +static const acc_app_t kAccAppRsaKeygen = ACC_APP_T_INIT(run_rsa_keygen); // Declare offsets for input and output buffers. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, mode); // Application mode. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_n); // Modulus n. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_p); // Cofactor p. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_q); // Cofactor q. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, - rsa_d_p); // Private exponent component d_p. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, - rsa_d_q); // Private exponent component d_p. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_i_q); // CRT coefficient i_p. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_cofactor); // Cofactor p or q. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_e); // Public exponent e. - -static const otbn_addr_t kOtbnVarRsaMode = - OTBN_ADDR_T_INIT(run_rsa_keygen, mode); -static const otbn_addr_t kOtbnVarRsaN = OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_n); -static const otbn_addr_t kOtbnVarRsaP = OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_p); -static const otbn_addr_t kOtbnVarRsaQ = OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_q); -static const otbn_addr_t kOtbnVarRsaDp = - OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_d_p); -static const otbn_addr_t kOtbnVarRsaDq = - OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_d_q); -static const otbn_addr_t kOtbnVarRsaIq = - OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_i_q); -static const otbn_addr_t kOtbnVarRsaCofactor = - OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_cofactor); -static const otbn_addr_t kOtbnVarRsaE = OTBN_ADDR_T_INIT(run_rsa_keygen, rsa_e); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, mode); // Application mode. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_n); // Modulus n. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_p); // Cofactor p. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_q); // Cofactor q. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, + rsa_d_p); // Private exponent component d_p. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, + rsa_d_q); // Private exponent component d_p. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_i_q); // CRT coefficient i_p. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_cofactor); // Cofactor p or q. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, rsa_e); // Public exponent e. + +static const acc_addr_t kAccVarRsaMode = ACC_ADDR_T_INIT(run_rsa_keygen, mode); +static const acc_addr_t kAccVarRsaN = ACC_ADDR_T_INIT(run_rsa_keygen, rsa_n); +static const acc_addr_t kAccVarRsaP = ACC_ADDR_T_INIT(run_rsa_keygen, rsa_p); +static const acc_addr_t kAccVarRsaQ = ACC_ADDR_T_INIT(run_rsa_keygen, rsa_q); +static const acc_addr_t kAccVarRsaDp = ACC_ADDR_T_INIT(run_rsa_keygen, rsa_d_p); +static const acc_addr_t kAccVarRsaDq = ACC_ADDR_T_INIT(run_rsa_keygen, rsa_d_q); +static const acc_addr_t kAccVarRsaIq = ACC_ADDR_T_INIT(run_rsa_keygen, rsa_i_q); +static const acc_addr_t kAccVarRsaCofactor = + ACC_ADDR_T_INIT(run_rsa_keygen, rsa_cofactor); +static const acc_addr_t kAccVarRsaE = ACC_ADDR_T_INIT(run_rsa_keygen, rsa_e); // Declare mode constants. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_GEN_RSA_2048); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_COFACTOR_RSA_2048); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_RSA_2048); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_2048); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_GEN_RSA_3072); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_COFACTOR_RSA_3072); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_RSA_3072); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_3072); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_GEN_RSA_4096); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_COFACTOR_RSA_4096); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_RSA_4096); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_4096); -static const uint32_t kOtbnRsaModeGen2048 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_GEN_RSA_2048); -static const uint32_t kOtbnRsaModeCofactor2048 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_COFACTOR_RSA_2048); -static const uint32_t kOtbnRsaModeCheck2048 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_RSA_2048); -static const uint32_t kOtbnRsaModeCheckWithPrimes2048 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_2048); -static const uint32_t kOtbnRsaModeGen3072 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_GEN_RSA_3072); -static const uint32_t kOtbnRsaModeCofactor3072 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_COFACTOR_RSA_3072); -static const uint32_t kOtbnRsaModeCheck3072 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_RSA_3072); -static const uint32_t kOtbnRsaModeCheckWithPrimes3072 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_3072); -static const uint32_t kOtbnRsaModeGen4096 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_GEN_RSA_4096); -static const uint32_t kOtbnRsaModeCofactor4096 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_COFACTOR_RSA_4096); -static const uint32_t kOtbnRsaModeCheck4096 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_RSA_4096); -static const uint32_t kOtbnRsaModeCheckWithPrimes4096 = - OTBN_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_4096); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_GEN_RSA_2048); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_COFACTOR_RSA_2048); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_RSA_2048); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_2048); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_GEN_RSA_3072); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_COFACTOR_RSA_3072); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_RSA_3072); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_3072); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_GEN_RSA_4096); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_COFACTOR_RSA_4096); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_RSA_4096); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_4096); +static const uint32_t kAccRsaModeGen2048 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_GEN_RSA_2048); +static const uint32_t kAccRsaModeCofactor2048 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_COFACTOR_RSA_2048); +static const uint32_t kAccRsaModeCheck2048 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_RSA_2048); +static const uint32_t kAccRsaModeCheckWithPrimes2048 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_2048); +static const uint32_t kAccRsaModeGen3072 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_GEN_RSA_3072); +static const uint32_t kAccRsaModeCofactor3072 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_COFACTOR_RSA_3072); +static const uint32_t kAccRsaModeCheck3072 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_RSA_3072); +static const uint32_t kAccRsaModeCheckWithPrimes3072 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_3072); +static const uint32_t kAccRsaModeGen4096 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_GEN_RSA_4096); +static const uint32_t kAccRsaModeCofactor4096 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_COFACTOR_RSA_4096); +static const uint32_t kAccRsaModeCheck4096 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_RSA_4096); +static const uint32_t kAccRsaModeCheckWithPrimes4096 = + ACC_ADDR_T_INIT(run_rsa_keygen, MODE_CHECK_WITH_PRIMES_RSA_4096); enum { /* Fixed public exponent for generated keys. This exponent is 2^16 + 1, also known as "F4" because it's the fourth Fermat number. */ kFixedPublicExponent = 65537, /* Number of words used to represent the application mode. */ - kOtbnRsaModeWords = 1, + kAccRsaModeWords = 1, /* Number of bits for the private exponent (d) check value for key import. */ kPrivateExponentCheckBits = 256, /* Number of bytes for the private exponent (d) check value for key import. */ @@ -98,7 +94,7 @@ enum { }; /** - * Start the OTBN key generation program in random-key mode. + * Start the ACC key generation program in random-key mode. * * Cofactor mode should not use this routine, because it wipes DMEM and * cofactor mode requires input data. @@ -108,12 +104,12 @@ enum { */ OT_WARN_UNUSED_RESULT static status_t keygen_start(uint32_t mode) { - // Load the RSA key generation app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaKeygen)); + // Load the RSA key generation app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppRsaKeygen)); - // Set mode and start OTBN. - HARDENED_TRY(otbn_dmem_write(kOtbnRsaModeWords, &mode, kOtbnVarRsaMode)); - return otbn_execute(); + // Set mode and start ACC. + HARDENED_TRY(acc_dmem_write(kAccRsaModeWords, &mode, kAccVarRsaMode)); + return acc_execute(); } /** @@ -136,45 +132,45 @@ OT_WARN_UNUSED_RESULT static status_t keygen_finalize(uint32_t exp_mode, size_t num_words, uint32_t *n, uint32_t *p, uint32_t *q, uint32_t *d_p, uint32_t *d_q, uint32_t *i_q) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); - // Read the mode from OTBN dmem and panic if it's not as expected. + // Read the mode from ACC dmem and panic if it's not as expected. uint32_t act_mode = 0; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarRsaMode, &act_mode)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarRsaMode, &act_mode)); if (act_mode != exp_mode) { return OTCRYPTO_FATAL_ERR; } - // Read the public modulus (n) from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(num_words, kOtbnVarRsaN, n)); + // Read the public modulus (n) from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(num_words, kAccVarRsaN, n)); - // Read the first cofactor (p) from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(num_words / 2, kOtbnVarRsaP, p)); + // Read the first cofactor (p) from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(num_words / 2, kAccVarRsaP, p)); - // Read the first cofactor (q) from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(num_words / 2, kOtbnVarRsaQ, q)); + // Read the first cofactor (q) from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(num_words / 2, kAccVarRsaQ, q)); - // Read the first private exponent CRT component (d_p) from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(num_words / 2, kOtbnVarRsaDp, d_p)); + // Read the first private exponent CRT component (d_p) from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(num_words / 2, kAccVarRsaDp, d_p)); - // Read the second private expoent CRT component (d_q) from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(num_words / 2, kOtbnVarRsaDq, d_q)); + // Read the second private expoent CRT component (d_q) from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(num_words / 2, kAccVarRsaDq, d_q)); - // Read the CRT coefficient (i_q) from OTBN dmem. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(num_words / 2, kOtbnVarRsaIq, i_q)); + // Read the CRT coefficient (i_q) from ACC dmem. + ACC_WIPE_IF_ERROR(acc_dmem_read(num_words / 2, kAccVarRsaIq, i_q)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t rsa_keygen_2048_start(void) { - return keygen_start(kOtbnRsaModeGen2048); + return keygen_start(kAccRsaModeGen2048); } status_t rsa_keygen_2048_finalize(rsa_2048_public_key_t *public_key, rsa_2048_private_key_t *private_key) { - HARDENED_TRY(keygen_finalize(kOtbnRsaModeGen2048, kRsa2048NumWords, + HARDENED_TRY(keygen_finalize(kAccRsaModeGen2048, kRsa2048NumWords, public_key->n.data, private_key->p.data, private_key->q.data, private_key->d_p.data, private_key->d_q.data, private_key->i_q.data)); @@ -187,12 +183,12 @@ status_t rsa_keygen_2048_finalize(rsa_2048_public_key_t *public_key, } status_t rsa_keygen_3072_start(void) { - return keygen_start(kOtbnRsaModeGen3072); + return keygen_start(kAccRsaModeGen3072); } status_t rsa_keygen_3072_finalize(rsa_3072_public_key_t *public_key, rsa_3072_private_key_t *private_key) { - HARDENED_TRY(keygen_finalize(kOtbnRsaModeGen3072, kRsa3072NumWords, + HARDENED_TRY(keygen_finalize(kAccRsaModeGen3072, kRsa3072NumWords, public_key->n.data, private_key->p.data, private_key->q.data, private_key->d_p.data, private_key->d_q.data, private_key->i_q.data)); @@ -205,12 +201,12 @@ status_t rsa_keygen_3072_finalize(rsa_3072_public_key_t *public_key, } status_t rsa_keygen_4096_start(void) { - return keygen_start(kOtbnRsaModeGen4096); + return keygen_start(kAccRsaModeGen4096); } status_t rsa_keygen_4096_finalize(rsa_4096_public_key_t *public_key, rsa_4096_private_key_t *private_key) { - HARDENED_TRY(keygen_finalize(kOtbnRsaModeGen4096, kRsa4096NumWords, + HARDENED_TRY(keygen_finalize(kAccRsaModeGen4096, kRsa4096NumWords, public_key->n.data, private_key->p.data, private_key->q.data, private_key->d_p.data, private_key->d_q.data, private_key->i_q.data)); @@ -229,24 +225,24 @@ status_t rsa_keygen_from_cofactor_2048_start( return OTCRYPTO_BAD_ARGS; } - // Load the RSA key generation app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaKeygen)); + // Load the RSA key generation app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppRsaKeygen)); // Write the modulus and cofactor into DMEM. - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(public_key->n.data), - public_key->n.data, kOtbnVarRsaN)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(cofactor->data), cofactor->data, - kOtbnVarRsaCofactor)); - - // Set mode and start OTBN. - uint32_t mode = kOtbnRsaModeCofactor2048; - HARDENED_TRY(otbn_dmem_write(kOtbnRsaModeWords, &mode, kOtbnVarRsaMode)); - return otbn_execute(); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(public_key->n.data), public_key->n.data, + kAccVarRsaN)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(cofactor->data), cofactor->data, + kAccVarRsaCofactor)); + + // Set mode and start ACC. + uint32_t mode = kAccRsaModeCofactor2048; + HARDENED_TRY(acc_dmem_write(kAccRsaModeWords, &mode, kAccVarRsaMode)); + return acc_execute(); } status_t rsa_keygen_from_cofactor_2048_finalize( rsa_2048_public_key_t *public_key, rsa_2048_private_key_t *private_key) { - HARDENED_TRY(keygen_finalize(kOtbnRsaModeCofactor2048, kRsa2048NumWords, + HARDENED_TRY(keygen_finalize(kAccRsaModeCofactor2048, kRsa2048NumWords, public_key->n.data, private_key->p.data, private_key->q.data, private_key->d_p.data, private_key->d_q.data, private_key->i_q.data)); @@ -265,24 +261,24 @@ status_t rsa_keygen_from_cofactor_3072_start( return OTCRYPTO_BAD_ARGS; } - // Load the RSA key generation app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaKeygen)); + // Load the RSA key generation app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppRsaKeygen)); // Write the modulus and cofactor into DMEM. - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(public_key->n.data), - public_key->n.data, kOtbnVarRsaN)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(cofactor->data), cofactor->data, - kOtbnVarRsaCofactor)); - - // Set mode and start OTBN. - uint32_t mode = kOtbnRsaModeCofactor3072; - HARDENED_TRY(otbn_dmem_write(kOtbnRsaModeWords, &mode, kOtbnVarRsaMode)); - return otbn_execute(); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(public_key->n.data), public_key->n.data, + kAccVarRsaN)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(cofactor->data), cofactor->data, + kAccVarRsaCofactor)); + + // Set mode and start ACC. + uint32_t mode = kAccRsaModeCofactor3072; + HARDENED_TRY(acc_dmem_write(kAccRsaModeWords, &mode, kAccVarRsaMode)); + return acc_execute(); } status_t rsa_keygen_from_cofactor_3072_finalize( rsa_3072_public_key_t *public_key, rsa_3072_private_key_t *private_key) { - HARDENED_TRY(keygen_finalize(kOtbnRsaModeCofactor3072, kRsa3072NumWords, + HARDENED_TRY(keygen_finalize(kAccRsaModeCofactor3072, kRsa3072NumWords, public_key->n.data, private_key->p.data, private_key->q.data, private_key->d_p.data, private_key->d_q.data, private_key->i_q.data)); @@ -301,24 +297,24 @@ status_t rsa_keygen_from_cofactor_4096_start( return OTCRYPTO_BAD_ARGS; } - // Load the RSA key generation app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaKeygen)); + // Load the RSA key generation app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppRsaKeygen)); // Write the modulus and cofactor into DMEM. - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(public_key->n.data), - public_key->n.data, kOtbnVarRsaN)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(cofactor->data), cofactor->data, - kOtbnVarRsaCofactor)); - - // Set mode and start OTBN. - uint32_t mode = kOtbnRsaModeCofactor4096; - HARDENED_TRY(otbn_dmem_write(kOtbnRsaModeWords, &mode, kOtbnVarRsaMode)); - return otbn_execute(); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(public_key->n.data), public_key->n.data, + kAccVarRsaN)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(cofactor->data), cofactor->data, + kAccVarRsaCofactor)); + + // Set mode and start ACC. + uint32_t mode = kAccRsaModeCofactor4096; + HARDENED_TRY(acc_dmem_write(kAccRsaModeWords, &mode, kAccVarRsaMode)); + return acc_execute(); } status_t rsa_keygen_from_cofactor_4096_finalize( rsa_4096_public_key_t *public_key, rsa_4096_private_key_t *private_key) { - HARDENED_TRY(keygen_finalize(kOtbnRsaModeCofactor4096, kRsa4096NumWords, + HARDENED_TRY(keygen_finalize(kAccRsaModeCofactor4096, kRsa4096NumWords, public_key->n.data, private_key->p.data, private_key->q.data, private_key->d_p.data, private_key->d_q.data, private_key->i_q.data)); @@ -333,63 +329,63 @@ status_t rsa_keygen_from_cofactor_4096_finalize( status_t rsa_key_check_2048_start(const rsa_2048_public_key_t *public_key, const rsa_2048_private_key_t *private_key, hardened_bool_t check_primes) { - // Load the RSA key generation app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaKeygen)); + // Load the RSA key generation app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppRsaKeygen)); // Write the public exponent into DMEM, zero-extended to a full processor // word. - HARDENED_TRY(otbn_dmem_write(1, &public_key->e, kOtbnVarRsaE)); + HARDENED_TRY(acc_dmem_write(1, &public_key->e, kAccVarRsaE)); // Write the primes, CRT components of the private exponent, and CRT // coefficient into DMEM. - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->p.data), - private_key->p.data, kOtbnVarRsaP)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->q.data), - private_key->q.data, kOtbnVarRsaQ)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->d_p.data), - private_key->d_p.data, kOtbnVarRsaDp)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->d_q.data), - private_key->d_q.data, kOtbnVarRsaDq)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->i_q.data), - private_key->i_q.data, kOtbnVarRsaIq)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->p.data), + private_key->p.data, kAccVarRsaP)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->q.data), + private_key->q.data, kAccVarRsaQ)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->d_p.data), + private_key->d_p.data, kAccVarRsaDp)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->d_q.data), + private_key->d_q.data, kAccVarRsaDq)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->i_q.data), + private_key->i_q.data, kAccVarRsaIq)); // Select mode based on whether we should perform primality checks. uint32_t mode; if (launder32(check_primes) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(check_primes, kHardenedBoolTrue); - mode = kOtbnRsaModeCheckWithPrimes2048; + mode = kAccRsaModeCheckWithPrimes2048; } else { HARDENED_CHECK_EQ(check_primes, kHardenedBoolFalse); - mode = kOtbnRsaModeCheck2048; + mode = kAccRsaModeCheck2048; } - // Set mode and start OTBN. - HARDENED_TRY(otbn_dmem_write(kOtbnRsaModeWords, &mode, kOtbnVarRsaMode)); - return otbn_execute(); + // Set mode and start ACC. + HARDENED_TRY(acc_dmem_write(kAccRsaModeWords, &mode, kAccVarRsaMode)); + return acc_execute(); } status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, const rsa_2048_private_key_t *private_key, hardened_bool_t check_primes, hardened_bool_t *key_valid) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); - // Spin here waiting for OTBN to complete. - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + // Spin here waiting for ACC to complete. + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); - // Read the mode from OTBN dmem and panic if it's not as expected. + // Read the mode from ACC dmem and panic if it's not as expected. uint32_t act_mode = 0; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarRsaMode, &act_mode)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarRsaMode, &act_mode)); // Get the expected mode from provided arguments. uint32_t exp_mode = 0; if (launder32(check_primes) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(check_primes, kHardenedBoolTrue); - exp_mode = kOtbnRsaModeCheckWithPrimes2048; + exp_mode = kAccRsaModeCheckWithPrimes2048; } else { HARDENED_CHECK_EQ(check_primes, kHardenedBoolFalse); - exp_mode = kOtbnRsaModeCheck2048; + exp_mode = kAccRsaModeCheck2048; } // Ensure that the actual mode is the same as the expected mode. @@ -404,36 +400,35 @@ status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, one[0] = 1; // Read the value of the first CRT component (d_p) validity check value from - // OTBN dmem. + // ACC dmem. uint32_t dp_check[kRsa2048NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa2048NumWords / 2, kOtbnVarRsaDp, dp_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa2048NumWords / 2, kAccVarRsaDp, dp_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t dp_valid = hardened_memeq(one, dp_check, ARRAYSIZE(dp_check)); // Read the value of the second CRT component (d_q) validity check value - // from OTBN dmem. + // from ACC dmem. uint32_t dq_check[kRsa2048NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa2048NumWords / 2, kOtbnVarRsaDq, dq_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa2048NumWords / 2, kAccVarRsaDq, dq_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t dq_valid = hardened_memeq(one, dq_check, ARRAYSIZE(dq_check)); // Read the value of the CRT coefficient (i_q) validity check value - // from OTBN dmem. + // from ACC dmem. uint32_t iq_check[kRsa2048NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa2048NumWords / 2, kOtbnVarRsaIq, iq_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa2048NumWords / 2, kAccVarRsaIq, iq_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t iq_valid = hardened_memeq(one, iq_check, ARRAYSIZE(iq_check)); - // Read the recovered public modulus (n) from OTBN dmem. + // Read the recovered public modulus (n) from ACC dmem. uint32_t recovered_n[kRsa2048NumWords]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa2048NumWords, kOtbnVarRsaN, recovered_n)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kRsa2048NumWords, kAccVarRsaN, recovered_n)); // Check that this matches the public key modulus, and update the validity. hardened_bool_t n_valid = @@ -441,8 +436,8 @@ status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, // Read the private exponent (d) check value uint32_t d_check[kPrivateExponentCheckWords]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kPrivateExponentCheckWords, kOtbnVarRsaE, d_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kPrivateExponentCheckWords, kAccVarRsaE, d_check)); // Prepare a multi-limb all ones constant for comparing to in validity checks. uint32_t all_ones[kPrivateExponentCheckWords]; @@ -455,8 +450,8 @@ status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, if (launder32(check_primes) == kHardenedBoolTrue) { // Read the first prime (p) check value uint32_t p_check[kRsa2048NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa2048NumWords / 2, kOtbnVarRsaE, p_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa2048NumWords / 2, kAccVarRsaE, p_check)); // Check whether the first prime check value is all ones. hardened_bool_t p_valid = @@ -464,8 +459,8 @@ status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, // Read the second prime (q) check value uint32_t q_check[kRsa2048NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa2048NumWords / 2, kOtbnVarRsaE, q_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa2048NumWords / 2, kAccVarRsaE, q_check)); // Check whether the first prime check value is all ones. hardened_bool_t q_valid = @@ -504,69 +499,69 @@ status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, } // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t rsa_key_check_3072_start(const rsa_3072_public_key_t *public_key, const rsa_3072_private_key_t *private_key, hardened_bool_t check_primes) { - // Load the RSA key generation app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaKeygen)); + // Load the RSA key generation app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppRsaKeygen)); // Write the public exponent into DMEM, zero-extended to a full processor // word. - HARDENED_TRY(otbn_dmem_write(1, &public_key->e, kOtbnVarRsaE)); + HARDENED_TRY(acc_dmem_write(1, &public_key->e, kAccVarRsaE)); // Write the primes, CRT components of the private exponent, and CRT // coefficient into DMEM. - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->p.data), - private_key->p.data, kOtbnVarRsaP)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->q.data), - private_key->q.data, kOtbnVarRsaQ)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->d_p.data), - private_key->d_p.data, kOtbnVarRsaDp)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->d_q.data), - private_key->d_q.data, kOtbnVarRsaDq)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->i_q.data), - private_key->i_q.data, kOtbnVarRsaIq)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->p.data), + private_key->p.data, kAccVarRsaP)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->q.data), + private_key->q.data, kAccVarRsaQ)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->d_p.data), + private_key->d_p.data, kAccVarRsaDp)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->d_q.data), + private_key->d_q.data, kAccVarRsaDq)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->i_q.data), + private_key->i_q.data, kAccVarRsaIq)); // Select mode based on whether we should perform primality checks. uint32_t mode; if (launder32(check_primes) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(check_primes, kHardenedBoolTrue); - mode = kOtbnRsaModeCheckWithPrimes3072; + mode = kAccRsaModeCheckWithPrimes3072; } else { HARDENED_CHECK_EQ(check_primes, kHardenedBoolFalse); - mode = kOtbnRsaModeCheck3072; + mode = kAccRsaModeCheck3072; } - // Set mode and start OTBN. - HARDENED_TRY(otbn_dmem_write(kOtbnRsaModeWords, &mode, kOtbnVarRsaMode)); - return otbn_execute(); + // Set mode and start ACC. + HARDENED_TRY(acc_dmem_write(kAccRsaModeWords, &mode, kAccVarRsaMode)); + return acc_execute(); } status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, const rsa_3072_private_key_t *private_key, hardened_bool_t check_primes, hardened_bool_t *key_valid) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); - // Spin here waiting for OTBN to complete. - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + // Spin here waiting for ACC to complete. + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); - // Read the mode from OTBN dmem and panic if it's not as expected. + // Read the mode from ACC dmem and panic if it's not as expected. uint32_t act_mode = 0; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarRsaMode, &act_mode)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarRsaMode, &act_mode)); // Get the expected mode from provided arguments. uint32_t exp_mode = 0; if (launder32(check_primes) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(check_primes, kHardenedBoolTrue); - exp_mode = kOtbnRsaModeCheckWithPrimes3072; + exp_mode = kAccRsaModeCheckWithPrimes3072; } else { HARDENED_CHECK_EQ(check_primes, kHardenedBoolFalse); - exp_mode = kOtbnRsaModeCheck3072; + exp_mode = kAccRsaModeCheck3072; } // Ensure that the actual mode is the same as the expected mode. @@ -581,36 +576,35 @@ status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, one[0] = 1; // Read the value of the first CRT component (d_p) validity check value from - // OTBN dmem. + // ACC dmem. uint32_t dp_check[kRsa3072NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa3072NumWords / 2, kOtbnVarRsaDp, dp_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa3072NumWords / 2, kAccVarRsaDp, dp_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t dp_valid = hardened_memeq(one, dp_check, ARRAYSIZE(dp_check)); // Read the value of the second CRT component (d_q) validity check value - // from OTBN dmem. + // from ACC dmem. uint32_t dq_check[kRsa3072NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa3072NumWords / 2, kOtbnVarRsaDq, dq_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa3072NumWords / 2, kAccVarRsaDq, dq_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t dq_valid = hardened_memeq(one, dq_check, ARRAYSIZE(dq_check)); // Read the value of the CRT coefficient (i_q) validity check value - // from OTBN dmem. + // from ACC dmem. uint32_t iq_check[kRsa3072NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa3072NumWords / 2, kOtbnVarRsaIq, iq_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa3072NumWords / 2, kAccVarRsaIq, iq_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t iq_valid = hardened_memeq(one, iq_check, ARRAYSIZE(iq_check)); - // Read the recovered public modulus (n) from OTBN dmem. + // Read the recovered public modulus (n) from ACC dmem. uint32_t recovered_n[kRsa3072NumWords]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa3072NumWords, kOtbnVarRsaN, recovered_n)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kRsa3072NumWords, kAccVarRsaN, recovered_n)); // Check that this matches the public key modulus, and update the validity. hardened_bool_t n_valid = @@ -618,8 +612,8 @@ status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, // Read the private exponent (d) check value uint32_t d_check[kPrivateExponentCheckWords]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kPrivateExponentCheckWords, kOtbnVarRsaE, d_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kPrivateExponentCheckWords, kAccVarRsaE, d_check)); // Prepare a multi-limb all ones constant for comparing to in validity checks. uint32_t all_ones[kPrivateExponentCheckWords]; @@ -632,8 +626,8 @@ status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, if (launder32(check_primes) == kHardenedBoolTrue) { // Read the first prime (p) check value uint32_t p_check[kRsa3072NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa3072NumWords / 2, kOtbnVarRsaE, p_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa3072NumWords / 2, kAccVarRsaE, p_check)); // Check whether the first prime check value is all ones. hardened_bool_t p_valid = @@ -641,8 +635,8 @@ status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, // Read the second prime (q) check value uint32_t q_check[kRsa3072NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa3072NumWords / 2, kOtbnVarRsaE, q_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa3072NumWords / 2, kAccVarRsaE, q_check)); // Check whether the first prime check value is all ones. hardened_bool_t q_valid = @@ -681,69 +675,69 @@ status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, } // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t rsa_key_check_4096_start(const rsa_4096_public_key_t *public_key, const rsa_4096_private_key_t *private_key, hardened_bool_t check_primes) { - // Load the RSA key generation app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaKeygen)); + // Load the RSA key generation app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppRsaKeygen)); // Write the public exponent into DMEM, zero-extended to a full processor // word. - HARDENED_TRY(otbn_dmem_write(1, &public_key->e, kOtbnVarRsaE)); + HARDENED_TRY(acc_dmem_write(1, &public_key->e, kAccVarRsaE)); // Write the primes, CRT components of the private exponent, and CRT // coefficient into DMEM. - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->p.data), - private_key->p.data, kOtbnVarRsaP)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->q.data), - private_key->q.data, kOtbnVarRsaQ)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->d_p.data), - private_key->d_p.data, kOtbnVarRsaDp)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->d_q.data), - private_key->d_q.data, kOtbnVarRsaDq)); - HARDENED_TRY(otbn_dmem_write(ARRAYSIZE(private_key->i_q.data), - private_key->i_q.data, kOtbnVarRsaIq)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->p.data), + private_key->p.data, kAccVarRsaP)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->q.data), + private_key->q.data, kAccVarRsaQ)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->d_p.data), + private_key->d_p.data, kAccVarRsaDp)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->d_q.data), + private_key->d_q.data, kAccVarRsaDq)); + HARDENED_TRY(acc_dmem_write(ARRAYSIZE(private_key->i_q.data), + private_key->i_q.data, kAccVarRsaIq)); // Select mode based on whether we should perform primality checks. uint32_t mode; if (launder32(check_primes) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(check_primes, kHardenedBoolTrue); - mode = kOtbnRsaModeCheckWithPrimes4096; + mode = kAccRsaModeCheckWithPrimes4096; } else { HARDENED_CHECK_EQ(check_primes, kHardenedBoolFalse); - mode = kOtbnRsaModeCheck4096; + mode = kAccRsaModeCheck4096; } - // Set mode and start OTBN. - HARDENED_TRY(otbn_dmem_write(kOtbnRsaModeWords, &mode, kOtbnVarRsaMode)); - return otbn_execute(); + // Set mode and start ACC. + HARDENED_TRY(acc_dmem_write(kAccRsaModeWords, &mode, kAccVarRsaMode)); + return acc_execute(); } status_t rsa_key_check_4096_finalize(const rsa_4096_public_key_t *public_key, const rsa_4096_private_key_t *private_key, hardened_bool_t check_primes, hardened_bool_t *key_valid) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); - // Spin here waiting for OTBN to complete. - OTBN_WIPE_IF_ERROR(otbn_busy_wait_for_done()); + // Spin here waiting for ACC to complete. + ACC_WIPE_IF_ERROR(acc_busy_wait_for_done()); - // Read the mode from OTBN dmem and panic if it's not as expected. + // Read the mode from ACC dmem and panic if it's not as expected. uint32_t act_mode = 0; - OTBN_WIPE_IF_ERROR(otbn_dmem_read(1, kOtbnVarRsaMode, &act_mode)); + ACC_WIPE_IF_ERROR(acc_dmem_read(1, kAccVarRsaMode, &act_mode)); // Get the expected mode from provided arguments. uint32_t exp_mode = 0; if (launder32(check_primes) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(check_primes, kHardenedBoolTrue); - exp_mode = kOtbnRsaModeCheckWithPrimes4096; + exp_mode = kAccRsaModeCheckWithPrimes4096; } else { HARDENED_CHECK_EQ(check_primes, kHardenedBoolFalse); - exp_mode = kOtbnRsaModeCheck4096; + exp_mode = kAccRsaModeCheck4096; } // Ensure that the actual mode is the same as the expected mode. @@ -758,36 +752,35 @@ status_t rsa_key_check_4096_finalize(const rsa_4096_public_key_t *public_key, one[0] = 1; // Read the value of the first CRT component (d_p) validity check value from - // OTBN dmem. + // ACC dmem. uint32_t dp_check[kRsa4096NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa4096NumWords / 2, kOtbnVarRsaDp, dp_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa4096NumWords / 2, kAccVarRsaDp, dp_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t dp_valid = hardened_memeq(one, dp_check, ARRAYSIZE(dp_check)); // Read the value of the second CRT component (d_q) validity check value - // from OTBN dmem. + // from ACC dmem. uint32_t dq_check[kRsa4096NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa4096NumWords / 2, kOtbnVarRsaDq, dq_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa4096NumWords / 2, kAccVarRsaDq, dq_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t dq_valid = hardened_memeq(one, dq_check, ARRAYSIZE(dq_check)); // Read the value of the CRT coefficient (i_q) validity check value - // from OTBN dmem. + // from ACC dmem. uint32_t iq_check[kRsa4096NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa4096NumWords / 2, kOtbnVarRsaIq, iq_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa4096NumWords / 2, kAccVarRsaIq, iq_check)); // Check that this matches the expected value of 1, and update the validity. hardened_bool_t iq_valid = hardened_memeq(one, iq_check, ARRAYSIZE(iq_check)); - // Read the recovered public modulus (n) from OTBN dmem. + // Read the recovered public modulus (n) from ACC dmem. uint32_t recovered_n[kRsa4096NumWords]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa4096NumWords, kOtbnVarRsaN, recovered_n)); + ACC_WIPE_IF_ERROR(acc_dmem_read(kRsa4096NumWords, kAccVarRsaN, recovered_n)); // Check that this matches the public key modulus, and update the validity. hardened_bool_t n_valid = @@ -795,8 +788,8 @@ status_t rsa_key_check_4096_finalize(const rsa_4096_public_key_t *public_key, // Read the private exponent (d) check value uint32_t d_check[kPrivateExponentCheckWords]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kPrivateExponentCheckWords, kOtbnVarRsaE, d_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kPrivateExponentCheckWords, kAccVarRsaE, d_check)); // Prepare a multi-limb all ones constant for comparing to in validity checks. uint32_t all_ones[kPrivateExponentCheckWords]; @@ -809,8 +802,8 @@ status_t rsa_key_check_4096_finalize(const rsa_4096_public_key_t *public_key, if (launder32(check_primes) == kHardenedBoolTrue) { // Read the first prime (p) check value uint32_t p_check[kRsa4096NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa4096NumWords / 2, kOtbnVarRsaE, p_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa4096NumWords / 2, kAccVarRsaE, p_check)); // Check whether the first prime check value is all ones. hardened_bool_t p_valid = @@ -818,8 +811,8 @@ status_t rsa_key_check_4096_finalize(const rsa_4096_public_key_t *public_key, // Read the second prime (q) check value uint32_t q_check[kRsa4096NumWords / 2]; - OTBN_WIPE_IF_ERROR( - otbn_dmem_read(kRsa4096NumWords / 2, kOtbnVarRsaE, q_check)); + ACC_WIPE_IF_ERROR( + acc_dmem_read(kRsa4096NumWords / 2, kAccVarRsaE, q_check)); // Check whether the first prime check value is all ones. hardened_bool_t q_valid = @@ -858,5 +851,5 @@ status_t rsa_key_check_4096_finalize(const rsa_4096_public_key_t *public_key, } // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } diff --git a/sw/device/lib/crypto/impl/rsa/rsa_keygen.h b/sw/device/lib/crypto/impl/rsa/rsa_keygen.h index 6dc3c26743b..5a599fde642 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_keygen.h +++ b/sw/device/lib/crypto/impl/rsa/rsa_keygen.h @@ -22,7 +22,7 @@ extern "C" { * * The key exponent is always F4=65537; no other exponents are supported. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @return Result of the operation (OK or error). */ @@ -32,7 +32,7 @@ status_t rsa_keygen_2048_start(void); /** * Waits for an RSA-2048 key generation to complete. * - * Should be invoked only after `rsa_keygen_2048_start`. Blocks until OTBN is + * Should be invoked only after `rsa_keygen_2048_start`. Blocks until ACC is * done processing. * * @param[out] public_key Generated public key (n, e). @@ -48,7 +48,7 @@ status_t rsa_keygen_2048_finalize(rsa_2048_public_key_t *public_key, * * The key exponent is always F4=65537; no other exponents are supported. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @return Result of the operation (OK or error). */ @@ -58,7 +58,7 @@ status_t rsa_keygen_3072_start(void); /** * Waits for an RSA-3072 key generation to complete. * - * Should be invoked only after `rsa_keygen_3072_start`. Blocks until OTBN is + * Should be invoked only after `rsa_keygen_3072_start`. Blocks until ACC is * done processing. * * @param[out] public_key Generated public key (n, e). @@ -74,7 +74,7 @@ status_t rsa_keygen_3072_finalize(rsa_3072_public_key_t *public_key, * * The key exponent is always F4=65537; no other exponents are supported. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @return Result of the operation (OK or error). */ @@ -84,7 +84,7 @@ status_t rsa_keygen_4096_start(void); /** * Waits for an RSA-4096 key generation to complete. * - * Should be invoked only after `rsa_keygen_4096_start`. Blocks until OTBN is + * Should be invoked only after `rsa_keygen_4096_start`. Blocks until ACC is * done processing. * * @param[out] public_key Generated public key (n, e). @@ -102,7 +102,7 @@ status_t rsa_keygen_4096_finalize(rsa_4096_public_key_t *public_key, * routine does not perform any checks on the generated keypair (e.g. primality * checks or even range checks). * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key Public key (n, e). * @param cofactor One of the prime cofactors (p or q). @@ -116,11 +116,11 @@ status_t rsa_keygen_from_cofactor_2048_start( * Waits for an RSA-2048 key-from-cofactor operation to complete. * * Should be invoked only after `rsa_keygen_from_cofactor_2048_start`. Blocks - * until OTBN is done processing. + * until ACC is done processing. * - * The public key returned by this function is recomputed by OTBN; callers may + * The public key returned by this function is recomputed by ACC; callers may * find it helpful to compare the public key modulus returned to the one that - * was passed to OTBN originally in order to check for errors. + * was passed to ACC originally in order to check for errors. * * @param[out] public_key Generated public key (n, e). * @param[out] private_key Generated private key (p, q, d_p, d_q, i_q). @@ -137,7 +137,7 @@ status_t rsa_keygen_from_cofactor_2048_finalize( * routine does not perform any checks on the generated keypair (e.g. primality * checks or even range checks). * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key Public key (n, e). * @param cofactor One of the prime cofactors (p or q). @@ -151,11 +151,11 @@ status_t rsa_keygen_from_cofactor_3072_start( * Waits for an RSA-3072 key-from-cofactor operation to complete. * * Should be invoked only after `rsa_keygen_from_cofactor_3072_start`. Blocks - * until OTBN is done processing. + * until ACC is done processing. * - * The public key returned by this function is recomputed by OTBN; callers may + * The public key returned by this function is recomputed by ACC; callers may * find it helpful to compare the public key modulus returned to the one that - * was passed to OTBN originally in order to check for errors. + * was passed to ACC originally in order to check for errors. * * @param[out] public_key Generated public key (n, e). * @param[out] private_key Generated private key (p, q, d_p, d_q, i_q). @@ -172,7 +172,7 @@ status_t rsa_keygen_from_cofactor_3072_finalize( * routine does not perform any checks on the generated keypair (e.g. primality * checks or even range checks). * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key Public key (n, e). * @param cofactor One of the prime cofactors (p or q). @@ -186,11 +186,11 @@ status_t rsa_keygen_from_cofactor_4096_start( * Waits for an RSA-4096 key-from-cofactor operation to complete. * * Should be invoked only after `rsa_keygen_from_cofactor_4096_start`. Blocks - * until OTBN is done processing. + * until ACC is done processing. * - * The public key returned by this function is recomputed by OTBN; callers may + * The public key returned by this function is recomputed by ACC; callers may * find it helpful to compare the public key modulus returned to the one that - * was passed to OTBN originally in order to check for errors. + * was passed to ACC originally in order to check for errors. * * @param[out] public_key Generated public key (n, e). * @param[out] private_key Generated private key (p, q, d_p, d_q, i_q). @@ -204,7 +204,7 @@ status_t rsa_keygen_from_cofactor_4096_finalize( * Checks the validity of a RSA-2048 private key with respect to a given * RSA-2048 public key. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * This method performs a series of checks to ensure that a private key is * internally consistent with a given public key. Namely, it checks that @@ -222,7 +222,7 @@ status_t rsa_keygen_from_cofactor_4096_finalize( * also checks that both primes pass Miller-Rabin primality tests and that * the primes aren't too close. * - * As part of performing these checks, check values are computed using the OTBN + * As part of performing these checks, check values are computed using the ACC * which are verified on the Ibex by performing hardened comparisons to expected * values. * @@ -239,12 +239,12 @@ status_t rsa_key_check_2048_start(const rsa_2048_public_key_t *public_key, /* * Waits for an RSA-2048 private key check to complete. * - * Should be invoked only after `rsa_key_check_2048_start`. Blocks until OTBN is + * Should be invoked only after `rsa_key_check_2048_start`. Blocks until ACC is * done processing. * * The `check_primes` flag should be provided exactly as it was to * `rsa_key_check_2048_start` in order to ensure that the correct set of check - * values returned from the OTBN as a result of `rsa_key_check_2048_start` are + * values returned from the ACC as a result of `rsa_key_check_2048_start` are * verified by the Ibex. * * @param public_key Public key (n, e). @@ -263,7 +263,7 @@ status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, * Checks the validity of a RSA-3072 private key with respect to a given * RSA-3072 public key. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * This method performs a series of checks to ensure that a private key is * internally consistent with a given public key. Namely, it checks that @@ -281,7 +281,7 @@ status_t rsa_key_check_2048_finalize(const rsa_2048_public_key_t *public_key, * also checks that both primes pass Miller-Rabin primality tests and that * the primes aren't too close. * - * As part of performing these checks, check values are computed using the OTBN + * As part of performing these checks, check values are computed using the ACC * which are verified on the Ibex by performing hardened comparisons to expected * values. * @@ -298,12 +298,12 @@ status_t rsa_key_check_3072_start(const rsa_3072_public_key_t *public_key, /* * Waits for an RSA-3072 private key check to complete. * - * Should be invoked only after `rsa_key_check_3072_start`. Blocks until OTBN is + * Should be invoked only after `rsa_key_check_3072_start`. Blocks until ACC is * done processing. * * The `check_primes` flag should be provided exactly as it was to * `rsa_key_check_3072_start` in order to ensure that the correct set of check - * values returned from the OTBN as a result of `rsa_key_check_3072_start` are + * values returned from the ACC as a result of `rsa_key_check_3072_start` are * verified by the Ibex. * * @param public_key Public key (n, e). @@ -322,7 +322,7 @@ status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, * Checks the validity of a RSA-4096 private key with respect to a given * RSA-4096 public key. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * This method performs a series of checks to ensure that a private key is * internally consistent with a given public key. Namely, it checks that @@ -340,7 +340,7 @@ status_t rsa_key_check_3072_finalize(const rsa_3072_public_key_t *public_key, * also checks that both primes pass Miller-Rabin primality tests and that * the primes aren't too close. * - * As part of performing these checks, check values are computed using the OTBN + * As part of performing these checks, check values are computed using the ACC * which are verified on the Ibex by performing hardened comparisons to expected * values. * @@ -357,12 +357,12 @@ status_t rsa_key_check_4096_start(const rsa_4096_public_key_t *public_key, /* * Waits for an RSA-4096 private key check to complete. * - * Should be invoked only after `rsa_key_check_4096_start`. Blocks until OTBN is + * Should be invoked only after `rsa_key_check_4096_start`. Blocks until ACC is * done processing. * * The `check_primes` flag should be provided exactly as it was to * `rsa_key_check_4096_start` in order to ensure that the correct set of check - * values returned from the OTBN as a result of `rsa_key_check_4096_start` are + * values returned from the ACC as a result of `rsa_key_check_4096_start` are * verified by the Ibex. * * @param public_key Public key (n, e). diff --git a/sw/device/lib/crypto/impl/rsa/rsa_modexp.c b/sw/device/lib/crypto/impl/rsa/rsa_modexp.c index 3818a7ebe5d..7353eaff19e 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_modexp.c +++ b/sw/device/lib/crypto/impl/rsa/rsa_modexp.c @@ -5,67 +5,66 @@ #include "sw/device/lib/crypto/impl/rsa/rsa_modexp.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/rsa/rsa_modexp_insn_counts.h" // Module ID for status codes. #define MODULE_ID MAKE_MODULE_ID('r', 'm', 'e') -// Declare the OTBN app. -OTBN_DECLARE_APP_SYMBOLS(run_rsa_modexp); -static const otbn_app_t kOtbnAppRsaModexp = OTBN_APP_T_INIT(run_rsa_modexp); +// Declare the ACC app. +ACC_DECLARE_APP_SYMBOLS(run_rsa_modexp); +static const acc_app_t kAccAppRsaModexp = ACC_APP_T_INIT(run_rsa_modexp); // Declare offsets for input and output buffers. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, mode); // Application mode. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, n); // Public modulus n. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, p); // Cofactor p. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, q); // Cofactor q. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, d); // Private exponent d. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, d_p); // CRT component d_p. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, d_q); // CRT component d_q. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, i_q); // CRT coefficient i_q. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, inout); // Input/output buffer. - -static const otbn_addr_t kOtbnVarRsaMode = - OTBN_ADDR_T_INIT(run_rsa_modexp, mode); -static const otbn_addr_t kOtbnVarRsaN = OTBN_ADDR_T_INIT(run_rsa_modexp, n); -static const otbn_addr_t kOtbnVarRsaP = OTBN_ADDR_T_INIT(run_rsa_modexp, p); -static const otbn_addr_t kOtbnVarRsaQ = OTBN_ADDR_T_INIT(run_rsa_modexp, q); -static const otbn_addr_t kOtbnVarRsaD = OTBN_ADDR_T_INIT(run_rsa_modexp, d); -static const otbn_addr_t kOtbnVarRsaDp = OTBN_ADDR_T_INIT(run_rsa_modexp, d_p); -static const otbn_addr_t kOtbnVarRsaDq = OTBN_ADDR_T_INIT(run_rsa_modexp, d_q); -static const otbn_addr_t kOtbnVarRsaIq = OTBN_ADDR_T_INIT(run_rsa_modexp, i_q); -static const otbn_addr_t kOtbnVarRsaInOut = - OTBN_ADDR_T_INIT(run_rsa_modexp, inout); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, mode); // Application mode. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, n); // Public modulus n. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, p); // Cofactor p. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, q); // Cofactor q. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, d); // Private exponent d. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, d_p); // CRT component d_p. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, d_q); // CRT component d_q. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, i_q); // CRT coefficient i_q. +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, inout); // Input/output buffer. + +static const acc_addr_t kAccVarRsaMode = ACC_ADDR_T_INIT(run_rsa_modexp, mode); +static const acc_addr_t kAccVarRsaN = ACC_ADDR_T_INIT(run_rsa_modexp, n); +static const acc_addr_t kAccVarRsaP = ACC_ADDR_T_INIT(run_rsa_modexp, p); +static const acc_addr_t kAccVarRsaQ = ACC_ADDR_T_INIT(run_rsa_modexp, q); +static const acc_addr_t kAccVarRsaD = ACC_ADDR_T_INIT(run_rsa_modexp, d); +static const acc_addr_t kAccVarRsaDp = ACC_ADDR_T_INIT(run_rsa_modexp, d_p); +static const acc_addr_t kAccVarRsaDq = ACC_ADDR_T_INIT(run_rsa_modexp, d_q); +static const acc_addr_t kAccVarRsaIq = ACC_ADDR_T_INIT(run_rsa_modexp, i_q); +static const acc_addr_t kAccVarRsaInOut = + ACC_ADDR_T_INIT(run_rsa_modexp, inout); // Declare mode constants. -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_2048_MODEXP); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_2048_MODEXP_CRT); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_2048_MODEXP_F4); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_3072_MODEXP); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_3072_MODEXP_CRT); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_3072_MODEXP_F4); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_4096_MODEXP); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_4096_MODEXP_CRT); -OTBN_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_4096_MODEXP_F4); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_2048_MODEXP); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_2048_MODEXP_CRT); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_2048_MODEXP_F4); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_3072_MODEXP); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_3072_MODEXP_CRT); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_3072_MODEXP_F4); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_4096_MODEXP); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_4096_MODEXP_CRT); +ACC_DECLARE_SYMBOL_ADDR(run_rsa_modexp, MODE_RSA_4096_MODEXP_F4); static const uint32_t kMode2048Modexp = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_2048_MODEXP); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_2048_MODEXP); static const uint32_t kMode2048ModexpCrt = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_2048_MODEXP_CRT); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_2048_MODEXP_CRT); static const uint32_t kMode2048ModexpF4 = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_2048_MODEXP_F4); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_2048_MODEXP_F4); static const uint32_t kMode3072Modexp = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_3072_MODEXP); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_3072_MODEXP); static const uint32_t kMode3072ModexpCrt = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_3072_MODEXP_CRT); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_3072_MODEXP_CRT); static const uint32_t kMode3072ModexpF4 = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_3072_MODEXP_F4); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_3072_MODEXP_F4); static const uint32_t kMode4096Modexp = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_4096_MODEXP); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_4096_MODEXP); static const uint32_t kMode4096ModexpCrt = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_4096_MODEXP_CRT); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_4096_MODEXP_CRT); static const uint32_t kMode4096ModexpF4 = - OTBN_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_4096_MODEXP_F4); + ACC_ADDR_T_INIT(run_rsa_modexp, MODE_RSA_4096_MODEXP_F4); enum { /** @@ -78,12 +77,12 @@ enum { }; status_t rsa_modexp_get_result_size(size_t *num_words) { - // Return `OTCRYTPO_ASYNC_INCOMPLETE` if OTBN not done. - HARDENED_TRY(otbn_assert_idle()); + // Return `OTCRYTPO_ASYNC_INCOMPLETE` if ACC not done. + HARDENED_TRY(acc_assert_idle()); // Read the application mode. uint32_t mode; - HARDENED_TRY(otbn_dmem_read(1, kOtbnVarRsaMode, &mode)); + HARDENED_TRY(acc_dmem_read(1, kAccVarRsaMode, &mode)); *num_words = 0; if (mode == kMode2048Modexp || mode == kMode2048ModexpCrt || @@ -97,7 +96,7 @@ status_t rsa_modexp_get_result_size(size_t *num_words) { *num_words = kRsa4096NumWords; } else { // Wipe DMEM. - otbn_dmem_sec_wipe_nofail(); + acc_dmem_sec_wipe_nofail(); // Unrecognized mode. return OTCRYPTO_FATAL_ERR; } @@ -108,8 +107,8 @@ status_t rsa_modexp_get_result_size(size_t *num_words) { /** * Finalizes a modular exponentiation of variable size. * - * Blocks until OTBN is done, checks for errors. Ensures the mode matches - * expectations. Reads back the result, and then performs an OTBN secure wipe. + * Blocks until ACC is done, checks for errors. Ensures the mode matches + * expectations. Reads back the result, and then performs an ACC secure wipe. * * @param num_words Number of words for the modexp result. * @param[out] result Result of the modexp operation. @@ -120,44 +119,43 @@ static status_t rsa_modexp_finalize(const size_t num_words, const uint32_t min_insn_count, const uint32_t max_insn_count, uint32_t *result) { - // Get the result size, failing if the OTBN isn't done. + // Get the result size, failing if the ACC isn't done. size_t num_words_inferred; - OTBN_WIPE_IF_ERROR(rsa_modexp_get_result_size(&num_words_inferred)); + ACC_WIPE_IF_ERROR(rsa_modexp_get_result_size(&num_words_inferred)); // Check that the inferred result size matches expectations. if (num_words != num_words_inferred) { - otbn_dmem_sec_wipe_nofail(); + acc_dmem_sec_wipe_nofail(); return OTCRYPTO_FATAL_ERR; } // Check instruction count. - OTBN_CHECK_INSN_COUNT(min_insn_count, max_insn_count); + ACC_CHECK_INSN_COUNT(min_insn_count, max_insn_count); // Read the result. - OTBN_WIPE_IF_ERROR(otbn_dmem_read(num_words, kOtbnVarRsaInOut, result)); + ACC_WIPE_IF_ERROR(acc_dmem_read(num_words, kAccVarRsaInOut, result)); // Wipe DMEM. - return otbn_dmem_sec_wipe(); + return acc_dmem_sec_wipe(); } status_t rsa_modexp_consttime_2048_start(const rsa_2048_int_t *base, const rsa_2048_int_t *exp, const rsa_2048_int_t *modulus) { - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode2048Modexp; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base, the modulus n and private exponent d. - HARDENED_TRY(otbn_dmem_write(kRsa2048NumWords, base->data, kOtbnVarRsaInOut)); - HARDENED_TRY(otbn_dmem_write(kRsa2048NumWords, modulus->data, kOtbnVarRsaN)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa2048NumWords, exp->data, kOtbnVarRsaD)); + HARDENED_TRY(acc_dmem_write(kRsa2048NumWords, base->data, kAccVarRsaInOut)); + HARDENED_TRY(acc_dmem_write(kRsa2048NumWords, modulus->data, kAccVarRsaN)); + ACC_WIPE_IF_ERROR(acc_dmem_write(kRsa2048NumWords, exp->data, kAccVarRsaD)); - // Start OTBN. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start ACC. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } @@ -171,28 +169,28 @@ status_t rsa_modexp_consttime_crt_2048_start( const rsa_2048_int_t *base, const rsa_2048_short_t *exp_p, const rsa_2048_short_t *exp_q, const rsa_2048_short_t *crt_coeff, const rsa_2048_short_t *modulus_p, const rsa_2048_short_t *modulus_q) { - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode2048ModexpCrt; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base, the cofactors, the CRT components, and the CRT coefficient. - HARDENED_TRY(otbn_dmem_write(kRsa2048NumWords, base->data, kOtbnVarRsaInOut)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa2048NumWords / 2, modulus_p->data, kOtbnVarRsaP)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa2048NumWords / 2, modulus_q->data, kOtbnVarRsaQ)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa2048NumWords / 2, exp_p->data, kOtbnVarRsaDp)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa2048NumWords / 2, exp_q->data, kOtbnVarRsaDq)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa2048NumWords / 2, crt_coeff->data, kOtbnVarRsaIq)); - - // Start OTBN. - OTBN_WIPE_IF_ERROR(otbn_execute()); + HARDENED_TRY(acc_dmem_write(kRsa2048NumWords, base->data, kAccVarRsaInOut)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa2048NumWords / 2, modulus_p->data, kAccVarRsaP)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa2048NumWords / 2, modulus_q->data, kAccVarRsaQ)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa2048NumWords / 2, exp_p->data, kAccVarRsaDp)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa2048NumWords / 2, exp_q->data, kAccVarRsaDq)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa2048NumWords / 2, crt_coeff->data, kAccVarRsaIq)); + + // Start ACC. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } @@ -214,19 +212,19 @@ status_t rsa_modexp_vartime_2048_start(const rsa_2048_int_t *base, return rsa_modexp_consttime_2048_start(base, &exp_rsa, modulus); } - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode2048ModexpF4; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base and the modulus n. - HARDENED_TRY(otbn_dmem_write(kRsa2048NumWords, base->data, kOtbnVarRsaInOut)); - HARDENED_TRY(otbn_dmem_write(kRsa2048NumWords, modulus->data, kOtbnVarRsaN)); + HARDENED_TRY(acc_dmem_write(kRsa2048NumWords, base->data, kAccVarRsaInOut)); + HARDENED_TRY(acc_dmem_write(kRsa2048NumWords, modulus->data, kAccVarRsaN)); - // Start OTBN. - return otbn_execute(); + // Start ACC. + return acc_execute(); } status_t rsa_modexp_vartime_2048_finalize(const uint32_t exp, @@ -245,21 +243,20 @@ status_t rsa_modexp_vartime_2048_finalize(const uint32_t exp, status_t rsa_modexp_consttime_3072_start(const rsa_3072_int_t *base, const rsa_3072_int_t *exp, const rsa_3072_int_t *modulus) { - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode3072Modexp; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base, the modulus n and private exponent d. - HARDENED_TRY(otbn_dmem_write(kRsa3072NumWords, base->data, kOtbnVarRsaInOut)); - HARDENED_TRY(otbn_dmem_write(kRsa3072NumWords, modulus->data, kOtbnVarRsaN)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa3072NumWords, exp->data, kOtbnVarRsaD)); + HARDENED_TRY(acc_dmem_write(kRsa3072NumWords, base->data, kAccVarRsaInOut)); + HARDENED_TRY(acc_dmem_write(kRsa3072NumWords, modulus->data, kAccVarRsaN)); + ACC_WIPE_IF_ERROR(acc_dmem_write(kRsa3072NumWords, exp->data, kAccVarRsaD)); - // Start OTBN. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start ACC. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } @@ -273,28 +270,28 @@ status_t rsa_modexp_consttime_crt_3072_start( const rsa_3072_int_t *base, const rsa_3072_short_t *exp_p, const rsa_3072_short_t *exp_q, const rsa_3072_short_t *crt_coeff, const rsa_3072_short_t *modulus_p, const rsa_3072_short_t *modulus_q) { - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode3072ModexpCrt; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base, the cofactors, the CRT components, and the CRT coefficient. - HARDENED_TRY(otbn_dmem_write(kRsa3072NumWords, base->data, kOtbnVarRsaInOut)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa3072NumWords / 2, modulus_p->data, kOtbnVarRsaP)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa3072NumWords / 2, modulus_q->data, kOtbnVarRsaQ)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa3072NumWords / 2, exp_p->data, kOtbnVarRsaDp)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa3072NumWords / 2, exp_q->data, kOtbnVarRsaDq)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa3072NumWords / 2, crt_coeff->data, kOtbnVarRsaIq)); - - // Start OTBN. - OTBN_WIPE_IF_ERROR(otbn_execute()); + HARDENED_TRY(acc_dmem_write(kRsa3072NumWords, base->data, kAccVarRsaInOut)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa3072NumWords / 2, modulus_p->data, kAccVarRsaP)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa3072NumWords / 2, modulus_q->data, kAccVarRsaQ)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa3072NumWords / 2, exp_p->data, kAccVarRsaDp)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa3072NumWords / 2, exp_q->data, kAccVarRsaDq)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa3072NumWords / 2, crt_coeff->data, kAccVarRsaIq)); + + // Start ACC. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } @@ -316,19 +313,19 @@ status_t rsa_modexp_vartime_3072_start(const rsa_3072_int_t *base, return rsa_modexp_consttime_3072_start(base, &exp_rsa, modulus); } - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode3072ModexpF4; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base and the modulus n. - HARDENED_TRY(otbn_dmem_write(kRsa3072NumWords, base->data, kOtbnVarRsaInOut)); - HARDENED_TRY(otbn_dmem_write(kRsa3072NumWords, modulus->data, kOtbnVarRsaN)); + HARDENED_TRY(acc_dmem_write(kRsa3072NumWords, base->data, kAccVarRsaInOut)); + HARDENED_TRY(acc_dmem_write(kRsa3072NumWords, modulus->data, kAccVarRsaN)); - // Start OTBN. - return otbn_execute(); + // Start ACC. + return acc_execute(); } status_t rsa_modexp_vartime_3072_finalize(const uint32_t exp, @@ -347,21 +344,20 @@ status_t rsa_modexp_vartime_3072_finalize(const uint32_t exp, status_t rsa_modexp_consttime_4096_start(const rsa_4096_int_t *base, const rsa_4096_int_t *exp, const rsa_4096_int_t *modulus) { - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode4096Modexp; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base, the modulus n and private exponent d. - HARDENED_TRY(otbn_dmem_write(kRsa4096NumWords, base->data, kOtbnVarRsaInOut)); - HARDENED_TRY(otbn_dmem_write(kRsa4096NumWords, modulus->data, kOtbnVarRsaN)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa4096NumWords, exp->data, kOtbnVarRsaD)); + HARDENED_TRY(acc_dmem_write(kRsa4096NumWords, base->data, kAccVarRsaInOut)); + HARDENED_TRY(acc_dmem_write(kRsa4096NumWords, modulus->data, kAccVarRsaN)); + ACC_WIPE_IF_ERROR(acc_dmem_write(kRsa4096NumWords, exp->data, kAccVarRsaD)); - // Start OTBN. - OTBN_WIPE_IF_ERROR(otbn_execute()); + // Start ACC. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } @@ -375,28 +371,28 @@ status_t rsa_modexp_consttime_crt_4096_start( const rsa_4096_int_t *base, const rsa_4096_short_t *exp_p, const rsa_4096_short_t *exp_q, const rsa_4096_short_t *crt_coeff, const rsa_4096_short_t *modulus_p, const rsa_4096_short_t *modulus_q) { - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode4096ModexpCrt; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base, the cofactors, the CRT components, and the CRT coefficient. - HARDENED_TRY(otbn_dmem_write(kRsa4096NumWords, base->data, kOtbnVarRsaInOut)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa4096NumWords / 2, modulus_p->data, kOtbnVarRsaP)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa4096NumWords / 2, modulus_q->data, kOtbnVarRsaQ)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa4096NumWords / 2, exp_p->data, kOtbnVarRsaDp)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa4096NumWords / 2, exp_q->data, kOtbnVarRsaDq)); - OTBN_WIPE_IF_ERROR( - otbn_dmem_write(kRsa4096NumWords / 2, crt_coeff->data, kOtbnVarRsaIq)); - - // Start OTBN. - OTBN_WIPE_IF_ERROR(otbn_execute()); + HARDENED_TRY(acc_dmem_write(kRsa4096NumWords, base->data, kAccVarRsaInOut)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa4096NumWords / 2, modulus_p->data, kAccVarRsaP)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa4096NumWords / 2, modulus_q->data, kAccVarRsaQ)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa4096NumWords / 2, exp_p->data, kAccVarRsaDp)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa4096NumWords / 2, exp_q->data, kAccVarRsaDq)); + ACC_WIPE_IF_ERROR( + acc_dmem_write(kRsa4096NumWords / 2, crt_coeff->data, kAccVarRsaIq)); + + // Start ACC. + ACC_WIPE_IF_ERROR(acc_execute()); return OTCRYPTO_OK; } @@ -418,19 +414,19 @@ status_t rsa_modexp_vartime_4096_start(const rsa_4096_int_t *base, return rsa_modexp_consttime_4096_start(base, &exp_rsa, modulus); } - // Load the OTBN app. Fails if OTBN is not idle. - HARDENED_TRY(otbn_load_app(kOtbnAppRsaModexp)); + // Load the ACC app. Fails if ACC is not idle. + HARDENED_TRY(acc_load_app(kAccAppRsaModexp)); // Set mode. uint32_t mode = kMode4096ModexpF4; - HARDENED_TRY(otbn_dmem_write(1, &mode, kOtbnVarRsaMode)); + HARDENED_TRY(acc_dmem_write(1, &mode, kAccVarRsaMode)); // Set the base and the modulus n. - HARDENED_TRY(otbn_dmem_write(kRsa4096NumWords, base->data, kOtbnVarRsaInOut)); - HARDENED_TRY(otbn_dmem_write(kRsa4096NumWords, modulus->data, kOtbnVarRsaN)); + HARDENED_TRY(acc_dmem_write(kRsa4096NumWords, base->data, kAccVarRsaInOut)); + HARDENED_TRY(acc_dmem_write(kRsa4096NumWords, modulus->data, kAccVarRsaN)); - // Start OTBN. - return otbn_execute(); + // Start ACC. + return acc_execute(); } status_t rsa_modexp_vartime_4096_finalize(const uint32_t exp, diff --git a/sw/device/lib/crypto/impl/rsa/rsa_modexp.h b/sw/device/lib/crypto/impl/rsa/rsa_modexp.h index b016288db01..7c29313fc5e 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_modexp.h +++ b/sw/device/lib/crypto/impl/rsa/rsa_modexp.h @@ -20,13 +20,13 @@ extern "C" { /** * Check that a modexp operation is complete and get the result size. * - * After OTBN finishes processing, this function reads the mode and infers the + * After ACC finishes processing, this function reads the mode and infers the * size of the modulus/signature for the just-finished operation. It then * populates the `num_words` parameter with this size (expressed in 32b words). * This is designed so that callers can call `rsa_modexp_wait()` and then use * the size to select the appropriate `finalize()` call. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param[out] num_words Number of words for result buffers. * @return Status of the operation (OK or error). @@ -40,7 +40,7 @@ status_t rsa_modexp_get_result_size(size_t *num_words); * This construct is for secret exponents, and is much slower than the * variable-time version. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp Exponent to raise the base to. @@ -67,7 +67,7 @@ status_t rsa_modexp_consttime_2048_finalize(rsa_2048_int_t *result); * This construct is for secret exponents, and is faster than the non-CRT * constant-time version. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp_p First CRT component of exponent to raise the base to. @@ -100,7 +100,7 @@ status_t rsa_modexp_consttime_crt_2048_finalize(rsa_2048_int_t *result); * Do not use this construct with secret exponents; its timing depends on the * exponent. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp Exponent to raise the base to. @@ -129,7 +129,7 @@ status_t rsa_modexp_vartime_2048_finalize(const uint32_t exp, * This construct is for secret exponents, and is much slower than the * variable-time version. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp Exponent to raise the base to. @@ -156,7 +156,7 @@ status_t rsa_modexp_consttime_3072_finalize(rsa_3072_int_t *result); * This construct is for secret exponents, and is faster than the non-CRT * constant-time version. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp_p First CRT component of exponent to raise the base to. @@ -189,7 +189,7 @@ status_t rsa_modexp_consttime_crt_3072_finalize(rsa_3072_int_t *result); * Do not use this construct with secret exponents; its timing depends on the * exponent. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp Exponent to raise the base to. @@ -218,7 +218,7 @@ status_t rsa_modexp_vartime_3072_finalize(const uint32_t exp, * This construct is for secret exponents, and is much slower than the * variable-time version. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp Exponent to raise the base to. @@ -245,7 +245,7 @@ status_t rsa_modexp_consttime_4096_finalize(rsa_4096_int_t *result); * This construct is for secret exponents, and is faster than the non-CRT * constant-time version. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp_p First CRT component of exponent to raise the base to. @@ -278,7 +278,7 @@ status_t rsa_modexp_consttime_crt_4096_finalize(rsa_4096_int_t *result); * Do not use this construct with secret exponents; its timing depends on the * exponent. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param base Exponentiation base. * @param exp Exponent to raise the base to. diff --git a/sw/device/lib/crypto/impl/rsa/rsa_padding.h b/sw/device/lib/crypto/impl/rsa/rsa_padding.h index b59b919eba8..61fd26f6359 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_padding.h +++ b/sw/device/lib/crypto/impl/rsa/rsa_padding.h @@ -24,7 +24,7 @@ extern "C" { * The caller must ensure that `encoded_message_len` 32-bit words are allocated * in the output buffer. * - * We encode the message in reversed byte-order from the RFC because OTBN + * We encode the message in reversed byte-order from the RFC because ACC * interprets the message as a fully little-endian integer. * * @param message_digest Message digest to encode. @@ -67,7 +67,7 @@ status_t rsa_padding_pkcs1v15_verify( * The caller must ensure that `encoded_message_len` 32-bit words are allocated * in the output buffer. * - * We encode the message in reversed byte-order from the RFC because OTBN + * We encode the message in reversed byte-order from the RFC because ACC * interprets the message as a fully little-endian integer. * * @param message_digest Message digest to encode. @@ -96,7 +96,7 @@ status_t rsa_padding_pss_encode(const otcrypto_hash_digest_t message_digest, * or logical error codes. * * Note that this function expects the encoded message in reversed byte-order - * compared to the RFC, since OTBN is little-endian. + * compared to the RFC, since ACC is little-endian. * * Warning: modifies the encoded message in-place during comparison * (specifically, reverses the byte-order). @@ -148,7 +148,7 @@ status_t rsa_padding_oaep_max_message_bytelen( * The hash function must be a fixed-length (SHA-2 or SHA-3) hash function. The * MGF will always be MGF1 with the same hash function. * - * We encode the message in reversed byte-order from the RFC because OTBN + * We encode the message in reversed byte-order from the RFC because ACC * interprets the message as a fully little-endian integer. * * @param hash_mode Hash function to use. @@ -180,7 +180,7 @@ status_t rsa_padding_oaep_encode(const otcrypto_hash_mode_t hash_mode, * MGF will always be MGF1 with the same hash function. * * Note that this function expects the encoded message in reversed byte-order - * compared to the RFC, since OTBN is little-endian. + * compared to the RFC, since ACC is little-endian. * * Warning: modifies the encoded message in-place during comparison * (specifically, reverses the byte-order). diff --git a/sw/device/lib/crypto/impl/rsa/rsa_signature.c b/sw/device/lib/crypto/impl/rsa/rsa_signature.c index b8731904fca..d11212e952e 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_signature.c +++ b/sw/device/lib/crypto/impl/rsa/rsa_signature.c @@ -12,8 +12,8 @@ #include "sw/device/lib/base/hardened.h" #include "sw/device/lib/base/hardened_memory.h" #include "sw/device/lib/base/math.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/rsa/rsa_modexp.h" #include "sw/device/lib/crypto/impl/rsa/rsa_padding.h" @@ -221,13 +221,13 @@ status_t rsa_signature_verify_2048_finalize( const otcrypto_hash_digest_t message_digest, const rsa_signature_padding_t padding_mode, hardened_bool_t *verification_result) { - // Get the result size, failing if the OTBN isn't done. + // Get the result size, failing if the ACC isn't done. size_t num_words; HARDENED_TRY(rsa_modexp_get_result_size(&num_words)); // Check that the inferred result size matches expectations. if (num_words != kRsa2048NumWords) { - otbn_dmem_sec_wipe_nofail(); + acc_dmem_sec_wipe_nofail(); return OTCRYPTO_FATAL_ERR; } @@ -250,13 +250,13 @@ status_t rsa_signature_verify_3072_finalize( const otcrypto_hash_digest_t message_digest, const rsa_signature_padding_t padding_mode, hardened_bool_t *verification_result) { - // Get the result size, failing if the OTBN isn't done. + // Get the result size, failing if the ACC isn't done. size_t num_words; HARDENED_TRY(rsa_modexp_get_result_size(&num_words)); // Check that the inferred result size matches expectations. if (num_words != kRsa3072NumWords) { - otbn_dmem_sec_wipe_nofail(); + acc_dmem_sec_wipe_nofail(); return OTCRYPTO_FATAL_ERR; } @@ -279,13 +279,13 @@ status_t rsa_signature_verify_4096_finalize( const otcrypto_hash_digest_t message_digest, const rsa_signature_padding_t padding_mode, hardened_bool_t *verification_result) { - // Get the result size, failing if the OTBN isn't done. + // Get the result size, failing if the ACC isn't done. size_t num_words; HARDENED_TRY(rsa_modexp_get_result_size(&num_words)); // Check that the inferred result size matches expectations. if (num_words != kRsa4096NumWords) { - otbn_dmem_sec_wipe_nofail(); + acc_dmem_sec_wipe_nofail(); return OTCRYPTO_FATAL_ERR; } diff --git a/sw/device/lib/crypto/impl/rsa/rsa_signature.h b/sw/device/lib/crypto/impl/rsa/rsa_signature.h index e6587054d25..99673c5d39f 100644 --- a/sw/device/lib/crypto/impl/rsa/rsa_signature.h +++ b/sw/device/lib/crypto/impl/rsa/rsa_signature.h @@ -45,7 +45,7 @@ typedef enum rsa_signature_padding { * * The key exponent must be F4=65537; no other exponents are supported. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key RSA private key. * @param message_digest Message digest to sign. @@ -61,7 +61,7 @@ status_t rsa_signature_generate_2048_start( /** * Waits for an RSA-2048 signature generation to complete. * - * Should be invoked only after `rsa_2048_sign_start`. Blocks until OTBN is + * Should be invoked only after `rsa_2048_sign_start`. Blocks until ACC is * done processing. * * @param[out] signature Generated signature. @@ -73,7 +73,7 @@ status_t rsa_signature_generate_2048_finalize(rsa_2048_int_t *signature); /** * Starts verifying an RSA-2048 signature; returns immediately. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key RSA public key. * @param signature Signature to verify. @@ -87,7 +87,7 @@ status_t rsa_signature_verify_2048_start( * Waits for a RSA-2048 signature verification to complete. * * Should be invoked only after a `rsa_signature_verify_2048_start` call. - * Blocks until OTBN is done processing. + * Blocks until ACC is done processing. * * The caller must check the `result` parameter to see if the signature passed * or failed verification; the return value of this function will always return @@ -112,7 +112,7 @@ status_t rsa_signature_verify_2048_finalize( * * The key exponent must be F4=65537; no other exponents are supported. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key RSA private key. * @param message_digest Message digest to sign. @@ -129,7 +129,7 @@ status_t rsa_signature_generate_3072_start( * Waits for a RSA-3072 signature verification to complete. * * Should be invoked only after a `rsa_signature_verify_3072_start` call. - * Blocks until OTBN is done processing. + * Blocks until ACC is done processing. * * The caller must check the `result` parameter to see if the signature passed * or failed verification; the return value of this function will always return @@ -152,7 +152,7 @@ status_t rsa_signature_verify_3072_finalize( /** * Waits for an RSA-3072 signature generation to complete. * - * Should be invoked only after `rsa_3072_sign_start`. Blocks until OTBN is + * Should be invoked only after `rsa_3072_sign_start`. Blocks until ACC is * done processing. * * @param[out] signature Generated signature. @@ -164,7 +164,7 @@ status_t rsa_signature_generate_3072_finalize(rsa_3072_int_t *signature); /** * Starts verifying an RSA-3072 signature; returns immediately. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key RSA public key. * @param signature Signature to verify. @@ -179,7 +179,7 @@ status_t rsa_signature_verify_3072_start( * * The key exponent must be F4=65537; no other exponents are supported. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param private_key RSA private key. * @param message_digest Message digest to sign. @@ -195,7 +195,7 @@ status_t rsa_signature_generate_4096_start( /** * Waits for an RSA-4096 signature generation to complete. * - * Should be invoked only after `rsa_4096_sign_start`. Blocks until OTBN is + * Should be invoked only after `rsa_4096_sign_start`. Blocks until ACC is * done processing. * * @param[out] signature Generated signature. @@ -207,7 +207,7 @@ status_t rsa_signature_generate_4096_finalize(rsa_4096_int_t *signature); /** * Starts verifying an RSA-4096 signature; returns immediately. * - * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if OTBN is busy. + * Returns an `OTCRYPTO_ASYNC_INCOMPLETE` error if ACC is busy. * * @param public_key RSA public key. * @param signature Signature to verify. @@ -221,7 +221,7 @@ status_t rsa_signature_verify_4096_start( * Waits for a RSA-4096 signature verification to complete. * * Should be invoked only after a `rsa_signature_verify_4096_start` call. - * Blocks until OTBN is done processing. + * Blocks until ACC is done processing. * * The caller must check the `result` parameter to see if the signature passed * or failed verification; the return value of this function will always return diff --git a/sw/device/lib/crypto/impl/sha2/BUILD b/sw/device/lib/crypto/impl/sha2/BUILD index 1e6a550269b..824991d20d6 100644 --- a/sw/device/lib/crypto/impl/sha2/BUILD +++ b/sw/device/lib/crypto/impl/sha2/BUILD @@ -10,7 +10,7 @@ package(default_visibility = ["//visibility:public"]) load("//rules/opentitan:defs.bzl", "OPENTITAN_CPU") -load("//rules:autogen.bzl", "autogen_otbn_insn_count_header") +load("//rules:autogen.bzl", "autogen_acc_insn_count_header") cc_library( name = "sha256", @@ -19,14 +19,14 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":sha256_insn_counts", + "//sw/acc/crypto:run_sha256", "//sw/device/lib/base:hardened", "//sw/device/lib/base:hardened_memory", "//sw/device/lib/base:macros", "//sw/device/lib/base:memory", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:hmac", - "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/drivers:rv_core_ibex", - "//sw/otbn/crypto:run_sha256", ], ) @@ -37,31 +37,31 @@ cc_library( target_compatible_with = [OPENTITAN_CPU], deps = [ ":sha512_insn_counts", + "//sw/acc/crypto:run_sha512", "//sw/device/lib/base:hardened", "//sw/device/lib/base:hardened_memory", "//sw/device/lib/base:macros", "//sw/device/lib/base:memory", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:hmac", - "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/drivers:rv_core_ibex", - "//sw/otbn/crypto:run_sha512", ], ) -autogen_otbn_insn_count_header( +autogen_acc_insn_count_header( name = "sha256_insn_counts", hjson = "sha256_modes.hjson", template = "sha256_insn_counts.h.tpl", deps = [ - "//sw/otbn/crypto:run_sha256", + "//sw/acc/crypto:run_sha256", ], ) -autogen_otbn_insn_count_header( +autogen_acc_insn_count_header( name = "sha512_insn_counts", hjson = "sha512_modes.hjson", template = "sha512_insn_counts.h.tpl", deps = [ - "//sw/otbn/crypto:run_sha512", + "//sw/acc/crypto:run_sha512", ], ) diff --git a/sw/device/lib/crypto/impl/sha2/sha256.c b/sw/device/lib/crypto/impl/sha2/sha256.c index 8bf21a106aa..2997129d668 100644 --- a/sw/device/lib/crypto/impl/sha2/sha256.c +++ b/sw/device/lib/crypto/impl/sha2/sha256.c @@ -12,8 +12,8 @@ #include "sw/device/lib/base/hardened_memory.h" #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/memory.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/drivers/rv_core_ibex.h" #include "sw/device/lib/crypto/impl/sha2/sha256_insn_counts.h" #include "sw/device/lib/crypto/impl/status.h" @@ -23,12 +23,12 @@ enum { /** - * Maximum number of message chunks that the OTBN app can accept. + * Maximum number of message chunks that the ACC app can accept. * * This number is based on the DMEM size limit and usage by the SHA-256 app * itself; see `run_sha256.s` for the detailed calculation. */ - kSha256MaxMessageChunksPerOtbnRun = 41, + kSha256MaxMessageChunksPerAccRun = 41, }; /** @@ -39,16 +39,16 @@ typedef struct sha256_message_block { } sha256_message_block_t; /** - * Context object for the OTBN message buffer. + * Context object for the ACC message buffer. */ -typedef struct sha256_otbn_ctx { +typedef struct sha256_acc_ctx { /** * Number of message blocks currently loaded. */ size_t num_blocks; -} sha256_otbn_ctx_t; +} sha256_acc_ctx_t; -// Initial state for SHA-256 (see FIPS 180-4, section 5.3.3). The SHA-256 OTBN +// Initial state for SHA-256 (see FIPS 180-4, section 5.3.3). The SHA-256 ACC // app represents the state with little-endian words and in reverse word-order // compared with FIPS 180-4. static const uint32_t kSha256InitialState[kSha256StateWords] = { @@ -58,18 +58,17 @@ static const uint32_t kSha256InitialState[kSha256StateWords] = { static_assert(sizeof(kSha256InitialState) == kSha256StateBytes, "Initial state for SHA-256 has an unexpected size."); -OTBN_DECLARE_APP_SYMBOLS(run_sha256); // The OTBN SHA-256 app. -OTBN_DECLARE_SYMBOL_ADDR(run_sha256, state); // Hash state. -OTBN_DECLARE_SYMBOL_ADDR(run_sha256, msg); // Input message. -OTBN_DECLARE_SYMBOL_ADDR(run_sha256, - num_msg_chunks); // Message length in blocks. +ACC_DECLARE_APP_SYMBOLS(run_sha256); // The ACC SHA-256 app. +ACC_DECLARE_SYMBOL_ADDR(run_sha256, state); // Hash state. +ACC_DECLARE_SYMBOL_ADDR(run_sha256, msg); // Input message. +ACC_DECLARE_SYMBOL_ADDR(run_sha256, + num_msg_chunks); // Message length in blocks. -static const otbn_app_t kOtbnAppSha256 = OTBN_APP_T_INIT(run_sha256); -static const otbn_addr_t kOtbnVarSha256State = - OTBN_ADDR_T_INIT(run_sha256, state); -static const otbn_addr_t kOtbnVarSha256Msg = OTBN_ADDR_T_INIT(run_sha256, msg); -static const otbn_addr_t kOtbnVarSha256NumMsgChunks = - OTBN_ADDR_T_INIT(run_sha256, num_msg_chunks); +static const acc_app_t kAccAppSha256 = ACC_APP_T_INIT(run_sha256); +static const acc_addr_t kAccVarSha256State = ACC_ADDR_T_INIT(run_sha256, state); +static const acc_addr_t kAccVarSha256Msg = ACC_ADDR_T_INIT(run_sha256, msg); +static const acc_addr_t kAccVarSha256NumMsgChunks = + ACC_ADDR_T_INIT(run_sha256, num_msg_chunks); void sha256_init(sha256_state_t *state) { // Set the initial state. @@ -81,23 +80,22 @@ void sha256_init(sha256_state_t *state) { } /** - * Run OTBN to process the data currently in DMEM. + * Run ACC to process the data currently in DMEM. * - * @param ctx OTBN message buffer context information (updated in place). + * @param ctx ACC message buffer context information (updated in place). * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -static status_t process_message_buffer(sha256_otbn_ctx_t *ctx) { +static status_t process_message_buffer(sha256_acc_ctx_t *ctx) { // Write the number of blocks to DMEM. - HARDENED_TRY( - otbn_dmem_write(1, &ctx->num_blocks, kOtbnVarSha256NumMsgChunks)); + HARDENED_TRY(acc_dmem_write(1, &ctx->num_blocks, kAccVarSha256NumMsgChunks)); - // Run the OTBN program. - HARDENED_TRY(otbn_execute()); - HARDENED_TRY(otbn_busy_wait_for_done()); + // Run the ACC program. + HARDENED_TRY(acc_execute()); + HARDENED_TRY(acc_busy_wait_for_done()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kSha256MinInstructionCount, kSha256MaxInstructionCount); + ACC_CHECK_INSN_COUNT(kSha256MinInstructionCount, kSha256MaxInstructionCount); // Reset the message buffer counter. ctx->num_blocks = 0; @@ -107,28 +105,28 @@ static status_t process_message_buffer(sha256_otbn_ctx_t *ctx) { /** * Add a single message block to the processing buffer. * - * Runs OTBN if the maximum number of message blocks has been reached. + * Runs ACC if the maximum number of message blocks has been reached. * - * @param ctx OTBN message buffer context information (updated in place). + * @param ctx ACC message buffer context information (updated in place). * @param block Block to write. * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -static status_t process_block(sha256_otbn_ctx_t *ctx, +static status_t process_block(sha256_acc_ctx_t *ctx, const sha256_message_block_t *block) { // Calculate the offset within the message buffer. size_t offset = ctx->num_blocks * kSha256MessageBlockBytes; - otbn_addr_t dst = kOtbnVarSha256Msg + offset; + acc_addr_t dst = kAccVarSha256Msg + offset; // Copy the message block into DMEM. - HARDENED_TRY(otbn_dmem_write(kSha256MessageBlockWords, block->data, dst)); + HARDENED_TRY(acc_dmem_write(kSha256MessageBlockWords, block->data, dst)); ctx->num_blocks += 1; // If we've reached the maximum number of message chunks for a single run, - // then run the OTBN program to update the state in-place. Note that there + // then run the ACC program to update the state in-place. Note that there // is no need to read back and then re-write the state; it'll stay updated // in DMEM for the next run. - if (ctx->num_blocks == kSha256MaxMessageChunksPerOtbnRun) { + if (ctx->num_blocks == kSha256MaxMessageChunksPerAccRun) { HARDENED_TRY(process_message_buffer(ctx)); } return OTCRYPTO_OK; @@ -138,19 +136,18 @@ static status_t process_block(sha256_otbn_ctx_t *ctx, * Pad the block as described in FIPS 180-4, section 5.1.1. * * Padding fills the current block and may require one additional block. This - * function calls `process_block` to load the padded block(s) into OTBN. + * function calls `process_block` to load the padded block(s) into ACC. * * The length of real data in the partial block should be the byte-length of * the message so far (total_len >> 3) modulo `kSha256MessageBlockBytes`. * - * @param ctx OTBN message buffer context information (updated in place). + * @param ctx ACC message buffer context information (updated in place). * @param total_len Total length of message so far. * @param block Current (partial) block. * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -static status_t process_padding(sha256_otbn_ctx_t *ctx, - const uint64_t total_len, +static status_t process_padding(sha256_acc_ctx_t *ctx, const uint64_t total_len, sha256_message_block_t *block) { size_t partial_block_len = (total_len >> 3) % kSha256MessageBlockBytes; @@ -198,8 +195,8 @@ OT_WARN_UNUSED_RESULT static status_t process_message(sha256_state_t *state, const uint8_t *msg, size_t msg_len, hardened_bool_t padding_needed) { - // Load the SHA-256 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppSha256)); + // Load the SHA-256 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppSha256)); // Check the message length. SHA-256 messages must be less than 2^64 bits // long in total. @@ -210,14 +207,14 @@ static status_t process_message(sha256_state_t *state, const uint8_t *msg, } // Calculate the new value of state->total_len. Do NOT update the state yet - // (because if we get an OTBN error, it would become out of sync). + // (because if we get an ACC error, it would become out of sync). sha256_state_t new_state; new_state.total_len = state->total_len + msg_bits; // Set the initial state if at least one block has been received before now. if (state->total_len >= kSha256MessageBlockBytes) { HARDENED_TRY( - otbn_dmem_write(kSha256StateWords, state->H, kOtbnVarSha256State)); + acc_dmem_write(kSha256StateWords, state->H, kAccVarSha256State)); } // Start computing the first block for the hash computation by simply copying @@ -227,8 +224,8 @@ static status_t process_message(sha256_state_t *state, const uint8_t *msg, size_t partial_block_len = (state->total_len >> 3) % kSha256MessageBlockBytes; memcpy(block.data, state->partial_block, partial_block_len); - // Initialize the context for the OTBN message buffer. - sha256_otbn_ctx_t ctx = {.num_blocks = 0}; + // Initialize the context for the ACC message buffer. + sha256_acc_ctx_t ctx = {.num_blocks = 0}; // Process the message one block at a time, including partial data if it is // present (which is only possible on the first iteration). @@ -257,12 +254,12 @@ static status_t process_message(sha256_state_t *state, const uint8_t *msg, HARDENED_TRY(process_message_buffer(&ctx)); } - // Read the final state from OTBN dmem. + // Read the final state from ACC dmem. HARDENED_TRY( - otbn_dmem_read(kSha256StateWords, kOtbnVarSha256State, new_state.H)); + acc_dmem_read(kSha256StateWords, kAccVarSha256State, new_state.H)); - // Clear OTBN's memory. - HARDENED_TRY(otbn_dmem_sec_wipe()); + // Clear ACC's memory. + HARDENED_TRY(acc_dmem_sec_wipe()); // At this point, no more errors are possible; it is safe to update the // context object. diff --git a/sw/device/lib/crypto/impl/sha2/sha256.h b/sw/device/lib/crypto/impl/sha2/sha256.h index bf77b649331..4ec553f1b60 100644 --- a/sw/device/lib/crypto/impl/sha2/sha256.h +++ b/sw/device/lib/crypto/impl/sha2/sha256.h @@ -7,7 +7,7 @@ #include "stdint.h" #include "sw/device/lib/base/hardened.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #ifdef __cplusplus extern "C" { @@ -82,7 +82,7 @@ typedef struct sha256_state { /** * One-shot SHA-256 hash computation. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param msg Input message * @param msg_len Input message length in bytes @@ -112,7 +112,7 @@ void sha256_init(sha256_state_t *state); * * Incorporates the new message data into the hash context. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param state Hash context object; updated in-place. * @param msg Input message. @@ -132,7 +132,7 @@ status_t sha256_update(sha256_state_t *state, const uint8_t *msg, * The caller must ensure that at least `kSha256DigestBytes` bytes of space are * available at the location pointed to by `digest`. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param state Hash context object. * @param msg Input message diff --git a/sw/device/lib/crypto/impl/sha2/sha512.c b/sw/device/lib/crypto/impl/sha2/sha512.c index cdceb8d16f1..a55c70d0a0e 100644 --- a/sw/device/lib/crypto/impl/sha2/sha512.c +++ b/sw/device/lib/crypto/impl/sha2/sha512.c @@ -13,8 +13,8 @@ #include "sw/device/lib/base/hardened_memory.h" #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/memory.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/drivers/rv_core_ibex.h" #include "sw/device/lib/crypto/impl/sha2/sha512_insn_counts.h" #include "sw/device/lib/crypto/impl/status.h" @@ -24,12 +24,12 @@ enum { /** - * Maximum number of message chunks that the OTBN app can accept. + * Maximum number of message chunks that the ACC app can accept. * * This number is based on the DMEM size limit and usage by the SHA-512 app * itself; see `run_sha512.s` for the detailed calculation. */ - kSha512MaxMessageChunksPerOtbnRun = 16, + kSha512MaxMessageChunksPerAccRun = 16, }; /** @@ -40,14 +40,14 @@ typedef struct sha512_message_block { } sha512_message_block_t; /** - * Context object for the OTBN message buffer. + * Context object for the ACC message buffer. */ -typedef struct sha512_otbn_ctx { +typedef struct sha512_acc_ctx { /** * Number of message blocks currently loaded. */ size_t num_blocks; -} sha512_otbn_ctx_t; +} sha512_acc_ctx_t; // Initial state for SHA-384 (see FIPS 180-4, section 5.3.4). static const uint32_t kSha384InitialState[] = { @@ -65,17 +65,16 @@ static const uint32_t kSha512InitialState[kSha512StateWords] = { static_assert(sizeof(kSha512InitialState) == kSha512StateBytes, "Initial state for SHA-512 has an unexpected size."); -OTBN_DECLARE_APP_SYMBOLS(run_sha512); // The OTBN SHA-512 app. -OTBN_DECLARE_SYMBOL_ADDR(run_sha512, state); // Hash state. -OTBN_DECLARE_SYMBOL_ADDR(run_sha512, msg); // Input message. -OTBN_DECLARE_SYMBOL_ADDR(run_sha512, n_chunks); // Message length in blocks. +ACC_DECLARE_APP_SYMBOLS(run_sha512); // The ACC SHA-512 app. +ACC_DECLARE_SYMBOL_ADDR(run_sha512, state); // Hash state. +ACC_DECLARE_SYMBOL_ADDR(run_sha512, msg); // Input message. +ACC_DECLARE_SYMBOL_ADDR(run_sha512, n_chunks); // Message length in blocks. -static const otbn_app_t kOtbnAppSha512 = OTBN_APP_T_INIT(run_sha512); -static const otbn_addr_t kOtbnVarSha512State = - OTBN_ADDR_T_INIT(run_sha512, state); -static const otbn_addr_t kOtbnVarSha512Msg = OTBN_ADDR_T_INIT(run_sha512, msg); -static const otbn_addr_t kOtbnVarSha512NChunks = - OTBN_ADDR_T_INIT(run_sha512, n_chunks); +static const acc_app_t kAccAppSha512 = ACC_APP_T_INIT(run_sha512); +static const acc_addr_t kAccVarSha512State = ACC_ADDR_T_INIT(run_sha512, state); +static const acc_addr_t kAccVarSha512Msg = ACC_ADDR_T_INIT(run_sha512, msg); +static const acc_addr_t kAccVarSha512NChunks = + ACC_ADDR_T_INIT(run_sha512, n_chunks); void sha512_init(sha512_state_t *state) { // Set the initial state. @@ -104,7 +103,7 @@ void sha384_init(sha512_state_t *state) { * message length exceeds the SHA-512/SHA-384 maximum of 2^128 bits. * * This function is does not modify the state object; this is because in case - * of OTBN errors partway through the operation, the state could get out of + * of ACC errors partway through the operation, the state could get out of * sync. * * @param state Context object. @@ -132,22 +131,22 @@ static status_t get_new_total_len(const sha512_state_t *state, size_t msg_len, } /** - * Run OTBN to process the data currently in DMEM. + * Run ACC to process the data currently in DMEM. * - * @param ctx OTBN message buffer context information (updated in place). + * @param ctx ACC message buffer context information (updated in place). * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -static status_t process_message_buffer(sha512_otbn_ctx_t *ctx) { +static status_t process_message_buffer(sha512_acc_ctx_t *ctx) { // Write the number of blocks to DMEM. - HARDENED_TRY(otbn_dmem_write(1, &ctx->num_blocks, kOtbnVarSha512NChunks)); + HARDENED_TRY(acc_dmem_write(1, &ctx->num_blocks, kAccVarSha512NChunks)); - // Run the OTBN program. - HARDENED_TRY(otbn_execute()); - HARDENED_TRY(otbn_busy_wait_for_done()); + // Run the ACC program. + HARDENED_TRY(acc_execute()); + HARDENED_TRY(acc_busy_wait_for_done()); // Check instruction count. - OTBN_CHECK_INSN_COUNT(kSha512MinInstructionCount, kSha512MaxInstructionCount); + ACC_CHECK_INSN_COUNT(kSha512MinInstructionCount, kSha512MaxInstructionCount); // Reset the message buffer counter. ctx->num_blocks = 0; @@ -157,18 +156,18 @@ static status_t process_message_buffer(sha512_otbn_ctx_t *ctx) { /** * Add a single message block to the processing buffer. * - * Runs OTBN if the maximum number of message blocks has been reached. + * Runs ACC if the maximum number of message blocks has been reached. * - * @param ctx OTBN message buffer context information (updated in place). + * @param ctx ACC message buffer context information (updated in place). * @param block Block to write. * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -static status_t process_block(sha512_otbn_ctx_t *ctx, +static status_t process_block(sha512_acc_ctx_t *ctx, const sha512_message_block_t *block) { // Calculate the offset within the message buffer. size_t offset = ctx->num_blocks * kSha512MessageBlockBytes; - otbn_addr_t dst = kOtbnVarSha512Msg + offset; + acc_addr_t dst = kAccVarSha512Msg + offset; // Copy the message block into DMEM. The SHA-512 app expects 64-bit words // within the message in big-endian form, so we copy 64 bits at a time and @@ -176,18 +175,18 @@ static status_t process_block(sha512_otbn_ctx_t *ctx, for (size_t i = 0; i + 1 < kSha512MessageBlockWords; i += 2) { uint32_t bytes_7to4 = __builtin_bswap32(block->data[i + 1]); uint32_t bytes_3to0 = __builtin_bswap32(block->data[i]); - HARDENED_TRY(otbn_dmem_write(1, &bytes_7to4, dst)); + HARDENED_TRY(acc_dmem_write(1, &bytes_7to4, dst)); dst += sizeof(uint32_t); - HARDENED_TRY(otbn_dmem_write(1, &bytes_3to0, dst)); + HARDENED_TRY(acc_dmem_write(1, &bytes_3to0, dst)); dst += sizeof(uint32_t); } ctx->num_blocks += 1; // If we've reached the maximum number of message chunks for a single run, - // then run the OTBN program to update the state in-place. Note that there + // then run the ACC program to update the state in-place. Note that there // is no need to read back and then re-write the state; it'll stay updated // in DMEM for the next run. - if (ctx->num_blocks == kSha512MaxMessageChunksPerOtbnRun) { + if (ctx->num_blocks == kSha512MaxMessageChunksPerAccRun) { HARDENED_TRY(process_message_buffer(ctx)); } return OTCRYPTO_OK; @@ -197,18 +196,18 @@ static status_t process_block(sha512_otbn_ctx_t *ctx, * Pad the block as described in FIPS 180-4, section 5.1.2. * * Padding fills the current block and may require one additional block. This - * function calls `process_block` to load the padded block(s) into OTBN. + * function calls `process_block` to load the padded block(s) into ACC. * * The length of real data in the partial block should be the byte-length of * the message so far (total_len >> 3) modulo `kSha512MessageBlockBytes`. * - * @param ctx OTBN message buffer context information (updated in place). + * @param ctx ACC message buffer context information (updated in place). * @param total_len Total length of message so far. * @param block Current (partial) block. * @return Result of the operation. */ OT_WARN_UNUSED_RESULT -static status_t process_padding(sha512_otbn_ctx_t *ctx, +static status_t process_padding(sha512_acc_ctx_t *ctx, const sha512_message_length_t total_len, sha512_message_block_t *block) { size_t partial_block_len = (total_len.lower >> 3) % kSha512MessageBlockBytes; @@ -261,22 +260,22 @@ OT_WARN_UNUSED_RESULT static status_t process_message(sha512_state_t *state, const uint8_t *msg, size_t msg_len, hardened_bool_t padding_needed) { - // Load the SHA-512 app. Fails if OTBN is non-idle. - HARDENED_TRY(otbn_load_app(kOtbnAppSha512)); + // Load the SHA-512 app. Fails if ACC is non-idle. + HARDENED_TRY(acc_load_app(kAccAppSha512)); // Calculate the new value of state->total_len. Do NOT update the state yet - // (because if we get an OTBN error, it would become out of sync). + // (because if we get an ACC error, it would become out of sync). sha512_state_t new_state; HARDENED_TRY(get_new_total_len(state, msg_len, &new_state.total_len)); - // Set the initial state. The OTBN app expects the state in a pre-processed + // Set the initial state. The ACC app expects the state in a pre-processed // format, with the 64-bit state words aligned to wide-word boundaries. - otbn_addr_t state_write_addr = kOtbnVarSha512State; + acc_addr_t state_write_addr = kAccVarSha512State; for (size_t i = 0; i + 1 < kSha512StateWords; i += 2) { - HARDENED_TRY(otbn_dmem_write(1, &state->H[i + 1], state_write_addr)); + HARDENED_TRY(acc_dmem_write(1, &state->H[i + 1], state_write_addr)); HARDENED_TRY( - otbn_dmem_write(1, &state->H[i], state_write_addr + sizeof(uint32_t))); - state_write_addr += kOtbnWideWordNumBytes; + acc_dmem_write(1, &state->H[i], state_write_addr + sizeof(uint32_t))); + state_write_addr += kAccWideWordNumBytes; } // Start computing the first block for the hash computation by simply copying @@ -287,8 +286,8 @@ static status_t process_message(sha512_state_t *state, const uint8_t *msg, (state->total_len.lower >> 3) % kSha512MessageBlockBytes; hardened_memcpy(block.data, state->partial_block, kSha512MessageBlockWords); - // Initialize the context for the OTBN message buffer. - sha512_otbn_ctx_t ctx = {.num_blocks = 0}; + // Initialize the context for the ACC message buffer. + sha512_acc_ctx_t ctx = {.num_blocks = 0}; // Process the message one block at a time, including partial data if it is // present (which is only possible on the first iteration). @@ -317,19 +316,19 @@ static status_t process_message(sha512_state_t *state, const uint8_t *msg, HARDENED_TRY(process_message_buffer(&ctx)); } - // Read the final state from OTBN dmem. The state is still in the special - // form the OTBN app uses, with the 64-bit state words aligned to wide-word + // Read the final state from ACC dmem. The state is still in the special + // form the ACC app uses, with the 64-bit state words aligned to wide-word // boundaries. - otbn_addr_t state_read_addr = kOtbnVarSha512State; + acc_addr_t state_read_addr = kAccVarSha512State; for (size_t i = 0; i + 1 < kSha512StateWords; i += 2) { - HARDENED_TRY(otbn_dmem_read(1, state_read_addr, &new_state.H[i + 1])); + HARDENED_TRY(acc_dmem_read(1, state_read_addr, &new_state.H[i + 1])); HARDENED_TRY( - otbn_dmem_read(1, state_read_addr + sizeof(uint32_t), &new_state.H[i])); - state_read_addr += kOtbnWideWordNumBytes; + acc_dmem_read(1, state_read_addr + sizeof(uint32_t), &new_state.H[i])); + state_read_addr += kAccWideWordNumBytes; } - // Clear OTBN's memory. - HARDENED_TRY(otbn_dmem_sec_wipe()); + // Clear ACC's memory. + HARDENED_TRY(acc_dmem_sec_wipe()); // At this point, no more errors are possible; it is safe to update the // context object. diff --git a/sw/device/lib/crypto/impl/sha2/sha512.h b/sw/device/lib/crypto/impl/sha2/sha512.h index 3605e75c22e..0d856a55810 100644 --- a/sw/device/lib/crypto/impl/sha2/sha512.h +++ b/sw/device/lib/crypto/impl/sha2/sha512.h @@ -6,7 +6,7 @@ #define OPENTITAN_SW_DEVICE_LIB_CRYPTO_IMPL_SHA2_SHA512_H_ #include "sw/device/lib/base/hardened.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #ifdef __cplusplus extern "C" { @@ -121,7 +121,7 @@ typedef sha512_state_t sha384_state_t; /** * One-shot SHA-384 hash computation. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param msg Input message * @param msg_len Input message length in bytes @@ -151,7 +151,7 @@ void sha384_init(sha384_state_t *state); * * Incorporates the new message data into the hash context. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param state Hash context object; updated in-place. * @param msg Input message. @@ -171,7 +171,7 @@ status_t sha384_update(sha384_state_t *state, const uint8_t *msg, * The caller must ensure that at least `kSha384DigestBytes` bytes of space are * available at the location pointed to by `digest`. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param state Hash context object. * @param msg Input message @@ -185,7 +185,7 @@ status_t sha384_final(sha384_state_t *state, uint32_t *digest); /** * One-shot SHA-512 hash computation. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param msg Input message * @param msg_len Input message length in bytes @@ -215,7 +215,7 @@ void sha512_init(sha512_state_t *state); * * Incorporates the new message data into the hash context. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param state Hash context object; updated in-place. * @param msg Input message. @@ -235,7 +235,7 @@ status_t sha512_update(sha512_state_t *state, const uint8_t *msg, * The caller must ensure that at least `kSha512DigestBytes` bytes of space are * available at the location pointed to by `digest`. * - * Returns OTCRYPTO_ASYNC_INCOMPLETE if OTBN is busy. + * Returns OTCRYPTO_ASYNC_INCOMPLETE if ACC is busy. * * @param state Hash context object. * @param msg Input message diff --git a/sw/device/lib/crypto/include/rsa.h b/sw/device/lib/crypto/include/rsa.h index 8dcfe12d592..a826caeda7b 100644 --- a/sw/device/lib/crypto/include/rsa.h +++ b/sw/device/lib/crypto/include/rsa.h @@ -393,7 +393,7 @@ otcrypto_status_t otcrypto_rsa_decrypt( /** * Starts the asynchronous RSA key generation function. * - * Initializes OTBN and starts the OTBN routine to compute the RSA + * Initializes ACC and starts the ACC routine to compute the RSA * private key (d), RSA public key exponent (e) and modulus (n). * * @param size RSA size parameter. @@ -458,7 +458,7 @@ otcrypto_status_t otcrypto_rsa_keypair_from_cofactor_async_finalize( /** * Starts the asynchronous digital signature generation function. * - * Initializes OTBN and starts the OTBN routine to compute the digital + * Initializes ACC and starts the ACC routine to compute the digital * signature on the input message. * * @param private_key Pointer to blinded private key struct. @@ -487,7 +487,7 @@ otcrypto_status_t otcrypto_rsa_sign_async_finalize( /** * Starts the asynchronous signature verification function. * - * Initializes OTBN and starts the OTBN routine to recover the message + * Initializes ACC and starts the ACC routine to recover the message * from the input signature. * * @param public_key Pointer to public key struct. @@ -540,7 +540,7 @@ otcrypto_status_t otcrypto_rsa_encrypt_async_start( * * See `otcrypto_rsa_encrypt` for details on the length requirements for * `ciphertext`. Infers the RSA size from `ciphertext`'s length, and will - * return an error if this does not match the RSA size for the current OTBN + * return an error if this does not match the RSA size for the current ACC * data. * * @param[out] ciphertext Buffer for the ciphertext. diff --git a/sw/device/lib/dif/BUILD b/sw/device/lib/dif/BUILD index 22bc782300d..c184c8629de 100644 --- a/sw/device/lib/dif/BUILD +++ b/sw/device/lib/dif/BUILD @@ -38,6 +38,7 @@ cc_library( DIFS = { "adc_ctrl": {}, + "acc": {}, "aes": {}, "alert_handler": { "ut_target_compatible_with": opentitan_require_top("earlgrey"), @@ -67,7 +68,6 @@ DIFS = { "mbx": { "deps": ["//sw/device/lib/base:abs_mmio"], }, - "otbn": {}, "otp_ctrl": { "ut_target_compatible_with": opentitan_require_top("earlgrey"), }, diff --git a/sw/device/lib/dif/dif_acc.c b/sw/device/lib/dif/dif_acc.c new file mode 100644 index 00000000000..ac0522aae96 --- /dev/null +++ b/sw/device/lib/dif/dif_acc.c @@ -0,0 +1,226 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/lib/dif/dif_acc.h" + +#include + +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "hw/top/acc_regs.h" // Generated. + +static_assert(kDifAccErrBitsBadDataAddr == + (1 << ACC_ERR_BITS_BAD_DATA_ADDR_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsBadInsnAddr == + (1 << ACC_ERR_BITS_BAD_INSN_ADDR_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsCallStack == (1 << ACC_ERR_BITS_CALL_STACK_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsIllegalInsn == (1 << ACC_ERR_BITS_ILLEGAL_INSN_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsLoop == (1 << ACC_ERR_BITS_LOOP_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsImemIntgViolation == + (1 << ACC_ERR_BITS_IMEM_INTG_VIOLATION_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsDmemIntgViolation == + (1 << ACC_ERR_BITS_DMEM_INTG_VIOLATION_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsRegIntgViolation == + (1 << ACC_ERR_BITS_REG_INTG_VIOLATION_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsBusIntgViolation == + (1 << ACC_ERR_BITS_BUS_INTG_VIOLATION_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsIllegalBusAccess == + (1 << ACC_ERR_BITS_ILLEGAL_BUS_ACCESS_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsLifecycleEscalation == + (1 << ACC_ERR_BITS_LIFECYCLE_ESCALATION_BIT), + "Layout of error bits changed."); +static_assert(kDifAccErrBitsFatalSoftware == + (1 << ACC_ERR_BITS_FATAL_SOFTWARE_BIT), + "Layout of error bits changed."); + +/** + * Data width of big number subset, in bytes. + */ +const int kDifAccWlenBytes = 256 / 8; + +/** + * Ensures that `offset` and `size` are valid for a given `mem_size`. + * + * Valid are 32b word accesses to 32b-aligned memory locations within + * `mem_size`. + */ +static bool check_offset_len(uint32_t offset_bytes, size_t len_bytes, + size_t mem_size) { + // The overflow check below assumes/requires two unsigned inputs. + return (len_bytes % sizeof(uint32_t) == 0 && + offset_bytes % sizeof(uint32_t) == 0 && + offset_bytes + len_bytes >= len_bytes && + offset_bytes + len_bytes <= mem_size); +} + +dif_result_t dif_acc_reset(const dif_acc_t *acc) { + if (acc == NULL) { + return kDifBadArg; + } + + mmio_region_write32(acc->base_addr, ACC_INTR_ENABLE_REG_OFFSET, 0); + + // Clear all pending interrupts. + mmio_region_write32(acc->base_addr, ACC_INTR_STATE_REG_OFFSET, 0xFFFFFFFF); + + return kDifOk; +} + +dif_result_t dif_acc_write_cmd(const dif_acc_t *acc, dif_acc_cmd_t cmd) { + if (acc == NULL) { + return kDifBadArg; + } + + mmio_region_write32(acc->base_addr, ACC_CMD_REG_OFFSET, cmd); + + return kDifOk; +} + +dif_result_t dif_acc_get_status(const dif_acc_t *acc, + dif_acc_status_t *status) { + if (acc == NULL || status == NULL) { + return kDifBadArg; + } + + *status = mmio_region_read32(acc->base_addr, ACC_STATUS_REG_OFFSET); + + return kDifOk; +} + +dif_result_t dif_acc_get_err_bits(const dif_acc_t *acc, + dif_acc_err_bits_t *err_bits) { + if (acc == NULL || err_bits == NULL) { + return kDifBadArg; + } + + uint32_t err_bits_raw = + mmio_region_read32(acc->base_addr, ACC_ERR_BITS_REG_OFFSET); + + *err_bits = err_bits_raw; + return kDifOk; +} + +dif_result_t dif_acc_get_insn_cnt(const dif_acc_t *acc, uint32_t *insn_cnt) { + if (acc == NULL || insn_cnt == NULL) { + return kDifBadArg; + } + + *insn_cnt = mmio_region_read32(acc->base_addr, ACC_INSN_CNT_REG_OFFSET); + return kDifOk; +} + +dif_result_t dif_acc_get_load_checksum(const dif_acc_t *acc, + uint32_t *checksum) { + if (acc == NULL || checksum == NULL) { + return kDifBadArg; + } + + *checksum = mmio_region_read32(acc->base_addr, ACC_LOAD_CHECKSUM_REG_OFFSET); + return kDifOk; +} + +dif_result_t dif_acc_clear_load_checksum(const dif_acc_t *acc) { + if (acc == NULL) { + return kDifBadArg; + } + + mmio_region_write32(acc->base_addr, ACC_LOAD_CHECKSUM_REG_OFFSET, 0); + + return kDifOk; +} + +dif_result_t dif_acc_imem_write(const dif_acc_t *acc, uint32_t offset_bytes, + const void *src, size_t len_bytes) { + if (acc == NULL || src == NULL || + !check_offset_len(offset_bytes, len_bytes, ACC_IMEM_SIZE_BYTES)) { + return kDifBadArg; + } + + mmio_region_memcpy_to_mmio32( + acc->base_addr, ACC_IMEM_REG_OFFSET + offset_bytes, src, len_bytes); + + return kDifOk; +} + +dif_result_t dif_acc_imem_read(const dif_acc_t *acc, uint32_t offset_bytes, + void *dest, size_t len_bytes) { + if (acc == NULL || dest == NULL || + !check_offset_len(offset_bytes, len_bytes, ACC_IMEM_SIZE_BYTES)) { + return kDifBadArg; + } + + mmio_region_memcpy_from_mmio32( + acc->base_addr, ACC_IMEM_REG_OFFSET + offset_bytes, dest, len_bytes); + + return kDifOk; +} + +dif_result_t dif_acc_dmem_write(const dif_acc_t *acc, uint32_t offset_bytes, + const void *src, size_t len_bytes) { + if (acc == NULL || src == NULL || + !check_offset_len(offset_bytes, len_bytes, ACC_DMEM_SIZE_BYTES)) { + return kDifBadArg; + } + + mmio_region_memcpy_to_mmio32( + acc->base_addr, ACC_DMEM_REG_OFFSET + offset_bytes, src, len_bytes); + + return kDifOk; +} + +dif_result_t dif_acc_dmem_read(const dif_acc_t *acc, uint32_t offset_bytes, + void *dest, size_t len_bytes) { + if (acc == NULL || dest == NULL || + !check_offset_len(offset_bytes, len_bytes, ACC_DMEM_SIZE_BYTES)) { + return kDifBadArg; + } + + mmio_region_memcpy_from_mmio32( + acc->base_addr, ACC_DMEM_REG_OFFSET + offset_bytes, dest, len_bytes); + + return kDifOk; +} + +dif_result_t dif_acc_set_ctrl_software_errs_fatal(const dif_acc_t *acc, + bool enable) { + if (acc == NULL) { + return kDifBadArg; + } + + // Only one bit in the CTRL register so no need to read current value. + uint32_t new_ctrl; + + if (enable) { + new_ctrl = 1; + } else { + new_ctrl = 0; + } + + mmio_region_write32(acc->base_addr, ACC_CTRL_REG_OFFSET, new_ctrl); + if (mmio_region_read32(acc->base_addr, ACC_CTRL_REG_OFFSET) != new_ctrl) { + return kDifUnavailable; + } + + return kDifOk; +} + +size_t dif_acc_get_dmem_size_bytes(const dif_acc_t *acc) { + return ACC_DMEM_SIZE_BYTES; +} + +size_t dif_acc_get_imem_size_bytes(const dif_acc_t *acc) { + return ACC_IMEM_SIZE_BYTES; +} diff --git a/sw/device/lib/dif/dif_acc.h b/sw/device/lib/dif/dif_acc.h new file mode 100644 index 00000000000..ed2066696ac --- /dev/null +++ b/sw/device/lib/dif/dif_acc.h @@ -0,0 +1,261 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_ACC_H_ +#define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_ACC_H_ + +/** + * @file + * @brief ACC Device Interface Functions. + */ + +#include +#include + +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "sw/device/lib/dif/autogen/dif_acc_autogen.h" + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * ACC commands. + */ +typedef enum dif_acc_cmd { + kDifAccCmdExecute = 0xd8, + kDifAccCmdSecWipeDmem = 0xc3, + kDifAccCmdSecWipeImem = 0x1e, +} dif_acc_cmd_t; + +/** + * ACC status. + */ +typedef enum dif_acc_status { + kDifAccStatusIdle = 0x00, + kDifAccStatusBusyExecute = 0x01, + kDifAccStatusBusySecWipeDmem = 0x02, + kDifAccStatusBusySecWipeImem = 0x03, + kDifAccStatusBusySecWipeInt = 0x04, + kDifAccStatusLocked = 0xFF, +} dif_acc_status_t; + +/** + * ACC Errors. + * + * ACC uses a bitfield to indicate which errors have been seen. Multiple errors + * can be seen at the same time. This enum gives the individual bits that may be + * set for different errors. + */ +typedef enum dif_acc_err_bits { + kDifAccErrBitsNoError = 0, + /** A BAD_DATA_ADDR error was observed. */ + kDifAccErrBitsBadDataAddr = (1 << 0), + /** A BAD_INSN_ADDR error was observed. */ + kDifAccErrBitsBadInsnAddr = (1 << 1), + /** A CALL_STACK error was observed. */ + kDifAccErrBitsCallStack = (1 << 2), + /** An ILLEGAL_INSN error was observed. */ + kDifAccErrBitsIllegalInsn = (1 << 3), + /** A LOOP error was observed. */ + kDifAccErrBitsLoop = (1 << 4), + /** A RND_FIPS_CHECK_FAIL error was observed. */ + kDifAccErrBitsRndFipsChkFail = (1 << 7), + /** A IMEM_INTG_VIOLATION error was observed. */ + kDifAccErrBitsImemIntgViolation = (1 << 16), + /** A DMEM_INTG_VIOLATION error was observed. */ + kDifAccErrBitsDmemIntgViolation = (1 << 17), + /** A REG_INTG_VIOLATION error was observed. */ + kDifAccErrBitsRegIntgViolation = (1 << 18), + /** A BUS_INTG_VIOLATION error was observed. */ + kDifAccErrBitsBusIntgViolation = (1 << 19), + /** A BAD_INTERNAL_STATE error was observed. */ + kDifAccErrBitsBadInternalState = (1 << 20), + /** An ILLEGAL_BUS_ACCESS error was observed. */ + kDifAccErrBitsIllegalBusAccess = (1 << 21), + /** A LIFECYCLE_ESCALATION error was observed. */ + kDifAccErrBitsLifecycleEscalation = (1 << 22), + /** A FATAL_SOFTWARE error was observed. */ + kDifAccErrBitsFatalSoftware = (1 << 23), +} dif_acc_err_bits_t; + +/** + * Reset ACC device. + * + * Resets the given ACC device by setting its configuration registers to + * reset values. Disables interrupts, output, and input filter. + * + * @param acc ACC instance. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_reset(const dif_acc_t *acc); + +/** + * Start an operation by issuing a command. + * + * @param acc ACC instance. + * @param cmd The command. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_write_cmd(const dif_acc_t *acc, dif_acc_cmd_t cmd); + +/** + * Gets the current status of ACC. + * + * @param acc ACC instance. + * @param[out] status ACC status. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_get_status(const dif_acc_t *acc, dif_acc_status_t *status); + +/** + * Get the error bits set by the device if the operation failed. + * + * @param acc ACC instance. + * @param[out] err_bits The error bits returned by the hardware. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_get_err_bits(const dif_acc_t *acc, + dif_acc_err_bits_t *err_bits); + +/** + * Gets the number of executed ACC instructions. + * + * Gets the number of instructions executed so far in the current ACC run if + * there is one. Otherwise, gets the number executed in total in the previous + * ACC run. + * + * @param acc ACC instance. + * @param[out] insn_cnt The number of instructions executed by ACC. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_get_insn_cnt(const dif_acc_t *acc, uint32_t *insn_cnt); + +/** + * Gets the content of the load checksum register. + * + * Gets the 32-bit CRC checksum of data written to memory. + * + * @param acc ACC instance. + * @param[out] insn_cnt The number of instructions executed by ACC. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_get_load_checksum(const dif_acc_t *acc, + uint32_t *insn_cnt); + +/** + * Clears the load checksum register. + * + * Writes 0 to the load checksum register to clear it. + * + * @param acc ACC instance. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_clear_load_checksum(const dif_acc_t *acc); + +/** + * Write an ACC application into its instruction memory (IMEM). + * + * Only 32b-aligned 32b word accesses are allowed. + * + * @param acc ACC instance. + * @param offset_bytes the byte offset in IMEM the first word is written to. + * @param src the main memory location to start reading from. + * @param len_bytes number of bytes to copy. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_imem_write(const dif_acc_t *acc, uint32_t offset_bytes, + const void *src, size_t len_bytes); + +/** + * Read from ACC's instruction memory (IMEM). + * + * Only 32b-aligned 32b word accesses are allowed. + * + * @param acc ACC instance + * @param offset_bytes the byte offset in IMEM the first word is read from. + * @param[out] dest the main memory location to copy the data to (preallocated). + * @param len_bytes number of bytes to copy. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_imem_read(const dif_acc_t *acc, uint32_t offset_bytes, + void *dest, size_t len_bytes); + +/** + * Write to ACC's data memory (DMEM). + * + * Only 32b-aligned 32b word accesses are allowed. + * + * @param acc ACC instance. + * @param offset_bytes the byte offset in DMEM the first word is written to. + * @param src the main memory location to start reading from. + * @param len_bytes number of bytes to copy. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_dmem_write(const dif_acc_t *acc, uint32_t offset_bytes, + const void *src, size_t len_bytes); + +/** + * Read from ACC's data memory (DMEM). + * + * Only 32b-aligned 32b word accesses are allowed. + * + * @param acc ACC instance + * @param offset_bytes the byte offset in DMEM the first word is read from. + * @param[out] dest the main memory location to copy the data to (preallocated). + * @param len_bytes number of bytes to copy. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_dmem_read(const dif_acc_t *acc, uint32_t offset_bytes, + void *dest, size_t len_bytes); + +/** + * Sets the software errors are fatal bit in the control register. + * + * When set any software error becomes a fatal error. The bit can only be + * changed when the ACC status is IDLE. + * + * @param acc ACC instance. + * @param enable Enable or disable whether software errors are fatal. + * @return The result of the operation, `kDifUnavailable` is returned when the + * requested change cannot be made. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_acc_set_ctrl_software_errs_fatal(const dif_acc_t *acc, + bool enable); + +/** + * Get the size of ACC's data memory in bytes. + * + * @param acc ACC instance. + * @return data memory size in bytes. + */ +size_t dif_acc_get_dmem_size_bytes(const dif_acc_t *acc); + +/** + * Get the size of ACC's instruction memory in bytes. + * + * @param acc ACC instance. + * @return instruction memory size in bytes. + */ +size_t dif_acc_get_imem_size_bytes(const dif_acc_t *acc); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_ACC_H_ diff --git a/sw/device/lib/dif/dif_otbn.md b/sw/device/lib/dif/dif_acc.md similarity index 95% rename from sw/device/lib/dif/dif_otbn.md rename to sw/device/lib/dif/dif_acc.md index f627e1ffc90..fb128e157f4 100644 --- a/sw/device/lib/dif/dif_otbn.md +++ b/sw/device/lib/dif/dif_acc.md @@ -1,6 +1,6 @@ -# OTBN DIF Checklist +# ACC DIF Checklist -This checklist is for [Development Stage](../../../../doc/project_governance/development_stages.md) transitions for the [OTBN DIF](../../../../hw/ip/otbn/README.md). +This checklist is for [Development Stage](../../../../doc/project_governance/development_stages.md) transitions for the [ACC DIF](../../../../hw/ip/acc/README.md). All checklist items refer to the content in the [Checklist](../../../../doc/project_governance/checklist/README.md).

            DIF Checklist

            diff --git a/sw/device/lib/dif/dif_acc_unittest.cc b/sw/device/lib/dif/dif_acc_unittest.cc new file mode 100644 index 00000000000..66d3824313c --- /dev/null +++ b/sw/device/lib/dif/dif_acc_unittest.cc @@ -0,0 +1,394 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/lib/dif/dif_acc.h" + +#include "gtest/gtest.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/base/mock_mmio.h" +#include "sw/device/lib/dif/dif_base.h" +#include "sw/device/lib/dif/dif_test_base.h" + +#include "hw/top/acc_regs.h" // Generated. + +namespace dif_acc_unittest { +namespace { +using mock_mmio::MmioTest; +using mock_mmio::MockDevice; +using testing::Each; +using testing::Eq; +using testing::Test; + +class AccTest : public Test, public MmioTest { + protected: + void ExpectDeviceReset() { + EXPECT_WRITE32(ACC_INTR_ENABLE_REG_OFFSET, 0); + EXPECT_WRITE32(ACC_INTR_STATE_REG_OFFSET, + std::numeric_limits::max()); + } + + dif_acc_t dif_acc_ = {.base_addr = dev().region()}; +}; + +class ResetTest : public AccTest {}; + +TEST_F(ResetTest, NullArgs) { EXPECT_DIF_BADARG(dif_acc_reset(nullptr)); } + +TEST_F(ResetTest, Default) { + ExpectDeviceReset(); + + EXPECT_DIF_OK(dif_acc_reset(&dif_acc_)); +} + +class WriteCmdTest : public AccTest {}; + +TEST_F(WriteCmdTest, NullArgs) { + EXPECT_DIF_BADARG(dif_acc_write_cmd(nullptr, kDifAccCmdExecute)); +} + +TEST_F(WriteCmdTest, Success) { + // Set EXECUTE command. + EXPECT_WRITE32(ACC_CMD_REG_OFFSET, kDifAccCmdExecute); + + EXPECT_DIF_OK(dif_acc_write_cmd(&dif_acc_, kDifAccCmdExecute)); +} + +class GetStatusTest : public AccTest {}; + +TEST_F(GetStatusTest, NullArgs) { + EXPECT_DIF_BADARG(dif_acc_get_status(nullptr, nullptr)); + + EXPECT_DIF_BADARG(dif_acc_get_status(&dif_acc_, nullptr)); + + dif_acc_status_t status = kDifAccStatusBusySecWipeDmem; + EXPECT_DIF_BADARG(dif_acc_get_status(nullptr, &status)); + EXPECT_EQ(status, kDifAccStatusBusySecWipeDmem); +} + +TEST_F(GetStatusTest, Success) { + EXPECT_READ32(ACC_STATUS_REG_OFFSET, kDifAccStatusBusyExecute); + + dif_acc_status_t status; + EXPECT_DIF_OK(dif_acc_get_status(&dif_acc_, &status)); + EXPECT_EQ(status, kDifAccStatusBusyExecute); +} + +class GetErrBitsTest : public AccTest {}; + +TEST_F(GetErrBitsTest, NullArgs) { + EXPECT_DIF_BADARG(dif_acc_get_err_bits(nullptr, nullptr)); + + EXPECT_DIF_BADARG(dif_acc_get_err_bits(&dif_acc_, nullptr)); + + dif_acc_err_bits_t err_bits = kDifAccErrBitsBadDataAddr; + EXPECT_DIF_BADARG(dif_acc_get_err_bits(nullptr, &err_bits)); + EXPECT_EQ(err_bits, kDifAccErrBitsBadDataAddr); +} + +TEST_F(GetErrBitsTest, Success) { + EXPECT_READ32(ACC_ERR_BITS_REG_OFFSET, + kDifAccErrBitsIllegalInsn | kDifAccErrBitsRegIntgViolation); + + dif_acc_err_bits_t err_bits; + EXPECT_DIF_OK(dif_acc_get_err_bits(&dif_acc_, &err_bits)); + EXPECT_EQ(err_bits, + kDifAccErrBitsIllegalInsn | kDifAccErrBitsRegIntgViolation); +} + +class GetInsnCntTest : public AccTest {}; + +TEST_F(GetInsnCntTest, NullArgs) { + EXPECT_DIF_BADARG(dif_acc_get_insn_cnt(nullptr, nullptr)); + + EXPECT_DIF_BADARG(dif_acc_get_insn_cnt(&dif_acc_, nullptr)); + + uint32_t insn_cnt = 55; + EXPECT_DIF_BADARG(dif_acc_get_insn_cnt(nullptr, &insn_cnt)); + EXPECT_EQ(insn_cnt, 55); +} + +TEST_F(GetInsnCntTest, Success) { + EXPECT_READ32(ACC_INSN_CNT_REG_OFFSET, 55); + + uint32_t insn_cnt; + EXPECT_DIF_OK(dif_acc_get_insn_cnt(&dif_acc_, &insn_cnt)); + EXPECT_EQ(insn_cnt, 55); +} + +class ImemWriteTest : public AccTest {}; + +TEST_F(ImemWriteTest, NullArgs) { + uint32_t test_data[] = {0}; + + EXPECT_DIF_BADARG(dif_acc_imem_write(nullptr, 0, nullptr, 4)); + + EXPECT_DIF_BADARG(dif_acc_imem_write(nullptr, 0, test_data, 4)); + + EXPECT_DIF_BADARG(dif_acc_imem_write(&dif_acc_, 0, nullptr, 4)); +} + +TEST_F(ImemWriteTest, BadLenBytes) { + uint32_t test_data[] = {0}; + + // `len_bytes` must be a multiple of 4 bytes. + EXPECT_DIF_BADARG(dif_acc_imem_write(&dif_acc_, 0, test_data, 1)); + + EXPECT_DIF_BADARG(dif_acc_imem_write(&dif_acc_, 0, test_data, 2)); +} + +TEST_F(ImemWriteTest, BadOffset) { + uint32_t test_data[] = {0}; + + // `offset` must be 32b-aligned. + EXPECT_DIF_BADARG(dif_acc_imem_write(&dif_acc_, 1, test_data, 4)); + + EXPECT_DIF_BADARG(dif_acc_imem_write(&dif_acc_, 2, test_data, 4)); +} + +TEST_F(ImemWriteTest, BadAddressBeyondMemorySize) { + uint32_t test_data[] = {0}; + + EXPECT_DIF_BADARG( + dif_acc_imem_write(&dif_acc_, ACC_IMEM_SIZE_BYTES, test_data, 4)); +} + +TEST_F(ImemWriteTest, BadAddressIntegerOverflow) { + uint32_t test_data[4] = {0}; + + EXPECT_DIF_BADARG(dif_acc_imem_write(&dif_acc_, 0xFFFFFFFC, test_data, 16)); +} + +TEST_F(ImemWriteTest, SuccessWithoutOffset) { + // Test assumption. + ASSERT_GE(ACC_IMEM_SIZE_BYTES, 8); + + uint32_t test_data[2] = {0x12345678, 0xabcdef01}; + + EXPECT_WRITE32(ACC_IMEM_REG_OFFSET, test_data[0]); + EXPECT_WRITE32(ACC_IMEM_REG_OFFSET + 4, test_data[1]); + + EXPECT_DIF_OK(dif_acc_imem_write(&dif_acc_, 0, test_data, 8)); +} + +TEST_F(ImemWriteTest, SuccessWithOffset) { + // Test assumption. + ASSERT_GE(ACC_IMEM_SIZE_BYTES, 12); + + uint32_t test_data[2] = {0x12345678, 0xabcdef01}; + + EXPECT_WRITE32(ACC_IMEM_REG_OFFSET + 4, test_data[0]); + EXPECT_WRITE32(ACC_IMEM_REG_OFFSET + 8, test_data[1]); + + EXPECT_DIF_OK(dif_acc_imem_write(&dif_acc_, 4, test_data, 8)); +} + +class ImemReadTest : public AccTest {}; + +TEST_F(ImemReadTest, NullArgs) { + uint32_t test_data[2] = {0x12345678, 0xabcdef01}; + + EXPECT_DIF_BADARG(dif_acc_imem_read(nullptr, 0, nullptr, sizeof(test_data))); + + EXPECT_DIF_BADARG( + dif_acc_imem_read(nullptr, 0, test_data, sizeof(test_data))); + + EXPECT_DIF_BADARG( + dif_acc_imem_read(&dif_acc_, 0, nullptr, sizeof(test_data))); + + // No side effects are expected. + EXPECT_EQ(test_data[0], 0x12345678); + EXPECT_EQ(test_data[1], 0xabcdef01); +} + +TEST_F(ImemReadTest, BadLenBytes) { + uint32_t test_data[2] = {0}; + + // `len_bytes` must be a multiple of 4 bytes. + EXPECT_DIF_BADARG(dif_acc_imem_read(&dif_acc_, 0, test_data, 1)); + + EXPECT_DIF_BADARG(dif_acc_imem_read(&dif_acc_, 0, test_data, 2)); +} + +TEST_F(ImemReadTest, BadOffset) { + uint32_t test_data[2] = {0}; + + // `offset` must be 32b-aligned. + EXPECT_DIF_BADARG( + dif_acc_imem_read(&dif_acc_, 1, test_data, sizeof(test_data))); + + EXPECT_DIF_BADARG( + dif_acc_imem_read(&dif_acc_, 2, test_data, sizeof(test_data))); +} + +TEST_F(ImemReadTest, SuccessWithoutOffset) { + // Assumption in the test. + ASSERT_GE(ACC_IMEM_SIZE_BYTES, 8); + + uint32_t test_data[2] = {0}; + + EXPECT_READ32(ACC_IMEM_REG_OFFSET, 0x12345678); + EXPECT_READ32(ACC_IMEM_REG_OFFSET + 4, 0xabcdef01); + + EXPECT_DIF_OK(dif_acc_imem_read(&dif_acc_, 0, test_data, 8)); + EXPECT_EQ(test_data[0], 0x12345678); + EXPECT_EQ(test_data[1], 0xabcdef01); +} + +TEST_F(ImemReadTest, SuccessWithOffset) { + // Assumption in the test. + ASSERT_GE(ACC_IMEM_SIZE_BYTES, 12); + + uint32_t test_data[2] = {0}; + + EXPECT_READ32(ACC_IMEM_REG_OFFSET + 4, 0x12345678); + EXPECT_READ32(ACC_IMEM_REG_OFFSET + 8, 0xabcdef01); + + EXPECT_DIF_OK(dif_acc_imem_read(&dif_acc_, 4, test_data, 8)); + EXPECT_EQ(test_data[0], 0x12345678); + EXPECT_EQ(test_data[1], 0xabcdef01); +} + +class DmemWriteTest : public AccTest {}; + +TEST_F(DmemWriteTest, NullArgs) { + uint32_t test_data[1] = {0}; + + EXPECT_DIF_BADARG(dif_acc_dmem_write(nullptr, 0, nullptr, 4)); + + EXPECT_DIF_BADARG(dif_acc_dmem_write(nullptr, 0, test_data, 4)); + + EXPECT_DIF_BADARG(dif_acc_dmem_write(&dif_acc_, 0, nullptr, 4)); +} + +TEST_F(DmemWriteTest, BadLenBytes) { + uint32_t test_data[1] = {0}; + + // `len_bytes` must be a multiple of 4 bytes. + EXPECT_DIF_BADARG(dif_acc_dmem_write(&dif_acc_, 0, test_data, 1)); + + EXPECT_DIF_BADARG(dif_acc_dmem_write(&dif_acc_, 0, test_data, 2)); +} + +TEST_F(DmemWriteTest, BadOffset) { + uint32_t test_data[1] = {0}; + + // `offset` must be 32b-aligned. + EXPECT_DIF_BADARG(dif_acc_dmem_write(&dif_acc_, 1, test_data, 4)); + + EXPECT_DIF_BADARG(dif_acc_dmem_write(&dif_acc_, 2, test_data, 4)); +} + +TEST_F(DmemWriteTest, SuccessWithoutOffset) { + // Test assumption. + ASSERT_GE(ACC_DMEM_SIZE_BYTES, 8); + + uint32_t test_data[2] = {0x12345678, 0xabcdef01}; + + EXPECT_WRITE32(ACC_DMEM_REG_OFFSET, test_data[0]); + EXPECT_WRITE32(ACC_DMEM_REG_OFFSET + 4, test_data[1]); + + EXPECT_DIF_OK(dif_acc_dmem_write(&dif_acc_, 0, test_data, 8)); +} + +TEST_F(DmemWriteTest, SuccessWithOffset) { + // Test assumption. + ASSERT_GE(ACC_DMEM_SIZE_BYTES, 12); + + uint32_t test_data[2] = {0x12345678, 0xabcdef01}; + + EXPECT_WRITE32(ACC_DMEM_REG_OFFSET + 4, test_data[0]); + EXPECT_WRITE32(ACC_DMEM_REG_OFFSET + 8, test_data[1]); + + EXPECT_DIF_OK(dif_acc_dmem_write(&dif_acc_, 4, test_data, 8)); +} + +class DmemReadTest : public AccTest {}; + +TEST_F(DmemReadTest, NullArgs) { + uint32_t test_data[2] = {0x12345678, 0xabcdef01}; + + EXPECT_DIF_BADARG(dif_acc_dmem_read(nullptr, 0, nullptr, sizeof(test_data))); + + EXPECT_DIF_BADARG( + dif_acc_dmem_read(nullptr, 0, test_data, sizeof(test_data))); + + EXPECT_DIF_BADARG( + dif_acc_dmem_read(&dif_acc_, 0, nullptr, sizeof(test_data))); + + // No side effects are expected. + EXPECT_EQ(test_data[0], 0x12345678); + EXPECT_EQ(test_data[1], 0xabcdef01); +} + +TEST_F(DmemReadTest, BadLenBytes) { + uint32_t test_data[2] = {0}; + + // `len_bytes` must be a multiple of 4 bytes. + EXPECT_DIF_BADARG(dif_acc_dmem_read(&dif_acc_, 0, test_data, 1)); + + EXPECT_DIF_BADARG(dif_acc_dmem_read(&dif_acc_, 0, test_data, 2)); +} + +TEST_F(DmemReadTest, BadOffset) { + uint32_t test_data[2] = {0}; + + // `offset` must be 32b-aligned. + EXPECT_DIF_BADARG( + dif_acc_dmem_read(&dif_acc_, 1, test_data, sizeof(test_data))); + + EXPECT_DIF_BADARG( + dif_acc_dmem_read(&dif_acc_, 2, test_data, sizeof(test_data))); +} + +TEST_F(DmemReadTest, SuccessWithoutOffset) { + // Assumption in the test. + ASSERT_GE(ACC_DMEM_SIZE_BYTES, 8); + + uint32_t test_data[2] = {0}; + + EXPECT_READ32(ACC_DMEM_REG_OFFSET, 0x12345678); + EXPECT_READ32(ACC_DMEM_REG_OFFSET + 4, 0xabcdef01); + + EXPECT_DIF_OK(dif_acc_dmem_read(&dif_acc_, 0, test_data, 8)); + EXPECT_EQ(test_data[0], 0x12345678); + EXPECT_EQ(test_data[1], 0xabcdef01); +} + +TEST_F(DmemReadTest, SuccessWithOffset) { + // Assumption in the test. + ASSERT_GE(ACC_DMEM_SIZE_BYTES, 12); + + uint32_t test_data[2] = {0}; + + EXPECT_READ32(ACC_DMEM_REG_OFFSET + 4, 0x12345678); + EXPECT_READ32(ACC_DMEM_REG_OFFSET + 8, 0xabcdef01); + + EXPECT_DIF_OK(dif_acc_dmem_read(&dif_acc_, 4, test_data, 8)); + EXPECT_EQ(test_data[0], 0x12345678); + EXPECT_EQ(test_data[1], 0xabcdef01); +} + +class ControlSoftwareErrorsFatalTest : public AccTest {}; + +TEST_F(ControlSoftwareErrorsFatalTest, NullArgs) { + EXPECT_DIF_BADARG(dif_acc_set_ctrl_software_errs_fatal(nullptr, false)); +} + +TEST_F(ControlSoftwareErrorsFatalTest, Success) { + EXPECT_WRITE32(ACC_CTRL_REG_OFFSET, 0x1); + EXPECT_READ32(ACC_CTRL_REG_OFFSET, 0x1); + + EXPECT_DIF_OK(dif_acc_set_ctrl_software_errs_fatal(&dif_acc_, true)); +} + +TEST_F(ControlSoftwareErrorsFatalTest, Failure) { + EXPECT_WRITE32(ACC_CTRL_REG_OFFSET, 0x0); + EXPECT_READ32(ACC_CTRL_REG_OFFSET, 0x1); + + EXPECT_EQ(dif_acc_set_ctrl_software_errs_fatal(&dif_acc_, false), + kDifUnavailable); +} + +} // namespace +} // namespace dif_acc_unittest diff --git a/sw/device/lib/dif/dif_clkmgr_unittest.cc b/sw/device/lib/dif/dif_clkmgr_unittest.cc index 0709bf2ebc5..93a7de32ebd 100644 --- a/sw/device/lib/dif/dif_clkmgr_unittest.cc +++ b/sw/device/lib/dif/dif_clkmgr_unittest.cc @@ -264,9 +264,9 @@ TEST_F(HintableClockTest, GetHint) { { dif_toggle_t state = kDifToggleEnabled; EXPECT_READ32(CLKMGR_CLK_HINTS_REG_OFFSET, - {{CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT, false}}); + {{CLKMGR_CLK_HINTS_CLK_MAIN_ACC_HINT_BIT, false}}); EXPECT_DIF_OK(dif_clkmgr_hintable_clock_get_hint( - &clkmgr_, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT, &state)); + &clkmgr_, CLKMGR_CLK_HINTS_CLK_MAIN_ACC_HINT_BIT, &state)); EXPECT_EQ(state, kDifToggleDisabled); } } @@ -305,9 +305,9 @@ TEST_F(HintableClockTest, GetEnabled) { { dif_toggle_t state = kDifToggleDisabled; EXPECT_READ32(CLKMGR_CLK_HINTS_STATUS_REG_OFFSET, - {{CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT, true}}); + {{CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_ACC_VAL_BIT, true}}); EXPECT_DIF_OK(dif_clkmgr_hintable_clock_get_enabled( - &clkmgr_, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT, &state)); + &clkmgr_, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_ACC_VAL_BIT, &state)); EXPECT_EQ(state, kDifToggleEnabled); } } diff --git a/sw/device/lib/dif/dif_keymgr.c b/sw/device/lib/dif/dif_keymgr.c index 087d37013cf..d2de18442dd 100644 --- a/sw/device/lib/dif/dif_keymgr.c +++ b/sw/device/lib/dif/dif_keymgr.c @@ -21,8 +21,8 @@ OT_ASSERT_ENUM_VALUE(kDifKeyMgrSideLoadClearAes, KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_AES); OT_ASSERT_ENUM_VALUE(kDifKeyMgrSideLoadClearKmac, KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_KMAC); -OT_ASSERT_ENUM_VALUE(kDifKeyMgrSideLoadClearOtbn, - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_OTBN); +OT_ASSERT_ENUM_VALUE(kDifKeyMgrSideLoadClearAcc, + KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_ACC); OT_ASSERT_ENUM_VALUE(kDifKeyMgrSideLoadClearAll, KEYMGR_SIDELOAD_CLEAR_VAL_MASK); @@ -518,9 +518,9 @@ dif_result_t dif_keymgr_generate_versioned_key( .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT, .cdi_type = params.cdi_type}; break; - case kDifKeymgrVersionedKeyDestOtbn: + case kDifKeymgrVersionedKeyDestAcc: hw_op_params = (start_operation_params_t){ - .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_OTBN, + .dest = KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_ACC, .op = KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT, .cdi_type = params.cdi_type}; break; diff --git a/sw/device/lib/dif/dif_keymgr.h b/sw/device/lib/dif/dif_keymgr.h index 8f1d5fd7c97..514de40faeb 100644 --- a/sw/device/lib/dif/dif_keymgr.h +++ b/sw/device/lib/dif/dif_keymgr.h @@ -52,7 +52,7 @@ typedef enum dif_keymgr_sideload_clr { kDifKeyMgrSideLoadClearNone = 0, kDifKeyMgrSideLoadClearAes = 1, kDifKeyMgrSideLoadClearKmac = 2, - kDifKeyMgrSideLoadClearOtbn = 3, + kDifKeyMgrSideLoadClearAcc = 3, // Using different value than those enumerated above should clear all slots, // so we can use the mask value of this field to denote ALL case. This was // we can statically assert this value on the .c side of this DIF. @@ -418,13 +418,13 @@ typedef enum dif_keymgr_versioned_key_dest { */ kDifKeymgrVersionedKeyDestKmac, /** - * Sideload the generated versioned key to Otbn device. + * Sideload the generated versioned key to Acc device. */ - kDifKeymgrVersionedKeyDestOtbn, + kDifKeymgrVersionedKeyDestAcc, /** * \internal Last key destination. */ - kDifKeymgrVersionedKeyDestLast = kDifKeymgrVersionedKeyDestOtbn, + kDifKeymgrVersionedKeyDestLast = kDifKeymgrVersionedKeyDestAcc, } dif_keymgr_versioned_key_dest_t; /** diff --git a/sw/device/lib/dif/dif_keymgr_dpe.c b/sw/device/lib/dif/dif_keymgr_dpe.c index fd69fbf485b..031467de8e6 100644 --- a/sw/device/lib/dif/dif_keymgr_dpe.c +++ b/sw/device/lib/dif/dif_keymgr_dpe.c @@ -118,8 +118,8 @@ static_assert(kDifKeymgrDpeKeyDestAes == static_assert(kDifKeymgrDpeKeyDestKmac == KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_KMAC, "Key destination macros must match the values from its enum."); -static_assert(kDifKeymgrDpeKeyDestOtbn == - KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_OTBN, +static_assert(kDifKeymgrDpeKeyDestAcc == + KEYMGR_DPE_CONTROL_SHADOWED_DEST_SEL_VALUE_ACC, "Key destination macros must match the values from its enum."); /** diff --git a/sw/device/lib/dif/dif_keymgr_dpe.h b/sw/device/lib/dif/dif_keymgr_dpe.h index b2daeda70a6..dbe90eea769 100644 --- a/sw/device/lib/dif/dif_keymgr_dpe.h +++ b/sw/device/lib/dif/dif_keymgr_dpe.h @@ -100,10 +100,10 @@ typedef enum dif_keymgr_dpe_key_dest { */ kDifKeymgrDpeKeyDestKmac = 2, /** - * Diversify the generated key for OTBN (and load it to OTBN peripheral port + * Diversify the generated key for ACC (and load it to ACC peripheral port * if sideload key). */ - kDifKeymgrDpeKeyDestOtbn = 3, + kDifKeymgrDpeKeyDestAcc = 3, } dif_keymgr_dpe_key_dest_t; /** @@ -111,7 +111,7 @@ typedef enum dif_keymgr_dpe_key_dest { */ typedef struct dif_keymgr_dpe_generate_params { /** - * Destination for {AES, KMAC, OTBN}, which is used for diversification. + * Destination for {AES, KMAC, ACC}, which is used for diversification. */ dif_keymgr_dpe_key_dest_t key_dest; diff --git a/sw/device/lib/dif/dif_otbn.c b/sw/device/lib/dif/dif_otbn.c deleted file mode 100644 index 12554690b1e..00000000000 --- a/sw/device/lib/dif/dif_otbn.c +++ /dev/null @@ -1,228 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/lib/dif/dif_otbn.h" - -#include - -#include "sw/device/lib/base/bitfield.h" -#include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/dif/dif_base.h" - -#include "hw/top/otbn_regs.h" // Generated. - -static_assert(kDifOtbnErrBitsBadDataAddr == - (1 << OTBN_ERR_BITS_BAD_DATA_ADDR_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsBadInsnAddr == - (1 << OTBN_ERR_BITS_BAD_INSN_ADDR_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsCallStack == (1 << OTBN_ERR_BITS_CALL_STACK_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsIllegalInsn == - (1 << OTBN_ERR_BITS_ILLEGAL_INSN_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsLoop == (1 << OTBN_ERR_BITS_LOOP_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsImemIntgViolation == - (1 << OTBN_ERR_BITS_IMEM_INTG_VIOLATION_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsDmemIntgViolation == - (1 << OTBN_ERR_BITS_DMEM_INTG_VIOLATION_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsRegIntgViolation == - (1 << OTBN_ERR_BITS_REG_INTG_VIOLATION_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsBusIntgViolation == - (1 << OTBN_ERR_BITS_BUS_INTG_VIOLATION_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsIllegalBusAccess == - (1 << OTBN_ERR_BITS_ILLEGAL_BUS_ACCESS_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsLifecycleEscalation == - (1 << OTBN_ERR_BITS_LIFECYCLE_ESCALATION_BIT), - "Layout of error bits changed."); -static_assert(kDifOtbnErrBitsFatalSoftware == - (1 << OTBN_ERR_BITS_FATAL_SOFTWARE_BIT), - "Layout of error bits changed."); - -/** - * Data width of big number subset, in bytes. - */ -const int kDifOtbnWlenBytes = 256 / 8; - -/** - * Ensures that `offset` and `size` are valid for a given `mem_size`. - * - * Valid are 32b word accesses to 32b-aligned memory locations within - * `mem_size`. - */ -static bool check_offset_len(uint32_t offset_bytes, size_t len_bytes, - size_t mem_size) { - // The overflow check below assumes/requires two unsigned inputs. - return (len_bytes % sizeof(uint32_t) == 0 && - offset_bytes % sizeof(uint32_t) == 0 && - offset_bytes + len_bytes >= len_bytes && - offset_bytes + len_bytes <= mem_size); -} - -dif_result_t dif_otbn_reset(const dif_otbn_t *otbn) { - if (otbn == NULL) { - return kDifBadArg; - } - - mmio_region_write32(otbn->base_addr, OTBN_INTR_ENABLE_REG_OFFSET, 0); - - // Clear all pending interrupts. - mmio_region_write32(otbn->base_addr, OTBN_INTR_STATE_REG_OFFSET, 0xFFFFFFFF); - - return kDifOk; -} - -dif_result_t dif_otbn_write_cmd(const dif_otbn_t *otbn, dif_otbn_cmd_t cmd) { - if (otbn == NULL) { - return kDifBadArg; - } - - mmio_region_write32(otbn->base_addr, OTBN_CMD_REG_OFFSET, cmd); - - return kDifOk; -} - -dif_result_t dif_otbn_get_status(const dif_otbn_t *otbn, - dif_otbn_status_t *status) { - if (otbn == NULL || status == NULL) { - return kDifBadArg; - } - - *status = mmio_region_read32(otbn->base_addr, OTBN_STATUS_REG_OFFSET); - - return kDifOk; -} - -dif_result_t dif_otbn_get_err_bits(const dif_otbn_t *otbn, - dif_otbn_err_bits_t *err_bits) { - if (otbn == NULL || err_bits == NULL) { - return kDifBadArg; - } - - uint32_t err_bits_raw = - mmio_region_read32(otbn->base_addr, OTBN_ERR_BITS_REG_OFFSET); - - *err_bits = err_bits_raw; - return kDifOk; -} - -dif_result_t dif_otbn_get_insn_cnt(const dif_otbn_t *otbn, uint32_t *insn_cnt) { - if (otbn == NULL || insn_cnt == NULL) { - return kDifBadArg; - } - - *insn_cnt = mmio_region_read32(otbn->base_addr, OTBN_INSN_CNT_REG_OFFSET); - return kDifOk; -} - -dif_result_t dif_otbn_get_load_checksum(const dif_otbn_t *otbn, - uint32_t *checksum) { - if (otbn == NULL || checksum == NULL) { - return kDifBadArg; - } - - *checksum = - mmio_region_read32(otbn->base_addr, OTBN_LOAD_CHECKSUM_REG_OFFSET); - return kDifOk; -} - -dif_result_t dif_otbn_clear_load_checksum(const dif_otbn_t *otbn) { - if (otbn == NULL) { - return kDifBadArg; - } - - mmio_region_write32(otbn->base_addr, OTBN_LOAD_CHECKSUM_REG_OFFSET, 0); - - return kDifOk; -} - -dif_result_t dif_otbn_imem_write(const dif_otbn_t *otbn, uint32_t offset_bytes, - const void *src, size_t len_bytes) { - if (otbn == NULL || src == NULL || - !check_offset_len(offset_bytes, len_bytes, OTBN_IMEM_SIZE_BYTES)) { - return kDifBadArg; - } - - mmio_region_memcpy_to_mmio32( - otbn->base_addr, OTBN_IMEM_REG_OFFSET + offset_bytes, src, len_bytes); - - return kDifOk; -} - -dif_result_t dif_otbn_imem_read(const dif_otbn_t *otbn, uint32_t offset_bytes, - void *dest, size_t len_bytes) { - if (otbn == NULL || dest == NULL || - !check_offset_len(offset_bytes, len_bytes, OTBN_IMEM_SIZE_BYTES)) { - return kDifBadArg; - } - - mmio_region_memcpy_from_mmio32( - otbn->base_addr, OTBN_IMEM_REG_OFFSET + offset_bytes, dest, len_bytes); - - return kDifOk; -} - -dif_result_t dif_otbn_dmem_write(const dif_otbn_t *otbn, uint32_t offset_bytes, - const void *src, size_t len_bytes) { - if (otbn == NULL || src == NULL || - !check_offset_len(offset_bytes, len_bytes, OTBN_DMEM_SIZE_BYTES)) { - return kDifBadArg; - } - - mmio_region_memcpy_to_mmio32( - otbn->base_addr, OTBN_DMEM_REG_OFFSET + offset_bytes, src, len_bytes); - - return kDifOk; -} - -dif_result_t dif_otbn_dmem_read(const dif_otbn_t *otbn, uint32_t offset_bytes, - void *dest, size_t len_bytes) { - if (otbn == NULL || dest == NULL || - !check_offset_len(offset_bytes, len_bytes, OTBN_DMEM_SIZE_BYTES)) { - return kDifBadArg; - } - - mmio_region_memcpy_from_mmio32( - otbn->base_addr, OTBN_DMEM_REG_OFFSET + offset_bytes, dest, len_bytes); - - return kDifOk; -} - -dif_result_t dif_otbn_set_ctrl_software_errs_fatal(const dif_otbn_t *otbn, - bool enable) { - if (otbn == NULL) { - return kDifBadArg; - } - - // Only one bit in the CTRL register so no need to read current value. - uint32_t new_ctrl; - - if (enable) { - new_ctrl = 1; - } else { - new_ctrl = 0; - } - - mmio_region_write32(otbn->base_addr, OTBN_CTRL_REG_OFFSET, new_ctrl); - if (mmio_region_read32(otbn->base_addr, OTBN_CTRL_REG_OFFSET) != new_ctrl) { - return kDifUnavailable; - } - - return kDifOk; -} - -size_t dif_otbn_get_dmem_size_bytes(const dif_otbn_t *otbn) { - return OTBN_DMEM_SIZE_BYTES; -} - -size_t dif_otbn_get_imem_size_bytes(const dif_otbn_t *otbn) { - return OTBN_IMEM_SIZE_BYTES; -} diff --git a/sw/device/lib/dif/dif_otbn.h b/sw/device/lib/dif/dif_otbn.h deleted file mode 100644 index 4f38e12b41d..00000000000 --- a/sw/device/lib/dif/dif_otbn.h +++ /dev/null @@ -1,262 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTBN_H_ -#define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTBN_H_ - -/** - * @file - * @brief OTBN Device Interface Functions. - */ - -#include -#include - -#include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/dif/dif_base.h" - -#include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -/** - * OTBN commands. - */ -typedef enum dif_otbn_cmd { - kDifOtbnCmdExecute = 0xd8, - kDifOtbnCmdSecWipeDmem = 0xc3, - kDifOtbnCmdSecWipeImem = 0x1e, -} dif_otbn_cmd_t; - -/** - * OTBN status. - */ -typedef enum dif_otbn_status { - kDifOtbnStatusIdle = 0x00, - kDifOtbnStatusBusyExecute = 0x01, - kDifOtbnStatusBusySecWipeDmem = 0x02, - kDifOtbnStatusBusySecWipeImem = 0x03, - kDifOtbnStatusBusySecWipeInt = 0x04, - kDifOtbnStatusLocked = 0xFF, -} dif_otbn_status_t; - -/** - * OTBN Errors. - * - * OTBN uses a bitfield to indicate which errors have been seen. Multiple errors - * can be seen at the same time. This enum gives the individual bits that may be - * set for different errors. - */ -typedef enum dif_otbn_err_bits { - kDifOtbnErrBitsNoError = 0, - /** A BAD_DATA_ADDR error was observed. */ - kDifOtbnErrBitsBadDataAddr = (1 << 0), - /** A BAD_INSN_ADDR error was observed. */ - kDifOtbnErrBitsBadInsnAddr = (1 << 1), - /** A CALL_STACK error was observed. */ - kDifOtbnErrBitsCallStack = (1 << 2), - /** An ILLEGAL_INSN error was observed. */ - kDifOtbnErrBitsIllegalInsn = (1 << 3), - /** A LOOP error was observed. */ - kDifOtbnErrBitsLoop = (1 << 4), - /** A RND_FIPS_CHECK_FAIL error was observed. */ - kDifOtbnErrBitsRndFipsChkFail = (1 << 7), - /** A IMEM_INTG_VIOLATION error was observed. */ - kDifOtbnErrBitsImemIntgViolation = (1 << 16), - /** A DMEM_INTG_VIOLATION error was observed. */ - kDifOtbnErrBitsDmemIntgViolation = (1 << 17), - /** A REG_INTG_VIOLATION error was observed. */ - kDifOtbnErrBitsRegIntgViolation = (1 << 18), - /** A BUS_INTG_VIOLATION error was observed. */ - kDifOtbnErrBitsBusIntgViolation = (1 << 19), - /** A BAD_INTERNAL_STATE error was observed. */ - kDifOtbnErrBitsBadInternalState = (1 << 20), - /** An ILLEGAL_BUS_ACCESS error was observed. */ - kDifOtbnErrBitsIllegalBusAccess = (1 << 21), - /** A LIFECYCLE_ESCALATION error was observed. */ - kDifOtbnErrBitsLifecycleEscalation = (1 << 22), - /** A FATAL_SOFTWARE error was observed. */ - kDifOtbnErrBitsFatalSoftware = (1 << 23), -} dif_otbn_err_bits_t; - -/** - * Reset OTBN device. - * - * Resets the given OTBN device by setting its configuration registers to - * reset values. Disables interrupts, output, and input filter. - * - * @param otbn OTBN instance. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_reset(const dif_otbn_t *otbn); - -/** - * Start an operation by issuing a command. - * - * @param otbn OTBN instance. - * @param cmd The command. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_write_cmd(const dif_otbn_t *otbn, dif_otbn_cmd_t cmd); - -/** - * Gets the current status of OTBN. - * - * @param otbn OTBN instance. - * @param[out] status OTBN status. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_get_status(const dif_otbn_t *otbn, - dif_otbn_status_t *status); - -/** - * Get the error bits set by the device if the operation failed. - * - * @param otbn OTBN instance. - * @param[out] err_bits The error bits returned by the hardware. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_get_err_bits(const dif_otbn_t *otbn, - dif_otbn_err_bits_t *err_bits); - -/** - * Gets the number of executed OTBN instructions. - * - * Gets the number of instructions executed so far in the current OTBN run if - * there is one. Otherwise, gets the number executed in total in the previous - * OTBN run. - * - * @param otbn OTBN instance. - * @param[out] insn_cnt The number of instructions executed by OTBN. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_get_insn_cnt(const dif_otbn_t *otbn, uint32_t *insn_cnt); - -/** - * Gets the content of the load checksum register. - * - * Gets the 32-bit CRC checksum of data written to memory. - * - * @param otbn OTBN instance. - * @param[out] insn_cnt The number of instructions executed by OTBN. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_get_load_checksum(const dif_otbn_t *otbn, - uint32_t *insn_cnt); - -/** - * Clears the load checksum register. - * - * Writes 0 to the load checksum register to clear it. - * - * @param otbn OTBN instance. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_clear_load_checksum(const dif_otbn_t *otbn); - -/** - * Write an OTBN application into its instruction memory (IMEM). - * - * Only 32b-aligned 32b word accesses are allowed. - * - * @param otbn OTBN instance. - * @param offset_bytes the byte offset in IMEM the first word is written to. - * @param src the main memory location to start reading from. - * @param len_bytes number of bytes to copy. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_imem_write(const dif_otbn_t *otbn, uint32_t offset_bytes, - const void *src, size_t len_bytes); - -/** - * Read from OTBN's instruction memory (IMEM). - * - * Only 32b-aligned 32b word accesses are allowed. - * - * @param otbn OTBN instance - * @param offset_bytes the byte offset in IMEM the first word is read from. - * @param[out] dest the main memory location to copy the data to (preallocated). - * @param len_bytes number of bytes to copy. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_imem_read(const dif_otbn_t *otbn, uint32_t offset_bytes, - void *dest, size_t len_bytes); - -/** - * Write to OTBN's data memory (DMEM). - * - * Only 32b-aligned 32b word accesses are allowed. - * - * @param otbn OTBN instance. - * @param offset_bytes the byte offset in DMEM the first word is written to. - * @param src the main memory location to start reading from. - * @param len_bytes number of bytes to copy. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_dmem_write(const dif_otbn_t *otbn, uint32_t offset_bytes, - const void *src, size_t len_bytes); - -/** - * Read from OTBN's data memory (DMEM). - * - * Only 32b-aligned 32b word accesses are allowed. - * - * @param otbn OTBN instance - * @param offset_bytes the byte offset in DMEM the first word is read from. - * @param[out] dest the main memory location to copy the data to (preallocated). - * @param len_bytes number of bytes to copy. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_dmem_read(const dif_otbn_t *otbn, uint32_t offset_bytes, - void *dest, size_t len_bytes); - -/** - * Sets the software errors are fatal bit in the control register. - * - * When set any software error becomes a fatal error. The bit can only be - * changed when the OTBN status is IDLE. - * - * @param otbn OTBN instance. - * @param enable Enable or disable whether software errors are fatal. - * @return The result of the operation, `kDifUnavailable` is returned when the - * requested change cannot be made. - */ -OT_WARN_UNUSED_RESULT -dif_result_t dif_otbn_set_ctrl_software_errs_fatal(const dif_otbn_t *otbn, - bool enable); - -/** - * Get the size of OTBN's data memory in bytes. - * - * @param otbn OTBN instance. - * @return data memory size in bytes. - */ -size_t dif_otbn_get_dmem_size_bytes(const dif_otbn_t *otbn); - -/** - * Get the size of OTBN's instruction memory in bytes. - * - * @param otbn OTBN instance. - * @return instruction memory size in bytes. - */ -size_t dif_otbn_get_imem_size_bytes(const dif_otbn_t *otbn); - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus - -#endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTBN_H_ diff --git a/sw/device/lib/dif/dif_otbn_unittest.cc b/sw/device/lib/dif/dif_otbn_unittest.cc deleted file mode 100644 index 0b1bcb7aff7..00000000000 --- a/sw/device/lib/dif/dif_otbn_unittest.cc +++ /dev/null @@ -1,394 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/lib/dif/dif_otbn.h" - -#include "gtest/gtest.h" -#include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/base/mock_mmio.h" -#include "sw/device/lib/dif/dif_base.h" -#include "sw/device/lib/dif/dif_test_base.h" - -#include "hw/top/otbn_regs.h" // Generated. - -namespace dif_otbn_unittest { -namespace { -using mock_mmio::MmioTest; -using mock_mmio::MockDevice; -using testing::Each; -using testing::Eq; -using testing::Test; - -class OtbnTest : public Test, public MmioTest { - protected: - void ExpectDeviceReset() { - EXPECT_WRITE32(OTBN_INTR_ENABLE_REG_OFFSET, 0); - EXPECT_WRITE32(OTBN_INTR_STATE_REG_OFFSET, - std::numeric_limits::max()); - } - - dif_otbn_t dif_otbn_ = {.base_addr = dev().region()}; -}; - -class ResetTest : public OtbnTest {}; - -TEST_F(ResetTest, NullArgs) { EXPECT_DIF_BADARG(dif_otbn_reset(nullptr)); } - -TEST_F(ResetTest, Default) { - ExpectDeviceReset(); - - EXPECT_DIF_OK(dif_otbn_reset(&dif_otbn_)); -} - -class WriteCmdTest : public OtbnTest {}; - -TEST_F(WriteCmdTest, NullArgs) { - EXPECT_DIF_BADARG(dif_otbn_write_cmd(nullptr, kDifOtbnCmdExecute)); -} - -TEST_F(WriteCmdTest, Success) { - // Set EXECUTE command. - EXPECT_WRITE32(OTBN_CMD_REG_OFFSET, kDifOtbnCmdExecute); - - EXPECT_DIF_OK(dif_otbn_write_cmd(&dif_otbn_, kDifOtbnCmdExecute)); -} - -class GetStatusTest : public OtbnTest {}; - -TEST_F(GetStatusTest, NullArgs) { - EXPECT_DIF_BADARG(dif_otbn_get_status(nullptr, nullptr)); - - EXPECT_DIF_BADARG(dif_otbn_get_status(&dif_otbn_, nullptr)); - - dif_otbn_status_t status = kDifOtbnStatusBusySecWipeDmem; - EXPECT_DIF_BADARG(dif_otbn_get_status(nullptr, &status)); - EXPECT_EQ(status, kDifOtbnStatusBusySecWipeDmem); -} - -TEST_F(GetStatusTest, Success) { - EXPECT_READ32(OTBN_STATUS_REG_OFFSET, kDifOtbnStatusBusyExecute); - - dif_otbn_status_t status; - EXPECT_DIF_OK(dif_otbn_get_status(&dif_otbn_, &status)); - EXPECT_EQ(status, kDifOtbnStatusBusyExecute); -} - -class GetErrBitsTest : public OtbnTest {}; - -TEST_F(GetErrBitsTest, NullArgs) { - EXPECT_DIF_BADARG(dif_otbn_get_err_bits(nullptr, nullptr)); - - EXPECT_DIF_BADARG(dif_otbn_get_err_bits(&dif_otbn_, nullptr)); - - dif_otbn_err_bits_t err_bits = kDifOtbnErrBitsBadDataAddr; - EXPECT_DIF_BADARG(dif_otbn_get_err_bits(nullptr, &err_bits)); - EXPECT_EQ(err_bits, kDifOtbnErrBitsBadDataAddr); -} - -TEST_F(GetErrBitsTest, Success) { - EXPECT_READ32(OTBN_ERR_BITS_REG_OFFSET, - kDifOtbnErrBitsIllegalInsn | kDifOtbnErrBitsRegIntgViolation); - - dif_otbn_err_bits_t err_bits; - EXPECT_DIF_OK(dif_otbn_get_err_bits(&dif_otbn_, &err_bits)); - EXPECT_EQ(err_bits, - kDifOtbnErrBitsIllegalInsn | kDifOtbnErrBitsRegIntgViolation); -} - -class GetInsnCntTest : public OtbnTest {}; - -TEST_F(GetInsnCntTest, NullArgs) { - EXPECT_DIF_BADARG(dif_otbn_get_insn_cnt(nullptr, nullptr)); - - EXPECT_DIF_BADARG(dif_otbn_get_insn_cnt(&dif_otbn_, nullptr)); - - uint32_t insn_cnt = 55; - EXPECT_DIF_BADARG(dif_otbn_get_insn_cnt(nullptr, &insn_cnt)); - EXPECT_EQ(insn_cnt, 55); -} - -TEST_F(GetInsnCntTest, Success) { - EXPECT_READ32(OTBN_INSN_CNT_REG_OFFSET, 55); - - uint32_t insn_cnt; - EXPECT_DIF_OK(dif_otbn_get_insn_cnt(&dif_otbn_, &insn_cnt)); - EXPECT_EQ(insn_cnt, 55); -} - -class ImemWriteTest : public OtbnTest {}; - -TEST_F(ImemWriteTest, NullArgs) { - uint32_t test_data[] = {0}; - - EXPECT_DIF_BADARG(dif_otbn_imem_write(nullptr, 0, nullptr, 4)); - - EXPECT_DIF_BADARG(dif_otbn_imem_write(nullptr, 0, test_data, 4)); - - EXPECT_DIF_BADARG(dif_otbn_imem_write(&dif_otbn_, 0, nullptr, 4)); -} - -TEST_F(ImemWriteTest, BadLenBytes) { - uint32_t test_data[] = {0}; - - // `len_bytes` must be a multiple of 4 bytes. - EXPECT_DIF_BADARG(dif_otbn_imem_write(&dif_otbn_, 0, test_data, 1)); - - EXPECT_DIF_BADARG(dif_otbn_imem_write(&dif_otbn_, 0, test_data, 2)); -} - -TEST_F(ImemWriteTest, BadOffset) { - uint32_t test_data[] = {0}; - - // `offset` must be 32b-aligned. - EXPECT_DIF_BADARG(dif_otbn_imem_write(&dif_otbn_, 1, test_data, 4)); - - EXPECT_DIF_BADARG(dif_otbn_imem_write(&dif_otbn_, 2, test_data, 4)); -} - -TEST_F(ImemWriteTest, BadAddressBeyondMemorySize) { - uint32_t test_data[] = {0}; - - EXPECT_DIF_BADARG( - dif_otbn_imem_write(&dif_otbn_, OTBN_IMEM_SIZE_BYTES, test_data, 4)); -} - -TEST_F(ImemWriteTest, BadAddressIntegerOverflow) { - uint32_t test_data[4] = {0}; - - EXPECT_DIF_BADARG(dif_otbn_imem_write(&dif_otbn_, 0xFFFFFFFC, test_data, 16)); -} - -TEST_F(ImemWriteTest, SuccessWithoutOffset) { - // Test assumption. - ASSERT_GE(OTBN_IMEM_SIZE_BYTES, 8); - - uint32_t test_data[2] = {0x12345678, 0xabcdef01}; - - EXPECT_WRITE32(OTBN_IMEM_REG_OFFSET, test_data[0]); - EXPECT_WRITE32(OTBN_IMEM_REG_OFFSET + 4, test_data[1]); - - EXPECT_DIF_OK(dif_otbn_imem_write(&dif_otbn_, 0, test_data, 8)); -} - -TEST_F(ImemWriteTest, SuccessWithOffset) { - // Test assumption. - ASSERT_GE(OTBN_IMEM_SIZE_BYTES, 12); - - uint32_t test_data[2] = {0x12345678, 0xabcdef01}; - - EXPECT_WRITE32(OTBN_IMEM_REG_OFFSET + 4, test_data[0]); - EXPECT_WRITE32(OTBN_IMEM_REG_OFFSET + 8, test_data[1]); - - EXPECT_DIF_OK(dif_otbn_imem_write(&dif_otbn_, 4, test_data, 8)); -} - -class ImemReadTest : public OtbnTest {}; - -TEST_F(ImemReadTest, NullArgs) { - uint32_t test_data[2] = {0x12345678, 0xabcdef01}; - - EXPECT_DIF_BADARG(dif_otbn_imem_read(nullptr, 0, nullptr, sizeof(test_data))); - - EXPECT_DIF_BADARG( - dif_otbn_imem_read(nullptr, 0, test_data, sizeof(test_data))); - - EXPECT_DIF_BADARG( - dif_otbn_imem_read(&dif_otbn_, 0, nullptr, sizeof(test_data))); - - // No side effects are expected. - EXPECT_EQ(test_data[0], 0x12345678); - EXPECT_EQ(test_data[1], 0xabcdef01); -} - -TEST_F(ImemReadTest, BadLenBytes) { - uint32_t test_data[2] = {0}; - - // `len_bytes` must be a multiple of 4 bytes. - EXPECT_DIF_BADARG(dif_otbn_imem_read(&dif_otbn_, 0, test_data, 1)); - - EXPECT_DIF_BADARG(dif_otbn_imem_read(&dif_otbn_, 0, test_data, 2)); -} - -TEST_F(ImemReadTest, BadOffset) { - uint32_t test_data[2] = {0}; - - // `offset` must be 32b-aligned. - EXPECT_DIF_BADARG( - dif_otbn_imem_read(&dif_otbn_, 1, test_data, sizeof(test_data))); - - EXPECT_DIF_BADARG( - dif_otbn_imem_read(&dif_otbn_, 2, test_data, sizeof(test_data))); -} - -TEST_F(ImemReadTest, SuccessWithoutOffset) { - // Assumption in the test. - ASSERT_GE(OTBN_IMEM_SIZE_BYTES, 8); - - uint32_t test_data[2] = {0}; - - EXPECT_READ32(OTBN_IMEM_REG_OFFSET, 0x12345678); - EXPECT_READ32(OTBN_IMEM_REG_OFFSET + 4, 0xabcdef01); - - EXPECT_DIF_OK(dif_otbn_imem_read(&dif_otbn_, 0, test_data, 8)); - EXPECT_EQ(test_data[0], 0x12345678); - EXPECT_EQ(test_data[1], 0xabcdef01); -} - -TEST_F(ImemReadTest, SuccessWithOffset) { - // Assumption in the test. - ASSERT_GE(OTBN_IMEM_SIZE_BYTES, 12); - - uint32_t test_data[2] = {0}; - - EXPECT_READ32(OTBN_IMEM_REG_OFFSET + 4, 0x12345678); - EXPECT_READ32(OTBN_IMEM_REG_OFFSET + 8, 0xabcdef01); - - EXPECT_DIF_OK(dif_otbn_imem_read(&dif_otbn_, 4, test_data, 8)); - EXPECT_EQ(test_data[0], 0x12345678); - EXPECT_EQ(test_data[1], 0xabcdef01); -} - -class DmemWriteTest : public OtbnTest {}; - -TEST_F(DmemWriteTest, NullArgs) { - uint32_t test_data[1] = {0}; - - EXPECT_DIF_BADARG(dif_otbn_dmem_write(nullptr, 0, nullptr, 4)); - - EXPECT_DIF_BADARG(dif_otbn_dmem_write(nullptr, 0, test_data, 4)); - - EXPECT_DIF_BADARG(dif_otbn_dmem_write(&dif_otbn_, 0, nullptr, 4)); -} - -TEST_F(DmemWriteTest, BadLenBytes) { - uint32_t test_data[1] = {0}; - - // `len_bytes` must be a multiple of 4 bytes. - EXPECT_DIF_BADARG(dif_otbn_dmem_write(&dif_otbn_, 0, test_data, 1)); - - EXPECT_DIF_BADARG(dif_otbn_dmem_write(&dif_otbn_, 0, test_data, 2)); -} - -TEST_F(DmemWriteTest, BadOffset) { - uint32_t test_data[1] = {0}; - - // `offset` must be 32b-aligned. - EXPECT_DIF_BADARG(dif_otbn_dmem_write(&dif_otbn_, 1, test_data, 4)); - - EXPECT_DIF_BADARG(dif_otbn_dmem_write(&dif_otbn_, 2, test_data, 4)); -} - -TEST_F(DmemWriteTest, SuccessWithoutOffset) { - // Test assumption. - ASSERT_GE(OTBN_DMEM_SIZE_BYTES, 8); - - uint32_t test_data[2] = {0x12345678, 0xabcdef01}; - - EXPECT_WRITE32(OTBN_DMEM_REG_OFFSET, test_data[0]); - EXPECT_WRITE32(OTBN_DMEM_REG_OFFSET + 4, test_data[1]); - - EXPECT_DIF_OK(dif_otbn_dmem_write(&dif_otbn_, 0, test_data, 8)); -} - -TEST_F(DmemWriteTest, SuccessWithOffset) { - // Test assumption. - ASSERT_GE(OTBN_DMEM_SIZE_BYTES, 12); - - uint32_t test_data[2] = {0x12345678, 0xabcdef01}; - - EXPECT_WRITE32(OTBN_DMEM_REG_OFFSET + 4, test_data[0]); - EXPECT_WRITE32(OTBN_DMEM_REG_OFFSET + 8, test_data[1]); - - EXPECT_DIF_OK(dif_otbn_dmem_write(&dif_otbn_, 4, test_data, 8)); -} - -class DmemReadTest : public OtbnTest {}; - -TEST_F(DmemReadTest, NullArgs) { - uint32_t test_data[2] = {0x12345678, 0xabcdef01}; - - EXPECT_DIF_BADARG(dif_otbn_dmem_read(nullptr, 0, nullptr, sizeof(test_data))); - - EXPECT_DIF_BADARG( - dif_otbn_dmem_read(nullptr, 0, test_data, sizeof(test_data))); - - EXPECT_DIF_BADARG( - dif_otbn_dmem_read(&dif_otbn_, 0, nullptr, sizeof(test_data))); - - // No side effects are expected. - EXPECT_EQ(test_data[0], 0x12345678); - EXPECT_EQ(test_data[1], 0xabcdef01); -} - -TEST_F(DmemReadTest, BadLenBytes) { - uint32_t test_data[2] = {0}; - - // `len_bytes` must be a multiple of 4 bytes. - EXPECT_DIF_BADARG(dif_otbn_dmem_read(&dif_otbn_, 0, test_data, 1)); - - EXPECT_DIF_BADARG(dif_otbn_dmem_read(&dif_otbn_, 0, test_data, 2)); -} - -TEST_F(DmemReadTest, BadOffset) { - uint32_t test_data[2] = {0}; - - // `offset` must be 32b-aligned. - EXPECT_DIF_BADARG( - dif_otbn_dmem_read(&dif_otbn_, 1, test_data, sizeof(test_data))); - - EXPECT_DIF_BADARG( - dif_otbn_dmem_read(&dif_otbn_, 2, test_data, sizeof(test_data))); -} - -TEST_F(DmemReadTest, SuccessWithoutOffset) { - // Assumption in the test. - ASSERT_GE(OTBN_DMEM_SIZE_BYTES, 8); - - uint32_t test_data[2] = {0}; - - EXPECT_READ32(OTBN_DMEM_REG_OFFSET, 0x12345678); - EXPECT_READ32(OTBN_DMEM_REG_OFFSET + 4, 0xabcdef01); - - EXPECT_DIF_OK(dif_otbn_dmem_read(&dif_otbn_, 0, test_data, 8)); - EXPECT_EQ(test_data[0], 0x12345678); - EXPECT_EQ(test_data[1], 0xabcdef01); -} - -TEST_F(DmemReadTest, SuccessWithOffset) { - // Assumption in the test. - ASSERT_GE(OTBN_DMEM_SIZE_BYTES, 12); - - uint32_t test_data[2] = {0}; - - EXPECT_READ32(OTBN_DMEM_REG_OFFSET + 4, 0x12345678); - EXPECT_READ32(OTBN_DMEM_REG_OFFSET + 8, 0xabcdef01); - - EXPECT_DIF_OK(dif_otbn_dmem_read(&dif_otbn_, 4, test_data, 8)); - EXPECT_EQ(test_data[0], 0x12345678); - EXPECT_EQ(test_data[1], 0xabcdef01); -} - -class ControlSoftwareErrorsFatalTest : public OtbnTest {}; - -TEST_F(ControlSoftwareErrorsFatalTest, NullArgs) { - EXPECT_DIF_BADARG(dif_otbn_set_ctrl_software_errs_fatal(nullptr, false)); -} - -TEST_F(ControlSoftwareErrorsFatalTest, Success) { - EXPECT_WRITE32(OTBN_CTRL_REG_OFFSET, 0x1); - EXPECT_READ32(OTBN_CTRL_REG_OFFSET, 0x1); - - EXPECT_DIF_OK(dif_otbn_set_ctrl_software_errs_fatal(&dif_otbn_, true)); -} - -TEST_F(ControlSoftwareErrorsFatalTest, Failure) { - EXPECT_WRITE32(OTBN_CTRL_REG_OFFSET, 0x0); - EXPECT_READ32(OTBN_CTRL_REG_OFFSET, 0x1); - - EXPECT_EQ(dif_otbn_set_ctrl_software_errs_fatal(&dif_otbn_, false), - kDifUnavailable); -} - -} // namespace -} // namespace dif_otbn_unittest diff --git a/sw/device/lib/testing/BUILD b/sw/device/lib/testing/BUILD index 54f7ad2d47b..72a508c4c4f 100644 --- a/sw/device/lib/testing/BUILD +++ b/sw/device/lib/testing/BUILD @@ -286,12 +286,12 @@ cc_library( ) cc_library( - name = "otbn_testutils", - srcs = ["otbn_testutils.c"], - hdrs = ["otbn_testutils.h"], + name = "acc_testutils", + srcs = ["acc_testutils.c"], + hdrs = ["acc_testutils.h"], target_compatible_with = [OPENTITAN_CPU], deps = [ - "//sw/device/lib/dif:otbn", + "//sw/device/lib/dif:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing/test_framework:check", @@ -299,15 +299,15 @@ cc_library( ) cc_library( - name = "otbn_testutils_rsa", - srcs = ["otbn_testutils_rsa.c"], - hdrs = ["otbn_testutils_rsa.h"], + name = "acc_testutils_rsa", + srcs = ["acc_testutils_rsa.c"], + hdrs = ["acc_testutils_rsa.h"], target_compatible_with = [OPENTITAN_CPU], deps = [ - ":otbn_testutils", + ":acc_testutils", + "//sw/acc/crypto:rsa", "//sw/device/lib/base:status", - "//sw/device/lib/dif:otbn", - "//sw/otbn/crypto:rsa", + "//sw/device/lib/dif:acc", ], ) diff --git a/sw/device/lib/testing/otbn_testutils.c b/sw/device/lib/testing/acc_testutils.c similarity index 50% rename from sw/device/lib/testing/otbn_testutils.c rename to sw/device/lib/testing/acc_testutils.c index 1a7451c0d5f..7a1b689b27d 100644 --- a/sw/device/lib/testing/otbn_testutils.c +++ b/sw/device/lib/testing/acc_testutils.c @@ -2,11 +2,11 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/testing/otbn_testutils.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_base.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/test_framework/check.h" @@ -16,56 +16,56 @@ enum { /** * Data width of big number subset, in bytes. */ - kOtbnWlenBytes = 256 / 8, + kAccWlenBytes = 256 / 8, }; -status_t otbn_testutils_wait_for_done(const dif_otbn_t *otbn, - dif_otbn_err_bits_t expected_err_bits) { +status_t acc_testutils_wait_for_done(const dif_acc_t *acc, + dif_acc_err_bits_t expected_err_bits) { bool busy = true; - dif_otbn_status_t status; + dif_acc_status_t status; while (busy) { - TRY(dif_otbn_get_status(otbn, &status)); - busy = status != kDifOtbnStatusIdle && status != kDifOtbnStatusLocked; + TRY(dif_acc_get_status(acc, &status)); + busy = status != kDifAccStatusIdle && status != kDifAccStatusLocked; } // Get instruction count so that we can print them to help with debugging. uint32_t instruction_count; - TRY(dif_otbn_get_insn_cnt(otbn, &instruction_count)); + TRY(dif_acc_get_insn_cnt(acc, &instruction_count)); - dif_otbn_err_bits_t err_bits; - TRY(dif_otbn_get_err_bits(otbn, &err_bits)); + dif_acc_err_bits_t err_bits; + TRY(dif_acc_get_err_bits(acc, &err_bits)); - // Error out if OTBN is locked. - TRY_CHECK(status == kDifOtbnStatusIdle, "OTBN is locked. Error bits: 0x%08x", + // Error out if ACC is locked. + TRY_CHECK(status == kDifAccStatusIdle, "ACC is locked. Error bits: 0x%08x", err_bits); // Error out if error bits do not match expectations. TRY_CHECK( err_bits == expected_err_bits, - "OTBN error bits: got: 0x%08x, expected: 0x%08x.\nInstruction count: " + "ACC error bits: got: 0x%08x, expected: 0x%08x.\nInstruction count: " "0x%08x", err_bits, expected_err_bits, instruction_count); return OK_STATUS(); } /** - * Checks if the OTBN application's IMEM and DMEM address parameters are valid. + * Checks if the ACC application's IMEM and DMEM address parameters are valid. * * IMEM and DMEM ranges must not be "backwards" in memory, with the end address * coming before the start address, and the IMEM range must additionally be * non-empty. Finally, separate sections in DMEM must not overlap each other * when converted to DMEM address space. * - * @param app the OTBN application to check + * @param app the ACC application to check */ -static void check_app_address_ranges(const otbn_app_t *app) { +static void check_app_address_ranges(const acc_app_t *app) { // IMEM must have a strictly positive range (cannot be backwards or empty) CHECK(app->imem_end > app->imem_start); // Initialised DMEM section must not be backwards CHECK(app->dmem_data_end >= app->dmem_data_start); } -status_t otbn_testutils_load_app(const dif_otbn_t *otbn, const otbn_app_t app) { +status_t acc_testutils_load_app(const dif_acc_t *acc, const acc_app_t app) { check_app_address_ranges(&app); const size_t imem_size = (size_t)(app.imem_end - app.imem_start); @@ -75,45 +75,45 @@ status_t otbn_testutils_load_app(const dif_otbn_t *otbn, const otbn_app_t app) { TRY_CHECK(imem_size % sizeof(uint32_t) == 0); TRY_CHECK(data_size % sizeof(uint32_t) == 0); - TRY(dif_otbn_imem_write(otbn, 0, app.imem_start, imem_size)); + TRY(dif_acc_imem_write(acc, 0, app.imem_start, imem_size)); // Write initialized data if (data_size > 0) { - TRY(dif_otbn_dmem_write(otbn, 0, app.dmem_data_start, data_size)); + TRY(dif_acc_dmem_write(acc, 0, app.dmem_data_start, data_size)); } return OK_STATUS(); } -status_t otbn_testutils_execute(const dif_otbn_t *otbn) { - TRY(dif_otbn_write_cmd(otbn, kDifOtbnCmdExecute)); +status_t acc_testutils_execute(const dif_acc_t *acc) { + TRY(dif_acc_write_cmd(acc, kDifAccCmdExecute)); return OK_STATUS(); } -status_t otbn_testutils_write_data(const dif_otbn_t *otbn, size_t len_bytes, - const void *src, otbn_addr_t dest) { - TRY(dif_otbn_dmem_write(otbn, dest, src, len_bytes)); +status_t acc_testutils_write_data(const dif_acc_t *acc, size_t len_bytes, + const void *src, acc_addr_t dest) { + TRY(dif_acc_dmem_write(acc, dest, src, len_bytes)); return OK_STATUS(); } -status_t otbn_testutils_read_data(const dif_otbn_t *otbn, size_t len_bytes, - otbn_addr_t src, void *dest) { - TRY(dif_otbn_dmem_read(otbn, src, dest, len_bytes)); +status_t acc_testutils_read_data(const dif_acc_t *acc, size_t len_bytes, + acc_addr_t src, void *dest) { + TRY(dif_acc_dmem_read(acc, src, dest, len_bytes)); return OK_STATUS(); } -status_t otbn_dump_dmem(const dif_otbn_t *otbn, uint32_t max_addr) { - TRY_CHECK(max_addr % kOtbnWlenBytes == 0); +status_t acc_dump_dmem(const dif_acc_t *acc, uint32_t max_addr) { + TRY_CHECK(max_addr % kAccWlenBytes == 0); if (max_addr == 0) { - max_addr = dif_otbn_get_dmem_size_bytes(otbn); + max_addr = dif_acc_get_dmem_size_bytes(acc); } TRY_CHECK(max_addr <= UINT32_MAX, "max_addr must fit in uint32_t"); - for (uint32_t i = 0; i < max_addr; i += kOtbnWlenBytes) { - uint32_t data[kOtbnWlenBytes / sizeof(uint32_t)]; - TRY(dif_otbn_dmem_read(otbn, i, data, kOtbnWlenBytes)); + for (uint32_t i = 0; i < max_addr; i += kAccWlenBytes) { + uint32_t data[kAccWlenBytes / sizeof(uint32_t)]; + TRY(dif_acc_dmem_read(acc, i, data, kAccWlenBytes)); LOG_INFO("DMEM @%04d: 0x%08x%08x%08x%08x%08x%08x%08x%08x", - i / kOtbnWlenBytes, data[7], data[6], data[5], data[4], data[3], + i / kAccWlenBytes, data[7], data[6], data[5], data[4], data[3], data[2], data[1], data[0]); } return OK_STATUS(); diff --git a/sw/device/lib/testing/acc_testutils.h b/sw/device/lib/testing/acc_testutils.h new file mode 100644 index 00000000000..7c9970d7731 --- /dev/null +++ b/sw/device/lib/testing/acc_testutils.h @@ -0,0 +1,222 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_LIB_TESTING_ACC_TESTUTILS_H_ +#define OPENTITAN_SW_DEVICE_LIB_TESTING_ACC_TESTUTILS_H_ + +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/base/status.h" +#include "sw/device/lib/dif/dif_acc.h" +#include "sw/device/lib/dif/dif_base.h" + +/** + * @file + * @brief OpenTitan Big Number Accelerator (ACC) driver + */ + +/** + * Information about an embedded ACC application image. + * + * All pointers reference data in the normal CPU address space. + * + * Use `ACC_DECLARE_APP_SYMBOLS()` together with `ACC_APP_T_INIT()` to + * initialize this structure. + */ +typedef struct acc_app { + /** + * Start of ACC instruction memory. + */ + const uint8_t *imem_start; + /** + * End of ACC instruction memory. + */ + const uint8_t *imem_end; + /** + * Start of initialized ACC data memory. + * + * Data in this section is copied into DMEM when the app is loaded. + */ + const uint8_t *dmem_data_start; + /** + * End of initialized ACC data memory. + */ + const uint8_t *dmem_data_end; +} acc_app_t; + +/** + * The address of an ACC symbol as seen by ACC + * + * Use `ACC_DECLARE_SYMBOL_ADDR()` together with `ACC_ADDR_T_INIT()` to + * initialize this type. + */ +typedef uint32_t acc_addr_t; + +/** + * Generate the prefix to add to an ACC symbol name used on the Ibex side + * + * The result is a pointer to Ibex's rodata that should be used to initialise + * memory for that symbol. + * + * This is needed by the ACC driver to support DMEM/IMEM ranges but + * application code shouldn't need to use this. Use the `acc_addr_t` type and + * supporting macros instead. + */ +#define ACC_SYMBOL_PTR(app_name, sym) _acc_local_app_##app_name##_##sym + +/** + * Generate the prefix to add to an ACC symbol name used on the ACC side + * + * The result is a pointer whose integer value is the address by which the + * symbol should be accessed in ACC memory. + * + * This is an internal macro used in `ACC_DECLARE_SYMBOL_ADDR` and + * `ACC_ADDR_T_INIT` but application code shouldn't need to use it directly. + */ +#define ACC_SYMBOL_ADDR(app_name, sym) _acc_remote_app_##app_name##_##sym + +/** + * Makes a symbol in the ACC application image available. + * + * This is needed by the ACC driver to support DMEM/IMEM ranges but + * application code shouldn't need to use this. To get access to ACC + * addresses, use `ACC_DECLARE_SYMBOL_ADDR` instead. + */ +#define ACC_DECLARE_SYMBOL_PTR(app_name, symbol_name) \ + extern const uint8_t ACC_SYMBOL_PTR(app_name, symbol_name)[] + +/** + * Makes the ACC address of a symbol in the ACC application available. + * + * Symbols are typically function or data pointers, i.e. labels in assembly + * code. Unlike ACC_DECLARE_SYMBOL_PTR, this will work for symbols in the .bss + * section (which exist on the ACC side, even though they don't have backing + * data on Ibex). + * + * Use this macro instead of manually declaring the symbols as symbol names + * might change. + * + * @param app_name Name of the application the function is contained in. + * @param symbol_name Name of the symbol (function, label). + */ +#define ACC_DECLARE_SYMBOL_ADDR(app_name, symbol_name) \ + extern const uint8_t ACC_SYMBOL_ADDR(app_name, symbol_name)[] + +/** + * Makes an embedded ACC application image available for use. + * + * Make symbols available that indicate the start and the end of instruction + * and data memory regions, as they are stored in the device memory. + * + * Use this macro instead of manually declaring the symbols as symbol names + * might change. + * + * @param app_name Name of the application to load, which is typically the + * name of the main (assembly) source file. + */ +#define ACC_DECLARE_APP_SYMBOLS(app_name) \ + ACC_DECLARE_SYMBOL_PTR(app_name, _imem_start); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _imem_end); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _dmem_data_start); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _dmem_data_end) + +/** + * Initializes the ACC application information structure. + * + * After making all required symbols from the application image available + * through `ACC_DECLARE_APP_SYMBOLS()`, use this macro to initialize an + * `acc_app_t` struct with those symbols. + * + * @param app_name Name of the application to load. + * @see ACC_DECLARE_APP_SYMBOLS() + */ +#define ACC_APP_T_INIT(app_name) \ + ((acc_app_t){ \ + .imem_start = ACC_SYMBOL_PTR(app_name, _imem_start), \ + .imem_end = ACC_SYMBOL_PTR(app_name, _imem_end), \ + .dmem_data_start = ACC_SYMBOL_PTR(app_name, _dmem_data_start), \ + .dmem_data_end = ACC_SYMBOL_PTR(app_name, _dmem_data_end), \ + }) + +/** + * Initializes an `acc_addr_t`. + */ +#define ACC_ADDR_T_INIT(app_name, symbol_name) \ + ((uint32_t)ACC_SYMBOL_ADDR(app_name, symbol_name)) + +/** + * (Re-)loads the application into ACC. + * + * Load the application image with both instruction and data segments into ACC. + * + * @param acc The context object. + * @param app The application to load into ACC. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t acc_testutils_load_app(const dif_acc_t *acc, const acc_app_t app); + +/** + * Starts the ACC execute operation. + * + * Use `acc_testutils_wait_for_done()` to wait for execution to complete. + * + * @param acc The context object. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t acc_testutils_execute(const dif_acc_t *acc); + +/** + * Waits for ACC to be done with the current operation. + * + * Polls the status register until ACC is idle. Produces a CHECK-fail if ACC + * is or becomes locked. Checks that the final error bits match expectations. + * + * @param acc The context object. + * @param expected_err_bits Expected error bits. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t acc_testutils_wait_for_done(const dif_acc_t *acc, + dif_acc_err_bits_t expected_err_bits); + +/** + * Copies data from the CPU memory to ACC data memory. + * + * @param acc The context object. + * @param len_bytes Number of bytes to copy. + * @param dest Address of the destination in ACC's data memory. + * @param src Source of the data to copy. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t acc_testutils_write_data(const dif_acc_t *acc, size_t len_bytes, + const void *src, acc_addr_t dest); + +/** + * Copies data from ACC's data memory to CPU memory. + * + * @param acc The context object. + * @param len_bytes The number of bytes to copy. + * @param src The address in ACC data memory to copy from. + * @param[out] dest The destination of the copied data in main memory + * (preallocated). + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t acc_testutils_read_data(const dif_acc_t *acc, size_t len_bytes, + acc_addr_t src, void *dest); + +/** + * Writes a LOG_INFO message with the contents of each 256b DMEM word. + * + * @param acc The context object. + * @param max_addr The highest address to dump. Set to 0 to output the whole + * DMEM. Must be a multiple of WLEN. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +status_t acc_testutils_dump_dmem(const dif_acc_t *acc, uint32_t max_addr); + +#endif // OPENTITAN_SW_DEVICE_LIB_TESTING_ACC_TESTUTILS_H_ diff --git a/sw/device/lib/testing/acc_testutils_rsa.c b/sw/device/lib/testing/acc_testutils_rsa.c new file mode 100644 index 00000000000..71ce5bbe864 --- /dev/null +++ b/sw/device/lib/testing/acc_testutils_rsa.c @@ -0,0 +1,116 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/lib/testing/acc_testutils_rsa.h" + +#include "sw/device/lib/base/status.h" +#include "sw/device/lib/dif/dif_acc.h" +#include "sw/device/lib/testing/acc_testutils.h" + +ACC_DECLARE_APP_SYMBOLS(rsa); +ACC_DECLARE_SYMBOL_ADDR(rsa, mode); +ACC_DECLARE_SYMBOL_ADDR(rsa, n_limbs); +ACC_DECLARE_SYMBOL_ADDR(rsa, inout); +ACC_DECLARE_SYMBOL_ADDR(rsa, modulus); +ACC_DECLARE_SYMBOL_ADDR(rsa, exp); + +static const acc_app_t kAccAppRsa = ACC_APP_T_INIT(rsa); +static const acc_addr_t kAccVarRsaMode = ACC_ADDR_T_INIT(rsa, mode); +static const acc_addr_t kAccVarRsaNLimbs = ACC_ADDR_T_INIT(rsa, n_limbs); +static const acc_addr_t kAccVarRsaInOut = ACC_ADDR_T_INIT(rsa, inout); +static const acc_addr_t kAccVarRsaModulus = ACC_ADDR_T_INIT(rsa, modulus); +static const acc_addr_t kAccVarRsaExp = ACC_ADDR_T_INIT(rsa, exp); + +enum { + kAccWideWordBytes = 256 / 8, + kModeEncrypt = 1, + kModeDecrypt = 2, +}; + +status_t acc_testutils_rsa_load(dif_acc_t *acc) { + if (acc == NULL) { + return INVALID_ARGUMENT(); + } + return acc_testutils_load_app(acc, kAccAppRsa); +} + +status_t acc_testutils_rsa_modexp_f4_start(dif_acc_t *acc, + const uint8_t *modulus, + const uint8_t *in, + size_t size_bytes) { + if (acc == NULL || size_bytes % kAccWideWordBytes != 0) { + return INVALID_ARGUMENT(); + } + + uint32_t n_limbs = size_bytes / kAccWideWordBytes; + if (n_limbs == 0 || n_limbs > 16) { + return INVALID_ARGUMENT(); + } + + // Write input arguments. + uint32_t mode = kModeEncrypt; + TRY(acc_testutils_write_data(acc, sizeof(uint32_t), &mode, kAccVarRsaMode)); + TRY(acc_testutils_write_data(acc, sizeof(uint32_t), &n_limbs, + kAccVarRsaNLimbs)); + TRY(acc_testutils_write_data(acc, size_bytes, modulus, kAccVarRsaModulus)); + TRY(acc_testutils_write_data(acc, size_bytes, in, kAccVarRsaInOut)); + + // Call ACC to start the operation. + return acc_testutils_execute(acc); +} + +status_t acc_testutils_rsa_modexp_consttime_start( + dif_acc_t *acc, const uint8_t *modulus, const uint8_t *private_exponent, + const uint8_t *in, size_t size_bytes) { + if (acc == NULL || size_bytes % kAccWideWordBytes != 0) { + return INVALID_ARGUMENT(); + } + + uint32_t n_limbs = size_bytes / kAccWideWordBytes; + if (n_limbs == 0 || n_limbs > 16) { + return INVALID_ARGUMENT(); + } + + // Write input arguments. + uint32_t mode = kModeDecrypt; + TRY(acc_testutils_write_data(acc, sizeof(mode), &mode, kAccVarRsaMode)); + TRY(acc_testutils_write_data(acc, sizeof(n_limbs), &n_limbs, + kAccVarRsaNLimbs)); + TRY(acc_testutils_write_data(acc, size_bytes, modulus, kAccVarRsaModulus)); + TRY(acc_testutils_write_data(acc, size_bytes, private_exponent, + kAccVarRsaExp)); + TRY(acc_testutils_write_data(acc, size_bytes, in, kAccVarRsaInOut)); + + // Call ACC to start the operation. + return acc_testutils_execute(acc); +} + +static status_t modexp_finalize(dif_acc_t *acc, uint8_t *out, + size_t size_bytes) { + if (acc == NULL || size_bytes % kAccWideWordBytes != 0) { + return INVALID_ARGUMENT(); + } + + uint32_t n_limbs = size_bytes / kAccWideWordBytes; + if (n_limbs == 0 || n_limbs > 16) { + return INVALID_ARGUMENT(); + } + + // Wait for ACC to complete. + TRY(acc_testutils_wait_for_done(acc, kDifAccErrBitsNoError)); + + // Read back results. + return acc_testutils_read_data(acc, size_bytes, kAccVarRsaInOut, out); +} + +status_t acc_testutils_rsa_modexp_f4_finalize(dif_acc_t *acc, uint8_t *out, + size_t size_bytes) { + return modexp_finalize(acc, out, size_bytes); +} + +status_t acc_testutils_rsa_modexp_consttime_finalize(dif_acc_t *acc, + uint8_t *out, + size_t size_bytes) { + return modexp_finalize(acc, out, size_bytes); +} diff --git a/sw/device/lib/testing/otbn_testutils_rsa.h b/sw/device/lib/testing/acc_testutils_rsa.h similarity index 55% rename from sw/device/lib/testing/otbn_testutils_rsa.h rename to sw/device/lib/testing/acc_testutils_rsa.h index 722cf3b14fb..86e8e6de5f6 100644 --- a/sw/device/lib/testing/otbn_testutils_rsa.h +++ b/sw/device/lib/testing/acc_testutils_rsa.h @@ -2,25 +2,25 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_SW_DEVICE_LIB_TESTING_OTBN_TESTUTILS_RSA_H_ -#define OPENTITAN_SW_DEVICE_LIB_TESTING_OTBN_TESTUTILS_RSA_H_ +#ifndef OPENTITAN_SW_DEVICE_LIB_TESTING_ACC_TESTUTILS_RSA_H_ +#define OPENTITAN_SW_DEVICE_LIB_TESTING_ACC_TESTUTILS_RSA_H_ #include "sw/device/lib/base/status.h" -#include "sw/device/lib/dif/dif_otbn.h" +#include "sw/device/lib/dif/dif_acc.h" /** - * @file Run RSA on OTBN as a testing tool. - * @brief This library is based on the DIF instead of a full OTBN driver, and + * @file Run RSA on ACC as a testing tool. + * @brief This library is based on the DIF instead of a full ACC driver, and * should be used for testing only. The library does not include message * hashing or encoding. */ /** - * Load the RSA application into OTBN. + * Load the RSA application into ACC. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. */ -status_t otbn_testutils_rsa_load(dif_otbn_t *otbn); +status_t acc_testutils_rsa_load(dif_acc_t *acc); /** * Start running modular exponentiation with the exponent 65537. @@ -30,35 +30,35 @@ status_t otbn_testutils_rsa_load(dif_otbn_t *otbn); * exponentiation. 65537 is also called "F4" because it is the 4th Fermat * number (2^16 + 1). * - * The RSA app should be loaded into OTBN with `otbn_testutils_rsa_load` before + * The RSA app should be loaded into ACC with `acc_testutils_rsa_load` before * calling this function. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. * @param modulus The modulus (n). * @param in The plaintext message. * @param size_bytes The size of all buffers in bytes, i.e. the key/modulus * length (i.e. 128 for RSA 1024). Valid range: 32..512 in * 32 byte-steps (i.e. RSA 256 to RSA 4096). */ -status_t otbn_testutils_rsa_modexp_f4_start(dif_otbn_t *otbn, - const uint8_t *modulus, - const uint8_t *in, - size_t size_bytes); +status_t acc_testutils_rsa_modexp_f4_start(dif_acc_t *acc, + const uint8_t *modulus, + const uint8_t *in, + size_t size_bytes); /** * Finish modular exponentiation with the exponent 65537. * - * Waits for OTBN to complete and reads back the result of modular - * exponentiation. Call only after `otbn_testutils_rsa_modexp_f4_start`. + * Waits for ACC to complete and reads back the result of modular + * exponentiation. Call only after `acc_testutils_rsa_modexp_f4_start`. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. * @param out The encrypted message. * @param size_bytes The size of all buffers in bytes, i.e. the key/modulus * length (i.e. 128 for RSA 1024). Valid range: 32..512 in * 32 byte-steps (i.e. RSA 256 to RSA 4096). */ -status_t otbn_testutils_rsa_modexp_f4_finalize(dif_otbn_t *otbn, uint8_t *out, - size_t size_bytes); +status_t acc_testutils_rsa_modexp_f4_finalize(dif_acc_t *acc, uint8_t *out, + size_t size_bytes); /** * Start a constant-time modular exponentiation. @@ -66,10 +66,10 @@ status_t otbn_testutils_rsa_modexp_f4_finalize(dif_otbn_t *otbn, uint8_t *out, * Computes (in^d) mod n. This corresponds to the core step in decryption or * signature generation and can be very slow. * - * The RSA app should be loaded into OTBN with `otbn_testutils_rsa_load` before + * The RSA app should be loaded into ACC with `acc_testutils_rsa_load` before * calling this function. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. * @param modulus The modulus (n). * @param private_exponent The private exponent (d). * @param in The encrypted message. @@ -78,23 +78,23 @@ status_t otbn_testutils_rsa_modexp_f4_finalize(dif_otbn_t *otbn, uint8_t *out, * length (i.e. 128 for RSA 1024). Valid range: 32..512 in * 32 byte-steps (i.e. RSA 256 to RSA 4096). */ -status_t otbn_testutils_rsa_modexp_consttime_start( - dif_otbn_t *otbn, const uint8_t *modulus, const uint8_t *private_exponent, +status_t acc_testutils_rsa_modexp_consttime_start( + dif_acc_t *acc, const uint8_t *modulus, const uint8_t *private_exponent, const uint8_t *in, size_t size_bytes); /** * Finish modular exponentiation with the exponent 65537. * - * Waits for OTBN to complete and reads back the result of modular - * exponentiation. Call only after `otbn_testutils_rsa_modexp_consttime_start`. + * Waits for ACC to complete and reads back the result of modular + * exponentiation. Call only after `acc_testutils_rsa_modexp_consttime_start`. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. * @param out The encrypted message. * @param size_bytes The size of all buffers in bytes, i.e. the key/modulus * length (i.e. 128 for RSA 1024). Valid range: 32..512 in * 32 byte-steps (i.e. RSA 256 to RSA 4096). */ -status_t otbn_testutils_rsa_modexp_consttime_finalize(dif_otbn_t *otbn, - uint8_t *out, - size_t size_bytes); +status_t acc_testutils_rsa_modexp_consttime_finalize(dif_acc_t *acc, + uint8_t *out, + size_t size_bytes); -#endif // OPENTITAN_SW_DEVICE_LIB_TESTING_OTBN_TESTUTILS_RSA_H_ +#endif // OPENTITAN_SW_DEVICE_LIB_TESTING_ACC_TESTUTILS_RSA_H_ diff --git a/sw/device/lib/testing/otbn_testutils.h b/sw/device/lib/testing/otbn_testutils.h deleted file mode 100644 index 7ec03d9c4b8..00000000000 --- a/sw/device/lib/testing/otbn_testutils.h +++ /dev/null @@ -1,222 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef OPENTITAN_SW_DEVICE_LIB_TESTING_OTBN_TESTUTILS_H_ -#define OPENTITAN_SW_DEVICE_LIB_TESTING_OTBN_TESTUTILS_H_ - -#include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/base/status.h" -#include "sw/device/lib/dif/dif_base.h" -#include "sw/device/lib/dif/dif_otbn.h" - -/** - * @file - * @brief OpenTitan Big Number Accelerator (OTBN) driver - */ - -/** - * Information about an embedded OTBN application image. - * - * All pointers reference data in the normal CPU address space. - * - * Use `OTBN_DECLARE_APP_SYMBOLS()` together with `OTBN_APP_T_INIT()` to - * initialize this structure. - */ -typedef struct otbn_app { - /** - * Start of OTBN instruction memory. - */ - const uint8_t *imem_start; - /** - * End of OTBN instruction memory. - */ - const uint8_t *imem_end; - /** - * Start of initialized OTBN data memory. - * - * Data in this section is copied into DMEM when the app is loaded. - */ - const uint8_t *dmem_data_start; - /** - * End of initialized OTBN data memory. - */ - const uint8_t *dmem_data_end; -} otbn_app_t; - -/** - * The address of an OTBN symbol as seen by OTBN - * - * Use `OTBN_DECLARE_SYMBOL_ADDR()` together with `OTBN_ADDR_T_INIT()` to - * initialize this type. - */ -typedef uint32_t otbn_addr_t; - -/** - * Generate the prefix to add to an OTBN symbol name used on the Ibex side - * - * The result is a pointer to Ibex's rodata that should be used to initialise - * memory for that symbol. - * - * This is needed by the OTBN driver to support DMEM/IMEM ranges but - * application code shouldn't need to use this. Use the `otbn_addr_t` type and - * supporting macros instead. - */ -#define OTBN_SYMBOL_PTR(app_name, sym) _otbn_local_app_##app_name##_##sym - -/** - * Generate the prefix to add to an OTBN symbol name used on the OTBN side - * - * The result is a pointer whose integer value is the address by which the - * symbol should be accessed in OTBN memory. - * - * This is an internal macro used in `OTBN_DECLARE_SYMBOL_ADDR` and - * `OTBN_ADDR_T_INIT` but application code shouldn't need to use it directly. - */ -#define OTBN_SYMBOL_ADDR(app_name, sym) _otbn_remote_app_##app_name##_##sym - -/** - * Makes a symbol in the OTBN application image available. - * - * This is needed by the OTBN driver to support DMEM/IMEM ranges but - * application code shouldn't need to use this. To get access to OTBN - * addresses, use `OTBN_DECLARE_SYMBOL_ADDR` instead. - */ -#define OTBN_DECLARE_SYMBOL_PTR(app_name, symbol_name) \ - extern const uint8_t OTBN_SYMBOL_PTR(app_name, symbol_name)[] - -/** - * Makes the OTBN address of a symbol in the OTBN application available. - * - * Symbols are typically function or data pointers, i.e. labels in assembly - * code. Unlike OTBN_DECLARE_SYMBOL_PTR, this will work for symbols in the .bss - * section (which exist on the OTBN side, even though they don't have backing - * data on Ibex). - * - * Use this macro instead of manually declaring the symbols as symbol names - * might change. - * - * @param app_name Name of the application the function is contained in. - * @param symbol_name Name of the symbol (function, label). - */ -#define OTBN_DECLARE_SYMBOL_ADDR(app_name, symbol_name) \ - extern const uint8_t OTBN_SYMBOL_ADDR(app_name, symbol_name)[] - -/** - * Makes an embedded OTBN application image available for use. - * - * Make symbols available that indicate the start and the end of instruction - * and data memory regions, as they are stored in the device memory. - * - * Use this macro instead of manually declaring the symbols as symbol names - * might change. - * - * @param app_name Name of the application to load, which is typically the - * name of the main (assembly) source file. - */ -#define OTBN_DECLARE_APP_SYMBOLS(app_name) \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _imem_start); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _imem_end); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _dmem_data_start); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _dmem_data_end) - -/** - * Initializes the OTBN application information structure. - * - * After making all required symbols from the application image available - * through `OTBN_DECLARE_APP_SYMBOLS()`, use this macro to initialize an - * `otbn_app_t` struct with those symbols. - * - * @param app_name Name of the application to load. - * @see OTBN_DECLARE_APP_SYMBOLS() - */ -#define OTBN_APP_T_INIT(app_name) \ - ((otbn_app_t){ \ - .imem_start = OTBN_SYMBOL_PTR(app_name, _imem_start), \ - .imem_end = OTBN_SYMBOL_PTR(app_name, _imem_end), \ - .dmem_data_start = OTBN_SYMBOL_PTR(app_name, _dmem_data_start), \ - .dmem_data_end = OTBN_SYMBOL_PTR(app_name, _dmem_data_end), \ - }) - -/** - * Initializes an `otbn_addr_t`. - */ -#define OTBN_ADDR_T_INIT(app_name, symbol_name) \ - ((uint32_t)OTBN_SYMBOL_ADDR(app_name, symbol_name)) - -/** - * (Re-)loads the application into OTBN. - * - * Load the application image with both instruction and data segments into OTBN. - * - * @param otbn The context object. - * @param app The application to load into OTBN. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -status_t otbn_testutils_load_app(const dif_otbn_t *otbn, const otbn_app_t app); - -/** - * Starts the OTBN execute operation. - * - * Use `otbn_testutils_wait_for_done()` to wait for execution to complete. - * - * @param otbn The context object. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -status_t otbn_testutils_execute(const dif_otbn_t *otbn); - -/** - * Waits for OTBN to be done with the current operation. - * - * Polls the status register until OTBN is idle. Produces a CHECK-fail if OTBN - * is or becomes locked. Checks that the final error bits match expectations. - * - * @param otbn The context object. - * @param expected_err_bits Expected error bits. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -status_t otbn_testutils_wait_for_done(const dif_otbn_t *otbn, - dif_otbn_err_bits_t expected_err_bits); - -/** - * Copies data from the CPU memory to OTBN data memory. - * - * @param otbn The context object. - * @param len_bytes Number of bytes to copy. - * @param dest Address of the destination in OTBN's data memory. - * @param src Source of the data to copy. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -status_t otbn_testutils_write_data(const dif_otbn_t *otbn, size_t len_bytes, - const void *src, otbn_addr_t dest); - -/** - * Copies data from OTBN's data memory to CPU memory. - * - * @param otbn The context object. - * @param len_bytes The number of bytes to copy. - * @param src The address in OTBN data memory to copy from. - * @param[out] dest The destination of the copied data in main memory - * (preallocated). - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -status_t otbn_testutils_read_data(const dif_otbn_t *otbn, size_t len_bytes, - otbn_addr_t src, void *dest); - -/** - * Writes a LOG_INFO message with the contents of each 256b DMEM word. - * - * @param otbn The context object. - * @param max_addr The highest address to dump. Set to 0 to output the whole - * DMEM. Must be a multiple of WLEN. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -status_t otbn_testutils_dump_dmem(const dif_otbn_t *otbn, uint32_t max_addr); - -#endif // OPENTITAN_SW_DEVICE_LIB_TESTING_OTBN_TESTUTILS_H_ diff --git a/sw/device/lib/testing/otbn_testutils_rsa.c b/sw/device/lib/testing/otbn_testutils_rsa.c deleted file mode 100644 index 353317adfa8..00000000000 --- a/sw/device/lib/testing/otbn_testutils_rsa.c +++ /dev/null @@ -1,117 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/lib/testing/otbn_testutils_rsa.h" - -#include "sw/device/lib/base/status.h" -#include "sw/device/lib/dif/dif_otbn.h" -#include "sw/device/lib/testing/otbn_testutils.h" - -OTBN_DECLARE_APP_SYMBOLS(rsa); -OTBN_DECLARE_SYMBOL_ADDR(rsa, mode); -OTBN_DECLARE_SYMBOL_ADDR(rsa, n_limbs); -OTBN_DECLARE_SYMBOL_ADDR(rsa, inout); -OTBN_DECLARE_SYMBOL_ADDR(rsa, modulus); -OTBN_DECLARE_SYMBOL_ADDR(rsa, exp); - -static const otbn_app_t kOtbnAppRsa = OTBN_APP_T_INIT(rsa); -static const otbn_addr_t kOtbnVarRsaMode = OTBN_ADDR_T_INIT(rsa, mode); -static const otbn_addr_t kOtbnVarRsaNLimbs = OTBN_ADDR_T_INIT(rsa, n_limbs); -static const otbn_addr_t kOtbnVarRsaInOut = OTBN_ADDR_T_INIT(rsa, inout); -static const otbn_addr_t kOtbnVarRsaModulus = OTBN_ADDR_T_INIT(rsa, modulus); -static const otbn_addr_t kOtbnVarRsaExp = OTBN_ADDR_T_INIT(rsa, exp); - -enum { - kOtbnWideWordBytes = 256 / 8, - kModeEncrypt = 1, - kModeDecrypt = 2, -}; - -status_t otbn_testutils_rsa_load(dif_otbn_t *otbn) { - if (otbn == NULL) { - return INVALID_ARGUMENT(); - } - return otbn_testutils_load_app(otbn, kOtbnAppRsa); -} - -status_t otbn_testutils_rsa_modexp_f4_start(dif_otbn_t *otbn, - const uint8_t *modulus, - const uint8_t *in, - size_t size_bytes) { - if (otbn == NULL || size_bytes % kOtbnWideWordBytes != 0) { - return INVALID_ARGUMENT(); - } - - uint32_t n_limbs = size_bytes / kOtbnWideWordBytes; - if (n_limbs == 0 || n_limbs > 16) { - return INVALID_ARGUMENT(); - } - - // Write input arguments. - uint32_t mode = kModeEncrypt; - TRY(otbn_testutils_write_data(otbn, sizeof(uint32_t), &mode, - kOtbnVarRsaMode)); - TRY(otbn_testutils_write_data(otbn, sizeof(uint32_t), &n_limbs, - kOtbnVarRsaNLimbs)); - TRY(otbn_testutils_write_data(otbn, size_bytes, modulus, kOtbnVarRsaModulus)); - TRY(otbn_testutils_write_data(otbn, size_bytes, in, kOtbnVarRsaInOut)); - - // Call OTBN to start the operation. - return otbn_testutils_execute(otbn); -} - -status_t otbn_testutils_rsa_modexp_consttime_start( - dif_otbn_t *otbn, const uint8_t *modulus, const uint8_t *private_exponent, - const uint8_t *in, size_t size_bytes) { - if (otbn == NULL || size_bytes % kOtbnWideWordBytes != 0) { - return INVALID_ARGUMENT(); - } - - uint32_t n_limbs = size_bytes / kOtbnWideWordBytes; - if (n_limbs == 0 || n_limbs > 16) { - return INVALID_ARGUMENT(); - } - - // Write input arguments. - uint32_t mode = kModeDecrypt; - TRY(otbn_testutils_write_data(otbn, sizeof(mode), &mode, kOtbnVarRsaMode)); - TRY(otbn_testutils_write_data(otbn, sizeof(n_limbs), &n_limbs, - kOtbnVarRsaNLimbs)); - TRY(otbn_testutils_write_data(otbn, size_bytes, modulus, kOtbnVarRsaModulus)); - TRY(otbn_testutils_write_data(otbn, size_bytes, private_exponent, - kOtbnVarRsaExp)); - TRY(otbn_testutils_write_data(otbn, size_bytes, in, kOtbnVarRsaInOut)); - - // Call OTBN to start the operation. - return otbn_testutils_execute(otbn); -} - -static status_t modexp_finalize(dif_otbn_t *otbn, uint8_t *out, - size_t size_bytes) { - if (otbn == NULL || size_bytes % kOtbnWideWordBytes != 0) { - return INVALID_ARGUMENT(); - } - - uint32_t n_limbs = size_bytes / kOtbnWideWordBytes; - if (n_limbs == 0 || n_limbs > 16) { - return INVALID_ARGUMENT(); - } - - // Wait for OTBN to complete. - TRY(otbn_testutils_wait_for_done(otbn, kDifOtbnErrBitsNoError)); - - // Read back results. - return otbn_testutils_read_data(otbn, size_bytes, kOtbnVarRsaInOut, out); -} - -status_t otbn_testutils_rsa_modexp_f4_finalize(dif_otbn_t *otbn, uint8_t *out, - size_t size_bytes) { - return modexp_finalize(otbn, out, size_bytes); -} - -status_t otbn_testutils_rsa_modexp_consttime_finalize(dif_otbn_t *otbn, - uint8_t *out, - size_t size_bytes) { - return modexp_finalize(otbn, out, size_bytes); -} diff --git a/sw/device/sca/BUILD b/sw/device/sca/BUILD index 1e4e82428b6..d8c9c527300 100644 --- a/sw/device/sca/BUILD +++ b/sw/device/sca/BUILD @@ -91,8 +91,9 @@ opentitan_binary( ], deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//sw/acc/crypto:p384_ecdsa_sca", "//sw/device/lib/base:memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", @@ -101,7 +102,6 @@ opentitan_binary( "//sw/device/sca/lib:prng", "//sw/device/sca/lib:simple_serial", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/otbn/crypto:p384_ecdsa_sca", ], ) @@ -115,9 +115,10 @@ opentitan_binary( ], deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//sw/acc/crypto:p256_ecdsa_sca", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", @@ -126,6 +127,5 @@ opentitan_binary( "//sw/device/sca/lib:prng", "//sw/device/sca/lib:simple_serial", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/otbn/crypto:p256_ecdsa_sca", ], ) diff --git a/sw/device/sca/otbn_vertical/BUILD b/sw/device/sca/acc_vertical/BUILD similarity index 83% rename from sw/device/sca/otbn_vertical/BUILD rename to sw/device/sca/acc_vertical/BUILD index 5c1576866a1..fd8eb1b2da0 100644 --- a/sw/device/sca/otbn_vertical/BUILD +++ b/sw/device/sca/acc_vertical/BUILD @@ -12,9 +12,10 @@ cc_library( hdrs = ["ecc256_keygen_serial.h"], deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//sw/acc/crypto:p256_key_from_seed_sca", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", @@ -23,7 +24,6 @@ cc_library( "//sw/device/sca/lib:prng", "//sw/device/sca/lib:simple_serial", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/otbn/crypto:p256_key_from_seed_sca", ], ) @@ -33,9 +33,10 @@ cc_library( hdrs = ["ecc256_modinv_serial.h"], deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//sw/acc/crypto:p256_mod_inv_sca", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", @@ -44,33 +45,32 @@ cc_library( "//sw/device/sca/lib:prng", "//sw/device/sca/lib:simple_serial", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/otbn/crypto:p256_mod_inv_sca", ], ) opentitan_binary( - name = "otbn_vertical_serial", + name = "acc_vertical_serial", testonly = True, - srcs = ["otbn_vertical_serial.c"], + srcs = ["acc_vertical_serial.c"], exec_env = [ "//hw/top_earlgrey:fpga_cw305", "//hw/top_earlgrey:fpga_cw310", ], deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//sw/acc/crypto:p256_mod_inv_sca", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_a", "//sw/device/lib/testing/test_framework:ottf_main", + "//sw/device/sca/acc_vertical:ecc256_keygen_serial", + "//sw/device/sca/acc_vertical:ecc256_modinv_serial", "//sw/device/sca/lib:prng", "//sw/device/sca/lib:simple_serial", - "//sw/device/sca/otbn_vertical:ecc256_keygen_serial", - "//sw/device/sca/otbn_vertical:ecc256_modinv_serial", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/otbn/crypto:p256_mod_inv_sca", ], ) diff --git a/sw/device/sca/otbn_vertical/otbn_vertical_serial.c b/sw/device/sca/acc_vertical/acc_vertical_serial.c similarity index 82% rename from sw/device/sca/otbn_vertical/otbn_vertical_serial.c rename to sw/device/sca/acc_vertical/acc_vertical_serial.c index 9cbdab45cd7..b50baca025c 100644 --- a/sw/device/sca/otbn_vertical/otbn_vertical_serial.c +++ b/sw/device/sca/acc_vertical/acc_vertical_serial.c @@ -4,26 +4,26 @@ #include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/entropy_testutils.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" #include "sw/device/lib/testing/test_framework/ottf_test_config.h" +#include "sw/device/sca/acc_vertical/ecc256_keygen_serial.h" +#include "sw/device/sca/acc_vertical/ecc256_modinv_serial.h" #include "sw/device/sca/lib/prng.h" #include "sw/device/sca/lib/simple_serial.h" -#include "sw/device/sca/otbn_vertical/ecc256_keygen_serial.h" -#include "sw/device/sca/otbn_vertical/ecc256_modinv_serial.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "hw/top/otbn_regs.h" +#include "hw/top/acc_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" /** - * OpenTitan program for OTBN vertical side-channel analysis. + * OpenTitan program for ACC vertical side-channel analysis. * * This program implements the following simple serial commands: - * - Select the required OTBN app (currently keygen/modinv) ('a') + * - Select the required ACC app (currently keygen/modinv) ('a') * - Set seed for ecc256 keygen ('x'), * - Secret ecc256 keygen key generation ('k'), * - Ecc256 keygen keypair generation ('p'), @@ -40,7 +40,7 @@ OTTF_DEFINE_TEST_CONFIG(); /** * Simple serial 'a' (app select) command handler. * - * This handler has to be called to load a new app to otbn. + * This handler has to be called to load a new app to acc. * * @param app_cmd 0 => ecc256 keygen, 1 => ecc256 modular inverse. * @param app_cmd_len Length of sent command value. @@ -49,10 +49,10 @@ static void ecc256_app_select(const uint8_t *app_cmd, size_t app_cmd_len) { SS_CHECK(app_cmd_len == 1); if (*app_cmd == 0) { // load keygen app - SS_CHECK_STATUS_OK(otbn_load_app(kOtbnAppP256KeyFromSeed)); + SS_CHECK_STATUS_OK(acc_load_app(kAccAppP256KeyFromSeed)); } else if (*app_cmd == 1) { // load mod inv app - SS_CHECK_STATUS_OK(otbn_load_app(kOtbnAppP256ModInv)); + SS_CHECK_STATUS_OK(acc_load_app(kAccAppP256ModInv)); } else { LOG_ERROR("Wrong app select command."); } @@ -66,9 +66,9 @@ static void simple_serial_main(void) { SS_CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); bool sensor_ctrl_enable = false; bool sensor_ctrl_en_fatal[SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS] = {false}; - pentest_init(kPentestTriggerSourceOtbn, + pentest_init(kPentestTriggerSourceAcc, kPentestPeripheralEntropy | kPentestPeripheralIoDiv4 | - kPentestPeripheralOtbn | kPentestPeripheralCsrng | + kPentestPeripheralAcc | kPentestPeripheralCsrng | kPentestPeripheralEdn | kPentestPeripheralHmac, sensor_ctrl_enable, sensor_ctrl_en_fatal); @@ -96,8 +96,8 @@ static void simple_serial_main(void) { kSimpleSerialOk); // load keygen app as default - LOG_INFO("Load p256 keygen from seed app into OTBN"); - SS_CHECK_STATUS_OK(otbn_load_app(kOtbnAppP256KeyFromSeed)); + LOG_INFO("Load p256 keygen from seed app into ACC"); + SS_CHECK_STATUS_OK(acc_load_app(kAccAppP256KeyFromSeed)); LOG_INFO("Starting simple serial packet handling."); while (true) { diff --git a/sw/device/sca/otbn_vertical/ecc256_keygen_serial.c b/sw/device/sca/acc_vertical/ecc256_keygen_serial.c similarity index 85% rename from sw/device/sca/otbn_vertical/ecc256_keygen_serial.c rename to sw/device/sca/acc_vertical/ecc256_keygen_serial.c index 38f9f62d649..73c257da5e1 100644 --- a/sw/device/sca/otbn_vertical/ecc256_keygen_serial.c +++ b/sw/device/sca/acc_vertical/ecc256_keygen_serial.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/sca/otbn_vertical/ecc256_keygen_serial.h" +#include "sw/device/sca/acc_vertical/ecc256_keygen_serial.h" #include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/memory.h" @@ -15,7 +15,7 @@ #include "sw/device/sca/lib/simple_serial.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "hw/top/otbn_regs.h" +#include "hw/top/acc_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" enum { @@ -48,34 +48,29 @@ enum { */ kNumBatchOpsMax = 256, /** - * Number of cycles that Ibex should sleep to minimize noise during OTBN + * Number of cycles that Ibex should sleep to minimize noise during ACC * operations. Caution: This number should be chosen to provide enough time - * to complete the operation. Otherwise, Ibex might wake up while OTBN is + * to complete the operation. Otherwise, Ibex might wake up while ACC is * still busy and disturb the capture. */ - kIbexOtbnSleepCycles = 800, + kIbexAccSleepCycles = 800, }; /** * App configuration for p256_key_from_seed_sca */ -const otbn_app_t kOtbnAppP256KeyFromSeed = - OTBN_APP_T_INIT(p256_key_from_seed_sca); - -static const otbn_addr_t kOtbnVarMode = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, mode); -static const otbn_addr_t kOtbnVarSeed0 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, seed0); -static const otbn_addr_t kOtbnVarSeed1 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, seed1); -static const otbn_addr_t kOtbnVarD0 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, d0); -static const otbn_addr_t kOtbnVarD1 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, d1); -static const otbn_addr_t kOtbnVarX = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, x); -static const otbn_addr_t kOtbnVarY = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, y); +const acc_app_t kAccAppP256KeyFromSeed = ACC_APP_T_INIT(p256_key_from_seed_sca); + +static const acc_addr_t kAccVarMode = + ACC_ADDR_T_INIT(p256_key_from_seed_sca, mode); +static const acc_addr_t kAccVarSeed0 = + ACC_ADDR_T_INIT(p256_key_from_seed_sca, seed0); +static const acc_addr_t kAccVarSeed1 = + ACC_ADDR_T_INIT(p256_key_from_seed_sca, seed1); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(p256_key_from_seed_sca, d0); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(p256_key_from_seed_sca, d1); +static const acc_addr_t kAccVarX = ACC_ADDR_T_INIT(p256_key_from_seed_sca, x); +static const acc_addr_t kAccVarY = ACC_ADDR_T_INIT(p256_key_from_seed_sca, y); /** * An array of seeds to be used in a batch @@ -113,7 +108,7 @@ static bool en_masks = false; * Seed value. * * The default value corresponds to the test data in - * sw/otbn/crypto/test/p256_key_from_seed_test.s + * sw/acc/crypto/test/p256_key_from_seed_test.s * * This default value can be overwritten via the simpleserial command `x` * (see ecc256_set_seed) @@ -178,12 +173,12 @@ void ecc256_set_c(const uint8_t *C, size_t len) { } /** - * Callback wrapper for OTBN manual trigger function. + * Callback wrapper for ACC manual trigger function. */ -static void otbn_manual_trigger(void) { SS_CHECK_STATUS_OK(otbn_execute()); } +static void acc_manual_trigger(void) { SS_CHECK_STATUS_OK(acc_execute()); } /** - * Runs the OTBN key generation program. + * Runs the ACC key generation program. * * The seed shares must be `kEcc256SeedNumWords` words long. * @@ -194,19 +189,16 @@ static void otbn_manual_trigger(void) { SS_CHECK_STATUS_OK(otbn_execute()); } static void p256_run_keygen(uint32_t mode, const uint32_t *share0, const uint32_t *share1) { // Write mode. - SS_CHECK_STATUS_OK(otbn_dmem_write(/*num_words=*/1, &mode, kOtbnVarMode)); + SS_CHECK_STATUS_OK(acc_dmem_write(/*num_words=*/1, &mode, kAccVarMode)); // Write seed shares. - SS_CHECK_STATUS_OK( - otbn_dmem_write(kEcc256SeedNumWords, share0, kOtbnVarSeed0)); - SS_CHECK_STATUS_OK( - otbn_dmem_write(kEcc256SeedNumWords, share1, kOtbnVarSeed1)); + SS_CHECK_STATUS_OK(acc_dmem_write(kEcc256SeedNumWords, share0, kAccVarSeed0)); + SS_CHECK_STATUS_OK(acc_dmem_write(kEcc256SeedNumWords, share1, kAccVarSeed1)); // Execute program. pentest_set_trigger_high(); - pentest_call_and_sleep(otbn_manual_trigger, kIbexOtbnSleepCycles, false, - false); - SS_CHECK_STATUS_OK(otbn_busy_wait_for_done()); + pentest_call_and_sleep(acc_manual_trigger, kIbexAccSleepCycles, false, false); + SS_CHECK_STATUS_OK(acc_busy_wait_for_done()); pentest_set_trigger_low(); } @@ -253,10 +245,8 @@ void ecc256_ecdsa_keygen_fvsr_seed_batch(const uint8_t *data, size_t data_len) { batch_share1[i]); // Read results. - SS_CHECK_STATUS_OK( - otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD0, d0_batch)); - SS_CHECK_STATUS_OK( - otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD1, d1_batch)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD0, d0_batch)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD1, d1_batch)); // The correctness of each batch is verified by computing and sending // the batch digest. This digest is computed by XORing all d0 shares of @@ -351,10 +341,8 @@ void ecc256_ecdsa_keygen_fvsr_key_batch(const uint8_t *data, size_t data_len) { batch_share1[i]); // Read results. - SS_CHECK_STATUS_OK( - otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD0, d0_batch)); - SS_CHECK_STATUS_OK( - otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD1, d1_batch)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD0, d0_batch)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD1, d1_batch)); // The correctness of each batch is verified by computing and sending // the batch digest. This digest is computed by XORing all d0 shares of @@ -393,8 +381,8 @@ static void p256_ecdsa_gen_secret_key(const uint32_t *seed, p256_run_keygen(kEcc256ModePrivateKeyOnly, share0, mask); // Read results. - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD0, d0)); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD1, d1)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD0, d0)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD1, d1)); } /** @@ -424,10 +412,10 @@ static void p256_ecdsa_gen_keypair(const uint32_t *seed, const uint32_t *mask, p256_run_keygen(kEcc256ModeKeypair, share0, mask); // Read results. - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD0, d0)); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD1, d1)); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256CoordNumWords, kOtbnVarX, x)); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256CoordNumWords, kOtbnVarY, y)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD0, d0)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256SeedNumWords, kAccVarD1, d1)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256CoordNumWords, kAccVarX, x)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256CoordNumWords, kAccVarY, y)); } void ecc256_ecdsa_secret_keygen(const uint8_t *mask, size_t mask_len) { diff --git a/sw/device/sca/otbn_vertical/ecc256_keygen_serial.h b/sw/device/sca/acc_vertical/ecc256_keygen_serial.h similarity index 76% rename from sw/device/sca/otbn_vertical/ecc256_keygen_serial.h rename to sw/device/sca/acc_vertical/ecc256_keygen_serial.h index 5798cf5d91b..d4b5a5ab414 100644 --- a/sw/device/sca/otbn_vertical/ecc256_keygen_serial.h +++ b/sw/device/sca/acc_vertical/ecc256_keygen_serial.h @@ -2,33 +2,33 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_SW_DEVICE_SCA_OTBN_VERTICAL_ECC256_KEYGEN_SERIAL_H_ -#define OPENTITAN_SW_DEVICE_SCA_OTBN_VERTICAL_ECC256_KEYGEN_SERIAL_H_ +#ifndef OPENTITAN_SW_DEVICE_SCA_ACC_VERTICAL_ECC256_KEYGEN_SERIAL_H_ +#define OPENTITAN_SW_DEVICE_SCA_ACC_VERTICAL_ECC256_KEYGEN_SERIAL_H_ -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" /** * App configuration for p256_key_from_seed_sca */ -OTBN_DECLARE_APP_SYMBOLS(p256_key_from_seed_sca); +ACC_DECLARE_APP_SYMBOLS(p256_key_from_seed_sca); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, mode); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed0); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed1); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d0); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d1); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, x); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, y); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, mode); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed0); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed1); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d0); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d1); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, x); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, y); -extern const otbn_app_t kOtbnAppP256KeyFromSeed; +extern const acc_app_t kAccAppP256KeyFromSeed; -static const otbn_addr_t kOtbnVarMode; -static const otbn_addr_t kOtbnVarSeed0; -static const otbn_addr_t kOtbnVarSeed1; -static const otbn_addr_t kOtbnVarD0; -static const otbn_addr_t kOtbnVarD1; -static const otbn_addr_t kOtbnVarX; -static const otbn_addr_t kOtbnVarY; +static const acc_addr_t kAccVarMode; +static const acc_addr_t kAccVarSeed0; +static const acc_addr_t kAccVarSeed1; +static const acc_addr_t kAccVarD0; +static const acc_addr_t kAccVarD1; +static const acc_addr_t kAccVarX; +static const acc_addr_t kAccVarY; /** * Simple serial 'm' (set masks enable) command handler. @@ -94,7 +94,7 @@ void ecc256_ecdsa_keygen_fvsr_seed_batch(const uint8_t *data, size_t data_len); /** * Simple serial 'k' (secret keygen) command handler. * - * Takes the mask value from the simple serial UART and triggers an OTBN + * Takes the mask value from the simple serial UART and triggers an ACC * secret key generation operation. The mask must be `kEcc256SeedNumBytes` * bytes long. * @@ -108,7 +108,7 @@ void ecc256_ecdsa_secret_keygen(const uint8_t *mask, size_t mask_len); /** * Simple serial 'p' (keypair generation) command handler. * - * Takes the mask value from the simple serial UART and triggers an OTBN + * Takes the mask value from the simple serial UART and triggers an ACC * secret key generation operation. The mask must be `kEcc256SeedNumBytes` * bytes long. * @@ -119,4 +119,4 @@ void ecc256_ecdsa_secret_keygen(const uint8_t *mask, size_t mask_len); */ void ecc256_ecdsa_gen_keypair(const uint8_t *mask, size_t mask_len); -#endif // OPENTITAN_SW_DEVICE_SCA_OTBN_VERTICAL_ECC256_KEYGEN_SERIAL_H_ +#endif // OPENTITAN_SW_DEVICE_SCA_ACC_VERTICAL_ECC256_KEYGEN_SERIAL_H_ diff --git a/sw/device/sca/otbn_vertical/ecc256_modinv_serial.c b/sw/device/sca/acc_vertical/ecc256_modinv_serial.c similarity index 69% rename from sw/device/sca/otbn_vertical/ecc256_modinv_serial.c rename to sw/device/sca/acc_vertical/ecc256_modinv_serial.c index 2e44fc65e42..e4b761ceb99 100644 --- a/sw/device/sca/otbn_vertical/ecc256_modinv_serial.c +++ b/sw/device/sca/acc_vertical/ecc256_modinv_serial.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/sca/otbn_vertical/ecc256_modinv_serial.h" +#include "sw/device/sca/acc_vertical/ecc256_modinv_serial.h" #include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/memory.h" @@ -15,17 +15,17 @@ #include "sw/device/sca/lib/simple_serial.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "hw/top/otbn_regs.h" +#include "hw/top/acc_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" enum { /** - * Number of cycles that Ibex should sleep to minimize noise during OTBN + * Number of cycles that Ibex should sleep to minimize noise during ACC * operations. Caution: This number should be chosen to provide enough time - * to complete the operation. Otherwise, Ibex might wake up while OTBN is + * to complete the operation. Otherwise, Ibex might wake up while ACC is * still busy and disturb the capture. */ - kIbexOtbnSleepCycles = 50000, + kIbexAccSleepCycles = 50000, /** * Number of bytes for ECDSA P-256 modular inverse input shares (k0,k1). */ @@ -60,41 +60,38 @@ enum { /** * App configuration for p256_mod_inv_sca */ -const otbn_app_t kOtbnAppP256ModInv = OTBN_APP_T_INIT(p256_mod_inv_sca); +const acc_app_t kAccAppP256ModInv = ACC_APP_T_INIT(p256_mod_inv_sca); -static const otbn_addr_t kOtbnVarModInvK0 = - OTBN_ADDR_T_INIT(p256_mod_inv_sca, k0); -static const otbn_addr_t kOtbnVarModInvK1 = - OTBN_ADDR_T_INIT(p256_mod_inv_sca, k1); -static const otbn_addr_t kOtbnVarModInvKAplhaInv = - OTBN_ADDR_T_INIT(p256_mod_inv_sca, kalpha_inv); -static const otbn_addr_t kOtbnVarModInvAlpha = - OTBN_ADDR_T_INIT(p256_mod_inv_sca, alpha); +static const acc_addr_t kAccVarModInvK0 = ACC_ADDR_T_INIT(p256_mod_inv_sca, k0); +static const acc_addr_t kAccVarModInvK1 = ACC_ADDR_T_INIT(p256_mod_inv_sca, k1); +static const acc_addr_t kAccVarModInvKAplhaInv = + ACC_ADDR_T_INIT(p256_mod_inv_sca, kalpha_inv); +static const acc_addr_t kAccVarModInvAlpha = + ACC_ADDR_T_INIT(p256_mod_inv_sca, alpha); /** - * Callback wrapper for OTBN manual trigger function. + * Callback wrapper for ACC manual trigger function. */ -static void otbn_manual_trigger(void) { SS_CHECK_STATUS_OK(otbn_execute()); } +static void acc_manual_trigger(void) { SS_CHECK_STATUS_OK(acc_execute()); } /** - * Runs the OTBN modular inverse program. + * Runs the ACC modular inverse program. * * The input must be `kEcc256ModInvInputShareNumWords` words long. * - * @param[in] input Iput value for the OTBN modular inverse. + * @param[in] input Iput value for the ACC modular inverse. */ static void p256_run_modinv(uint32_t *k0, uint32_t *k1) { // Write input. SS_CHECK_STATUS_OK( - otbn_dmem_write(kEcc256ModInvInputShareNumWords, k0, kOtbnVarModInvK0)); + acc_dmem_write(kEcc256ModInvInputShareNumWords, k0, kAccVarModInvK0)); SS_CHECK_STATUS_OK( - otbn_dmem_write(kEcc256ModInvInputShareNumWords, k1, kOtbnVarModInvK1)); + acc_dmem_write(kEcc256ModInvInputShareNumWords, k1, kAccVarModInvK1)); // Execute program. pentest_set_trigger_high(); - pentest_call_and_sleep(otbn_manual_trigger, kIbexOtbnSleepCycles, false, - false); - SS_CHECK_STATUS_OK(otbn_busy_wait_for_done()); + pentest_call_and_sleep(acc_manual_trigger, kIbexAccSleepCycles, false, false); + SS_CHECK_STATUS_OK(acc_busy_wait_for_done()); pentest_set_trigger_low(); } @@ -117,11 +114,10 @@ void ecc256_modinv(const uint8_t *k0_k1, size_t k0_k1_len) { // Read result. uint32_t modinv_kalpha_inv[kEcc256ModInvOutputKAlphaInvNumWords]; uint32_t modinv_alpha[kEcc256ModInvOutputAlphaNumWords]; - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256ModInvOutputKAlphaInvNumWords, - kOtbnVarModInvKAplhaInv, - modinv_kalpha_inv)); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256ModInvOutputAlphaNumWords, - kOtbnVarModInvAlpha, modinv_alpha)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256ModInvOutputKAlphaInvNumWords, + kAccVarModInvKAplhaInv, modinv_kalpha_inv)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256ModInvOutputAlphaNumWords, + kAccVarModInvAlpha, modinv_alpha)); simple_serial_send_packet('r', (unsigned char *)modinv_kalpha_inv, kEcc256ModInvOutputKAlphaInvNumBytes); diff --git a/sw/device/sca/acc_vertical/ecc256_modinv_serial.h b/sw/device/sca/acc_vertical/ecc256_modinv_serial.h new file mode 100644 index 00000000000..1583da9fef3 --- /dev/null +++ b/sw/device/sca/acc_vertical/ecc256_modinv_serial.h @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_SCA_ACC_VERTICAL_ECC256_MODINV_SERIAL_H_ +#define OPENTITAN_SW_DEVICE_SCA_ACC_VERTICAL_ECC256_MODINV_SERIAL_H_ + +#include "sw/device/lib/crypto/drivers/acc.h" + +/** + * App configuration for p256_mod_inv_sca + */ +ACC_DECLARE_APP_SYMBOLS(p256_mod_inv_sca); + +ACC_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, k0); +ACC_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, k1); +ACC_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, kalpha_inv); +ACC_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, alpha); + +extern const acc_app_t kAccAppP256ModInv; + +static const acc_addr_t kAccVarModInvK0; +static const acc_addr_t kAccVarModInvK1; +static const acc_addr_t kAccVarModInvKAplhaInv; +static const acc_addr_t kAccVarModInvAlpha; + +/** + * Computes the modular inverse of a certain input. + * + * The input must be `kEcc256ModInvInputShareNumWords` words long. + * + * @param[in] input Input for modular inverse computation. + */ +void ecc256_modinv(const uint8_t *k0_k1, size_t k0_k1_len); + +#endif // OPENTITAN_SW_DEVICE_SCA_ACC_VERTICAL_ECC256_MODINV_SERIAL_H_ diff --git a/sw/device/sca/ecc256_sign_serial.c b/sw/device/sca/ecc256_sign_serial.c index 0cad88db7f8..e4e0e9f18e2 100644 --- a/sw/device/sca/ecc256_sign_serial.c +++ b/sw/device/sca/ecc256_sign_serial.c @@ -4,7 +4,7 @@ #include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/entropy_testutils.h" @@ -13,11 +13,11 @@ #include "sw/device/sca/lib/simple_serial.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "hw/top/otbn_regs.h" +#include "hw/top/acc_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" /** - * OpenTitan program for OTBN ECDSA-P256 side-channel analysis. + * OpenTitan program for ACC ECDSA-P256 side-channel analysis. * * This program implements the following simple serial commands: * - Set ephemeral secret key ('k')*, @@ -30,7 +30,7 @@ * implemented in the simple serial library. * See https://wiki.newae.com/SimpleSerial for details on the protocol. * - * The OTBN-related code was developed based on + * The ACC-related code was developed based on * https://github.com/lowRISC/opentitan/tree/master/sw/device/lib/crypto/ecc/ecdsa_p256.c * and * https://github.com/lowRISC/opentitan/blob/master/sw/device/tests/crypto/ecdsa_p256_functest.c @@ -71,7 +71,7 @@ uint32_t ecc256_secret_k[2 * kEcc256NumWords] = { * Private key d * This is the default value used by NewAE in their experiments * https://github.com/newaetech/ot-sca/blob/ecc-analysis/reports/ecc/REPORT.md - * https://github.com/newaetech/opentitan/tree/sca_otbninst + * https://github.com/newaetech/opentitan/tree/sca_accinst * * * The value of this variable can be overwritten via @@ -96,33 +96,33 @@ uint32_t ecc256_msg[kEcc256NumWords] = { }; // p256_ecdsa_sca has randomnization removed. -OTBN_DECLARE_APP_SYMBOLS(p256_ecdsa_sca); +ACC_DECLARE_APP_SYMBOLS(p256_ecdsa_sca); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, mode); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, msg); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, r); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, s); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, y); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d0); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d1); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k0); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k1); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x_r); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, mode); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, msg); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, r); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, s); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, y); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d0); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d1); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k0); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k1); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x_r); -static const otbn_app_t kOtbnAppP256Ecdsa = OTBN_APP_T_INIT(p256_ecdsa_sca); +static const acc_app_t kAccAppP256Ecdsa = ACC_APP_T_INIT(p256_ecdsa_sca); -static const otbn_addr_t kOtbnVarMode = OTBN_ADDR_T_INIT(p256_ecdsa_sca, mode); -static const otbn_addr_t kOtbnVarMsg = OTBN_ADDR_T_INIT(p256_ecdsa_sca, msg); -static const otbn_addr_t kOtbnVarR = OTBN_ADDR_T_INIT(p256_ecdsa_sca, r); -static const otbn_addr_t kOtbnVarS = OTBN_ADDR_T_INIT(p256_ecdsa_sca, s); -static const otbn_addr_t kOtbnVarX = OTBN_ADDR_T_INIT(p256_ecdsa_sca, x); -static const otbn_addr_t kOtbnVarY = OTBN_ADDR_T_INIT(p256_ecdsa_sca, y); -static const otbn_addr_t kOtbnVarD0 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, d0); -static const otbn_addr_t kOtbnVarD1 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, d1); -static const otbn_addr_t kOtbnVarXR = OTBN_ADDR_T_INIT(p256_ecdsa_sca, x_r); -static const otbn_addr_t kOtbnVarK0 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, k0); -static const otbn_addr_t kOtbnVarK1 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, k1); +static const acc_addr_t kAccVarMode = ACC_ADDR_T_INIT(p256_ecdsa_sca, mode); +static const acc_addr_t kAccVarMsg = ACC_ADDR_T_INIT(p256_ecdsa_sca, msg); +static const acc_addr_t kAccVarR = ACC_ADDR_T_INIT(p256_ecdsa_sca, r); +static const acc_addr_t kAccVarS = ACC_ADDR_T_INIT(p256_ecdsa_sca, s); +static const acc_addr_t kAccVarX = ACC_ADDR_T_INIT(p256_ecdsa_sca, x); +static const acc_addr_t kAccVarY = ACC_ADDR_T_INIT(p256_ecdsa_sca, y); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(p256_ecdsa_sca, d0); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(p256_ecdsa_sca, d1); +static const acc_addr_t kAccVarXR = ACC_ADDR_T_INIT(p256_ecdsa_sca, x_r); +static const acc_addr_t kAccVarK0 = ACC_ADDR_T_INIT(p256_ecdsa_sca, k0); +static const acc_addr_t kAccVarK1 = ACC_ADDR_T_INIT(p256_ecdsa_sca, k1); /** * Simple serial 'k' (set ephemeral key) command handler. @@ -189,7 +189,7 @@ static void ecc256_set_msg(const uint8_t *msg, size_t msg_len) { * r = x-coordinate of R * s = k^(-1)(msg + r*d) mod n * - * @param otbn_ctx The OTBN context object. + * @param acc_ctx The ACC context object. * @param msg The message to sign, msg (32B). * @param private_key_d The private key, d (32B). * @param k The ephemeral key, k (random scalar) (32B). @@ -202,40 +202,39 @@ static void p256_ecdsa_sign(const uint32_t *msg, const uint32_t *private_key_d, uint32_t *signature_r, uint32_t *signature_s, const uint32_t *k) { uint32_t mode = 1; // mode 1 => sign - // Send operation mode to OTBN - SS_CHECK_STATUS_OK(otbn_dmem_write(/*num_words=*/1, &mode, kOtbnVarMode)); - // Send Msg to OTBN - SS_CHECK_STATUS_OK(otbn_dmem_write(kEcc256NumWords, msg, kOtbnVarMsg)); - // Send two shares of private_key_d to OTBN + // Send operation mode to ACC + SS_CHECK_STATUS_OK(acc_dmem_write(/*num_words=*/1, &mode, kAccVarMode)); + // Send Msg to ACC + SS_CHECK_STATUS_OK(acc_dmem_write(kEcc256NumWords, msg, kAccVarMsg)); + // Send two shares of private_key_d to ACC + SS_CHECK_STATUS_OK(acc_dmem_write(kEcc256NumWords, private_key_d, kAccVarD0)); + SS_CHECK_STATUS_OK(acc_dmem_write( + kEcc256NumWords, private_key_d + kEcc256NumWords, kAccVarD1)); + // Send two shares of secret_k to ACC + SS_CHECK_STATUS_OK(acc_dmem_write(kEcc256NumWords, k, kAccVarK0)); SS_CHECK_STATUS_OK( - otbn_dmem_write(kEcc256NumWords, private_key_d, kOtbnVarD0)); - SS_CHECK_STATUS_OK(otbn_dmem_write( - kEcc256NumWords, private_key_d + kEcc256NumWords, kOtbnVarD1)); - // Send two shares of secret_k to OTBN - SS_CHECK_STATUS_OK(otbn_dmem_write(kEcc256NumWords, k, kOtbnVarK0)); - SS_CHECK_STATUS_OK( - otbn_dmem_write(kEcc256NumWords, k + kEcc256NumWords, kOtbnVarK1)); + acc_dmem_write(kEcc256NumWords, k + kEcc256NumWords, kAccVarK1)); - // Start OTBN execution - SS_CHECK_STATUS_OK(otbn_execute()); - SS_CHECK_STATUS_OK(otbn_busy_wait_for_done()); + // Start ACC execution + SS_CHECK_STATUS_OK(acc_execute()); + SS_CHECK_STATUS_OK(acc_busy_wait_for_done()); // Read the results back (sig_r, sig_s) - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256NumWords, kOtbnVarR, signature_r)); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc256NumWords, kOtbnVarS, signature_s)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256NumWords, kAccVarR, signature_r)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc256NumWords, kAccVarS, signature_s)); } /** * Simple serial 'p' (sign) command handler. * - * Triggers OTBN_P256_sign operation. + * Triggers ACC_P256_sign operation. * */ static void ecc256_ecdsa(const uint8_t *arg, size_t len) { LOG_INFO("SSECDSA starting..."); - SS_CHECK_STATUS_OK(otbn_load_app(kOtbnAppP256Ecdsa)); - LOG_INFO("otbn_status: 0x%08x", abs_mmio_read32(TOP_EARLGREY_OTBN_BASE_ADDR + - OTBN_STATUS_REG_OFFSET)); + SS_CHECK_STATUS_OK(acc_load_app(kAccAppP256Ecdsa)); + LOG_INFO("acc_status: 0x%08x", + abs_mmio_read32(TOP_EARLGREY_ACC_BASE_ADDR + ACC_STATUS_REG_OFFSET)); uint32_t ecc256_signature_r[kEcc256NumWords]; uint32_t ecc256_signature_s[kEcc256NumWords]; @@ -258,9 +257,9 @@ static void ecc256_ecdsa(const uint8_t *arg, size_t len) { simple_serial_send_packet('r', ecc256_signature_r_bytes, kEcc256NumBytes); simple_serial_send_packet('r', ecc256_signature_s_bytes, kEcc256NumBytes); - // Clear OTBN memory - SS_CHECK_STATUS_OK(otbn_dmem_sec_wipe()); - SS_CHECK_STATUS_OK(otbn_imem_sec_wipe()); + // Clear ACC memory + SS_CHECK_STATUS_OK(acc_dmem_sec_wipe()); + SS_CHECK_STATUS_OK(acc_imem_sec_wipe()); } /** @@ -271,9 +270,9 @@ static void simple_serial_main(void) { SS_CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); bool sensor_ctrl_enable = false; bool sensor_ctrl_en_fatal[SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS] = {false}; - pentest_init(kPentestTriggerSourceOtbn, + pentest_init(kPentestTriggerSourceAcc, kPentestPeripheralEntropy | kPentestPeripheralIoDiv4 | - kPentestPeripheralOtbn | kPentestPeripheralCsrng | + kPentestPeripheralAcc | kPentestPeripheralCsrng | kPentestPeripheralEdn | kPentestPeripheralHmac, sensor_ctrl_enable, sensor_ctrl_en_fatal); @@ -297,9 +296,9 @@ static void simple_serial_main(void) { } bool test_main(void) { - (void)kOtbnVarX; - (void)kOtbnVarY; - (void)kOtbnVarXR; + (void)kAccVarX; + (void)kAccVarY; + (void)kAccVarXR; simple_serial_main(); return true; diff --git a/sw/device/sca/ecc384_serial.c b/sw/device/sca/ecc384_serial.c index 39438dd7579..22f77585790 100644 --- a/sw/device/sca/ecc384_serial.c +++ b/sw/device/sca/ecc384_serial.c @@ -4,7 +4,7 @@ #include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/entropy_testutils.h" @@ -13,11 +13,11 @@ #include "sw/device/sca/lib/simple_serial.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "hw/top/otbn_regs.h" +#include "hw/top/acc_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" /** - * OpenTitan program for OTBN ECDSA-P384 side-channel analysis. + * OpenTitan program for ACC ECDSA-P384 side-channel analysis. * * This program implements the following simple serial commands: * - Set ephemeral secret key ('k')*, @@ -44,9 +44,9 @@ enum { * Number of 32b words for ECDSA P-384 private keys, message digests, and * point coordinates. * - * Note: Since this is not an even multiple of `kOtbnWideWordNumWords`, the - * caller needs to write zeroes to OTBN to fill out the last wide word. - * Otherwise, OTBN will encounter an error when it tries to read the + * Note: Since this is not an even multiple of `kAccWideWordNumWords`, the + * caller needs to write zeroes to ACC to fill out the last wide word. + * Otherwise, ACC will encounter an error when it tries to read the * uninitialized data. */ kEcc384NumWords = kEcc384NumBytes / sizeof(uint32_t), @@ -97,31 +97,31 @@ uint32_t ecc384_msg[kEcc384NumWords] = { }; // p384_ecdsa_sca has randomnization removed. -OTBN_DECLARE_APP_SYMBOLS(p384_ecdsa_sca); - -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, mode); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, msg); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, r); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, s); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, x); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, y); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, d0); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, d1); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, k0); -OTBN_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, k1); - -static const otbn_app_t kOtbnAppP384Ecdsa = OTBN_APP_T_INIT(p384_ecdsa_sca); - -static const otbn_addr_t kOtbnVarMode = OTBN_ADDR_T_INIT(p384_ecdsa_sca, mode); -static const otbn_addr_t kOtbnVarMsg = OTBN_ADDR_T_INIT(p384_ecdsa_sca, msg); -static const otbn_addr_t kOtbnVarR = OTBN_ADDR_T_INIT(p384_ecdsa_sca, r); -static const otbn_addr_t kOtbnVarS = OTBN_ADDR_T_INIT(p384_ecdsa_sca, s); -static const otbn_addr_t kOtbnVarX = OTBN_ADDR_T_INIT(p384_ecdsa_sca, x); -static const otbn_addr_t kOtbnVarY = OTBN_ADDR_T_INIT(p384_ecdsa_sca, y); -static const otbn_addr_t kOtbnVarD0 = OTBN_ADDR_T_INIT(p384_ecdsa_sca, d0); -static const otbn_addr_t kOtbnVarD1 = OTBN_ADDR_T_INIT(p384_ecdsa_sca, d1); -static const otbn_addr_t kOtbnVarK0 = OTBN_ADDR_T_INIT(p384_ecdsa_sca, k0); -static const otbn_addr_t kOtbnVarK1 = OTBN_ADDR_T_INIT(p384_ecdsa_sca, k1); +ACC_DECLARE_APP_SYMBOLS(p384_ecdsa_sca); + +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, mode); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, msg); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, r); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, s); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, x); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, y); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, d0); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, d1); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, k0); +ACC_DECLARE_SYMBOL_ADDR(p384_ecdsa_sca, k1); + +static const acc_app_t kAccAppP384Ecdsa = ACC_APP_T_INIT(p384_ecdsa_sca); + +static const acc_addr_t kAccVarMode = ACC_ADDR_T_INIT(p384_ecdsa_sca, mode); +static const acc_addr_t kAccVarMsg = ACC_ADDR_T_INIT(p384_ecdsa_sca, msg); +static const acc_addr_t kAccVarR = ACC_ADDR_T_INIT(p384_ecdsa_sca, r); +static const acc_addr_t kAccVarS = ACC_ADDR_T_INIT(p384_ecdsa_sca, s); +static const acc_addr_t kAccVarX = ACC_ADDR_T_INIT(p384_ecdsa_sca, x); +static const acc_addr_t kAccVarY = ACC_ADDR_T_INIT(p384_ecdsa_sca, y); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(p384_ecdsa_sca, d0); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(p384_ecdsa_sca, d1); +static const acc_addr_t kAccVarK0 = ACC_ADDR_T_INIT(p384_ecdsa_sca, k0); +static const acc_addr_t kAccVarK1 = ACC_ADDR_T_INIT(p384_ecdsa_sca, k1); /** * Simple serial 'k' (set ephemeral key) command handler. @@ -182,17 +182,17 @@ static void ecc384_set_msg(const uint8_t *msg, size_t msg_len) { } /** - * Write a 384-bit value to OTBN. + * Write a 384-bit value to ACC. * * This function actually writes 512 bits -- 384 bits with the real data and * the rest with zeroes -- to avoid read-of-uninitialized-data errors during - * OTBN execution. + * ACC execution. */ static void p384_dmem_write(const uint32_t src[kEcc384NumWords], - const otbn_addr_t dest) { - static const uint32_t zero[kEcc384NumWords % kOtbnWideWordNumWords] = {0}; - SS_CHECK_STATUS_OK(otbn_dmem_write(kEcc384NumWords, src, dest)); - SS_CHECK_STATUS_OK(otbn_dmem_write(ARRAYSIZE(zero), zero, dest)); + const acc_addr_t dest) { + static const uint32_t zero[kEcc384NumWords % kAccWideWordNumWords] = {0}; + SS_CHECK_STATUS_OK(acc_dmem_write(kEcc384NumWords, src, dest)); + SS_CHECK_STATUS_OK(acc_dmem_write(ARRAYSIZE(zero), zero, dest)); } /** @@ -202,7 +202,7 @@ static void p384_dmem_write(const uint32_t src[kEcc384NumWords], * r = x-coordinate of R * s = k^(-1)(msg + r*d) mod n * - * @param otbn_ctx The OTBN context object. + * @param acc_ctx The ACC context object. * @param msg The message to sign, msg (48B). * @param private_key_d The private key d (48B). * @param k The ephemeral key k (random scalar) (48B). @@ -216,27 +216,27 @@ static void p384_ecdsa_sign(const uint32_t *msg, const uint32_t *private_key_d, const uint32_t *k) { uint32_t mode = 1; // mode 1 => sign // LOG_INFO("Copy data"); - SS_CHECK_STATUS_OK(otbn_dmem_write(/*num_words=*/1, &mode, kOtbnVarMode)); - p384_dmem_write(msg, kOtbnVarMsg); - p384_dmem_write(private_key_d, kOtbnVarD0); - p384_dmem_write(private_key_d + kEcc384NumWords, kOtbnVarD1); + SS_CHECK_STATUS_OK(acc_dmem_write(/*num_words=*/1, &mode, kAccVarMode)); + p384_dmem_write(msg, kAccVarMsg); + p384_dmem_write(private_key_d, kAccVarD0); + p384_dmem_write(private_key_d + kEcc384NumWords, kAccVarD1); - SS_CHECK_STATUS_OK(otbn_dmem_write(kEcc384NumWords, k, kOtbnVarK0)); + SS_CHECK_STATUS_OK(acc_dmem_write(kEcc384NumWords, k, kAccVarK0)); SS_CHECK_STATUS_OK( - otbn_dmem_write(kEcc384NumWords, k + kEcc384NumWords, kOtbnVarK1)); + acc_dmem_write(kEcc384NumWords, k + kEcc384NumWords, kAccVarK1)); - SS_CHECK_STATUS_OK(otbn_execute()); - SS_CHECK_STATUS_OK(otbn_busy_wait_for_done()); + SS_CHECK_STATUS_OK(acc_execute()); + SS_CHECK_STATUS_OK(acc_busy_wait_for_done()); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc384NumWords, kOtbnVarR, signature_r)); - SS_CHECK_STATUS_OK(otbn_dmem_read(kEcc384NumWords, kOtbnVarS, signature_s)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc384NumWords, kAccVarR, signature_r)); + SS_CHECK_STATUS_OK(acc_dmem_read(kEcc384NumWords, kAccVarS, signature_s)); } /** * Simple serial 'p' (sign) command handler. * * Takes the scalar value from the simple serial UART and triggers - * OTBN_P384_sign operation. + * ACC_P384_sign operation. * * To overwrite the message, use the simpleserial command 'n' * To overwrite the private key value, use the simpleserial command 'd' @@ -248,9 +248,9 @@ static void p384_ecdsa_sign(const uint32_t *msg, const uint32_t *private_key_d, static void ecc384_ecdsa(const uint8_t *ecc384_secret_k_bytes, size_t secret_k_len) { LOG_INFO("SSECDSA starting..."); - SS_CHECK_STATUS_OK(otbn_load_app(kOtbnAppP384Ecdsa)); - LOG_INFO("otbn_status: 0x%08x", abs_mmio_read32(TOP_EARLGREY_OTBN_BASE_ADDR + - OTBN_STATUS_REG_OFFSET)); + SS_CHECK_STATUS_OK(acc_load_app(kAccAppP384Ecdsa)); + LOG_INFO("acc_status: 0x%08x", + abs_mmio_read32(TOP_EARLGREY_ACC_BASE_ADDR + ACC_STATUS_REG_OFFSET)); uint32_t ecc384_signature_r[kEcc384NumWords]; uint32_t ecc384_signature_s[kEcc384NumWords]; @@ -277,9 +277,9 @@ static void ecc384_ecdsa(const uint8_t *ecc384_secret_k_bytes, simple_serial_send_packet('r', ecc384_signature_r_bytes, kEcc384NumBytes); simple_serial_send_packet('r', ecc384_signature_s_bytes, kEcc384NumBytes); - // Clear OTBN memory - SS_CHECK_STATUS_OK(otbn_dmem_sec_wipe()); - SS_CHECK_STATUS_OK(otbn_imem_sec_wipe()); + // Clear ACC memory + SS_CHECK_STATUS_OK(acc_dmem_sec_wipe()); + SS_CHECK_STATUS_OK(acc_imem_sec_wipe()); } /** @@ -290,9 +290,9 @@ static void simple_serial_main(void) { SS_CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); bool sensor_ctrl_enable = false; bool sensor_ctrl_en_fatal[SENSOR_CTRL_PARAM_NUM_ALERT_EVENTS] = {false}; - pentest_init(kPentestTriggerSourceOtbn, + pentest_init(kPentestTriggerSourceAcc, kPentestPeripheralEntropy | kPentestPeripheralIoDiv4 | - kPentestPeripheralOtbn | kPentestPeripheralCsrng | + kPentestPeripheralAcc | kPentestPeripheralCsrng | kPentestPeripheralEdn | kPentestPeripheralHmac, sensor_ctrl_enable, sensor_ctrl_en_fatal); @@ -316,8 +316,8 @@ static void simple_serial_main(void) { } bool test_main(void) { - (void)kOtbnVarX; - (void)kOtbnVarY; + (void)kAccVarX; + (void)kAccVarY; simple_serial_main(); return true; diff --git a/sw/device/sca/otbn_vertical/ecc256_modinv_serial.h b/sw/device/sca/otbn_vertical/ecc256_modinv_serial.h deleted file mode 100644 index 582f776a799..00000000000 --- a/sw/device/sca/otbn_vertical/ecc256_modinv_serial.h +++ /dev/null @@ -1,36 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef OPENTITAN_SW_DEVICE_SCA_OTBN_VERTICAL_ECC256_MODINV_SERIAL_H_ -#define OPENTITAN_SW_DEVICE_SCA_OTBN_VERTICAL_ECC256_MODINV_SERIAL_H_ - -#include "sw/device/lib/crypto/drivers/otbn.h" - -/** - * App configuration for p256_mod_inv_sca - */ -OTBN_DECLARE_APP_SYMBOLS(p256_mod_inv_sca); - -OTBN_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, k0); -OTBN_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, k1); -OTBN_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, kalpha_inv); -OTBN_DECLARE_SYMBOL_ADDR(p256_mod_inv_sca, alpha); - -extern const otbn_app_t kOtbnAppP256ModInv; - -static const otbn_addr_t kOtbnVarModInvK0; -static const otbn_addr_t kOtbnVarModInvK1; -static const otbn_addr_t kOtbnVarModInvKAplhaInv; -static const otbn_addr_t kOtbnVarModInvAlpha; - -/** - * Computes the modular inverse of a certain input. - * - * The input must be `kEcc256ModInvInputShareNumWords` words long. - * - * @param[in] input Input for modular inverse computation. - */ -void ecc256_modinv(const uint8_t *k0_k1, size_t k0_k1_len); - -#endif // OPENTITAN_SW_DEVICE_SCA_OTBN_VERTICAL_ECC256_MODINV_SERIAL_H_ diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD index 926c6716db3..abce56326b4 100644 --- a/sw/device/silicon_creator/lib/BUILD +++ b/sw/device/silicon_creator/lib/BUILD @@ -494,32 +494,32 @@ cc_library( ) cc_library( - name = "otbn_boot_services", - srcs = ["otbn_boot_services.c"], - hdrs = ["otbn_boot_services.h"], - # This target uses OTBN pointers internally, so it cannot work host-side. + name = "acc_boot_services", + srcs = ["acc_boot_services.c"], + hdrs = ["acc_boot_services.h"], + # This target uses ACC pointers internally, so it cannot work host-side. target_compatible_with = [OPENTITAN_CPU], deps = [ ":attestation", + "//sw/acc/crypto:boot", "//sw/device/lib/base:macros", "//sw/device/lib/base:memory", "//sw/device/silicon_creator/lib:dbg_print", "//sw/device/silicon_creator/lib:error", "//sw/device/silicon_creator/lib/base:sec_mmio", "//sw/device/silicon_creator/lib/base:util", + "//sw/device/silicon_creator/lib/drivers:acc", "//sw/device/silicon_creator/lib/drivers:flash_ctrl", "//sw/device/silicon_creator/lib/drivers:hmac", "//sw/device/silicon_creator/lib/drivers:keymgr", - "//sw/device/silicon_creator/lib/drivers:otbn", "//sw/device/silicon_creator/lib/sigverify:ecdsa_p256_key", "//sw/device/silicon_creator/lib/sigverify:rsa_key", - "//sw/otbn/crypto:boot", ], ) opentitan_test( - name = "otbn_boot_services_functest", - srcs = ["otbn_boot_services_functest.c"], + name = "acc_boot_services_functest", + srcs = ["acc_boot_services_functest.c"], broken = fpga_params(tags = ["broken"]), exec_env = dicts.add( EARLGREY_TEST_ENVS, @@ -532,9 +532,9 @@ opentitan_test( # This test can take > 40 minutes, so mark it manual as it shouldn't run # in CI/nightlies. verilator = verilator_params(tags = ["manual"]), - # This target uses OTBN pointers internally, so it cannot work host-side. + # This target uses ACC pointers internally, so it cannot work host-side. deps = [ - ":otbn_boot_services", + ":acc_boot_services", "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/crypto/drivers:entropy", "//sw/device/lib/testing:keymgr_testutils", diff --git a/sw/device/silicon_creator/lib/acc_boot_services.c b/sw/device/silicon_creator/lib/acc_boot_services.c new file mode 100644 index 00000000000..1ca66410621 --- /dev/null +++ b/sw/device/silicon_creator/lib/acc_boot_services.c @@ -0,0 +1,318 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/silicon_creator/lib/acc_boot_services.h" + +#include "sw/device/lib/base/memory.h" +#include "sw/device/silicon_creator/lib/attestation.h" +#include "sw/device/silicon_creator/lib/base/sec_mmio.h" +#include "sw/device/silicon_creator/lib/base/util.h" +#include "sw/device/silicon_creator/lib/dbg_print.h" +#include "sw/device/silicon_creator/lib/drivers/acc.h" +#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" +#include "sw/device/silicon_creator/lib/drivers/hmac.h" +#include "sw/device/silicon_creator/lib/drivers/keymgr.h" + +#include "hw/top/acc_regs.h" // Generated. + +static_assert(kAttestationSeedWords <= 16, + "Additional attestation seed needs must be <= 516 bits."); + +ACC_DECLARE_APP_SYMBOLS(boot); // The ACC boot-services app. +ACC_DECLARE_SYMBOL_ADDR(boot, mode); // Application mode. +ACC_DECLARE_SYMBOL_ADDR(boot, msg); // ECDSA message digest. +ACC_DECLARE_SYMBOL_ADDR(boot, x); // ECDSA public key x-coordinate. +ACC_DECLARE_SYMBOL_ADDR(boot, y); // ECDSA public key y-coordinate. +ACC_DECLARE_SYMBOL_ADDR(boot, r); // ECDSA signature component r. +ACC_DECLARE_SYMBOL_ADDR(boot, s); // ECDSA signature component s. +ACC_DECLARE_SYMBOL_ADDR(boot, x_r); // ECDSA verification result. +ACC_DECLARE_SYMBOL_ADDR(boot, ok); // ECDSA verification status. +ACC_DECLARE_SYMBOL_ADDR( + boot, attestation_additional_seed); // Additional seed for ECDSA keygen. + +static const sc_acc_app_t kAccAppBoot = ACC_APP_T_INIT(boot); +static const sc_acc_addr_t kAccVarBootMode = ACC_ADDR_T_INIT(boot, mode); +static const sc_acc_addr_t kAccVarBootMsg = ACC_ADDR_T_INIT(boot, msg); +static const sc_acc_addr_t kAccVarBootX = ACC_ADDR_T_INIT(boot, x); +static const sc_acc_addr_t kAccVarBootY = ACC_ADDR_T_INIT(boot, y); +static const sc_acc_addr_t kAccVarBootR = ACC_ADDR_T_INIT(boot, r); +static const sc_acc_addr_t kAccVarBootS = ACC_ADDR_T_INIT(boot, s); +static const sc_acc_addr_t kAccVarBootXr = ACC_ADDR_T_INIT(boot, x_r); +static const sc_acc_addr_t kAccVarBootOk = ACC_ADDR_T_INIT(boot, ok); +static const sc_acc_addr_t kAccVarBootAttestationAdditionalSeed = + ACC_ADDR_T_INIT(boot, attestation_additional_seed); + +enum { + /* + * Mode is represented by a single word. + */ + kAccBootModeWords = 1, + /* + * Mode to run signature verification. + * + * Value taken from `boot.s`. + */ + kAccBootModeSigverify = 0x7d3, + /* + * Mode to generate an attestation keypair. + * + * Value taken from `boot.s`. + */ + kAccBootModeAttestationKeygen = 0x2bf, + /* + * Mode to endorse a message with a saved private key. + * + * Value taken from `boot.s`. + */ + kAccBootModeAttestationEndorse = 0x5e8, + /* + * Mode to save an attesation private key. + * + * Value taken from `boot.s`. + */ + kAccBootModeAttestationKeySave = 0x64d, + /* Size of the ACC attestation seed buffer in 32-bit words (rounding the + attestation seed size up to the next ACC wide word). */ + kAccAttestationSeedBufferWords = + ((kAttestationSeedWords + kScAccWideWordNumWords - 1) / + kScAccWideWordNumWords) * + kScAccWideWordNumWords, +}; + +OT_WARN_UNUSED_RESULT +static rom_error_t load_attestation_keygen_seed(uint32_t additional_seed_idx, + uint32_t *seed) { + // Read seed from flash info page. + uint32_t seed_flash_offset = + 0 + (additional_seed_idx * kAttestationSeedBytes); + rom_error_t err = + flash_ctrl_info_read(&kFlashCtrlInfoPageAttestationKeySeeds, + seed_flash_offset, kAttestationSeedWords, seed); + + if (err != kErrorOk) { + flash_ctrl_error_code_t flash_ctrl_err_code; + flash_ctrl_error_code_get(&flash_ctrl_err_code); + if (flash_ctrl_err_code.rd_err) { + // If we encountered a read error, this means the attestation seed page + // has not been provisioned yet. In this case, we clear the seed and + // continue, which will simply result in generating an invalid identity. + memset(seed, 0, kAttestationSeedBytes); + return kErrorOk; + } + return err; + } + + return kErrorOk; +} + +rom_error_t acc_boot_app_load(void) { return sc_acc_load_app(kAccAppBoot); } + +rom_error_t acc_boot_attestation_keygen( + uint32_t additional_seed_idx, sc_keymgr_key_type_t key_type, + sc_keymgr_diversification_t diversification, + ecdsa_p256_public_key_t *public_key) { + // Trigger key manager to sideload the attestation key into ACC. + HARDENED_RETURN_IF_ERROR( + sc_keymgr_generate_key_acc(key_type, diversification)); + + // Write the mode. + uint32_t mode = kAccBootModeAttestationKeygen; + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kAccBootModeWords, &mode, kAccVarBootMode)); + + // Load the additional seed from flash info. + uint32_t seed[kAttestationSeedWords]; + HARDENED_RETURN_IF_ERROR( + load_attestation_keygen_seed(additional_seed_idx, seed)); + + // Write the additional seed to ACC DMEM. + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_write( + kAttestationSeedWords, seed, kAccVarBootAttestationAdditionalSeed)); + // Pad remaining DMEM field with zeros to prevent a DMEM integrity error + // (since data is aligned to 256-bit words). + uint32_t zero_buf[kAccAttestationSeedBufferWords - kAttestationSeedWords] = { + 0}; + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_write( + ARRAYSIZE(zero_buf), zero_buf, + kAccVarBootAttestationAdditionalSeed + kAttestationSeedBytes)); + + // Run the ACC program (blocks until ACC is done). + HARDENED_RETURN_IF_ERROR(sc_acc_execute()); + SEC_MMIO_WRITE_INCREMENT(kScAccSecMmioExecute); + + // TODO(#20023): Check the instruction count register (see `mod_exp_acc`). + + // Retrieve the public key. + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_read(kEcdsaP256PublicKeyCoordWords, + kAccVarBootX, public_key->x)); + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_read(kEcdsaP256PublicKeyCoordWords, + kAccVarBootY, public_key->y)); + + return kErrorOk; +} + +/** + * Helper function to convert an ECC P256 public key from little to big endian + * in place. + */ +static void pubkey_le_to_be_convert(ecdsa_p256_public_key_t *pubkey) { + util_reverse_bytes(pubkey->x, kEcdsaP256PublicKeyCoordBytes); + util_reverse_bytes(pubkey->y, kEcdsaP256PublicKeyCoordBytes); +} + +rom_error_t acc_boot_cert_ecc_p256_keygen(sc_keymgr_ecc_key_t key, + hmac_digest_t *pubkey_id, + ecdsa_p256_public_key_t *pubkey) { + HARDENED_RETURN_IF_ERROR(sc_keymgr_state_check(key.required_keymgr_state)); + + // Generate / sideload key material into ACC, and generate the ECC keypair. + HARDENED_RETURN_IF_ERROR(acc_boot_attestation_keygen( + key.keygen_seed_idx, key.type, *key.keymgr_diversifier, pubkey)); + + // Keys are represented in certificates in big endian format, but the key is + // output from ACC in little endian format, so we convert the key to + // big endian format. + pubkey_le_to_be_convert(pubkey); + + // Generate the key ID. + // + // Note: the certificate generation functions expect the digest to be in big + // endian form, but the HMAC driver returns the digest in little endian, so we + // re-format it. + hmac_sha256(pubkey, sizeof(*pubkey), pubkey_id); + util_reverse_bytes(pubkey_id, sizeof(*pubkey_id)); + + return kErrorOk; +} + +rom_error_t acc_boot_attestation_key_save( + uint32_t additional_seed_idx, sc_keymgr_key_type_t key_type, + sc_keymgr_diversification_t diversification) { + // Trigger key manager to sideload the attestation key into ACC. + HARDENED_RETURN_IF_ERROR( + sc_keymgr_generate_key_acc(key_type, diversification)); + + // Write the mode. + uint32_t mode = kAccBootModeAttestationKeySave; + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kAccBootModeWords, &mode, kAccVarBootMode)); + + // Load the additional seed from flash info. + uint32_t seed[kAttestationSeedWords]; + HARDENED_RETURN_IF_ERROR( + load_attestation_keygen_seed(additional_seed_idx, seed)); + // Pad remaining DMEM field with zeros to prevent a DMEM integrity error + // (since data is aligned to 256-bit words). + uint32_t zero_buf[kAccAttestationSeedBufferWords - kAttestationSeedWords] = { + 0}; + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_write( + ARRAYSIZE(zero_buf), zero_buf, + kAccVarBootAttestationAdditionalSeed + kAttestationSeedBytes)); + + // Write the additional seed to ACC DMEM. + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_write( + kAttestationSeedWords, seed, kAccVarBootAttestationAdditionalSeed)); + + // Run the ACC program (blocks until ACC is done). + HARDENED_RETURN_IF_ERROR(sc_acc_execute()); + SEC_MMIO_WRITE_INCREMENT(kScAccSecMmioExecute); + + // TODO(#20023): Check the instruction count register (see `mod_exp_acc`). + + return kErrorOk; +} + +rom_error_t acc_boot_attestation_key_clear(void) { + // Trigger a full DMEM wipe. + RETURN_IF_ERROR(sc_acc_dmem_sec_wipe()); + HARDENED_RETURN_IF_ERROR(sc_acc_busy_wait_for_done()); + + // Re-load the data portion of the boot services app. This is like a + // stripped-down version of `sc_acc_load_app`, where we skip the IMEM. + if (kAccAppBoot.dmem_data_end < kAccAppBoot.dmem_data_start) { + return kErrorAccInvalidArgument; + } + HARDENED_CHECK_GE(kAccAppBoot.dmem_data_end, kAccAppBoot.dmem_data_start); + const size_t data_num_words = + (size_t)(kAccAppBoot.dmem_data_end - kAccAppBoot.dmem_data_start); + if (data_num_words > 0) { + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(data_num_words, kAccAppBoot.dmem_data_start, + kAccAppBoot.dmem_data_start_addr)); + } + return kErrorOk; +} + +rom_error_t acc_boot_attestation_endorse(const hmac_digest_t *digest, + ecdsa_p256_signature_t *sig) { + // Write the mode. + uint32_t mode = kAccBootModeAttestationEndorse; + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kAccBootModeWords, &mode, kAccVarBootMode)); + + // Write the message digest. + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kHmacDigestNumWords, digest->digest, kAccVarBootMsg)); + + // Run the ACC program (blocks until ACC is done). + HARDENED_RETURN_IF_ERROR(sc_acc_execute()); + SEC_MMIO_WRITE_INCREMENT(kScAccSecMmioExecute); + + // TODO(#20023): Check the instruction count register (see `mod_exp_acc`). + + // Retrieve the signature (in two parts, r and s). + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_read(kEcdsaP256SignatureComponentWords, + kAccVarBootR, sig->r)); + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_read(kEcdsaP256SignatureComponentWords, + kAccVarBootS, sig->s)); + + return kErrorOk; +} + +rom_error_t acc_boot_sigverify(const ecdsa_p256_public_key_t *key, + const ecdsa_p256_signature_t *sig, + const hmac_digest_t *digest, + uint32_t *recovered_r) { + // Write the mode. + uint32_t mode = kAccBootModeSigverify; + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kAccBootModeWords, &mode, kAccVarBootMode)); + + // Write the public key. + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kEcdsaP256PublicKeyCoordWords, key->x, kAccVarBootX)); + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kEcdsaP256PublicKeyCoordWords, key->y, kAccVarBootY)); + + // Write the message digest. + HARDENED_RETURN_IF_ERROR( + sc_acc_dmem_write(kHmacDigestNumWords, digest->digest, kAccVarBootMsg)); + + // Write the signature. + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_write(kEcdsaP256SignatureComponentWords, + sig->r, kAccVarBootR)); + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_write(kEcdsaP256SignatureComponentWords, + sig->s, kAccVarBootS)); + + // Start the ACC routine. + HARDENED_RETURN_IF_ERROR(sc_acc_execute()); + SEC_MMIO_WRITE_INCREMENT(kScAccSecMmioExecute); + + // Check if the signature passed basic checks. + uint32_t ok; + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_read(1, kAccVarBootOk, &ok)); + if (launder32(ok) != kHardenedBoolTrue) { + return kErrorSigverifyBadEcdsaSignature; + } + + // Read the status value again as an extra hardening measure. + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_read(1, kAccVarBootOk, &ok)); + HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); + + // TODO(#20023): Check the instruction count register (see `mod_exp_acc`). + + // Read the recovered `r` value from DMEM. + return sc_acc_dmem_read(kEcdsaP256SignatureComponentWords, kAccVarBootXr, + recovered_r); +} diff --git a/sw/device/silicon_creator/lib/otbn_boot_services.h b/sw/device/silicon_creator/lib/acc_boot_services.h similarity index 69% rename from sw/device/silicon_creator/lib/otbn_boot_services.h rename to sw/device/silicon_creator/lib/acc_boot_services.h index 9ffa3ab5d1b..9edae1f50fb 100644 --- a/sw/device/silicon_creator/lib/otbn_boot_services.h +++ b/sw/device/silicon_creator/lib/acc_boot_services.h @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_OTBN_BOOT_SERVICES_H_ -#define OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_OTBN_BOOT_SERVICES_H_ +#ifndef OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_ACC_BOOT_SERVICES_H_ +#define OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_ACC_BOOT_SERVICES_H_ #include #include @@ -19,21 +19,21 @@ extern "C" { #endif // __cplusplus /** - * Loads the OTBN boot-services application. + * Loads the ACC boot-services application. * - * Loads the OTBN program that runs attestation and code-signature - * verification. The program can later be cleared by wiping OTBN's IMEM and - * DMEM, or by loading a diffierent OTBN application. + * Loads the ACC program that runs attestation and code-signature + * verification. The program can later be cleared by wiping ACC's IMEM and + * DMEM, or by loading a diffierent ACC application. * * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_app_load(void); +rom_error_t acc_boot_app_load(void); /** * Generate an attestation public key from a keymgr-derived secret. * - * This routine triggers the key manager to sideload key material into OTBN, + * This routine triggers the key manager to sideload key material into ACC, * and also loads in an extra seed to XOR with the key material. The final * private key is: * d = (additional_seed ^ keymgr_seed) mod n @@ -44,8 +44,8 @@ rom_error_t otbn_boot_app_load(void); * is provisioned into flash at manufacturing time. It must be fully independent * from the key manager seed. * - * Expects the OTBN boot-services program to already be loaded; see - * `otbn_boot_app_load`. + * Expects the ACC boot-services program to already be loaded; see + * `acc_boot_app_load`. * * @param additional_seed_idx The attestation key generation seed index to load. * The index corresponds to the seed offset in flash @@ -56,7 +56,7 @@ rom_error_t otbn_boot_app_load(void); * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_attestation_keygen( +rom_error_t acc_boot_attestation_keygen( uint32_t additional_seed_idx, sc_keymgr_key_type_t key_type, sc_keymgr_diversification_t diversification, ecdsa_p256_public_key_t *public_key); @@ -72,7 +72,7 @@ rom_error_t otbn_boot_attestation_keygen( * firmware updates, and change when ROM_EXT or Owner firmware is updated. The * latter remain stable across the lifetime of an ownership of the chip. * - * This routine triggers the key manager to sideload key material into OTBN, + * This routine triggers the key manager to sideload key material into ACC, * and also loads in an extra seed to XOR with the key material. The final * private key is: * d = (additional_seed ^ keymgr_seed) mod n @@ -83,8 +83,8 @@ rom_error_t otbn_boot_attestation_keygen( * is provisioned into flash at manufacturing time. It must be fully independent * from the key manager seed. * - * Expects the OTBN boot-services program to already be loaded; see - * `otbn_boot_app_load`. + * Expects the ACC boot-services program to already be loaded; see + * `acc_boot_app_load`. * * @param additional_seed_idx The attestation key generation seed index to load. * The index corresponds to the seed offset in flash @@ -95,14 +95,14 @@ rom_error_t otbn_boot_attestation_keygen( * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_attestation_keygen( +rom_error_t acc_boot_attestation_keygen( uint32_t additional_seed_idx, sc_keymgr_key_type_t key_type, sc_keymgr_diversification_t diversification, ecdsa_p256_public_key_t *public_key); /** - * Wrapper for `otbn_boot_attestation_keygen()` that generates an ECC P256 - * keypair to build a certificate around, using Keymgr and OTBN, returning the + * Wrapper for `acc_boot_attestation_keygen()` that generates an ECC P256 + * keypair to build a certificate around, using Keymgr and ACC, returning the * public key (in big endian order for inserting into a cert) and a key ID * (which is a SHA256 digest of the public key). * @@ -114,79 +114,79 @@ rom_error_t otbn_boot_attestation_keygen( * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_cert_ecc_p256_keygen(sc_keymgr_ecc_key_t key, - hmac_digest_t *pubkey_id, - ecdsa_p256_public_key_t *pubkey); +rom_error_t acc_boot_cert_ecc_p256_keygen(sc_keymgr_ecc_key_t key, + hmac_digest_t *pubkey_id, + ecdsa_p256_public_key_t *pubkey); /** - * Saves an attestation private key to OTBN's scratchpad. + * Saves an attestation private key to ACC's scratchpad. * - * This routine takes the same arguments as `otbn_boot_attestation_keygen`, but + * This routine takes the same arguments as `acc_boot_attestation_keygen`, but * instead of computing the public key, it computes only the private key and - * saves it to OTBN's scratchpad memory. + * saves it to ACC's scratchpad memory. * - * Expects the OTBN boot-services program to already be loaded; see - * `otbn_boot_app_load`. + * Expects the ACC boot-services program to already be loaded; see + * `acc_boot_app_load`. * * @param additional_seed The attestation key generation seed to load. - * @param key_type OTBN attestation key type to generate. "DICE" attestation + * @param key_type ACC attestation key type to generate. "DICE" attestation * keys are based on "attestation" keys from the keymgr; "TPM" * attestation keys are based on "sealing keys from the keymgr. * @param diversification Salt and version information for key manager. * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_attestation_key_save( +rom_error_t acc_boot_attestation_key_save( uint32_t additional_seed, sc_keymgr_key_type_t key_type, sc_keymgr_diversification_t diversification); /** - * Clears any saved attestation key from OTBN's scratchpad. + * Clears any saved attestation key from ACC's scratchpad. * - * This routine clears OTBN's DMEM. If called after - * `otbn_boot_attestation_key_save`, it will clear the saved key. + * This routine clears ACC's DMEM. If called after + * `acc_boot_attestation_key_save`, it will clear the saved key. * * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_attestation_key_clear(void); +rom_error_t acc_boot_attestation_key_clear(void); /** * Signs the message with the saved attestation key, and clears the key. * - * Must be called when there is a saved attestation key in OTBN's scratchpad; - * use `otbn_boot_attestation_key_save` to store one. + * Must be called when there is a saved attestation key in ACC's scratchpad; + * use `acc_boot_attestation_key_save` to store one. * * The intended purpose of this function is to sign the current stage's * attestation certificate with the private key of the previous stage. The * caller should hash the certificate with SHA-256 before calling this * function. * - * Note that the digest gets interpreted by OTBN in little-endian order. If the + * Note that the digest gets interpreted by ACC in little-endian order. If the * HMAC block has not been set to produce little-endian digests, then the * digest bytes should be reversed before they are passed here. * - * Expects the OTBN boot-services program to already be loaded; see - * `otbn_boot_app_load`. + * Expects the ACC boot-services program to already be loaded; see + * `acc_boot_app_load`. * * @param digest Digest to sign. * @param[out] sig Resulting signature. * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_attestation_endorse(const hmac_digest_t *digest, - ecdsa_p256_signature_t *sig); +rom_error_t acc_boot_attestation_endorse(const hmac_digest_t *digest, + ecdsa_p256_signature_t *sig); /** - * Computes an ECDSA-P256 signature verification on OTBN. + * Computes an ECDSA-P256 signature verification on ACC. * * May be used for code signatures as well as attestation signatures. Returns * the recovered `r` value in `result`. The signature is valid if this `r` * value matches the `r` component of the signature, but the caller is * responsible for the final comparison. * - * Expects the OTBN boot-services program to already be loaded; see - * `otbn_boot_app_load`. + * Expects the ACC boot-services program to already be loaded; see + * `acc_boot_app_load`. * * @param key An ECDSA-P256 public key. * @param sig An ECDSA-P256 signature. @@ -195,13 +195,13 @@ rom_error_t otbn_boot_attestation_endorse(const hmac_digest_t *digest, * @return The result of the operation. */ OT_WARN_UNUSED_RESULT -rom_error_t otbn_boot_sigverify(const ecdsa_p256_public_key_t *key, - const ecdsa_p256_signature_t *sig, - const hmac_digest_t *digest, - uint32_t *recovered_r); +rom_error_t acc_boot_sigverify(const ecdsa_p256_public_key_t *key, + const ecdsa_p256_signature_t *sig, + const hmac_digest_t *digest, + uint32_t *recovered_r); #ifdef __cplusplus } // extern "C" #endif // __cplusplus -#endif // OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_OTBN_BOOT_SERVICES_H_ +#endif // OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_ACC_BOOT_SERVICES_H_ diff --git a/sw/device/silicon_creator/lib/otbn_boot_services_functest.c b/sw/device/silicon_creator/lib/acc_boot_services_functest.c similarity index 73% rename from sw/device/silicon_creator/lib/otbn_boot_services_functest.c rename to sw/device/silicon_creator/lib/acc_boot_services_functest.c index 0161bb543d4..6838bf19d20 100644 --- a/sw/device/silicon_creator/lib/otbn_boot_services_functest.c +++ b/sw/device/silicon_creator/lib/acc_boot_services_functest.c @@ -9,8 +9,8 @@ #include "sw/device/lib/testing/keymgr_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/drivers/hmac.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/manuf/lib/flash_info_fields.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated. @@ -68,7 +68,7 @@ rom_error_t sigverify_test(void) { // `r` value. uint32_t recovered_r[kEcdsaP256SignatureComponentWords]; RETURN_IF_ERROR( - otbn_boot_sigverify(&kEcdsaKey, &kEcdsaSignature, &digest, recovered_r)); + acc_boot_sigverify(&kEcdsaKey, &kEcdsaSignature, &digest, recovered_r)); CHECK_ARRAYS_EQ(recovered_r, kEcdsaSignature.r, ARRAYSIZE(kEcdsaSignature.r)); return kErrorOk; } @@ -76,21 +76,21 @@ rom_error_t sigverify_test(void) { rom_error_t attestation_keygen_test(void) { // Check that key generations with different seeds result in different keys. ecdsa_p256_public_key_t pk_uds; - RETURN_IF_ERROR(otbn_boot_attestation_keygen(kFlashInfoFieldUdsKeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification, &pk_uds)); + RETURN_IF_ERROR(acc_boot_attestation_keygen(kFlashInfoFieldUdsKeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification, &pk_uds)); ecdsa_p256_public_key_t pk_cdi0; - RETURN_IF_ERROR(otbn_boot_attestation_keygen(kFlashInfoFieldCdi0KeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification, &pk_cdi0)); + RETURN_IF_ERROR(acc_boot_attestation_keygen(kFlashInfoFieldCdi0KeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification, &pk_cdi0)); ecdsa_p256_public_key_t pk_cdi1; - RETURN_IF_ERROR(otbn_boot_attestation_keygen(kFlashInfoFieldCdi1KeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification, &pk_cdi1)); + RETURN_IF_ERROR(acc_boot_attestation_keygen(kFlashInfoFieldCdi1KeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification, &pk_cdi1)); ecdsa_p256_public_key_t pk_tpm_ek; - RETURN_IF_ERROR(otbn_boot_attestation_keygen(kFlashInfoFieldTpmEkKeySeedIdx, - kScKeymgrKeyTypeSealing, - kDiversification, &pk_tpm_ek)); + RETURN_IF_ERROR(acc_boot_attestation_keygen(kFlashInfoFieldTpmEkKeySeedIdx, + kScKeymgrKeyTypeSealing, + kDiversification, &pk_tpm_ek)); CHECK_ARRAYS_NE((unsigned char *)&pk_uds, (unsigned char *)&pk_cdi0, sizeof(pk_uds)); CHECK_ARRAYS_NE((unsigned char *)&pk_uds, (unsigned char *)&pk_cdi1, @@ -102,9 +102,9 @@ rom_error_t attestation_keygen_test(void) { // Check that running the same key generation twice results in the same key. ecdsa_p256_public_key_t pk_uds_again; - RETURN_IF_ERROR(otbn_boot_attestation_keygen( - kFlashInfoFieldUdsKeySeedIdx, kScKeymgrKeyTypeAttestation, - kDiversification, &pk_uds_again)); + RETURN_IF_ERROR(acc_boot_attestation_keygen(kFlashInfoFieldUdsKeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification, &pk_uds_again)); CHECK_ARRAYS_EQ((unsigned char *)&pk_uds_again, (unsigned char *)&pk_uds, sizeof(pk_uds)); @@ -115,7 +115,7 @@ rom_error_t attestation_keygen_test(void) { sizeof(diversification_modified)); diversification_modified.salt[0] ^= 1; ecdsa_p256_public_key_t pk_uds_div; - RETURN_IF_ERROR(otbn_boot_attestation_keygen( + RETURN_IF_ERROR(acc_boot_attestation_keygen( kFlashInfoFieldUdsKeySeedIdx, kScKeymgrKeyTypeAttestation, diversification_modified, &pk_uds_div)); CHECK_ARRAYS_NE((unsigned char *)&pk_uds_div, (unsigned char *)&pk_uds, @@ -126,12 +126,12 @@ rom_error_t attestation_keygen_test(void) { rom_error_t attestation_advance_and_endorse_test(void) { // Generate and save the a keypair. ecdsa_p256_public_key_t pk; - RETURN_IF_ERROR(otbn_boot_attestation_keygen(kFlashInfoFieldUdsKeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification, &pk)); - RETURN_IF_ERROR(otbn_boot_attestation_key_save(kFlashInfoFieldUdsKeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification)); + RETURN_IF_ERROR(acc_boot_attestation_keygen(kFlashInfoFieldUdsKeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification, &pk)); + RETURN_IF_ERROR(acc_boot_attestation_key_save(kFlashInfoFieldUdsKeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification)); // Advance keymgr to the next stage. if (num_keymgr_advances == 0) { @@ -152,55 +152,55 @@ rom_error_t attestation_advance_and_endorse_test(void) { hmac_digest_t digest; hmac_sha256(kTestMessage, kTestMessageLen, &digest); ecdsa_p256_signature_t sig; - RETURN_IF_ERROR(otbn_boot_attestation_endorse(&digest, &sig)); + RETURN_IF_ERROR(acc_boot_attestation_endorse(&digest, &sig)); // Check that the signature is valid (recovered r == r). uint32_t recovered_r[kEcdsaP256SignatureComponentWords]; - RETURN_IF_ERROR(otbn_boot_sigverify(&pk, &sig, &digest, recovered_r)); + RETURN_IF_ERROR(acc_boot_sigverify(&pk, &sig, &digest, recovered_r)); CHECK_ARRAYS_EQ(recovered_r, sig.r, ARRAYSIZE(sig.r)); // Run endorsement again (should not return an error, but should produce an // invalid signature). - RETURN_IF_ERROR(otbn_boot_attestation_endorse(&digest, &sig)); + RETURN_IF_ERROR(acc_boot_attestation_endorse(&digest, &sig)); // Check that the signature is invalid (recovered r != r). - RETURN_IF_ERROR(otbn_boot_sigverify(&pk, &sig, &digest, recovered_r)); + RETURN_IF_ERROR(acc_boot_sigverify(&pk, &sig, &digest, recovered_r)); CHECK_ARRAYS_NE(recovered_r, sig.r, ARRAYSIZE(sig.r)); // Check that generating a new key with the same diversification as before // now gets a different public key because keymgr has advanced. ecdsa_p256_public_key_t pk_adv; - RETURN_IF_ERROR(otbn_boot_attestation_keygen(kFlashInfoFieldUdsKeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification, &pk_adv)); + RETURN_IF_ERROR(acc_boot_attestation_keygen(kFlashInfoFieldUdsKeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification, &pk_adv)); CHECK_ARRAYS_NE((unsigned char *)&pk, (unsigned char *)&pk_adv, sizeof(pk)); return kErrorOk; } -// N.B. This test will lock OTBN, so it needs to be the last test that runs. +// N.B. This test will lock ACC, so it needs to be the last test that runs. rom_error_t attestation_save_clear_key_test(void) { // Save and then clear a private key. - RETURN_IF_ERROR(otbn_boot_attestation_key_save(kFlashInfoFieldUdsKeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification)); - RETURN_IF_ERROR(otbn_boot_attestation_key_clear()); + RETURN_IF_ERROR(acc_boot_attestation_key_save(kFlashInfoFieldUdsKeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification)); + RETURN_IF_ERROR(acc_boot_attestation_key_clear()); // Save the private key again and check that endorsing succeeds. - RETURN_IF_ERROR(otbn_boot_attestation_key_save(kFlashInfoFieldUdsKeySeedIdx, - kScKeymgrKeyTypeAttestation, - kDiversification)); + RETURN_IF_ERROR(acc_boot_attestation_key_save(kFlashInfoFieldUdsKeySeedIdx, + kScKeymgrKeyTypeAttestation, + kDiversification)); hmac_digest_t digest; hmac_sha256(kTestMessage, kTestMessageLen, &digest); ecdsa_p256_signature_t sig; - RETURN_IF_ERROR(otbn_boot_attestation_endorse(&digest, &sig)); + RETURN_IF_ERROR(acc_boot_attestation_endorse(&digest, &sig)); // Clear the key and check that endorsing now fails (it should even lock - // OTBN). - RETURN_IF_ERROR(otbn_boot_attestation_key_clear()); + // ACC). + RETURN_IF_ERROR(acc_boot_attestation_key_clear()); hmac_sha256(kTestMessage, kTestMessageLen, &digest); - CHECK(otbn_boot_attestation_endorse(&digest, &sig) == - kErrorOtbnExecutionFailed); + CHECK(acc_boot_attestation_endorse(&digest, &sig) == + kErrorAccExecutionFailed); return kErrorOk; } @@ -246,8 +246,8 @@ bool test_main(void) { kDifFlashCtrlPartitionTypeInfo, kAttestationSeedWords)); } - // Load the boot services OTBN app. - CHECK(otbn_boot_app_load() == kErrorOk); + // Load the boot services ACC app. + CHECK(acc_boot_app_load() == kErrorOk); EXECUTE_TEST(result, sigverify_test); EXECUTE_TEST(result, attestation_keygen_test); diff --git a/sw/device/silicon_creator/lib/cert/BUILD b/sw/device/silicon_creator/lib/cert/BUILD index cf4ebb1e46b..7892ed8d2e7 100644 --- a/sw/device/silicon_creator/lib/cert/BUILD +++ b/sw/device/silicon_creator/lib/cert/BUILD @@ -144,8 +144,8 @@ cc_library( "//sw/device/lib/base:memory", "//sw/device/lib/base:status", "//sw/device/lib/testing/test_framework:check", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib:attestation", - "//sw/device/silicon_creator/lib:otbn_boot_services", "//sw/device/silicon_creator/lib/base:util", "//sw/device/silicon_creator/lib/cert:cdi_0_template_library", "//sw/device/silicon_creator/lib/cert:cdi_1_template_library", @@ -192,8 +192,8 @@ cc_library( "//hw/top:dt", "//hw/top:otp_ctrl_c_regs", "//sw/device/lib/base:status", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib:attestation", - "//sw/device/silicon_creator/lib:otbn_boot_services", "//sw/device/silicon_creator/lib/base:util", "//sw/device/silicon_creator/lib/cert:dice_keys", "//sw/device/silicon_creator/lib/drivers:lifecycle", @@ -238,10 +238,10 @@ cc_library( "//sw/device/lib/base:macros", "//sw/device/lib/base:memory", "//sw/device/lib/crypto/drivers:entropy", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib:dbg_print", "//sw/device/silicon_creator/lib:keymgr_binding", "//sw/device/silicon_creator/lib:manifest", - "//sw/device/silicon_creator/lib:otbn_boot_services", "//sw/device/silicon_creator/lib/base:boot_measurements", "//sw/device/silicon_creator/lib/base:sec_mmio", "//sw/device/silicon_creator/lib/base:static_dice_cdi_0", diff --git a/sw/device/silicon_creator/lib/cert/dice.c b/sw/device/silicon_creator/lib/cert/dice.c index 872523cb452..d6ad8788a3c 100644 --- a/sw/device/silicon_creator/lib/cert/dice.c +++ b/sw/device/silicon_creator/lib/cert/dice.c @@ -8,6 +8,7 @@ #include "sw/device/lib/base/memory.h" #include "sw/device/lib/testing/test_framework/check.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/base/util.h" #include "sw/device/silicon_creator/lib/cert/cdi_0.h" // Generated. #include "sw/device/silicon_creator/lib/cert/cdi_1.h" // Generated. @@ -18,7 +19,6 @@ #include "sw/device/silicon_creator/lib/drivers/hmac.h" #include "sw/device/silicon_creator/lib/drivers/lifecycle.h" #include "sw/device/silicon_creator/lib/error.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/lib/ownership/datatypes.h" #include "sw/device/silicon_creator/lib/sigverify/ecdsa_p256_key.h" #include "sw/device/silicon_creator/manuf/base/perso_tlv_data.h" @@ -124,7 +124,7 @@ rom_error_t dice_cdi_0_cert_build(hmac_digest_t *rom_ext_measurement, hmac_digest_t tbs_digest; hmac_sha256(cdi_0_tbs_buffer, tbs_size, &tbs_digest); HARDENED_RETURN_IF_ERROR( - otbn_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); + acc_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); util_p256_signature_le_to_be_convert(curr_tbs_signature.r, curr_tbs_signature.s); @@ -137,8 +137,8 @@ rom_error_t dice_cdi_0_cert_build(hmac_digest_t *rom_ext_measurement, HARDENED_RETURN_IF_ERROR(cdi_0_build_cert(&cdi_0_params, cert, cert_size)); - // Save the CDI_0 private key to OTBN DMEM so it can endorse the next stage. - HARDENED_RETURN_IF_ERROR(otbn_boot_attestation_key_save( + // Save the CDI_0 private key to ACC DMEM so it can endorse the next stage. + HARDENED_RETURN_IF_ERROR(acc_boot_attestation_key_save( kDiceKeyCdi0.keygen_seed_idx, kDiceKeyCdi0.type, *kDiceKeyCdi0.keymgr_diversifier)); @@ -185,7 +185,7 @@ rom_error_t dice_cdi_1_cert_build(hmac_digest_t *owner_measurement, hmac_digest_t tbs_digest; hmac_sha256(cdi_1_tbs_buffer, tbs_size, &tbs_digest); HARDENED_RETURN_IF_ERROR( - otbn_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); + acc_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); util_p256_signature_le_to_be_convert(curr_tbs_signature.r, curr_tbs_signature.s); @@ -198,8 +198,8 @@ rom_error_t dice_cdi_1_cert_build(hmac_digest_t *owner_measurement, HARDENED_RETURN_IF_ERROR(cdi_1_build_cert(&cdi_1_params, cert, cert_size)); - // Save the CDI_1 private key to OTBN DMEM so it can endorse the next stage. - HARDENED_RETURN_IF_ERROR(otbn_boot_attestation_key_save( + // Save the CDI_1 private key to ACC DMEM so it can endorse the next stage. + HARDENED_RETURN_IF_ERROR(acc_boot_attestation_key_save( kDiceKeyCdi1.keygen_seed_idx, kDiceKeyCdi1.type, *kDiceKeyCdi1.keymgr_diversifier)); diff --git a/sw/device/silicon_creator/lib/cert/dice_chain.c b/sw/device/silicon_creator/lib/cert/dice_chain.c index af56884494a..bf5319b4f73 100644 --- a/sw/device/silicon_creator/lib/cert/dice_chain.c +++ b/sw/device/silicon_creator/lib/cert/dice_chain.c @@ -8,6 +8,7 @@ #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/crypto/drivers/entropy.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/base/boot_measurements.h" #include "sw/device/silicon_creator/lib/base/sec_mmio.h" #include "sw/device/silicon_creator/lib/base/static_dice_cdi_0.h" @@ -18,7 +19,6 @@ #include "sw/device/silicon_creator/lib/drivers/kmac.h" #include "sw/device/silicon_creator/lib/error.h" #include "sw/device/silicon_creator/lib/manifest.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/lib/ownership/datatypes.h" #include "sw/device/silicon_creator/manuf/base/perso_tlv_data.h" @@ -291,12 +291,12 @@ rom_error_t dice_chain_attestation_silicon(void) { // Generate UDS keys. sc_keymgr_advance_state(); HARDENED_RETURN_IF_ERROR(sc_keymgr_state_check(kScKeymgrStateCreatorRootKey)); - HARDENED_RETURN_IF_ERROR(otbn_boot_cert_ecc_p256_keygen( + HARDENED_RETURN_IF_ERROR(acc_boot_cert_ecc_p256_keygen( kDiceKeyUds, &static_dice_cdi_0.uds_pubkey_id, &static_dice_cdi_0.uds_pubkey)); // Save UDS key for signing next stage cert. - RETURN_IF_ERROR(otbn_boot_attestation_key_save( + RETURN_IF_ERROR(acc_boot_attestation_key_save( kDiceKeyUds.keygen_seed_idx, kDiceKeyUds.type, *kDiceKeyUds.keymgr_diversifier)); @@ -315,7 +315,7 @@ rom_error_t dice_chain_attestation_creator( /*sealing_binding=*/&seal_binding_value, /*attest_binding=*/rom_ext_measurement, rom_ext_manifest->max_key_version)); - HARDENED_RETURN_IF_ERROR(otbn_boot_cert_ecc_p256_keygen( + HARDENED_RETURN_IF_ERROR(acc_boot_cert_ecc_p256_keygen( kDiceKeyCdi0, &static_dice_cdi_0.cdi_0_pubkey_id, &static_dice_cdi_0.cdi_0_pubkey)); @@ -337,7 +337,7 @@ rom_error_t dice_chain_attestation_creator( &static_dice_cdi_0.cert_size)); } else { // Replace UDS with CDI_0 key for endorsing next stage cert. - HARDENED_RETURN_IF_ERROR(otbn_boot_attestation_key_save( + HARDENED_RETURN_IF_ERROR(acc_boot_attestation_key_save( kDiceKeyCdi0.keygen_seed_idx, kDiceKeyCdi0.type, *kDiceKeyCdi0.keymgr_diversifier)); } @@ -431,7 +431,7 @@ rom_error_t dice_chain_attestation_owner( /*sealing_binding=*/sealing_binding, /*attest_binding=*/(keymgr_binding_value_t *)&attest_measurement, owner_manifest->max_key_version)); - HARDENED_RETURN_IF_ERROR(otbn_boot_cert_ecc_p256_keygen( + HARDENED_RETURN_IF_ERROR(acc_boot_cert_ecc_p256_keygen( kDiceKeyCdi1, &dice_chain.subject_pubkey_id, &dice_chain.subject_pubkey)); // Check if the current CDI_1 cert is valid. @@ -453,7 +453,7 @@ rom_error_t dice_chain_attestation_owner( dice_chain_next_cert_obj(); // Replace CDI_0 with CDI_1 key for endorsing next stage cert. - HARDENED_RETURN_IF_ERROR(otbn_boot_attestation_key_save( + HARDENED_RETURN_IF_ERROR(acc_boot_attestation_key_save( kDiceKeyCdi1.keygen_seed_idx, kDiceKeyCdi1.type, *kDiceKeyCdi1.keymgr_diversifier)); } diff --git a/sw/device/silicon_creator/lib/cert/dice_cwt.c b/sw/device/silicon_creator/lib/cert/dice_cwt.c index 78ebd2bb9ca..0c048b94cfa 100644 --- a/sw/device/silicon_creator/lib/cert/dice_cwt.c +++ b/sw/device/silicon_creator/lib/cert/dice_cwt.c @@ -6,6 +6,7 @@ #include "include/dice/cbor_reader.h" #include "sw/device/lib/base/memory.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/base/util.h" #include "sw/device/silicon_creator/lib/cert/cbor.h" #include "sw/device/silicon_creator/lib/cert/cert.h" @@ -19,7 +20,6 @@ #include "sw/device/silicon_creator/lib/drivers/lifecycle.h" #include "sw/device/silicon_creator/lib/drivers/otp.h" #include "sw/device/silicon_creator/lib/error.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/lib/ownership/datatypes.h" #include "sw/device/silicon_creator/lib/sigverify/ecdsa_p256_key.h" #include "sw/device/silicon_creator/manuf/base/perso_tlv_data.h" @@ -240,7 +240,7 @@ rom_error_t dice_cdi_0_cert_build(hmac_digest_t *rom_ext_measurement, hmac_digest_t tbs_digest; hmac_sha256(cert, cdi0_entry_input_size, &tbs_digest); HARDENED_RETURN_IF_ERROR( - otbn_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); + acc_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); util_p256_signature_le_to_be_convert(curr_tbs_signature.r, curr_tbs_signature.s); @@ -253,8 +253,8 @@ rom_error_t dice_cdi_0_cert_build(hmac_digest_t *rom_ext_measurement, HARDENED_RETURN_IF_ERROR(cwt_dice_chain_entry_build( &cwt_dice_chain_entry_params, cert, cert_size)); - // Save the CDI_0 private key to OTBN DMEM so it can endorse the next stage. - HARDENED_RETURN_IF_ERROR(otbn_boot_attestation_key_save( + // Save the CDI_0 private key to ACC DMEM so it can endorse the next stage. + HARDENED_RETURN_IF_ERROR(acc_boot_attestation_key_save( kDiceKeyCdi0.keygen_seed_idx, kDiceKeyCdi0.type, *kDiceKeyCdi0.keymgr_diversifier)); return kErrorOk; @@ -338,7 +338,7 @@ rom_error_t dice_cdi_1_cert_build(hmac_digest_t *owner_measurement, hmac_digest_t tbs_digest; hmac_sha256(cert, cdi1_entry_input_size, &tbs_digest); HARDENED_RETURN_IF_ERROR( - otbn_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); + acc_boot_attestation_endorse(&tbs_digest, &curr_tbs_signature)); util_p256_signature_le_to_be_convert(curr_tbs_signature.r, curr_tbs_signature.s); @@ -351,8 +351,8 @@ rom_error_t dice_cdi_1_cert_build(hmac_digest_t *owner_measurement, HARDENED_RETURN_IF_ERROR(cwt_dice_chain_entry_build( &cwt_dice_chain_entry_params, cert, cert_size)); - // Save the CDI_1 private key to OTBN DMEM so it can endorse the next stage. - HARDENED_RETURN_IF_ERROR(otbn_boot_attestation_key_save( + // Save the CDI_1 private key to ACC DMEM so it can endorse the next stage. + HARDENED_RETURN_IF_ERROR(acc_boot_attestation_key_save( kDiceKeyCdi1.keygen_seed_idx, kDiceKeyCdi1.type, *kDiceKeyCdi1.keymgr_diversifier)); diff --git a/sw/device/silicon_creator/lib/drivers/BUILD b/sw/device/silicon_creator/lib/drivers/BUILD index 6078515475a..68dee4b74ce 100644 --- a/sw/device/silicon_creator/lib/drivers/BUILD +++ b/sw/device/silicon_creator/lib/drivers/BUILD @@ -433,12 +433,12 @@ cc_test( ) cc_library( - name = "otbn", - srcs = ["otbn.c"], - hdrs = ["otbn.h"], + name = "acc", + srcs = ["acc.c"], + hdrs = ["acc.h"], deps = [ + "//hw/top:acc_c_regs", "//hw/top:dt", - "//hw/top:otbn_c_regs", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:bitfield", "//sw/device/silicon_creator/lib:error", @@ -448,10 +448,10 @@ cc_library( ) cc_test( - name = "otbn_unittest", - srcs = ["otbn_unittest.cc"], + name = "acc_unittest", + srcs = ["acc_unittest.cc"], deps = [ - ":otbn", + ":acc", "//sw/device/silicon_creator/testing:rom_test", "@googletest//:gtest_main", ], diff --git a/sw/device/silicon_creator/lib/drivers/acc.c b/sw/device/silicon_creator/lib/drivers/acc.c new file mode 100644 index 00000000000..d8cb791ca75 --- /dev/null +++ b/sw/device/silicon_creator/lib/drivers/acc.c @@ -0,0 +1,250 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/silicon_creator/lib/drivers/acc.h" + +#include +#include +#include + +#include "hw/top/dt/dt_acc.h" +#include "sw/device/lib/base/abs_mmio.h" +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/silicon_creator/lib/base/sec_mmio.h" +#include "sw/device/silicon_creator/lib/drivers/rnd.h" +#include "sw/device/silicon_creator/lib/error.h" + +#include "hw/top/acc_regs.h" // Generated. + +static inline uint32_t acc_base(void) { + return dt_acc_primary_reg_block(kDtAcc); +} + +enum { + /** + * Highest index of ACC error bits. + */ + kAccErrBitsLast = ACC_ERR_BITS_FATAL_SOFTWARE_BIT, +}; + +/** + * Ensures that `offset_bytes` and `len` are valid for a given `mem_size`. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t check_offset_len(uint32_t offset_bytes, size_t num_words, + size_t mem_size) { + if (num_words > UINT32_MAX / sizeof(uint32_t)) { + return kErrorAccBadOffsetLen; + } + uint32_t num_bytes = num_words * sizeof(uint32_t); + + if (offset_bytes > UINT32_MAX - num_bytes) { + return kErrorAccBadOffsetLen; + } + uint32_t adjusted_offset_bytes = offset_bytes + num_bytes; + + if (adjusted_offset_bytes > mem_size) { + return kErrorAccBadOffsetLen; + } + + return kErrorOk; +} + +rom_error_t sc_acc_busy_wait_for_done(void) { + uint32_t status = launder32(UINT32_MAX); + rom_error_t res = launder32(kErrorOk ^ status); + do { + status = abs_mmio_read32(acc_base() + ACC_STATUS_REG_OFFSET); + } while (launder32(status) != kScAccStatusIdle && + launder32(status) != kScAccStatusLocked); + res ^= ~status; + if (launder32(res) == kErrorOk) { + HARDENED_CHECK_EQ(res, kErrorOk); + HARDENED_CHECK_EQ(abs_mmio_read32(acc_base() + ACC_STATUS_REG_OFFSET), + kScAccStatusIdle); + return res; + } + return kErrorAccUnavailable; +} + +/** + * Helper function for writing to ACC's DMEM or IMEM. + * + * @param dest_addr Destination address. + * @param src Source buffer. + * @param num_words Number of words to copy. + */ +static void sc_acc_write(uint32_t dest_addr, const uint32_t *src, + size_t num_words) { + // Start from a random index less than `num_words`. + uint32_t i = ((uint64_t)rnd_uint32() * (uint64_t)num_words) >> 32; + enum { kStep = 1 }; + uint32_t iter_cnt = 0, r_iter_cnt = num_words - 1; + for (; launder32(iter_cnt) < num_words && launder32(r_iter_cnt) < num_words; + ++iter_cnt, --r_iter_cnt) { + abs_mmio_write32(dest_addr + i * sizeof(uint32_t), src[i]); + i += kStep; + if (launder32(i) >= num_words) { + i -= num_words; + } + HARDENED_CHECK_LT(i, num_words); + } + HARDENED_CHECK_EQ(iter_cnt, num_words); + HARDENED_CHECK_EQ(r_iter_cnt, UINT32_MAX); +} + +OT_WARN_UNUSED_RESULT +static rom_error_t sc_acc_imem_write(size_t num_words, const uint32_t *src, + sc_acc_addr_t dest) { + HARDENED_RETURN_IF_ERROR( + check_offset_len(dest, num_words, ACC_IMEM_SIZE_BYTES)); + sc_acc_write(acc_base() + ACC_IMEM_REG_OFFSET + dest, src, num_words); + return kErrorOk; +} + +rom_error_t sc_acc_dmem_write(size_t num_words, const uint32_t *src, + sc_acc_addr_t dest) { + HARDENED_RETURN_IF_ERROR( + check_offset_len(dest, num_words, ACC_DMEM_SIZE_BYTES)); + sc_acc_write(acc_base() + ACC_DMEM_REG_OFFSET + dest, src, num_words); + return kErrorOk; +} + +rom_error_t sc_acc_dmem_read(size_t num_words, sc_acc_addr_t src, + uint32_t *dest) { + HARDENED_RETURN_IF_ERROR( + check_offset_len(src, num_words, ACC_DMEM_SIZE_BYTES)); + uint32_t i = 0, r = num_words - 1; + for (; launder32(i) < num_words && launder32(r) < num_words; ++i, --r) { + dest[i] = abs_mmio_read32(acc_base() + ACC_DMEM_REG_OFFSET + src + + i * sizeof(uint32_t)); + } + HARDENED_CHECK_EQ(i, num_words); + HARDENED_CHECK_EQ(r, UINT32_MAX); + return kErrorOk; +} + +/** + * Helper function for running an ACC command. + * + * This function blocks until ACC is idle. + * + * @param cmd ACC command. + * @param error Error to return if operation fails. + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t sc_acc_cmd_run(sc_acc_cmd_t cmd, rom_error_t error) { + enum { + kIntrStateDone = (1 << ACC_INTR_COMMON_DONE_BIT), + // Use a bit index that doesn't overlap with error bits. + kResDoneBit = 31, + }; + static_assert((UINT32_C(1) << kResDoneBit) > kAccErrBitsLast, + "kResDoneBit must not overlap with ACC error bits"); + + abs_mmio_write32(acc_base() + ACC_INTR_STATE_REG_OFFSET, kIntrStateDone); + abs_mmio_write32(acc_base() + ACC_CMD_REG_OFFSET, cmd); + + rom_error_t res = kErrorOk ^ (UINT32_C(1) << kResDoneBit); + uint32_t reg = 0; + do { + reg = abs_mmio_read32(acc_base() + ACC_INTR_STATE_REG_OFFSET); + res ^= (uint32_t)bitfield_bit32_read(reg, ACC_INTR_COMMON_DONE_BIT) + << kResDoneBit; + } while (launder32(reg) != kIntrStateDone); + HARDENED_CHECK_EQ(reg, kIntrStateDone); + abs_mmio_write32(acc_base() + ACC_INTR_STATE_REG_OFFSET, kIntrStateDone); + + // Error bits register should be 0 (no errors). + uint32_t err_bits = abs_mmio_read32(acc_base() + ACC_ERR_BITS_REG_OFFSET); + res ^= err_bits; + + // Status should be kScAccStatusIdle; ACC can also issue a done interrupt + // when transitioning to the "locked" state, so it is important to check + // the status here. + uint32_t status = abs_mmio_read32(acc_base() + ACC_STATUS_REG_OFFSET); + + if (launder32(res) == kErrorOk && launder32(err_bits) == 0 && + launder32(status) == kScAccStatusIdle) { + HARDENED_CHECK_EQ(res, kErrorOk); + HARDENED_CHECK_EQ(err_bits, 0); + HARDENED_CHECK_EQ(abs_mmio_read32(acc_base() + ACC_STATUS_REG_OFFSET), + kScAccStatusIdle); + return res; + } + return error; +} + +rom_error_t sc_acc_execute(void) { + // If ACC is busy, wait for it to be done. + HARDENED_RETURN_IF_ERROR(sc_acc_busy_wait_for_done()); + + // Set software errors to fatal before running the program. Note: the CTRL + // register has only this one setting, so we have no need to read the + // previous value. + sec_mmio_write32(acc_base() + ACC_CTRL_REG_OFFSET, + 1 << ACC_CTRL_SOFTWARE_ERRS_FATAL_BIT); + + return sc_acc_cmd_run(kScAccCmdExecute, kErrorAccExecutionFailed); +} + +uint32_t sc_acc_instruction_count_get(void) { + return abs_mmio_read32(acc_base() + ACC_INSN_CNT_REG_OFFSET); +} + +rom_error_t sc_acc_imem_sec_wipe(void) { + return sc_acc_cmd_run(kScAccCmdSecWipeImem, kErrorAccSecWipeImemFailed); +} + +rom_error_t sc_acc_dmem_sec_wipe(void) { + return sc_acc_cmd_run(kScAccCmdSecWipeDmem, kErrorAccSecWipeDmemFailed); +} + +/** + * Checks if the ACC application's IMEM and DMEM address parameters are valid. + * + * IMEM and DMEM ranges must not be "backwards" in memory, with the end address + * coming before the start address, and the IMEM range must additionally be + * non-empty. + * + * @param app the ACC application to check + * @return OK if the addresses are valid, otherwise `kErrorAccInvalidArgument`. + */ +OT_WARN_UNUSED_RESULT +static rom_error_t check_app_address_ranges(const sc_acc_app_t app) { + if (app.imem_end > app.imem_start && + app.dmem_data_end >= app.dmem_data_start) { + HARDENED_CHECK_GT(app.imem_end, app.imem_start); + HARDENED_CHECK_GE(app.dmem_data_end, app.dmem_data_start); + return kErrorOk; + } + return kErrorAccInvalidArgument; +} + +rom_error_t sc_acc_load_app(const sc_acc_app_t app) { + HARDENED_RETURN_IF_ERROR(check_app_address_ranges(app)); + + // If ACC is busy, wait for it to be done. + HARDENED_RETURN_IF_ERROR(sc_acc_busy_wait_for_done()); + + // Wipe memories. + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_sec_wipe()); + HARDENED_RETURN_IF_ERROR(sc_acc_imem_sec_wipe()); + + const size_t imem_num_words = (size_t)(app.imem_end - app.imem_start); + const size_t data_num_words = + (size_t)(app.dmem_data_end - app.dmem_data_start); + + // IMEM always starts at 0. + sc_acc_addr_t imem_start_addr = 0; + HARDENED_RETURN_IF_ERROR( + sc_acc_imem_write(imem_num_words, app.imem_start, imem_start_addr)); + + if (data_num_words > 0) { + HARDENED_RETURN_IF_ERROR(sc_acc_dmem_write( + data_num_words, app.dmem_data_start, app.dmem_data_start_addr)); + } + return kErrorOk; +} diff --git a/sw/device/silicon_creator/lib/drivers/acc.h b/sw/device/silicon_creator/lib/drivers/acc.h new file mode 100644 index 00000000000..56f0deee537 --- /dev/null +++ b/sw/device/silicon_creator/lib/drivers/acc.h @@ -0,0 +1,310 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_ACC_H_ +#define OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_ACC_H_ + +#include +#include +#include + +#include "sw/device/silicon_creator/lib/error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Constants related to ACC wide words + */ +enum { + /* Length of an ACC wide word in bits */ + kScAccWideWordNumBits = 256, + /* Length of an ACC wide word in words */ + kScAccWideWordNumWords = kScAccWideWordNumBits / (sizeof(uint32_t) * 8), +}; + +/** + * The following constants represent the expected number of sec_mmio register + * writes performed by functions in provided in this module. See + * `SEC_MMIO_WRITE_INCREMENT()` for more details. + * + * Example: + * ``` + * sc_acc_execute(); + * SEC_MMIO_WRITE_INCREMENT(kScAccSecMmioExecute); + * ``` + */ +enum { + kScAccSecMmioExecute = 1, +}; + +/** + * ACC commands + * + * TODO(#16754): replace these with constants from acc_regs.h + */ +typedef enum sc_acc_cmd { + kScAccCmdExecute = 0xd8, + kScAccCmdSecWipeDmem = 0xc3, + kScAccCmdSecWipeImem = 0x1e, +} sc_acc_cmd_t; + +/** + * ACC status + * + * TODO(#16754): replace these with constants from acc_regs.h + */ +typedef enum sc_acc_status { + kScAccStatusIdle = 0x00, + kScAccStatusBusyExecute = 0x01, + kScAccStatusBusySecWipeDmem = 0x02, + kScAccStatusBusySecWipeImem = 0x03, + kScAccStatusBusySecWipeInt = 0x04, + kScAccStatusLocked = 0xFF, +} sc_acc_status_t; + +/** + * The address of an ACC symbol as seen by ACC + * + * Use `ACC_DECLARE_SYMBOL_ADDR()` together with `ACC_ADDR_T_INIT()` to + * initialize this type. + */ +typedef uint32_t sc_acc_addr_t; + +/** + * Information about an embedded ACC application image. + * + * All pointers reference data in the normal CPU address space. + * uint32_t values are addresses in the ACC address space. + * + * Use `ACC_DECLARE_APP_SYMBOLS()` together with `ACC_APP_T_INIT()` to + * initialize this structure. + */ +typedef struct sc_acc_app { + /** + * Start of ACC instruction memory. + */ + const uint32_t *imem_start; + /** + * The first word after ACC instruction memory. + * + * This address satifies `imem_len = imem_end - imem_start`. + */ + const uint32_t *imem_end; + /** + * Start of initialized ACC data. + * + * Data in between dmem_data_start and dmem_data_end will be copied to ACC + * at app load time. + */ + const uint32_t *dmem_data_start; + /** + * The first word after initialized ACC data. + * + * Should satisfy `dmem_data_start <= dmem_data_end`. + */ + const uint32_t *dmem_data_end; + /** + * Start of initialized data section in ACC's DMEM. + * + * This pointer references ACC's memory and is used to copy data at app load + * time. + */ + const sc_acc_addr_t dmem_data_start_addr; +} sc_acc_app_t; + +/** + * Generate the prefix to add to an ACC symbol name used on the Ibex side + * + * The result is a pointer to Ibex's rodata that should be used to initialise + * memory for that symbol. + * + * This is needed by the ACC driver to support DMEM/IMEM ranges but + * application code shouldn't need to use this. Use the `sc_acc_addr_t` type + * and supporting macros instead. + */ +#define ACC_SYMBOL_PTR(app_name, sym) _acc_local_app_##app_name##_##sym + +/** + * Generate the prefix to add to an ACC symbol name used on the ACC side + * + * The result is a pointer whose integer value is the address by which the + * symbol should be accessed in ACC memory. + * + * This is an internal macro used in `ACC_DECLARE_SYMBOL_ADDR` and + * `ACC_ADDR_T_INIT` but application code shouldn't need to use it directly. + */ +#define ACC_SYMBOL_ADDR(app_name, sym) _acc_remote_app_##app_name##_##sym + +/** + * Makes a symbol in the ACC application image available. + * + * This is needed by the ACC driver to support DMEM/IMEM ranges but + * application code shouldn't need to use this. To get access to ACC + * addresses, use `ACC_DECLARE_SYMBOL_ADDR` instead. + */ +#define ACC_DECLARE_SYMBOL_PTR(app_name, symbol_name) \ + extern const uint32_t ACC_SYMBOL_PTR(app_name, symbol_name)[] + +/** + * Makes the ACC address of a symbol in the ACC application available. + * + * Symbols are typically function or data pointers, i.e. labels in assembly + * code. Unlike ACC_DECLARE_SYMBOL_PTR, this will work for symbols in the .bss + * section (which exist on the ACC side, even though they don't have backing + * data on Ibex). + * + * Use this macro instead of manually declaring the symbols as symbol names + * might change. + * + * @param app_name Name of the application the function is contained in. + * @param symbol_name Name of the symbol (function, label). + */ +#define ACC_DECLARE_SYMBOL_ADDR(app_name, symbol_name) \ + extern const uint32_t ACC_SYMBOL_ADDR(app_name, symbol_name)[] + +/** + * Makes an embedded ACC application image available for use. + * + * Make symbols available that indicate the start and the end of instruction + * and data memory regions, as they are stored in the device memory. + * + * Use this macro instead of manually declaring the symbols as symbol names + * might change. + * + * @param app_name Name of the application to load, which is typically the + * name of the main (assembly) source file. + */ +#define ACC_DECLARE_APP_SYMBOLS(app_name) \ + ACC_DECLARE_SYMBOL_PTR(app_name, _imem_start); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _imem_end); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _dmem_data_start); \ + ACC_DECLARE_SYMBOL_PTR(app_name, _dmem_data_end); \ + ACC_DECLARE_SYMBOL_ADDR(app_name, _dmem_data_start); + +/** + * Initializes the ACC application information structure. + * + * After making all required symbols from the application image available + * through `ACC_DECLARE_APP_SYMBOLS()`, use this macro to initialize an + * `sc_acc_app_t` struct with those symbols. + * + * @param app_name Name of the application to load. + * @see ACC_DECLARE_APP_SYMBOLS() + */ +#define ACC_APP_T_INIT(app_name) \ + ((sc_acc_app_t){ \ + .imem_start = ACC_SYMBOL_PTR(app_name, _imem_start), \ + .imem_end = ACC_SYMBOL_PTR(app_name, _imem_end), \ + .dmem_data_start = ACC_SYMBOL_PTR(app_name, _dmem_data_start), \ + .dmem_data_end = ACC_SYMBOL_PTR(app_name, _dmem_data_end), \ + .dmem_data_start_addr = ACC_ADDR_T_INIT(app_name, _dmem_data_start), \ + }) + +/** + * Initializes an `sc_acc_addr_t`. + */ +#define ACC_ADDR_T_INIT(app_name, symbol_name) \ + ((uint32_t)ACC_SYMBOL_ADDR(app_name, symbol_name)) + +/** + * (Re-)loads an application into ACC. + * + * Load the application image with both instruction and data segments into + * ACC. + * + * @param app The application to load into ACC. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t sc_acc_load_app(const sc_acc_app_t app); + +/** + * Copies data from the CPU memory to ACC data memory. + * + * @param num_words Number of 32b words to copy. + * @param dest Address of the destination in ACC's data memory. + * @param src Source of the data to copy. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t sc_acc_dmem_write(size_t num_words, const uint32_t *src, + sc_acc_addr_t dest); + +/** + * Copies data from ACC's data memory to CPU memory. + * + * @param num_words The number of 32b words to copy. + * @param src The address in ACC data memory to copy from. + * @param[out] dest The destination of the copied data in main memory + * (preallocated). + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t sc_acc_dmem_read(size_t num_words, const sc_acc_addr_t src, + uint32_t *dest); + +/** + * Start the execution of the application loaded into ACC. + * + * This function blocks until ACC is idle. + * + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t sc_acc_execute(void); + +/** + * Blocks until ACC is idle. + * + * If ACC is or becomes locked, an error will occur. + * + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t sc_acc_busy_wait_for_done(void); + +/** + * Read ACC's instruction count register. + * + * ACC automatically calculates how many instructions are executed in a given + * program and writes the result to this register. Software can read it to + * verify that instructions were not unexpectedly skipped or added (for + * instance, due to fault injection attacks). + * + * Note that the ACC hardware resets the instruction count register to 0 when + * the EXECUTE command is issued, so there is no need for software to reset the + * counter between programs. + * + * @return count the value from the instruction count register + */ +OT_WARN_UNUSED_RESULT +uint32_t sc_acc_instruction_count_get(void); + +/** + * Wipe IMEM securely. + * + * This function blocks until ACC is idle. + * + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t sc_acc_imem_sec_wipe(void); + +/** + * Wipe DMEM securely. + * + * This function blocks until ACC is idle. + * + * @return Result of the operation. + */ +OT_WARN_UNUSED_RESULT +rom_error_t sc_acc_dmem_sec_wipe(void); + +#ifdef __cplusplus +} +#endif + +#endif // OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_ACC_H_ diff --git a/sw/device/silicon_creator/lib/drivers/acc_unittest.cc b/sw/device/silicon_creator/lib/drivers/acc_unittest.cc new file mode 100644 index 00000000000..baf99931226 --- /dev/null +++ b/sw/device/silicon_creator/lib/drivers/acc_unittest.cc @@ -0,0 +1,392 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/silicon_creator/lib/drivers/acc.h" + +#include +#include + +#include "gtest/gtest.h" +#include "sw/device/lib/base/mock_abs_mmio.h" +#include "sw/device/silicon_creator/lib/base/mock_sec_mmio.h" +#include "sw/device/silicon_creator/lib/drivers/mock_rnd.h" +#include "sw/device/silicon_creator/testing/rom_test.h" + +#include "hw/top/acc_regs.h" // Generated. +#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" + +namespace acc_unittest { +namespace { +using ::testing::ElementsAre; +using ::testing::Return; + +class AccTest : public rom_test::RomTest { + protected: + /** + * Sets expectations for running an ACC command. + * + * @param cmd Command expected to be run. + * @param err_bits Error bits to be returned. + * @param status Status of ACC to be returned after the command is done. + */ + void ExpectCmdRun(sc_acc_cmd_t cmd, uint32_t err_bits, + sc_acc_status_t status) { + EXPECT_ABS_WRITE32(base_ + ACC_INTR_STATE_REG_OFFSET, + { + {ACC_INTR_COMMON_DONE_BIT, 1}, + }); + EXPECT_ABS_WRITE32(base_ + ACC_CMD_REG_OFFSET, cmd); + + EXPECT_ABS_READ32(base_ + ACC_INTR_STATE_REG_OFFSET, 0); + EXPECT_ABS_READ32(base_ + ACC_INTR_STATE_REG_OFFSET, + { + {ACC_INTR_COMMON_DONE_BIT, 1}, + }); + EXPECT_ABS_WRITE32(base_ + ACC_INTR_STATE_REG_OFFSET, + { + {ACC_INTR_COMMON_DONE_BIT, 1}, + }); + + EXPECT_ABS_READ32(base_ + ACC_ERR_BITS_REG_OFFSET, err_bits); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, status); + + if (err_bits == err_bits_ok_ && status == kScAccStatusIdle) { + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, status); + } + } + + uint32_t base_ = TOP_EARLGREY_ACC_BASE_ADDR; + uint32_t err_bits_ok_ = 0; + rom_test::MockAbsMmio abs_mmio_; + rom_test::MockRnd rnd_; + rom_test::MockSecMmio sec_mmio_; +}; + +class ExecuteTest : public AccTest {}; + +TEST_F(ExecuteTest, ExecuteSuccess) { + // Test assumption. + static_assert(ACC_IMEM_SIZE_BYTES >= 8, "ACC IMEM size too small."); + + // Read twice for hardening. + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + + EXPECT_SEC_WRITE32(base_ + ACC_CTRL_REG_OFFSET, 0x1); + + ExpectCmdRun(kScAccCmdExecute, err_bits_ok_, kScAccStatusIdle); + + EXPECT_EQ(sc_acc_execute(), kErrorOk); +} + +TEST_F(ExecuteTest, ExecuteError) { + // Read twice for hardening. + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + + EXPECT_SEC_WRITE32(base_ + ACC_CTRL_REG_OFFSET, 0x1); + + // Nonzero error bits. + ExpectCmdRun(kScAccCmdExecute, 1 << ACC_ERR_BITS_FATAL_SOFTWARE_BIT, + kScAccStatusIdle); + + EXPECT_EQ(sc_acc_execute(), kErrorAccExecutionFailed); +} + +TEST_F(ExecuteTest, ExecuteBusy) { + // Read twice for hardening. + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + + EXPECT_SEC_WRITE32(base_ + ACC_CTRL_REG_OFFSET, 0x01); + + // Return a busy status after the `done` interrupt. + ExpectCmdRun(kScAccCmdExecute, err_bits_ok_, kScAccStatusBusyExecute); + + EXPECT_EQ(sc_acc_execute(), kErrorAccExecutionFailed); +} + +TEST_F(ExecuteTest, ExecuteBlockUntilIdle) { + // Test assumption. + static_assert(ACC_IMEM_SIZE_BYTES >= 8, "ACC IMEM size too small."); + + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusySecWipeDmem); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusySecWipeDmem); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusySecWipeDmem); + + // Read twice for hardening. + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + + EXPECT_SEC_WRITE32(base_ + ACC_CTRL_REG_OFFSET, 0x1); + + ExpectCmdRun(kScAccCmdExecute, err_bits_ok_, kScAccStatusIdle); + + EXPECT_EQ(sc_acc_execute(), kErrorOk); +} + +class IsBusyTest : public AccTest {}; + +TEST_F(IsBusyTest, Success) { + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusyExecute); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusyExecute); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusyExecute); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusyExecute); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + + EXPECT_EQ(sc_acc_busy_wait_for_done(), kErrorOk); +} + +class ImemSecWipeTest : public AccTest {}; + +TEST_F(ImemSecWipeTest, Success) { + ExpectCmdRun(kScAccCmdSecWipeImem, err_bits_ok_, kScAccStatusIdle); + + EXPECT_EQ(sc_acc_imem_sec_wipe(), kErrorOk); +} + +TEST_F(ImemSecWipeTest, Failure) { + ExpectCmdRun(kScAccCmdSecWipeImem, 1 << ACC_ERR_BITS_FATAL_SOFTWARE_BIT, + kScAccStatusIdle); + + EXPECT_EQ(sc_acc_imem_sec_wipe(), kErrorAccSecWipeImemFailed); +} + +class DmemSecWipeTest : public AccTest {}; + +TEST_F(DmemSecWipeTest, Success) { + ExpectCmdRun(kScAccCmdSecWipeDmem, err_bits_ok_, kScAccStatusIdle); + + EXPECT_EQ(sc_acc_dmem_sec_wipe(), kErrorOk); +} + +TEST_F(DmemSecWipeTest, Failure) { + ExpectCmdRun(kScAccCmdSecWipeDmem, 1 << ACC_ERR_BITS_FATAL_SOFTWARE_BIT, + kScAccStatusIdle); + + EXPECT_EQ(sc_acc_dmem_sec_wipe(), kErrorAccSecWipeDmemFailed); +} + +class DmemWriteTest : public AccTest {}; + +TEST_F(DmemWriteTest, SuccessWithoutOffset) { + // Test assumption. + static_assert(ACC_DMEM_SIZE_BYTES >= 8, "ACC DMEM size too small."); + + std::array test_data = {0x12345678, 0xabcdef01}; + sc_acc_addr_t dest_addr = 0; + + EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); + EXPECT_ABS_WRITE32(base_ + ACC_DMEM_REG_OFFSET + dest_addr, test_data[0]); + EXPECT_ABS_WRITE32(base_ + ACC_DMEM_REG_OFFSET + dest_addr + 4, test_data[1]); + + EXPECT_EQ(sc_acc_dmem_write(2, test_data.data(), dest_addr), kErrorOk); +} + +TEST_F(DmemWriteTest, SuccessWithOffset) { + // Test assumption. + static_assert(ACC_DMEM_SIZE_BYTES >= 12, "ACC DMEM size too small."); + + std::array test_data = {0x12345678, 0xabcdef01}; + sc_acc_addr_t dest_addr = 4; + + EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); + EXPECT_ABS_WRITE32(base_ + ACC_DMEM_REG_OFFSET + dest_addr, test_data[0]); + EXPECT_ABS_WRITE32(base_ + ACC_DMEM_REG_OFFSET + dest_addr + 4, test_data[1]); + + EXPECT_EQ(sc_acc_dmem_write(2, test_data.data(), dest_addr), kErrorOk); +} + +TEST_F(DmemWriteTest, FailureOutOfRange) { + std::array test_data = {0x12345678, 0xabcdef01}; + sc_acc_addr_t dest_addr = ACC_DMEM_SIZE_BYTES; + + EXPECT_EQ(sc_acc_dmem_write(2, test_data.data(), dest_addr), + kErrorAccBadOffsetLen); +} + +TEST_F(DmemWriteTest, FailureOverflowNumWords) { + // Try to trigger an integer overflow with `num_words`. + size_t num_words = + (std::numeric_limits::max() / sizeof(uint32_t)) + 1; + sc_acc_addr_t dest_addr = 0; + + EXPECT_EQ(sc_acc_dmem_write(num_words, NULL, dest_addr), + kErrorAccBadOffsetLen); +} + +TEST_F(DmemWriteTest, FailureOverflowOffset) { + // Try to trigger an integer overflow with `dest_addr`. + std::array test_data = {0x12345678, 0xabcdef01}; + sc_acc_addr_t dest_addr = std::numeric_limits::max(); + + EXPECT_EQ(sc_acc_dmem_write(test_data.size(), test_data.data(), dest_addr), + kErrorAccBadOffsetLen); +} + +class DmemReadTest : public AccTest {}; + +TEST_F(DmemReadTest, SuccessWithoutOffset) { + // Assumption in the test. + ASSERT_GE(ACC_DMEM_SIZE_BYTES, 8); + static_assert(ACC_DMEM_SIZE_BYTES >= 8, "ACC DMEM size too small."); + + EXPECT_ABS_READ32(base_ + ACC_DMEM_REG_OFFSET, 0x12345678); + EXPECT_ABS_READ32(base_ + ACC_DMEM_REG_OFFSET + 4, 0xabcdef01); + + std::array test_data = {0}; + + sc_acc_addr_t src_addr = 0; + EXPECT_EQ(sc_acc_dmem_read(2, src_addr, test_data.data()), kErrorOk); + EXPECT_THAT(test_data, ElementsAre(0x12345678, 0xabcdef01)); +} + +TEST_F(DmemReadTest, SuccessWithOffset) { + // Assumption in the test. + static_assert(ACC_DMEM_SIZE_BYTES >= 12, "ACC DMEM size too small."); + + EXPECT_ABS_READ32(base_ + ACC_DMEM_REG_OFFSET + 4, 0x12345678); + EXPECT_ABS_READ32(base_ + ACC_DMEM_REG_OFFSET + 8, 0xabcdef01); + + std::array test_data = {0}; + + sc_acc_addr_t src_addr = 4; + EXPECT_EQ(sc_acc_dmem_read(2, src_addr, test_data.data()), kErrorOk); + EXPECT_THAT(test_data, ElementsAre(0x12345678, 0xabcdef01)); +} + +class AccAppTest : public AccTest {}; + +TEST_F(AccAppTest, AccLoadAppSuccess) { + std::array imem_data = {0x01234567, 0x89abcdef}; + std::array dmem_data = {0x456789ab, 0xcdef0123}; + sc_acc_addr_t dmem_data_offset = 0x12; + sc_acc_app_t app = { + .imem_start = imem_data.data(), + .imem_end = imem_data.data() + imem_data.size(), + .dmem_data_start = dmem_data.data(), + .dmem_data_end = dmem_data.data() + imem_data.size(), + .dmem_data_start_addr = dmem_data_offset, + }; + + // Test assumption. + static_assert(ACC_DMEM_SIZE_BYTES >= sizeof(uint32_t) * dmem_data.size(), + "ACC DMEM size too small"); + static_assert(ACC_IMEM_SIZE_BYTES >= sizeof(uint32_t) * imem_data.size(), + "ACC IMEM size too small"); + + // `sc_acc_busy_wait_for_done` - begin with busy to ensure we wait until + // idle. + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusyExecute); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusBusySecWipeDmem); + // Read twice for hardening. + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + // `sc_acc_dmem_sec_wipe` + ExpectCmdRun(kScAccCmdSecWipeDmem, err_bits_ok_, kScAccStatusIdle); + // `sc_acc_imem_sec_wipe` + ExpectCmdRun(kScAccCmdSecWipeImem, err_bits_ok_, kScAccStatusIdle); + // `acc_imem_write` + EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); + EXPECT_ABS_WRITE32(base_ + ACC_IMEM_REG_OFFSET, imem_data[0]); + EXPECT_ABS_WRITE32(base_ + ACC_IMEM_REG_OFFSET + sizeof(uint32_t), + imem_data[1]); + // `sc_acc_dmem_write` + EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); + EXPECT_ABS_WRITE32(base_ + ACC_DMEM_REG_OFFSET + dmem_data_offset, + dmem_data[0]); + EXPECT_ABS_WRITE32( + base_ + ACC_DMEM_REG_OFFSET + dmem_data_offset + sizeof(uint32_t), + dmem_data[1]); + + EXPECT_EQ(sc_acc_load_app(app), kErrorOk); +} + +TEST_F(AccAppTest, AccLoadInvalidAppEmptyImem) { + // Create an invalid app with an empty IMEM range. + std::array imem_data = {}; + std::array dmem_data = {0x456789ab, 0xcdef0123}; + sc_acc_addr_t dmem_data_offset = 0x12; + sc_acc_app_t app = { + .imem_start = imem_data.data(), + .imem_end = imem_data.data() + imem_data.size(), + .dmem_data_start = dmem_data.data(), + .dmem_data_end = dmem_data.data() + dmem_data.size(), + .dmem_data_start_addr = dmem_data_offset, + }; + + // Test assumption. + static_assert(ACC_DMEM_SIZE_BYTES >= sizeof(uint32_t) * dmem_data.size(), + "ACC DMEM size too small"); + static_assert(ACC_IMEM_SIZE_BYTES >= sizeof(uint32_t) * imem_data.size(), + "ACC IMEM size too small"); + + EXPECT_EQ(sc_acc_load_app(app), kErrorAccInvalidArgument); +} + +TEST_F(AccAppTest, AccLoadInvalidAppImemOutOfRange) { + // Create an invalid app with a too-large IMEM range. + std::array imem_data = + {0}; + std::array dmem_data = {0x456789ab, 0xcdef0123}; + sc_acc_addr_t dmem_data_offset = 0x12; + sc_acc_app_t app = { + .imem_start = imem_data.data(), + .imem_end = imem_data.data() + imem_data.size(), + .dmem_data_start = dmem_data.data(), + .dmem_data_end = dmem_data.data() + dmem_data.size(), + .dmem_data_start_addr = dmem_data_offset, + }; + + // Read twice for hardening. + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + EXPECT_ABS_READ32(base_ + ACC_STATUS_REG_OFFSET, kScAccStatusIdle); + // `sc_acc_dmem_sec_wipe` + ExpectCmdRun(kScAccCmdSecWipeDmem, err_bits_ok_, kScAccStatusIdle); + // `sc_acc_imem_sec_wipe` + ExpectCmdRun(kScAccCmdSecWipeImem, err_bits_ok_, kScAccStatusIdle); + + EXPECT_EQ(sc_acc_load_app(app), kErrorAccBadOffsetLen); +} + +class AccWriteTest : public AccTest {}; + +TEST_F(AccWriteTest, Success) { + constexpr uint32_t kDestAddr = 6; + std::array test_data = {0x12345678, 0xabcdef01}; + + // Test assumption. + static_assert( + ACC_DMEM_SIZE_BYTES >= sizeof(uint32_t) * test_data.size() + kDestAddr, + "ACC DMEM size too small."); + + EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); + EXPECT_ABS_WRITE32(base_ + ACC_DMEM_REG_OFFSET + kDestAddr, test_data[0]); + EXPECT_ABS_WRITE32(base_ + ACC_DMEM_REG_OFFSET + kDestAddr + sizeof(uint32_t), + test_data[1]); + + EXPECT_EQ(sc_acc_dmem_write(2, test_data.data(), kDestAddr), kErrorOk); +} + +class AccReadTest : public AccTest {}; + +TEST_F(AccReadTest, Success) { + constexpr uint32_t kSrcAddr = 6; + std::array test_data = {0}; + + // Test assumption. + static_assert( + ACC_DMEM_SIZE_BYTES >= sizeof(uint32_t) * test_data.size() + kSrcAddr, + "ACC DMEM size too small."); + + EXPECT_ABS_READ32(base_ + ACC_DMEM_REG_OFFSET + kSrcAddr, 0x12345678); + EXPECT_ABS_READ32(base_ + ACC_DMEM_REG_OFFSET + kSrcAddr + sizeof(uint32_t), + 0xabcdef01); + + EXPECT_EQ(sc_acc_dmem_read(2, kSrcAddr, test_data.data()), kErrorOk); + EXPECT_THAT(test_data, ElementsAre(0x12345678, 0xabcdef01)); +} +} // namespace +} // namespace acc_unittest diff --git a/sw/device/silicon_creator/lib/drivers/keymgr.c b/sw/device/silicon_creator/lib/drivers/keymgr.c index eba3c493951..9d309b8404b 100644 --- a/sw/device/silicon_creator/lib/drivers/keymgr.c +++ b/sw/device/silicon_creator/lib/drivers/keymgr.c @@ -226,7 +226,7 @@ rom_error_t sc_keymgr_generate_key( uint32_t ctrl = 0; - // Select OTBN as the destination. + // Select ACC as the destination. ctrl = bitfield_field32_write(0, KEYMGR_CONTROL_SHADOWED_DEST_SEL_FIELD, destination); @@ -330,6 +330,6 @@ void sc_keymgr_disable(void) { abs_mmio_write32(sc_keymgr_base() + KEYMGR_SIDELOAD_CLEAR_REG_OFFSET, 1); } -extern rom_error_t sc_keymgr_generate_key_otbn( +extern rom_error_t sc_keymgr_generate_key_acc( sc_keymgr_key_type_t key_type, sc_keymgr_diversification_t diversification); -extern rom_error_t sc_keymgr_sideload_clear_otbn(void); +extern rom_error_t sc_keymgr_sideload_clear_acc(void); diff --git a/sw/device/silicon_creator/lib/drivers/keymgr.h b/sw/device/silicon_creator/lib/drivers/keymgr.h index e9aa69f3d95..767852d8542 100644 --- a/sw/device/silicon_creator/lib/drivers/keymgr.h +++ b/sw/device/silicon_creator/lib/drivers/keymgr.h @@ -85,7 +85,7 @@ typedef enum sc_keymgr_dest { kScKeymgrDestNone = 0, kScKeymgrDestAes = 1, kScKeymgrDestKmac = 2, - kScKeymgrDestOtbn = 3, + kScKeymgrDestAcc = 3, } sc_keymgr_dest_t; /** @@ -221,7 +221,7 @@ typedef struct sc_keymgr_ecc_key { /** * Pointer to the keymgr diversifier that is used when actuating the keymgr's * "output-generate" function to generate another ECC keygen seed that will be - * sideloaded to OTBN. + * sideloaded to ACC. */ const sc_keymgr_diversification_t *keymgr_diversifier; /** @@ -261,9 +261,9 @@ OT_WARN_UNUSED_RESULT rom_error_t sc_keymgr_sideload_clear(sc_keymgr_dest_t destination); /** - * Generate a key manager key and sideload to the OTBN block. + * Generate a key manager key and sideload to the ACC block. * - * Calls the key manager to sideload a key into the OTBN hardware block and + * Calls the key manager to sideload a key into the ACC hardware block and * waits until the operation is complete before returning. Can sideload an * attestation or sealing key based on user input. * @@ -272,14 +272,14 @@ rom_error_t sc_keymgr_sideload_clear(sc_keymgr_dest_t destination); * @return OK or error. */ OT_WARN_UNUSED_RESULT -inline rom_error_t sc_keymgr_generate_key_otbn( +inline rom_error_t sc_keymgr_generate_key_acc( sc_keymgr_key_type_t key_type, sc_keymgr_diversification_t diversification) { - return sc_keymgr_generate_key(kScKeymgrDestOtbn, key_type, diversification); + return sc_keymgr_generate_key(kScKeymgrDestAcc, key_type, diversification); } /** - * Clear OTBN's sideloaded key slot. + * Clear ACC's sideloaded key slot. * * The entropy complex needs to be initialized before calling this function, so * that keymgr can use it to clear the slot. @@ -287,8 +287,8 @@ inline rom_error_t sc_keymgr_generate_key_otbn( * @return OK or error. */ OT_WARN_UNUSED_RESULT -inline rom_error_t sc_keymgr_sideload_clear_otbn(void) { - return sc_keymgr_sideload_clear(kScKeymgrDestOtbn); +inline rom_error_t sc_keymgr_sideload_clear_acc(void) { + return sc_keymgr_sideload_clear(kScKeymgrDestAcc); } /** diff --git a/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc b/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc index 38621c2ba37..b81b06552c9 100644 --- a/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc +++ b/sw/device/silicon_creator/lib/drivers/keymgr_unittest.cc @@ -211,7 +211,7 @@ TEST_F(KeymgrTest, CheckStateInvalidResponse) { kErrorKeymgrInternal); } -TEST_F(KeymgrTest, GenOtbnAttestationKey) { +TEST_F(KeymgrTest, GenAccAttestationKey) { sc_keymgr_diversification_t test_diversification = { .salt = {0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf}, @@ -223,7 +223,7 @@ TEST_F(KeymgrTest, GenOtbnAttestationKey) { base_ + KEYMGR_CONTROL_SHADOWED_REG_OFFSET, { {KEYMGR_CONTROL_SHADOWED_DEST_SEL_OFFSET, - KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_OTBN}, + KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_ACC}, {KEYMGR_CONTROL_SHADOWED_CDI_SEL_BIT, true}, {KEYMGR_CONTROL_SHADOWED_OPERATION_OFFSET, KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT}, @@ -236,12 +236,12 @@ TEST_F(KeymgrTest, GenOtbnAttestationKey) { ExpectWaitUntilDone(/*busy_cycles=*/2, KEYMGR_OP_STATUS_STATUS_VALUE_DONE_SUCCESS); - EXPECT_EQ(sc_keymgr_generate_key_otbn(kScKeymgrKeyTypeAttestation, - test_diversification), + EXPECT_EQ(sc_keymgr_generate_key_acc(kScKeymgrKeyTypeAttestation, + test_diversification), kErrorOk); } -TEST_F(KeymgrTest, GenOtbnSealingKey) { +TEST_F(KeymgrTest, GenAccSealingKey) { sc_keymgr_diversification_t test_diversification = { .salt = {0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf}, @@ -253,7 +253,7 @@ TEST_F(KeymgrTest, GenOtbnSealingKey) { base_ + KEYMGR_CONTROL_SHADOWED_REG_OFFSET, { {KEYMGR_CONTROL_SHADOWED_DEST_SEL_OFFSET, - KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_OTBN}, + KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_ACC}, {KEYMGR_CONTROL_SHADOWED_CDI_SEL_BIT, false}, {KEYMGR_CONTROL_SHADOWED_OPERATION_OFFSET, KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT}, @@ -266,12 +266,12 @@ TEST_F(KeymgrTest, GenOtbnSealingKey) { ExpectWaitUntilDone(/*busy_cycles=*/2, KEYMGR_OP_STATUS_STATUS_VALUE_DONE_SUCCESS); - EXPECT_EQ(sc_keymgr_generate_key_otbn(kScKeymgrKeyTypeSealing, - test_diversification), - kErrorOk); + EXPECT_EQ( + sc_keymgr_generate_key_acc(kScKeymgrKeyTypeSealing, test_diversification), + kErrorOk); } -TEST_F(KeymgrTest, GenOtbnKeyNotIdle) { +TEST_F(KeymgrTest, GenAccKeyNotIdle) { sc_keymgr_diversification_t test_diversification = { .salt = {0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf}, @@ -279,20 +279,20 @@ TEST_F(KeymgrTest, GenOtbnKeyNotIdle) { }; ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_WIP); - EXPECT_EQ(sc_keymgr_generate_key_otbn(kScKeymgrKeyTypeAttestation, - test_diversification), + EXPECT_EQ(sc_keymgr_generate_key_acc(kScKeymgrKeyTypeAttestation, + test_diversification), kErrorKeymgrInternal); ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_DONE_ERROR); - EXPECT_EQ(sc_keymgr_generate_key_otbn(kScKeymgrKeyTypeAttestation, - test_diversification), + EXPECT_EQ(sc_keymgr_generate_key_acc(kScKeymgrKeyTypeAttestation, + test_diversification), kErrorKeymgrInternal); ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_DONE_SUCCESS); - EXPECT_EQ(sc_keymgr_generate_key_otbn(kScKeymgrKeyTypeAttestation, - test_diversification), + EXPECT_EQ(sc_keymgr_generate_key_acc(kScKeymgrKeyTypeAttestation, + test_diversification), kErrorKeymgrInternal); } -TEST_F(KeymgrTest, GenOtbnKeyError) { +TEST_F(KeymgrTest, GenAccKeyError) { sc_keymgr_diversification_t test_diversification = { .salt = {0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf}, @@ -305,7 +305,7 @@ TEST_F(KeymgrTest, GenOtbnKeyError) { base_ + KEYMGR_CONTROL_SHADOWED_REG_OFFSET, { {KEYMGR_CONTROL_SHADOWED_DEST_SEL_OFFSET, - KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_OTBN}, + KEYMGR_CONTROL_SHADOWED_DEST_SEL_VALUE_ACC}, {KEYMGR_CONTROL_SHADOWED_CDI_SEL_BIT, true}, {KEYMGR_CONTROL_SHADOWED_OPERATION_OFFSET, KEYMGR_CONTROL_SHADOWED_OPERATION_VALUE_GENERATE_HW_OUTPUT}, @@ -320,22 +320,22 @@ TEST_F(KeymgrTest, GenOtbnKeyError) { EXPECT_ABS_READ32(base_ + KEYMGR_ERR_CODE_REG_OFFSET, err_code); EXPECT_ABS_WRITE32(base_ + KEYMGR_ERR_CODE_REG_OFFSET, err_code); - EXPECT_EQ(sc_keymgr_generate_key_otbn(kScKeymgrKeyTypeAttestation, - test_diversification), + EXPECT_EQ(sc_keymgr_generate_key_acc(kScKeymgrKeyTypeAttestation, + test_diversification), kErrorKeymgrInternal); } -TEST_F(KeymgrTest, SideloadClearOtbn) { +TEST_F(KeymgrTest, SideloadClearAcc) { ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_IDLE); EXPECT_ABS_WRITE32(base_ + KEYMGR_SIDELOAD_CLEAR_REG_OFFSET, { {KEYMGR_SIDELOAD_CLEAR_VAL_OFFSET, - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_OTBN}, + KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_ACC}, }); EXPECT_ABS_READ32(base_ + KEYMGR_SIDELOAD_CLEAR_REG_OFFSET, { {KEYMGR_SIDELOAD_CLEAR_VAL_OFFSET, - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_OTBN}, + KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_ACC}, }); EXPECT_ABS_WRITE32(base_ + KEYMGR_SIDELOAD_CLEAR_REG_OFFSET, { @@ -343,24 +343,24 @@ TEST_F(KeymgrTest, SideloadClearOtbn) { KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_NONE}, }); - EXPECT_EQ(sc_keymgr_sideload_clear_otbn(), kErrorOk); + EXPECT_EQ(sc_keymgr_sideload_clear_acc(), kErrorOk); } -TEST_F(KeymgrTest, SideloadClearOtbnNotIdle) { +TEST_F(KeymgrTest, SideloadClearAccNotIdle) { ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_WIP); - EXPECT_EQ(sc_keymgr_sideload_clear_otbn(), kErrorKeymgrInternal); + EXPECT_EQ(sc_keymgr_sideload_clear_acc(), kErrorKeymgrInternal); ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_DONE_SUCCESS); - EXPECT_EQ(sc_keymgr_sideload_clear_otbn(), kErrorKeymgrInternal); + EXPECT_EQ(sc_keymgr_sideload_clear_acc(), kErrorKeymgrInternal); ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_DONE_ERROR); - EXPECT_EQ(sc_keymgr_sideload_clear_otbn(), kErrorKeymgrInternal); + EXPECT_EQ(sc_keymgr_sideload_clear_acc(), kErrorKeymgrInternal); } -TEST_F(KeymgrTest, SideloadClearOtbnReadbackMismatch) { +TEST_F(KeymgrTest, SideloadClearAccReadbackMismatch) { ExpectIdleCheck(KEYMGR_OP_STATUS_STATUS_VALUE_IDLE); EXPECT_ABS_WRITE32(base_ + KEYMGR_SIDELOAD_CLEAR_REG_OFFSET, { {KEYMGR_SIDELOAD_CLEAR_VAL_OFFSET, - KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_OTBN}, + KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_ACC}, }); // Readback does not match the value written. @@ -370,7 +370,7 @@ TEST_F(KeymgrTest, SideloadClearOtbnReadbackMismatch) { KEYMGR_SIDELOAD_CLEAR_VAL_VALUE_AES}, }); - EXPECT_EQ(sc_keymgr_sideload_clear_otbn(), kErrorKeymgrInternal); + EXPECT_EQ(sc_keymgr_sideload_clear_acc(), kErrorKeymgrInternal); } TEST_F(KeymgrTest, OwnerIntAdvance) { diff --git a/sw/device/silicon_creator/lib/drivers/otbn.c b/sw/device/silicon_creator/lib/drivers/otbn.c deleted file mode 100644 index 9e05bc998d7..00000000000 --- a/sw/device/silicon_creator/lib/drivers/otbn.c +++ /dev/null @@ -1,250 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/silicon_creator/lib/drivers/otbn.h" - -#include -#include -#include - -#include "hw/top/dt/dt_otbn.h" -#include "sw/device/lib/base/abs_mmio.h" -#include "sw/device/lib/base/bitfield.h" -#include "sw/device/silicon_creator/lib/base/sec_mmio.h" -#include "sw/device/silicon_creator/lib/drivers/rnd.h" -#include "sw/device/silicon_creator/lib/error.h" - -#include "hw/top/otbn_regs.h" // Generated. - -static inline uint32_t otbn_base(void) { - return dt_otbn_primary_reg_block(kDtOtbn); -} - -enum { - /** - * Highest index of OTBN error bits. - */ - kOtbnErrBitsLast = OTBN_ERR_BITS_FATAL_SOFTWARE_BIT, -}; - -/** - * Ensures that `offset_bytes` and `len` are valid for a given `mem_size`. - */ -OT_WARN_UNUSED_RESULT -static rom_error_t check_offset_len(uint32_t offset_bytes, size_t num_words, - size_t mem_size) { - if (num_words > UINT32_MAX / sizeof(uint32_t)) { - return kErrorOtbnBadOffsetLen; - } - uint32_t num_bytes = num_words * sizeof(uint32_t); - - if (offset_bytes > UINT32_MAX - num_bytes) { - return kErrorOtbnBadOffsetLen; - } - uint32_t adjusted_offset_bytes = offset_bytes + num_bytes; - - if (adjusted_offset_bytes > mem_size) { - return kErrorOtbnBadOffsetLen; - } - - return kErrorOk; -} - -rom_error_t sc_otbn_busy_wait_for_done(void) { - uint32_t status = launder32(UINT32_MAX); - rom_error_t res = launder32(kErrorOk ^ status); - do { - status = abs_mmio_read32(otbn_base() + OTBN_STATUS_REG_OFFSET); - } while (launder32(status) != kScOtbnStatusIdle && - launder32(status) != kScOtbnStatusLocked); - res ^= ~status; - if (launder32(res) == kErrorOk) { - HARDENED_CHECK_EQ(res, kErrorOk); - HARDENED_CHECK_EQ(abs_mmio_read32(otbn_base() + OTBN_STATUS_REG_OFFSET), - kScOtbnStatusIdle); - return res; - } - return kErrorOtbnUnavailable; -} - -/** - * Helper function for writing to OTBN's DMEM or IMEM. - * - * @param dest_addr Destination address. - * @param src Source buffer. - * @param num_words Number of words to copy. - */ -static void sc_otbn_write(uint32_t dest_addr, const uint32_t *src, - size_t num_words) { - // Start from a random index less than `num_words`. - uint32_t i = ((uint64_t)rnd_uint32() * (uint64_t)num_words) >> 32; - enum { kStep = 1 }; - uint32_t iter_cnt = 0, r_iter_cnt = num_words - 1; - for (; launder32(iter_cnt) < num_words && launder32(r_iter_cnt) < num_words; - ++iter_cnt, --r_iter_cnt) { - abs_mmio_write32(dest_addr + i * sizeof(uint32_t), src[i]); - i += kStep; - if (launder32(i) >= num_words) { - i -= num_words; - } - HARDENED_CHECK_LT(i, num_words); - } - HARDENED_CHECK_EQ(iter_cnt, num_words); - HARDENED_CHECK_EQ(r_iter_cnt, UINT32_MAX); -} - -OT_WARN_UNUSED_RESULT -static rom_error_t sc_otbn_imem_write(size_t num_words, const uint32_t *src, - sc_otbn_addr_t dest) { - HARDENED_RETURN_IF_ERROR( - check_offset_len(dest, num_words, OTBN_IMEM_SIZE_BYTES)); - sc_otbn_write(otbn_base() + OTBN_IMEM_REG_OFFSET + dest, src, num_words); - return kErrorOk; -} - -rom_error_t sc_otbn_dmem_write(size_t num_words, const uint32_t *src, - sc_otbn_addr_t dest) { - HARDENED_RETURN_IF_ERROR( - check_offset_len(dest, num_words, OTBN_DMEM_SIZE_BYTES)); - sc_otbn_write(otbn_base() + OTBN_DMEM_REG_OFFSET + dest, src, num_words); - return kErrorOk; -} - -rom_error_t sc_otbn_dmem_read(size_t num_words, sc_otbn_addr_t src, - uint32_t *dest) { - HARDENED_RETURN_IF_ERROR( - check_offset_len(src, num_words, OTBN_DMEM_SIZE_BYTES)); - uint32_t i = 0, r = num_words - 1; - for (; launder32(i) < num_words && launder32(r) < num_words; ++i, --r) { - dest[i] = abs_mmio_read32(otbn_base() + OTBN_DMEM_REG_OFFSET + src + - i * sizeof(uint32_t)); - } - HARDENED_CHECK_EQ(i, num_words); - HARDENED_CHECK_EQ(r, UINT32_MAX); - return kErrorOk; -} - -/** - * Helper function for running an OTBN command. - * - * This function blocks until OTBN is idle. - * - * @param cmd OTBN command. - * @param error Error to return if operation fails. - * @return Result of the operation. - */ -OT_WARN_UNUSED_RESULT -static rom_error_t sc_otbn_cmd_run(sc_otbn_cmd_t cmd, rom_error_t error) { - enum { - kIntrStateDone = (1 << OTBN_INTR_COMMON_DONE_BIT), - // Use a bit index that doesn't overlap with error bits. - kResDoneBit = 31, - }; - static_assert((UINT32_C(1) << kResDoneBit) > kOtbnErrBitsLast, - "kResDoneBit must not overlap with OTBN error bits"); - - abs_mmio_write32(otbn_base() + OTBN_INTR_STATE_REG_OFFSET, kIntrStateDone); - abs_mmio_write32(otbn_base() + OTBN_CMD_REG_OFFSET, cmd); - - rom_error_t res = kErrorOk ^ (UINT32_C(1) << kResDoneBit); - uint32_t reg = 0; - do { - reg = abs_mmio_read32(otbn_base() + OTBN_INTR_STATE_REG_OFFSET); - res ^= (uint32_t)bitfield_bit32_read(reg, OTBN_INTR_COMMON_DONE_BIT) - << kResDoneBit; - } while (launder32(reg) != kIntrStateDone); - HARDENED_CHECK_EQ(reg, kIntrStateDone); - abs_mmio_write32(otbn_base() + OTBN_INTR_STATE_REG_OFFSET, kIntrStateDone); - - // Error bits register should be 0 (no errors). - uint32_t err_bits = abs_mmio_read32(otbn_base() + OTBN_ERR_BITS_REG_OFFSET); - res ^= err_bits; - - // Status should be kScOtbnStatusIdle; OTBN can also issue a done interrupt - // when transitioning to the "locked" state, so it is important to check - // the status here. - uint32_t status = abs_mmio_read32(otbn_base() + OTBN_STATUS_REG_OFFSET); - - if (launder32(res) == kErrorOk && launder32(err_bits) == 0 && - launder32(status) == kScOtbnStatusIdle) { - HARDENED_CHECK_EQ(res, kErrorOk); - HARDENED_CHECK_EQ(err_bits, 0); - HARDENED_CHECK_EQ(abs_mmio_read32(otbn_base() + OTBN_STATUS_REG_OFFSET), - kScOtbnStatusIdle); - return res; - } - return error; -} - -rom_error_t sc_otbn_execute(void) { - // If OTBN is busy, wait for it to be done. - HARDENED_RETURN_IF_ERROR(sc_otbn_busy_wait_for_done()); - - // Set software errors to fatal before running the program. Note: the CTRL - // register has only this one setting, so we have no need to read the - // previous value. - sec_mmio_write32(otbn_base() + OTBN_CTRL_REG_OFFSET, - 1 << OTBN_CTRL_SOFTWARE_ERRS_FATAL_BIT); - - return sc_otbn_cmd_run(kScOtbnCmdExecute, kErrorOtbnExecutionFailed); -} - -uint32_t sc_otbn_instruction_count_get(void) { - return abs_mmio_read32(otbn_base() + OTBN_INSN_CNT_REG_OFFSET); -} - -rom_error_t sc_otbn_imem_sec_wipe(void) { - return sc_otbn_cmd_run(kScOtbnCmdSecWipeImem, kErrorOtbnSecWipeImemFailed); -} - -rom_error_t sc_otbn_dmem_sec_wipe(void) { - return sc_otbn_cmd_run(kScOtbnCmdSecWipeDmem, kErrorOtbnSecWipeDmemFailed); -} - -/** - * Checks if the OTBN application's IMEM and DMEM address parameters are valid. - * - * IMEM and DMEM ranges must not be "backwards" in memory, with the end address - * coming before the start address, and the IMEM range must additionally be - * non-empty. - * - * @param app the OTBN application to check - * @return OK if the addresses are valid, otherwise `kErrorOtbnInvalidArgument`. - */ -OT_WARN_UNUSED_RESULT -static rom_error_t check_app_address_ranges(const sc_otbn_app_t app) { - if (app.imem_end > app.imem_start && - app.dmem_data_end >= app.dmem_data_start) { - HARDENED_CHECK_GT(app.imem_end, app.imem_start); - HARDENED_CHECK_GE(app.dmem_data_end, app.dmem_data_start); - return kErrorOk; - } - return kErrorOtbnInvalidArgument; -} - -rom_error_t sc_otbn_load_app(const sc_otbn_app_t app) { - HARDENED_RETURN_IF_ERROR(check_app_address_ranges(app)); - - // If OTBN is busy, wait for it to be done. - HARDENED_RETURN_IF_ERROR(sc_otbn_busy_wait_for_done()); - - // Wipe memories. - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_sec_wipe()); - HARDENED_RETURN_IF_ERROR(sc_otbn_imem_sec_wipe()); - - const size_t imem_num_words = (size_t)(app.imem_end - app.imem_start); - const size_t data_num_words = - (size_t)(app.dmem_data_end - app.dmem_data_start); - - // IMEM always starts at 0. - sc_otbn_addr_t imem_start_addr = 0; - HARDENED_RETURN_IF_ERROR( - sc_otbn_imem_write(imem_num_words, app.imem_start, imem_start_addr)); - - if (data_num_words > 0) { - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_write( - data_num_words, app.dmem_data_start, app.dmem_data_start_addr)); - } - return kErrorOk; -} diff --git a/sw/device/silicon_creator/lib/drivers/otbn.h b/sw/device/silicon_creator/lib/drivers/otbn.h deleted file mode 100644 index 577257f3dd3..00000000000 --- a/sw/device/silicon_creator/lib/drivers/otbn.h +++ /dev/null @@ -1,310 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_OTBN_H_ -#define OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_OTBN_H_ - -#include -#include -#include - -#include "sw/device/silicon_creator/lib/error.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Constants related to OTBN wide words - */ -enum { - /* Length of an OTBN wide word in bits */ - kScOtbnWideWordNumBits = 256, - /* Length of an OTBN wide word in words */ - kScOtbnWideWordNumWords = kScOtbnWideWordNumBits / (sizeof(uint32_t) * 8), -}; - -/** - * The following constants represent the expected number of sec_mmio register - * writes performed by functions in provided in this module. See - * `SEC_MMIO_WRITE_INCREMENT()` for more details. - * - * Example: - * ``` - * sc_otbn_execute(); - * SEC_MMIO_WRITE_INCREMENT(kScOtbnSecMmioExecute); - * ``` - */ -enum { - kScOtbnSecMmioExecute = 1, -}; - -/** - * OTBN commands - * - * TODO(#16754): replace these with constants from otbn_regs.h - */ -typedef enum sc_otbn_cmd { - kScOtbnCmdExecute = 0xd8, - kScOtbnCmdSecWipeDmem = 0xc3, - kScOtbnCmdSecWipeImem = 0x1e, -} sc_otbn_cmd_t; - -/** - * OTBN status - * - * TODO(#16754): replace these with constants from otbn_regs.h - */ -typedef enum sc_otbn_status { - kScOtbnStatusIdle = 0x00, - kScOtbnStatusBusyExecute = 0x01, - kScOtbnStatusBusySecWipeDmem = 0x02, - kScOtbnStatusBusySecWipeImem = 0x03, - kScOtbnStatusBusySecWipeInt = 0x04, - kScOtbnStatusLocked = 0xFF, -} sc_otbn_status_t; - -/** - * The address of an OTBN symbol as seen by OTBN - * - * Use `OTBN_DECLARE_SYMBOL_ADDR()` together with `OTBN_ADDR_T_INIT()` to - * initialize this type. - */ -typedef uint32_t sc_otbn_addr_t; - -/** - * Information about an embedded OTBN application image. - * - * All pointers reference data in the normal CPU address space. - * uint32_t values are addresses in the OTBN address space. - * - * Use `OTBN_DECLARE_APP_SYMBOLS()` together with `OTBN_APP_T_INIT()` to - * initialize this structure. - */ -typedef struct sc_otbn_app { - /** - * Start of OTBN instruction memory. - */ - const uint32_t *imem_start; - /** - * The first word after OTBN instruction memory. - * - * This address satifies `imem_len = imem_end - imem_start`. - */ - const uint32_t *imem_end; - /** - * Start of initialized OTBN data. - * - * Data in between dmem_data_start and dmem_data_end will be copied to OTBN - * at app load time. - */ - const uint32_t *dmem_data_start; - /** - * The first word after initialized OTBN data. - * - * Should satisfy `dmem_data_start <= dmem_data_end`. - */ - const uint32_t *dmem_data_end; - /** - * Start of initialized data section in OTBN's DMEM. - * - * This pointer references OTBN's memory and is used to copy data at app load - * time. - */ - const sc_otbn_addr_t dmem_data_start_addr; -} sc_otbn_app_t; - -/** - * Generate the prefix to add to an OTBN symbol name used on the Ibex side - * - * The result is a pointer to Ibex's rodata that should be used to initialise - * memory for that symbol. - * - * This is needed by the OTBN driver to support DMEM/IMEM ranges but - * application code shouldn't need to use this. Use the `sc_otbn_addr_t` type - * and supporting macros instead. - */ -#define OTBN_SYMBOL_PTR(app_name, sym) _otbn_local_app_##app_name##_##sym - -/** - * Generate the prefix to add to an OTBN symbol name used on the OTBN side - * - * The result is a pointer whose integer value is the address by which the - * symbol should be accessed in OTBN memory. - * - * This is an internal macro used in `OTBN_DECLARE_SYMBOL_ADDR` and - * `OTBN_ADDR_T_INIT` but application code shouldn't need to use it directly. - */ -#define OTBN_SYMBOL_ADDR(app_name, sym) _otbn_remote_app_##app_name##_##sym - -/** - * Makes a symbol in the OTBN application image available. - * - * This is needed by the OTBN driver to support DMEM/IMEM ranges but - * application code shouldn't need to use this. To get access to OTBN - * addresses, use `OTBN_DECLARE_SYMBOL_ADDR` instead. - */ -#define OTBN_DECLARE_SYMBOL_PTR(app_name, symbol_name) \ - extern const uint32_t OTBN_SYMBOL_PTR(app_name, symbol_name)[] - -/** - * Makes the OTBN address of a symbol in the OTBN application available. - * - * Symbols are typically function or data pointers, i.e. labels in assembly - * code. Unlike OTBN_DECLARE_SYMBOL_PTR, this will work for symbols in the .bss - * section (which exist on the OTBN side, even though they don't have backing - * data on Ibex). - * - * Use this macro instead of manually declaring the symbols as symbol names - * might change. - * - * @param app_name Name of the application the function is contained in. - * @param symbol_name Name of the symbol (function, label). - */ -#define OTBN_DECLARE_SYMBOL_ADDR(app_name, symbol_name) \ - extern const uint32_t OTBN_SYMBOL_ADDR(app_name, symbol_name)[] - -/** - * Makes an embedded OTBN application image available for use. - * - * Make symbols available that indicate the start and the end of instruction - * and data memory regions, as they are stored in the device memory. - * - * Use this macro instead of manually declaring the symbols as symbol names - * might change. - * - * @param app_name Name of the application to load, which is typically the - * name of the main (assembly) source file. - */ -#define OTBN_DECLARE_APP_SYMBOLS(app_name) \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _imem_start); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _imem_end); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _dmem_data_start); \ - OTBN_DECLARE_SYMBOL_PTR(app_name, _dmem_data_end); \ - OTBN_DECLARE_SYMBOL_ADDR(app_name, _dmem_data_start); - -/** - * Initializes the OTBN application information structure. - * - * After making all required symbols from the application image available - * through `OTBN_DECLARE_APP_SYMBOLS()`, use this macro to initialize an - * `sc_otbn_app_t` struct with those symbols. - * - * @param app_name Name of the application to load. - * @see OTBN_DECLARE_APP_SYMBOLS() - */ -#define OTBN_APP_T_INIT(app_name) \ - ((sc_otbn_app_t){ \ - .imem_start = OTBN_SYMBOL_PTR(app_name, _imem_start), \ - .imem_end = OTBN_SYMBOL_PTR(app_name, _imem_end), \ - .dmem_data_start = OTBN_SYMBOL_PTR(app_name, _dmem_data_start), \ - .dmem_data_end = OTBN_SYMBOL_PTR(app_name, _dmem_data_end), \ - .dmem_data_start_addr = OTBN_ADDR_T_INIT(app_name, _dmem_data_start), \ - }) - -/** - * Initializes an `sc_otbn_addr_t`. - */ -#define OTBN_ADDR_T_INIT(app_name, symbol_name) \ - ((uint32_t)OTBN_SYMBOL_ADDR(app_name, symbol_name)) - -/** - * (Re-)loads an application into OTBN. - * - * Load the application image with both instruction and data segments into - * OTBN. - * - * @param app The application to load into OTBN. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -rom_error_t sc_otbn_load_app(const sc_otbn_app_t app); - -/** - * Copies data from the CPU memory to OTBN data memory. - * - * @param num_words Number of 32b words to copy. - * @param dest Address of the destination in OTBN's data memory. - * @param src Source of the data to copy. - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -rom_error_t sc_otbn_dmem_write(size_t num_words, const uint32_t *src, - sc_otbn_addr_t dest); - -/** - * Copies data from OTBN's data memory to CPU memory. - * - * @param num_words The number of 32b words to copy. - * @param src The address in OTBN data memory to copy from. - * @param[out] dest The destination of the copied data in main memory - * (preallocated). - * @return The result of the operation. - */ -OT_WARN_UNUSED_RESULT -rom_error_t sc_otbn_dmem_read(size_t num_words, const sc_otbn_addr_t src, - uint32_t *dest); - -/** - * Start the execution of the application loaded into OTBN. - * - * This function blocks until OTBN is idle. - * - * @return Result of the operation. - */ -OT_WARN_UNUSED_RESULT -rom_error_t sc_otbn_execute(void); - -/** - * Blocks until OTBN is idle. - * - * If OTBN is or becomes locked, an error will occur. - * - * @return Result of the operation. - */ -OT_WARN_UNUSED_RESULT -rom_error_t sc_otbn_busy_wait_for_done(void); - -/** - * Read OTBN's instruction count register. - * - * OTBN automatically calculates how many instructions are executed in a given - * program and writes the result to this register. Software can read it to - * verify that instructions were not unexpectedly skipped or added (for - * instance, due to fault injection attacks). - * - * Note that the OTBN hardware resets the instruction count register to 0 when - * the EXECUTE command is issued, so there is no need for software to reset the - * counter between programs. - * - * @return count the value from the instruction count register - */ -OT_WARN_UNUSED_RESULT -uint32_t sc_otbn_instruction_count_get(void); - -/** - * Wipe IMEM securely. - * - * This function blocks until OTBN is idle. - * - * @return Result of the operation. - */ -OT_WARN_UNUSED_RESULT -rom_error_t sc_otbn_imem_sec_wipe(void); - -/** - * Wipe DMEM securely. - * - * This function blocks until OTBN is idle. - * - * @return Result of the operation. - */ -OT_WARN_UNUSED_RESULT -rom_error_t sc_otbn_dmem_sec_wipe(void); - -#ifdef __cplusplus -} -#endif - -#endif // OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_DRIVERS_OTBN_H_ diff --git a/sw/device/silicon_creator/lib/drivers/otbn_unittest.cc b/sw/device/silicon_creator/lib/drivers/otbn_unittest.cc deleted file mode 100644 index 6282a0a0329..00000000000 --- a/sw/device/silicon_creator/lib/drivers/otbn_unittest.cc +++ /dev/null @@ -1,399 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/silicon_creator/lib/drivers/otbn.h" - -#include -#include - -#include "gtest/gtest.h" -#include "sw/device/lib/base/mock_abs_mmio.h" -#include "sw/device/silicon_creator/lib/base/mock_sec_mmio.h" -#include "sw/device/silicon_creator/lib/drivers/mock_rnd.h" -#include "sw/device/silicon_creator/testing/rom_test.h" - -#include "hw/top/otbn_regs.h" // Generated. -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" - -namespace otbn_unittest { -namespace { -using ::testing::ElementsAre; -using ::testing::Return; - -class OtbnTest : public rom_test::RomTest { - protected: - /** - * Sets expectations for running an OTBN command. - * - * @param cmd Command expected to be run. - * @param err_bits Error bits to be returned. - * @param status Status of OTBN to be returned after the command is done. - */ - void ExpectCmdRun(sc_otbn_cmd_t cmd, uint32_t err_bits, - sc_otbn_status_t status) { - EXPECT_ABS_WRITE32(base_ + OTBN_INTR_STATE_REG_OFFSET, - { - {OTBN_INTR_COMMON_DONE_BIT, 1}, - }); - EXPECT_ABS_WRITE32(base_ + OTBN_CMD_REG_OFFSET, cmd); - - EXPECT_ABS_READ32(base_ + OTBN_INTR_STATE_REG_OFFSET, 0); - EXPECT_ABS_READ32(base_ + OTBN_INTR_STATE_REG_OFFSET, - { - {OTBN_INTR_COMMON_DONE_BIT, 1}, - }); - EXPECT_ABS_WRITE32(base_ + OTBN_INTR_STATE_REG_OFFSET, - { - {OTBN_INTR_COMMON_DONE_BIT, 1}, - }); - - EXPECT_ABS_READ32(base_ + OTBN_ERR_BITS_REG_OFFSET, err_bits); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, status); - - if (err_bits == err_bits_ok_ && status == kScOtbnStatusIdle) { - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, status); - } - } - - uint32_t base_ = TOP_EARLGREY_OTBN_BASE_ADDR; - uint32_t err_bits_ok_ = 0; - rom_test::MockAbsMmio abs_mmio_; - rom_test::MockRnd rnd_; - rom_test::MockSecMmio sec_mmio_; -}; - -class ExecuteTest : public OtbnTest {}; - -TEST_F(ExecuteTest, ExecuteSuccess) { - // Test assumption. - static_assert(OTBN_IMEM_SIZE_BYTES >= 8, "OTBN IMEM size too small."); - - // Read twice for hardening. - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - - EXPECT_SEC_WRITE32(base_ + OTBN_CTRL_REG_OFFSET, 0x1); - - ExpectCmdRun(kScOtbnCmdExecute, err_bits_ok_, kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_execute(), kErrorOk); -} - -TEST_F(ExecuteTest, ExecuteError) { - // Read twice for hardening. - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - - EXPECT_SEC_WRITE32(base_ + OTBN_CTRL_REG_OFFSET, 0x1); - - // Nonzero error bits. - ExpectCmdRun(kScOtbnCmdExecute, 1 << OTBN_ERR_BITS_FATAL_SOFTWARE_BIT, - kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_execute(), kErrorOtbnExecutionFailed); -} - -TEST_F(ExecuteTest, ExecuteBusy) { - // Read twice for hardening. - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - - EXPECT_SEC_WRITE32(base_ + OTBN_CTRL_REG_OFFSET, 0x01); - - // Return a busy status after the `done` interrupt. - ExpectCmdRun(kScOtbnCmdExecute, err_bits_ok_, kScOtbnStatusBusyExecute); - - EXPECT_EQ(sc_otbn_execute(), kErrorOtbnExecutionFailed); -} - -TEST_F(ExecuteTest, ExecuteBlockUntilIdle) { - // Test assumption. - static_assert(OTBN_IMEM_SIZE_BYTES >= 8, "OTBN IMEM size too small."); - - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, - kScOtbnStatusBusySecWipeDmem); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, - kScOtbnStatusBusySecWipeDmem); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, - kScOtbnStatusBusySecWipeDmem); - - // Read twice for hardening. - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - - EXPECT_SEC_WRITE32(base_ + OTBN_CTRL_REG_OFFSET, 0x1); - - ExpectCmdRun(kScOtbnCmdExecute, err_bits_ok_, kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_execute(), kErrorOk); -} - -class IsBusyTest : public OtbnTest {}; - -TEST_F(IsBusyTest, Success) { - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusBusyExecute); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusBusyExecute); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusBusyExecute); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusBusyExecute); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_busy_wait_for_done(), kErrorOk); -} - -class ImemSecWipeTest : public OtbnTest {}; - -TEST_F(ImemSecWipeTest, Success) { - ExpectCmdRun(kScOtbnCmdSecWipeImem, err_bits_ok_, kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_imem_sec_wipe(), kErrorOk); -} - -TEST_F(ImemSecWipeTest, Failure) { - ExpectCmdRun(kScOtbnCmdSecWipeImem, 1 << OTBN_ERR_BITS_FATAL_SOFTWARE_BIT, - kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_imem_sec_wipe(), kErrorOtbnSecWipeImemFailed); -} - -class DmemSecWipeTest : public OtbnTest {}; - -TEST_F(DmemSecWipeTest, Success) { - ExpectCmdRun(kScOtbnCmdSecWipeDmem, err_bits_ok_, kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_dmem_sec_wipe(), kErrorOk); -} - -TEST_F(DmemSecWipeTest, Failure) { - ExpectCmdRun(kScOtbnCmdSecWipeDmem, 1 << OTBN_ERR_BITS_FATAL_SOFTWARE_BIT, - kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_dmem_sec_wipe(), kErrorOtbnSecWipeDmemFailed); -} - -class DmemWriteTest : public OtbnTest {}; - -TEST_F(DmemWriteTest, SuccessWithoutOffset) { - // Test assumption. - static_assert(OTBN_DMEM_SIZE_BYTES >= 8, "OTBN DMEM size too small."); - - std::array test_data = {0x12345678, 0xabcdef01}; - sc_otbn_addr_t dest_addr = 0; - - EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); - EXPECT_ABS_WRITE32(base_ + OTBN_DMEM_REG_OFFSET + dest_addr, test_data[0]); - EXPECT_ABS_WRITE32(base_ + OTBN_DMEM_REG_OFFSET + dest_addr + 4, - test_data[1]); - - EXPECT_EQ(sc_otbn_dmem_write(2, test_data.data(), dest_addr), kErrorOk); -} - -TEST_F(DmemWriteTest, SuccessWithOffset) { - // Test assumption. - static_assert(OTBN_DMEM_SIZE_BYTES >= 12, "OTBN DMEM size too small."); - - std::array test_data = {0x12345678, 0xabcdef01}; - sc_otbn_addr_t dest_addr = 4; - - EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); - EXPECT_ABS_WRITE32(base_ + OTBN_DMEM_REG_OFFSET + dest_addr, test_data[0]); - EXPECT_ABS_WRITE32(base_ + OTBN_DMEM_REG_OFFSET + dest_addr + 4, - test_data[1]); - - EXPECT_EQ(sc_otbn_dmem_write(2, test_data.data(), dest_addr), kErrorOk); -} - -TEST_F(DmemWriteTest, FailureOutOfRange) { - std::array test_data = {0x12345678, 0xabcdef01}; - sc_otbn_addr_t dest_addr = OTBN_DMEM_SIZE_BYTES; - - EXPECT_EQ(sc_otbn_dmem_write(2, test_data.data(), dest_addr), - kErrorOtbnBadOffsetLen); -} - -TEST_F(DmemWriteTest, FailureOverflowNumWords) { - // Try to trigger an integer overflow with `num_words`. - size_t num_words = - (std::numeric_limits::max() / sizeof(uint32_t)) + 1; - sc_otbn_addr_t dest_addr = 0; - - EXPECT_EQ(sc_otbn_dmem_write(num_words, NULL, dest_addr), - kErrorOtbnBadOffsetLen); -} - -TEST_F(DmemWriteTest, FailureOverflowOffset) { - // Try to trigger an integer overflow with `dest_addr`. - std::array test_data = {0x12345678, 0xabcdef01}; - sc_otbn_addr_t dest_addr = std::numeric_limits::max(); - - EXPECT_EQ(sc_otbn_dmem_write(test_data.size(), test_data.data(), dest_addr), - kErrorOtbnBadOffsetLen); -} - -class DmemReadTest : public OtbnTest {}; - -TEST_F(DmemReadTest, SuccessWithoutOffset) { - // Assumption in the test. - ASSERT_GE(OTBN_DMEM_SIZE_BYTES, 8); - static_assert(OTBN_DMEM_SIZE_BYTES >= 8, "OTBN DMEM size too small."); - - EXPECT_ABS_READ32(base_ + OTBN_DMEM_REG_OFFSET, 0x12345678); - EXPECT_ABS_READ32(base_ + OTBN_DMEM_REG_OFFSET + 4, 0xabcdef01); - - std::array test_data = {0}; - - sc_otbn_addr_t src_addr = 0; - EXPECT_EQ(sc_otbn_dmem_read(2, src_addr, test_data.data()), kErrorOk); - EXPECT_THAT(test_data, ElementsAre(0x12345678, 0xabcdef01)); -} - -TEST_F(DmemReadTest, SuccessWithOffset) { - // Assumption in the test. - static_assert(OTBN_DMEM_SIZE_BYTES >= 12, "OTBN DMEM size too small."); - - EXPECT_ABS_READ32(base_ + OTBN_DMEM_REG_OFFSET + 4, 0x12345678); - EXPECT_ABS_READ32(base_ + OTBN_DMEM_REG_OFFSET + 8, 0xabcdef01); - - std::array test_data = {0}; - - sc_otbn_addr_t src_addr = 4; - EXPECT_EQ(sc_otbn_dmem_read(2, src_addr, test_data.data()), kErrorOk); - EXPECT_THAT(test_data, ElementsAre(0x12345678, 0xabcdef01)); -} - -class OtbnAppTest : public OtbnTest {}; - -TEST_F(OtbnAppTest, OtbnLoadAppSuccess) { - std::array imem_data = {0x01234567, 0x89abcdef}; - std::array dmem_data = {0x456789ab, 0xcdef0123}; - sc_otbn_addr_t dmem_data_offset = 0x12; - sc_otbn_app_t app = { - .imem_start = imem_data.data(), - .imem_end = imem_data.data() + imem_data.size(), - .dmem_data_start = dmem_data.data(), - .dmem_data_end = dmem_data.data() + imem_data.size(), - .dmem_data_start_addr = dmem_data_offset, - }; - - // Test assumption. - static_assert(OTBN_DMEM_SIZE_BYTES >= sizeof(uint32_t) * dmem_data.size(), - "OTBN DMEM size too small"); - static_assert(OTBN_IMEM_SIZE_BYTES >= sizeof(uint32_t) * imem_data.size(), - "OTBN IMEM size too small"); - - // `sc_otbn_busy_wait_for_done` - begin with busy to ensure we wait until - // idle. - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusBusyExecute); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, - kScOtbnStatusBusySecWipeDmem); - // Read twice for hardening. - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - // `sc_otbn_dmem_sec_wipe` - ExpectCmdRun(kScOtbnCmdSecWipeDmem, err_bits_ok_, kScOtbnStatusIdle); - // `sc_otbn_imem_sec_wipe` - ExpectCmdRun(kScOtbnCmdSecWipeImem, err_bits_ok_, kScOtbnStatusIdle); - // `otbn_imem_write` - EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); - EXPECT_ABS_WRITE32(base_ + OTBN_IMEM_REG_OFFSET, imem_data[0]); - EXPECT_ABS_WRITE32(base_ + OTBN_IMEM_REG_OFFSET + sizeof(uint32_t), - imem_data[1]); - // `sc_otbn_dmem_write` - EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); - EXPECT_ABS_WRITE32(base_ + OTBN_DMEM_REG_OFFSET + dmem_data_offset, - dmem_data[0]); - EXPECT_ABS_WRITE32( - base_ + OTBN_DMEM_REG_OFFSET + dmem_data_offset + sizeof(uint32_t), - dmem_data[1]); - - EXPECT_EQ(sc_otbn_load_app(app), kErrorOk); -} - -TEST_F(OtbnAppTest, OtbnLoadInvalidAppEmptyImem) { - // Create an invalid app with an empty IMEM range. - std::array imem_data = {}; - std::array dmem_data = {0x456789ab, 0xcdef0123}; - sc_otbn_addr_t dmem_data_offset = 0x12; - sc_otbn_app_t app = { - .imem_start = imem_data.data(), - .imem_end = imem_data.data() + imem_data.size(), - .dmem_data_start = dmem_data.data(), - .dmem_data_end = dmem_data.data() + dmem_data.size(), - .dmem_data_start_addr = dmem_data_offset, - }; - - // Test assumption. - static_assert(OTBN_DMEM_SIZE_BYTES >= sizeof(uint32_t) * dmem_data.size(), - "OTBN DMEM size too small"); - static_assert(OTBN_IMEM_SIZE_BYTES >= sizeof(uint32_t) * imem_data.size(), - "OTBN IMEM size too small"); - - EXPECT_EQ(sc_otbn_load_app(app), kErrorOtbnInvalidArgument); -} - -TEST_F(OtbnAppTest, OtbnLoadInvalidAppImemOutOfRange) { - // Create an invalid app with a too-large IMEM range. - std::array - imem_data = {0}; - std::array dmem_data = {0x456789ab, 0xcdef0123}; - sc_otbn_addr_t dmem_data_offset = 0x12; - sc_otbn_app_t app = { - .imem_start = imem_data.data(), - .imem_end = imem_data.data() + imem_data.size(), - .dmem_data_start = dmem_data.data(), - .dmem_data_end = dmem_data.data() + dmem_data.size(), - .dmem_data_start_addr = dmem_data_offset, - }; - - // Read twice for hardening. - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - EXPECT_ABS_READ32(base_ + OTBN_STATUS_REG_OFFSET, kScOtbnStatusIdle); - // `sc_otbn_dmem_sec_wipe` - ExpectCmdRun(kScOtbnCmdSecWipeDmem, err_bits_ok_, kScOtbnStatusIdle); - // `sc_otbn_imem_sec_wipe` - ExpectCmdRun(kScOtbnCmdSecWipeImem, err_bits_ok_, kScOtbnStatusIdle); - - EXPECT_EQ(sc_otbn_load_app(app), kErrorOtbnBadOffsetLen); -} - -class OtbnWriteTest : public OtbnTest {}; - -TEST_F(OtbnWriteTest, Success) { - constexpr uint32_t kDestAddr = 6; - std::array test_data = {0x12345678, 0xabcdef01}; - - // Test assumption. - static_assert( - OTBN_DMEM_SIZE_BYTES >= sizeof(uint32_t) * test_data.size() + kDestAddr, - "OTBN DMEM size too small."); - - EXPECT_CALL(rnd_, Uint32()).WillOnce(Return(0)); - EXPECT_ABS_WRITE32(base_ + OTBN_DMEM_REG_OFFSET + kDestAddr, test_data[0]); - EXPECT_ABS_WRITE32( - base_ + OTBN_DMEM_REG_OFFSET + kDestAddr + sizeof(uint32_t), - test_data[1]); - - EXPECT_EQ(sc_otbn_dmem_write(2, test_data.data(), kDestAddr), kErrorOk); -} - -class OtbnReadTest : public OtbnTest {}; - -TEST_F(OtbnReadTest, Success) { - constexpr uint32_t kSrcAddr = 6; - std::array test_data = {0}; - - // Test assumption. - static_assert( - OTBN_DMEM_SIZE_BYTES >= sizeof(uint32_t) * test_data.size() + kSrcAddr, - "OTBN DMEM size too small."); - - EXPECT_ABS_READ32(base_ + OTBN_DMEM_REG_OFFSET + kSrcAddr, 0x12345678); - EXPECT_ABS_READ32(base_ + OTBN_DMEM_REG_OFFSET + kSrcAddr + sizeof(uint32_t), - 0xabcdef01); - - EXPECT_EQ(sc_otbn_dmem_read(2, kSrcAddr, test_data.data()), kErrorOk); - EXPECT_THAT(test_data, ElementsAre(0x12345678, 0xabcdef01)); -} -} // namespace -} // namespace otbn_unittest diff --git a/sw/device/silicon_creator/lib/error.h b/sw/device/silicon_creator/lib/error.h index 6bdaf8c0fe6..c6b83fe0767 100644 --- a/sw/device/silicon_creator/lib/error.h +++ b/sw/device/silicon_creator/lib/error.h @@ -34,7 +34,7 @@ enum module_ { kModuleInterrupt = MODULE_CODE('I', 'R'), kModuleEpmp = MODULE_CODE('E', 'P'), kModuleKmac = MODULE_CODE('K', 'C'), - kModuleOtbn = MODULE_CODE('B', 'N'), + kModuleAcc = MODULE_CODE('B', 'N'), kModuleFlashCtrl = MODULE_CODE('F', 'C'), kModuleBootPolicy = MODULE_CODE('B', 'P'), kModuleBootstrap = MODULE_CODE('B', 'S'), @@ -124,13 +124,13 @@ enum module_ { X(kErrorKmacInvalidStatus, ERROR_(1, kModuleKmac, kInternal)), \ X(kErrorKmacInvalidKeySize, ERROR_(2, kModuleKmac, kInvalidArgument)), \ \ - X(kErrorOtbnInvalidArgument, ERROR_(1, kModuleOtbn, kInvalidArgument)), \ - X(kErrorOtbnBadOffsetLen, ERROR_(2, kModuleOtbn, kInvalidArgument)), \ - X(kErrorOtbnExecutionFailed, ERROR_(3, kModuleOtbn, kInternal)), \ - X(kErrorOtbnSecWipeImemFailed, ERROR_(4, kModuleOtbn, kInternal)), \ - X(kErrorOtbnSecWipeDmemFailed, ERROR_(5, kModuleOtbn, kInternal)), \ - X(kErrorOtbnBadInsnCount, ERROR_(6, kModuleOtbn, kInternal)), \ - X(kErrorOtbnUnavailable, ERROR_(7, kModuleOtbn, kInternal)), \ + X(kErrorAccInvalidArgument, ERROR_(1, kModuleAcc, kInvalidArgument)), \ + X(kErrorAccBadOffsetLen, ERROR_(2, kModuleAcc, kInvalidArgument)), \ + X(kErrorAccExecutionFailed, ERROR_(3, kModuleAcc, kInternal)), \ + X(kErrorAccSecWipeImemFailed, ERROR_(4, kModuleAcc, kInternal)), \ + X(kErrorAccSecWipeDmemFailed, ERROR_(5, kModuleAcc, kInternal)), \ + X(kErrorAccBadInsnCount, ERROR_(6, kModuleAcc, kInternal)), \ + X(kErrorAccUnavailable, ERROR_(7, kModuleAcc, kInternal)), \ \ X(kErrorFlashCtrlDataRead, ERROR_(1, kModuleFlashCtrl, kInternal)), \ X(kErrorFlashCtrlInfoRead, ERROR_(2, kModuleFlashCtrl, kInternal)), \ diff --git a/sw/device/silicon_creator/lib/otbn_boot_services.c b/sw/device/silicon_creator/lib/otbn_boot_services.c deleted file mode 100644 index 4a780f19a51..00000000000 --- a/sw/device/silicon_creator/lib/otbn_boot_services.c +++ /dev/null @@ -1,318 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" - -#include "sw/device/lib/base/memory.h" -#include "sw/device/silicon_creator/lib/attestation.h" -#include "sw/device/silicon_creator/lib/base/sec_mmio.h" -#include "sw/device/silicon_creator/lib/base/util.h" -#include "sw/device/silicon_creator/lib/dbg_print.h" -#include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" -#include "sw/device/silicon_creator/lib/drivers/hmac.h" -#include "sw/device/silicon_creator/lib/drivers/keymgr.h" -#include "sw/device/silicon_creator/lib/drivers/otbn.h" - -#include "hw/top/otbn_regs.h" // Generated. - -static_assert(kAttestationSeedWords <= 16, - "Additional attestation seed needs must be <= 516 bits."); - -OTBN_DECLARE_APP_SYMBOLS(boot); // The OTBN boot-services app. -OTBN_DECLARE_SYMBOL_ADDR(boot, mode); // Application mode. -OTBN_DECLARE_SYMBOL_ADDR(boot, msg); // ECDSA message digest. -OTBN_DECLARE_SYMBOL_ADDR(boot, x); // ECDSA public key x-coordinate. -OTBN_DECLARE_SYMBOL_ADDR(boot, y); // ECDSA public key y-coordinate. -OTBN_DECLARE_SYMBOL_ADDR(boot, r); // ECDSA signature component r. -OTBN_DECLARE_SYMBOL_ADDR(boot, s); // ECDSA signature component s. -OTBN_DECLARE_SYMBOL_ADDR(boot, x_r); // ECDSA verification result. -OTBN_DECLARE_SYMBOL_ADDR(boot, ok); // ECDSA verification status. -OTBN_DECLARE_SYMBOL_ADDR( - boot, attestation_additional_seed); // Additional seed for ECDSA keygen. - -static const sc_otbn_app_t kOtbnAppBoot = OTBN_APP_T_INIT(boot); -static const sc_otbn_addr_t kOtbnVarBootMode = OTBN_ADDR_T_INIT(boot, mode); -static const sc_otbn_addr_t kOtbnVarBootMsg = OTBN_ADDR_T_INIT(boot, msg); -static const sc_otbn_addr_t kOtbnVarBootX = OTBN_ADDR_T_INIT(boot, x); -static const sc_otbn_addr_t kOtbnVarBootY = OTBN_ADDR_T_INIT(boot, y); -static const sc_otbn_addr_t kOtbnVarBootR = OTBN_ADDR_T_INIT(boot, r); -static const sc_otbn_addr_t kOtbnVarBootS = OTBN_ADDR_T_INIT(boot, s); -static const sc_otbn_addr_t kOtbnVarBootXr = OTBN_ADDR_T_INIT(boot, x_r); -static const sc_otbn_addr_t kOtbnVarBootOk = OTBN_ADDR_T_INIT(boot, ok); -static const sc_otbn_addr_t kOtbnVarBootAttestationAdditionalSeed = - OTBN_ADDR_T_INIT(boot, attestation_additional_seed); - -enum { - /* - * Mode is represented by a single word. - */ - kOtbnBootModeWords = 1, - /* - * Mode to run signature verification. - * - * Value taken from `boot.s`. - */ - kOtbnBootModeSigverify = 0x7d3, - /* - * Mode to generate an attestation keypair. - * - * Value taken from `boot.s`. - */ - kOtbnBootModeAttestationKeygen = 0x2bf, - /* - * Mode to endorse a message with a saved private key. - * - * Value taken from `boot.s`. - */ - kOtbnBootModeAttestationEndorse = 0x5e8, - /* - * Mode to save an attesation private key. - * - * Value taken from `boot.s`. - */ - kOtbnBootModeAttestationKeySave = 0x64d, - /* Size of the OTBN attestation seed buffer in 32-bit words (rounding the - attestation seed size up to the next OTBN wide word). */ - kOtbnAttestationSeedBufferWords = - ((kAttestationSeedWords + kScOtbnWideWordNumWords - 1) / - kScOtbnWideWordNumWords) * - kScOtbnWideWordNumWords, -}; - -OT_WARN_UNUSED_RESULT -static rom_error_t load_attestation_keygen_seed(uint32_t additional_seed_idx, - uint32_t *seed) { - // Read seed from flash info page. - uint32_t seed_flash_offset = - 0 + (additional_seed_idx * kAttestationSeedBytes); - rom_error_t err = - flash_ctrl_info_read(&kFlashCtrlInfoPageAttestationKeySeeds, - seed_flash_offset, kAttestationSeedWords, seed); - - if (err != kErrorOk) { - flash_ctrl_error_code_t flash_ctrl_err_code; - flash_ctrl_error_code_get(&flash_ctrl_err_code); - if (flash_ctrl_err_code.rd_err) { - // If we encountered a read error, this means the attestation seed page - // has not been provisioned yet. In this case, we clear the seed and - // continue, which will simply result in generating an invalid identity. - memset(seed, 0, kAttestationSeedBytes); - return kErrorOk; - } - return err; - } - - return kErrorOk; -} - -rom_error_t otbn_boot_app_load(void) { return sc_otbn_load_app(kOtbnAppBoot); } - -rom_error_t otbn_boot_attestation_keygen( - uint32_t additional_seed_idx, sc_keymgr_key_type_t key_type, - sc_keymgr_diversification_t diversification, - ecdsa_p256_public_key_t *public_key) { - // Trigger key manager to sideload the attestation key into OTBN. - HARDENED_RETURN_IF_ERROR( - sc_keymgr_generate_key_otbn(key_type, diversification)); - - // Write the mode. - uint32_t mode = kOtbnBootModeAttestationKeygen; - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kOtbnBootModeWords, &mode, kOtbnVarBootMode)); - - // Load the additional seed from flash info. - uint32_t seed[kAttestationSeedWords]; - HARDENED_RETURN_IF_ERROR( - load_attestation_keygen_seed(additional_seed_idx, seed)); - - // Write the additional seed to OTBN DMEM. - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_write( - kAttestationSeedWords, seed, kOtbnVarBootAttestationAdditionalSeed)); - // Pad remaining DMEM field with zeros to prevent a DMEM integrity error - // (since data is aligned to 256-bit words). - uint32_t zero_buf[kOtbnAttestationSeedBufferWords - kAttestationSeedWords] = { - 0}; - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_write( - ARRAYSIZE(zero_buf), zero_buf, - kOtbnVarBootAttestationAdditionalSeed + kAttestationSeedBytes)); - - // Run the OTBN program (blocks until OTBN is done). - HARDENED_RETURN_IF_ERROR(sc_otbn_execute()); - SEC_MMIO_WRITE_INCREMENT(kScOtbnSecMmioExecute); - - // TODO(#20023): Check the instruction count register (see `mod_exp_otbn`). - - // Retrieve the public key. - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_read(kEcdsaP256PublicKeyCoordWords, - kOtbnVarBootX, public_key->x)); - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_read(kEcdsaP256PublicKeyCoordWords, - kOtbnVarBootY, public_key->y)); - - return kErrorOk; -} - -/** - * Helper function to convert an ECC P256 public key from little to big endian - * in place. - */ -static void pubkey_le_to_be_convert(ecdsa_p256_public_key_t *pubkey) { - util_reverse_bytes(pubkey->x, kEcdsaP256PublicKeyCoordBytes); - util_reverse_bytes(pubkey->y, kEcdsaP256PublicKeyCoordBytes); -} - -rom_error_t otbn_boot_cert_ecc_p256_keygen(sc_keymgr_ecc_key_t key, - hmac_digest_t *pubkey_id, - ecdsa_p256_public_key_t *pubkey) { - HARDENED_RETURN_IF_ERROR(sc_keymgr_state_check(key.required_keymgr_state)); - - // Generate / sideload key material into OTBN, and generate the ECC keypair. - HARDENED_RETURN_IF_ERROR(otbn_boot_attestation_keygen( - key.keygen_seed_idx, key.type, *key.keymgr_diversifier, pubkey)); - - // Keys are represented in certificates in big endian format, but the key is - // output from OTBN in little endian format, so we convert the key to - // big endian format. - pubkey_le_to_be_convert(pubkey); - - // Generate the key ID. - // - // Note: the certificate generation functions expect the digest to be in big - // endian form, but the HMAC driver returns the digest in little endian, so we - // re-format it. - hmac_sha256(pubkey, sizeof(*pubkey), pubkey_id); - util_reverse_bytes(pubkey_id, sizeof(*pubkey_id)); - - return kErrorOk; -} - -rom_error_t otbn_boot_attestation_key_save( - uint32_t additional_seed_idx, sc_keymgr_key_type_t key_type, - sc_keymgr_diversification_t diversification) { - // Trigger key manager to sideload the attestation key into OTBN. - HARDENED_RETURN_IF_ERROR( - sc_keymgr_generate_key_otbn(key_type, diversification)); - - // Write the mode. - uint32_t mode = kOtbnBootModeAttestationKeySave; - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kOtbnBootModeWords, &mode, kOtbnVarBootMode)); - - // Load the additional seed from flash info. - uint32_t seed[kAttestationSeedWords]; - HARDENED_RETURN_IF_ERROR( - load_attestation_keygen_seed(additional_seed_idx, seed)); - // Pad remaining DMEM field with zeros to prevent a DMEM integrity error - // (since data is aligned to 256-bit words). - uint32_t zero_buf[kOtbnAttestationSeedBufferWords - kAttestationSeedWords] = { - 0}; - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_write( - ARRAYSIZE(zero_buf), zero_buf, - kOtbnVarBootAttestationAdditionalSeed + kAttestationSeedBytes)); - - // Write the additional seed to OTBN DMEM. - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_write( - kAttestationSeedWords, seed, kOtbnVarBootAttestationAdditionalSeed)); - - // Run the OTBN program (blocks until OTBN is done). - HARDENED_RETURN_IF_ERROR(sc_otbn_execute()); - SEC_MMIO_WRITE_INCREMENT(kScOtbnSecMmioExecute); - - // TODO(#20023): Check the instruction count register (see `mod_exp_otbn`). - - return kErrorOk; -} - -rom_error_t otbn_boot_attestation_key_clear(void) { - // Trigger a full DMEM wipe. - RETURN_IF_ERROR(sc_otbn_dmem_sec_wipe()); - HARDENED_RETURN_IF_ERROR(sc_otbn_busy_wait_for_done()); - - // Re-load the data portion of the boot services app. This is like a - // stripped-down version of `sc_otbn_load_app`, where we skip the IMEM. - if (kOtbnAppBoot.dmem_data_end < kOtbnAppBoot.dmem_data_start) { - return kErrorOtbnInvalidArgument; - } - HARDENED_CHECK_GE(kOtbnAppBoot.dmem_data_end, kOtbnAppBoot.dmem_data_start); - const size_t data_num_words = - (size_t)(kOtbnAppBoot.dmem_data_end - kOtbnAppBoot.dmem_data_start); - if (data_num_words > 0) { - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(data_num_words, kOtbnAppBoot.dmem_data_start, - kOtbnAppBoot.dmem_data_start_addr)); - } - return kErrorOk; -} - -rom_error_t otbn_boot_attestation_endorse(const hmac_digest_t *digest, - ecdsa_p256_signature_t *sig) { - // Write the mode. - uint32_t mode = kOtbnBootModeAttestationEndorse; - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kOtbnBootModeWords, &mode, kOtbnVarBootMode)); - - // Write the message digest. - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kHmacDigestNumWords, digest->digest, kOtbnVarBootMsg)); - - // Run the OTBN program (blocks until OTBN is done). - HARDENED_RETURN_IF_ERROR(sc_otbn_execute()); - SEC_MMIO_WRITE_INCREMENT(kScOtbnSecMmioExecute); - - // TODO(#20023): Check the instruction count register (see `mod_exp_otbn`). - - // Retrieve the signature (in two parts, r and s). - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_read(kEcdsaP256SignatureComponentWords, - kOtbnVarBootR, sig->r)); - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_read(kEcdsaP256SignatureComponentWords, - kOtbnVarBootS, sig->s)); - - return kErrorOk; -} - -rom_error_t otbn_boot_sigverify(const ecdsa_p256_public_key_t *key, - const ecdsa_p256_signature_t *sig, - const hmac_digest_t *digest, - uint32_t *recovered_r) { - // Write the mode. - uint32_t mode = kOtbnBootModeSigverify; - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kOtbnBootModeWords, &mode, kOtbnVarBootMode)); - - // Write the public key. - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kEcdsaP256PublicKeyCoordWords, key->x, kOtbnVarBootX)); - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kEcdsaP256PublicKeyCoordWords, key->y, kOtbnVarBootY)); - - // Write the message digest. - HARDENED_RETURN_IF_ERROR( - sc_otbn_dmem_write(kHmacDigestNumWords, digest->digest, kOtbnVarBootMsg)); - - // Write the signature. - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_write(kEcdsaP256SignatureComponentWords, - sig->r, kOtbnVarBootR)); - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_write(kEcdsaP256SignatureComponentWords, - sig->s, kOtbnVarBootS)); - - // Start the OTBN routine. - HARDENED_RETURN_IF_ERROR(sc_otbn_execute()); - SEC_MMIO_WRITE_INCREMENT(kScOtbnSecMmioExecute); - - // Check if the signature passed basic checks. - uint32_t ok; - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_read(1, kOtbnVarBootOk, &ok)); - if (launder32(ok) != kHardenedBoolTrue) { - return kErrorSigverifyBadEcdsaSignature; - } - - // Read the status value again as an extra hardening measure. - HARDENED_RETURN_IF_ERROR(sc_otbn_dmem_read(1, kOtbnVarBootOk, &ok)); - HARDENED_CHECK_EQ(ok, kHardenedBoolTrue); - - // TODO(#20023): Check the instruction count register (see `mod_exp_otbn`). - - // Read the recovered `r` value from DMEM. - return sc_otbn_dmem_read(kEcdsaP256SignatureComponentWords, kOtbnVarBootXr, - recovered_r); -} diff --git a/sw/device/silicon_creator/lib/ownership/BUILD b/sw/device/silicon_creator/lib/ownership/BUILD index 94c7f6df1e9..23978d17a58 100644 --- a/sw/device/silicon_creator/lib/ownership/BUILD +++ b/sw/device/silicon_creator/lib/ownership/BUILD @@ -30,7 +30,7 @@ cc_library( srcs = ["ecdsa.c"], hdrs = ["ecdsa.h"], defines = [ - "USE_OTBN=1", + "USE_ACC=1", #"USE_CRYPTOC=1", ], deps = [ @@ -41,7 +41,7 @@ cc_library( "//sw/device/lib/base:macros", "//sw/device/silicon_creator/lib:error", "//sw/device/silicon_creator/lib/drivers:hmac", - "//sw/device/silicon_creator/lib:otbn_boot_services", + "//sw/device/silicon_creator/lib:acc_boot_services", #"//sw/vendor:cryptoc", ], ) diff --git a/sw/device/silicon_creator/lib/ownership/ecdsa.c b/sw/device/silicon_creator/lib/ownership/ecdsa.c index 1f594abe646..8b17e7956b9 100644 --- a/sw/device/silicon_creator/lib/ownership/ecdsa.c +++ b/sw/device/silicon_creator/lib/ownership/ecdsa.c @@ -9,8 +9,8 @@ #include "sw/device/lib/base/hardened_memory.h" #include "sw/device/lib/base/macros.h" #include "sw/device/silicon_creator/lib/drivers/hmac.h" -#if USE_OTBN == 1 -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" +#if USE_ACC == 1 +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #elif USE_CRYPTOC == 1 // TODO(cfrantz): Replace the CryptoC implementation with a native OpenTitan // implementation. @@ -29,8 +29,8 @@ OT_WEAK void __assert_func(const char *file, int line, const char *func, #endif rom_error_t ecdsa_init(void) { -#if USE_OTBN == 1 - return otbn_boot_app_load(); +#if USE_ACC == 1 + return acc_boot_app_load(); #elif USE_CRYPTOC == 1 return kErrorOk; #endif @@ -39,9 +39,9 @@ rom_error_t ecdsa_init(void) { hardened_bool_t ecdsa_verify_digest(const ecdsa_p256_public_key_t *pubkey, const ecdsa_p256_signature_t *signature, const hmac_digest_t *digest) { -#if USE_OTBN == 1 +#if USE_ACC == 1 uint32_t rr[8]; - rom_error_t error = otbn_boot_sigverify(pubkey, signature, digest, rr); + rom_error_t error = acc_boot_sigverify(pubkey, signature, digest, rr); if (error != kErrorOk) { return kHardenedBoolFalse; } diff --git a/sw/device/silicon_creator/lib/shutdown_unittest.cc b/sw/device/silicon_creator/lib/shutdown_unittest.cc index 1dd2507cdb9..704a7637ea9 100644 --- a/sw/device/silicon_creator/lib/shutdown_unittest.cc +++ b/sw/device/silicon_creator/lib/shutdown_unittest.cc @@ -155,8 +155,8 @@ constexpr uint32_t Pack32(uint8_t a, uint8_t b, uint8_t c, uint8_t d) { Xmacro("Edn1FatalAlert", A, A, X, X), \ Xmacro("SramCtrlMainFatalIntgError", A, A, X, X), \ Xmacro("SramCtrlMainFatalParityError", A, A, X, X), \ - Xmacro("OtbnFatal", A, A, X, X), \ - Xmacro("OtbnRecov", D, D, X, X), \ + Xmacro("AccFatal", A, A, X, X), \ + Xmacro("AccRecov", D, D, X, X), \ Xmacro("RomCtrlFatal", A, A, X, X), \ Xmacro("Dummy61", X, X, X, X), \ Xmacro("Dummy62", X, X, X, X), \ diff --git a/sw/device/silicon_creator/lib/sigverify/BUILD b/sw/device/silicon_creator/lib/sigverify/BUILD index 6bbf7214cb6..3ea922e843f 100644 --- a/sw/device/silicon_creator/lib/sigverify/BUILD +++ b/sw/device/silicon_creator/lib/sigverify/BUILD @@ -139,7 +139,7 @@ cc_library( deps = [ ":ecdsa_p256_key", "//sw/device/lib/base:hardened", - "//sw/device/silicon_creator/lib:otbn_boot_services", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib/drivers:hmac", ], ) diff --git a/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify.c b/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify.c index 4278b362ead..82032f6096e 100644 --- a/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify.c +++ b/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify.c @@ -5,7 +5,7 @@ #include "sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify.h" #include "sw/device/lib/base/macros.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/sigverify/ecdsa_p256_key.h" #include "hw/top/otp_ctrl_regs.h" @@ -124,7 +124,7 @@ rom_error_t sigverify_ecdsa_p256_verify(const ecdsa_p256_signature_t *signature, uint32_t *flash_exec) { ecdsa_p256_signature_t recovered_r; rom_error_t error = - otbn_boot_sigverify(key, signature, act_digest, (uint32_t *)&recovered_r); + acc_boot_sigverify(key, signature, act_digest, (uint32_t *)&recovered_r); if (launder32(error) != kErrorOk) { *flash_exec ^= UINT32_MAX; return error; diff --git a/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify_functest.c b/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify_functest.c index 631e869f735..0152f4197f1 100644 --- a/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify_functest.c +++ b/sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify_functest.c @@ -4,7 +4,7 @@ #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify.h" OTTF_DEFINE_TEST_CONFIG(); @@ -113,7 +113,7 @@ rom_error_t ecdsa_p256_verify_negative_test(void) { } bool test_main(void) { - CHECK(otbn_boot_app_load() == kErrorOk); + CHECK(acc_boot_app_load() == kErrorOk); status_t result = OK_STATUS(); hmac_sha256(kTestMessage, kTestMessageLen, &digest); diff --git a/sw/device/silicon_creator/lib/sigverify/rsa_key.h b/sw/device/silicon_creator/lib/sigverify/rsa_key.h index 07f7053e8c5..44c65a21c65 100644 --- a/sw/device/silicon_creator/lib/sigverify/rsa_key.h +++ b/sw/device/silicon_creator/lib/sigverify/rsa_key.h @@ -49,7 +49,7 @@ typedef struct sigverify_rsa_key { /** * Negative of the multiplicative inverse of n modulo 2^256, little-endian. * - * Calculations performed on OTBN (word size: 256 bits) use the whole array + * Calculations performed on ACC (word size: 256 bits) use the whole array * while calculations performed on Ibex (word size: 32 bits) use only the * first word, which is equal to -n^-1 mod 2^32. */ diff --git a/sw/device/silicon_creator/lib/sigverify/rsa_verify.h b/sw/device/silicon_creator/lib/sigverify/rsa_verify.h index 60e7973b678..6844311af0a 100644 --- a/sw/device/silicon_creator/lib/sigverify/rsa_verify.h +++ b/sw/device/silicon_creator/lib/sigverify/rsa_verify.h @@ -25,7 +25,7 @@ enum { /** * Verifies an RSASSA-PKCS1-v1_5 signature. * - * The actual implementation that is used (software or OTBN) is determined by + * The actual implementation that is used (software or ACC) is determined by * the life cycle state of the device and the OTP value. * * @param signature Signature to be verified. diff --git a/sw/device/silicon_creator/lib/sigverify/sigverify_tests/BUILD b/sw/device/silicon_creator/lib/sigverify/sigverify_tests/BUILD index a87c4c62086..6f45f715c03 100644 --- a/sw/device/silicon_creator/lib/sigverify/sigverify_tests/BUILD +++ b/sw/device/silicon_creator/lib/sigverify/sigverify_tests/BUILD @@ -44,7 +44,7 @@ opentitan_test( "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/lib/testing/test_framework:ujson_ottf", "//sw/device/lib/ujson", - "//sw/device/silicon_creator/lib:otbn_boot_services", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib/drivers:hmac", "//sw/device/silicon_creator/lib/sigverify:ecdsa_p256_key", "//sw/device/silicon_creator/lib/sigverify:ecdsa_p256_verify", diff --git a/sw/device/silicon_creator/lib/sigverify/sigverify_tests/sigverify_cryptotest.c b/sw/device/silicon_creator/lib/sigverify/sigverify_tests/sigverify_cryptotest.c index 70d0057a2fd..44f0e368680 100644 --- a/sw/device/silicon_creator/lib/sigverify/sigverify_tests/sigverify_cryptotest.c +++ b/sw/device/silicon_creator/lib/sigverify/sigverify_tests/sigverify_cryptotest.c @@ -8,8 +8,8 @@ #include "sw/device/lib/testing/test_framework/ottf_main.h" #include "sw/device/lib/testing/test_framework/ujson_ottf.h" #include "sw/device/lib/ujson/ujson.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/drivers/hmac.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/lib/sigverify/ecdsa_p256_key.h" #include "sw/device/silicon_creator/lib/sigverify/ecdsa_p256_verify.h" #include "sw/device/tests/crypto/cryptotest/json/ecdsa_commands.h" @@ -182,7 +182,7 @@ status_t process_cmd(ujson_t *uj) { } bool test_main(void) { - CHECK(otbn_boot_app_load() == kErrorOk); + CHECK(acc_boot_app_load() == kErrorOk); ujson_t uj = ujson_ottf_console(); return status_ok(process_cmd(&uj)); diff --git a/sw/device/silicon_creator/manuf/base/BUILD b/sw/device/silicon_creator/manuf/base/BUILD index d2ab0dcd2f9..de38365fdc2 100644 --- a/sw/device/silicon_creator/manuf/base/BUILD +++ b/sw/device/silicon_creator/manuf/base/BUILD @@ -264,8 +264,8 @@ cc_library( "//sw/device/lib/runtime:print", "//sw/device/lib/testing/test_framework:status", "//sw/device/lib/testing/test_framework:ujson_ottf", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib:attestation", - "//sw/device/silicon_creator/lib:otbn_boot_services", "//sw/device/silicon_creator/lib/cert", "//sw/device/silicon_creator/lib/cert:tpm", "//sw/device/silicon_creator/lib/cert:tpm_ek_template_library", @@ -289,7 +289,7 @@ cc_library( # Need a separate library for the headers, because adding a dependency on #//sw/device/silicon_creator/lib/cert required by perso_tlv_data above causes -# bindgen failures due to otbn (which is a cert dependency) requiring risc32 +# bindgen failures due to acc (which is a cert dependency) requiring risc32 # environment. cc_library( name = "perso_tlv_headers", @@ -341,9 +341,9 @@ manifest(d = { "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/lib/testing/test_framework:status", "//sw/device/lib/testing/test_framework:ujson_ottf", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib:attestation", "//sw/device/silicon_creator/lib:boot_data", - "//sw/device/silicon_creator/lib:otbn_boot_services", "//sw/device/silicon_creator/lib/base:chip", "//sw/device/silicon_creator/lib/base:util", "//sw/device/silicon_creator/lib/cert", diff --git a/sw/device/silicon_creator/manuf/base/ft_personalize.c b/sw/device/silicon_creator/manuf/base/ft_personalize.c index 1857ba4300a..1dce786dd9d 100644 --- a/sw/device/silicon_creator/manuf/base/ft_personalize.c +++ b/sw/device/silicon_creator/manuf/base/ft_personalize.c @@ -20,6 +20,7 @@ #include "sw/device/lib/testing/test_framework/ottf_test_config.h" #include "sw/device/lib/testing/test_framework/status.h" #include "sw/device/lib/testing/test_framework/ujson_ottf.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/attestation.h" #include "sw/device/silicon_creator/lib/base/boot_measurements.h" #include "sw/device/silicon_creator/lib/base/chip.h" @@ -37,7 +38,6 @@ #include "sw/device/silicon_creator/lib/drivers/otp.h" #include "sw/device/silicon_creator/lib/error.h" #include "sw/device/silicon_creator/lib/manifest.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/lib/ownership/datatypes.h" #include "sw/device/silicon_creator/lib/ownership/owner_block.h" #include "sw/device/silicon_creator/lib/ownership/ownership_key.h" @@ -446,9 +446,9 @@ static status_t personalize_gen_dice_certificates(ujson_t *uj) { /***************************************************************************** * Initialization. ****************************************************************************/ - // Load OTBN attestation keygen program. + // Load ACC attestation keygen program. // TODO(#21550): this should already be loaded by the ROM. - TRY(otbn_boot_app_load()); + TRY(acc_boot_app_load()); // Configure certificate flash info page permissions. TRY(config_and_erase_certificate_flash_pages()); @@ -501,12 +501,11 @@ static status_t personalize_gen_dice_certificates(ujson_t *uj) { // Generate UDS keys and (TBS) cert. curr_cert_size = kUdsMaxTbsSizeBytes; - TRY(otbn_boot_cert_ecc_p256_keygen(kDiceKeyUds, &uds_pubkey_id, - &curr_pubkey)); + TRY(acc_boot_cert_ecc_p256_keygen(kDiceKeyUds, &uds_pubkey_id, &curr_pubkey)); memcpy(&uds_pubkey, &curr_pubkey, sizeof(ecdsa_p256_public_key_t)); - TRY(otbn_boot_attestation_key_save(kDiceKeyUds.keygen_seed_idx, - kDiceKeyUds.type, - *kDiceKeyUds.keymgr_diversifier)); + TRY(acc_boot_attestation_key_save(kDiceKeyUds.keygen_seed_idx, + kDiceKeyUds.type, + *kDiceKeyUds.keymgr_diversifier)); // Build the certificate in a temp buffer, use all_certs for that. TRY(dice_uds_tbs_cert_build( @@ -532,8 +531,8 @@ static status_t personalize_gen_dice_certificates(ujson_t *uj) { TRY(sc_keymgr_owner_int_advance(&sealing_binding_value, &attestation_binding_value, /*max_key_version=*/0)); - TRY(otbn_boot_cert_ecc_p256_keygen(kDiceKeyCdi0, &cdi_0_pubkey_id, - &curr_pubkey)); + TRY(acc_boot_cert_ecc_p256_keygen(kDiceKeyCdi0, &cdi_0_pubkey_id, + &curr_pubkey)); TRY(dice_cdi_0_cert_build((hmac_digest_t *)certgen_inputs.rom_ext_measurement, certgen_inputs.rom_ext_security_version, &cdi_0_key_ids, &curr_pubkey, all_certs, @@ -552,8 +551,8 @@ static status_t personalize_gen_dice_certificates(ujson_t *uj) { TRY(sc_keymgr_owner_advance(&sealing_binding_value, &attestation_binding_value, /*max_key_version=*/0)); - TRY(otbn_boot_cert_ecc_p256_keygen(kDiceKeyCdi1, &cdi_1_pubkey_id, - &curr_pubkey)); + TRY(acc_boot_cert_ecc_p256_keygen(kDiceKeyCdi1, &cdi_1_pubkey_id, + &curr_pubkey)); TRY(dice_cdi_1_cert_build( (hmac_digest_t *)certgen_inputs.owner_measurement, (hmac_digest_t *)certgen_inputs.owner_manifest_measurement, diff --git a/sw/device/silicon_creator/manuf/base/tpm_personalize_ext.c b/sw/device/silicon_creator/manuf/base/tpm_personalize_ext.c index 29dad258639..1abc6e14ca8 100644 --- a/sw/device/silicon_creator/manuf/base/tpm_personalize_ext.c +++ b/sw/device/silicon_creator/manuf/base/tpm_personalize_ext.c @@ -7,13 +7,13 @@ #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/test_framework/status.h" #include "sw/device/lib/testing/test_framework/ujson_ottf.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/attestation.h" #include "sw/device/silicon_creator/lib/cert/cert.h" #include "sw/device/silicon_creator/lib/cert/tpm.h" #include "sw/device/silicon_creator/lib/cert/tpm_ek.h" // Generated. #include "sw/device/silicon_creator/lib/drivers/flash_ctrl.h" #include "sw/device/silicon_creator/lib/drivers/hmac.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/manuf/base/personalize_ext.h" #include "sw/device/silicon_creator/manuf/lib/personalize.h" @@ -75,7 +75,7 @@ static status_t personalize_gen_tpm_ek_certificate( kAttestationSeedWords)); // Generate TPM EK keys and (TBS) cert. - TRY(otbn_boot_cert_ecc_p256_keygen(kTpmKeyEk, &tpm_pubkey_id, &curr_pubkey)); + TRY(acc_boot_cert_ecc_p256_keygen(kTpmKeyEk, &tpm_pubkey_id, &curr_pubkey)); curr_cert_size = sizeof(cert_buffer); TRY(tpm_ek_tbs_cert_build(&tpm_key_ids, &curr_pubkey, cert_buffer, diff --git a/sw/device/silicon_creator/rom/BUILD b/sw/device/silicon_creator/rom/BUILD index 0086f2b56a3..7dc1dc9d857 100644 --- a/sw/device/silicon_creator/rom/BUILD +++ b/sw/device/silicon_creator/rom/BUILD @@ -161,6 +161,7 @@ cc_library( "//sw/device/lib/base:stdasm", "//sw/device/lib/crt", "//sw/device/lib/runtime:hart", + "//sw/device/silicon_creator/lib:acc_boot_services", "//sw/device/silicon_creator/lib:boot_log", "//sw/device/silicon_creator/lib:cfi", "//sw/device/silicon_creator/lib:chip_info", @@ -168,7 +169,6 @@ cc_library( "//sw/device/silicon_creator/lib:error", "//sw/device/silicon_creator/lib:irq_asm", "//sw/device/silicon_creator/lib:manifest", - "//sw/device/silicon_creator/lib:otbn_boot_services", "//sw/device/silicon_creator/lib:shutdown", "//sw/device/silicon_creator/lib:stack_utilization", "//sw/device/silicon_creator/lib/base:chip", diff --git a/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_fpga_cw310.elf b/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_fpga_cw310.elf index 74cd2d80c37..8501ea36bdc 100644 Binary files a/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_fpga_cw310.elf and b/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_fpga_cw310.elf differ diff --git a/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_dv.elf b/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_dv.elf index 3cdbdd701d0..81eaa86f641 100644 Binary files a/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_dv.elf and b/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_dv.elf differ diff --git a/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_verilator.elf b/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_verilator.elf index 4faf8616f26..f62f20eb2a8 100644 Binary files a/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_verilator.elf and b/sw/device/silicon_creator/rom/binaries/rom_with_real_keys_sim_verilator.elf differ diff --git a/sw/device/silicon_creator/rom/doc/shutdown.md b/sw/device/silicon_creator/rom/doc/shutdown.md index 36133f8d566..5d435edd4d7 100644 --- a/sw/device/silicon_creator/rom/doc/shutdown.md +++ b/sw/device/silicon_creator/rom/doc/shutdown.md @@ -143,8 +143,8 @@ The suggested default classification is detailed in the following table. | Edn1FatalAlert | 48 | X | A | A | D | X | X | | Edn1RecovAlert | 49 | X | D | D | D | X | X | | SramCtrlMainFatalError | 50 | X | A | A | D | X | X | -| OtbnFatal | 51 | X | A | A | D | X | X | -| OtbnRecov | 52 | X | D | D | D | X | X | +| AccFatal | 51 | X | A | A | D | X | X | +| AccRecov | 52 | X | D | D | D | X | X | | RomCtrlFatal | 53 | X | A | A | D | X | X | | RvCoreIbexFatalSwErr | 54 | X | A | A | D | X | X | | RvCoreIbexRecovSwErr | 55 | X | D | D | D | X | X | diff --git a/sw/device/silicon_creator/rom/rom.c b/sw/device/silicon_creator/rom/rom.c index 0f646a47656..1edf82e6b0b 100644 --- a/sw/device/silicon_creator/rom/rom.c +++ b/sw/device/silicon_creator/rom/rom.c @@ -15,6 +15,7 @@ #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/stdasm.h" +#include "sw/device/silicon_creator/lib/acc_boot_services.h" #include "sw/device/silicon_creator/lib/base/boot_measurements.h" #include "sw/device/silicon_creator/lib/base/sec_mmio.h" #include "sw/device/silicon_creator/lib/base/static_critical_version.h" @@ -39,7 +40,6 @@ #include "sw/device/silicon_creator/lib/drivers/uart.h" #include "sw/device/silicon_creator/lib/drivers/watchdog.h" #include "sw/device/silicon_creator/lib/error.h" -#include "sw/device/silicon_creator/lib/otbn_boot_services.h" #include "sw/device/silicon_creator/lib/shutdown.h" #include "sw/device/silicon_creator/lib/sigverify/sigverify.h" #include "sw/device/silicon_creator/lib/stack_utilization.h" @@ -326,10 +326,10 @@ static rom_error_t rom_verify(const manifest_t *manifest, *flash_exec = 0; HARDENED_RETURN_IF_ERROR(boot_policy_manifest_check(manifest, &boot_data)); - // Load OTBN boot services app. + // Load ACC boot services app. // // This will be reused by later boot stages. - HARDENED_RETURN_IF_ERROR(otbn_boot_app_load()); + HARDENED_RETURN_IF_ERROR(acc_boot_app_load()); CFI_FUNC_COUNTER_INCREMENT(rom_counters, kCfiRomVerify, 1); // Load secure boot keys from OTP into RAM. diff --git a/sw/device/silicon_creator/rom_ext/BUILD b/sw/device/silicon_creator/rom_ext/BUILD index ee7a39104b6..e90d0016c0a 100644 --- a/sw/device/silicon_creator/rom_ext/BUILD +++ b/sw/device/silicon_creator/rom_ext/BUILD @@ -184,6 +184,7 @@ cc_test( "//hw/top:dt", "//hw/top:flash_ctrl_c_regs", "//hw/top:sram_ctrl_c_regs", + "//sw/acc/crypto:boot", "//sw/device/lib/arch:device", "//sw/device/lib/base:csr", "//sw/device/lib/base:macros", @@ -220,7 +221,6 @@ cc_test( "//sw/device/silicon_creator/lib/ownership:ownership_unlock", "//sw/device/silicon_creator/lib/sigverify", "//sw/device/silicon_creator/rom_ext/imm_section:imm_section_version", - "//sw/otbn/crypto:boot", ] + variation_deps, ) for variation_name, variation_deps in ROM_EXT_VARIATIONS.items() diff --git a/sw/device/silicon_creator/rom_ext/rom_ext.c b/sw/device/silicon_creator/rom_ext/rom_ext.c index 1e44ae84b80..cfb2eeaa2fe 100644 --- a/sw/device/silicon_creator/rom_ext/rom_ext.c +++ b/sw/device/silicon_creator/rom_ext/rom_ext.c @@ -345,7 +345,7 @@ static rom_error_t rom_ext_verify(const manifest_t *manifest, kOwnershipKeyAlgCategoryHybrid) { // Hybrid signatures check both ECDSA and SPX+ signatures. // TODO: as a future optimization, start the ECDSA verify operation on - // OTBN and compute the SPX+ verify in parallel on Ibex. + // ACC and compute the SPX+ verify in parallel on Ibex. HARDENED_RETURN_IF_ERROR(sigverify_ecdsa_p256_verify( &manifest->ecdsa_signature, &keyring.key[verify_key]->data.hybrid.ecdsa, &act_digest, &flash_exec)); diff --git a/sw/device/silicon_owner/tock/kernel/BUILD b/sw/device/silicon_owner/tock/kernel/BUILD index ee6c7131e08..fdd41b6dc34 100644 --- a/sw/device/silicon_owner/tock/kernel/BUILD +++ b/sw/device/silicon_owner/tock/kernel/BUILD @@ -25,9 +25,9 @@ cc_library( rust_binary( name = "kernel", srcs = [ + "src/acc.rs", "src/io.rs", "src/main.rs", - "src/otbn.rs", ], rustc_flags = [ "-g", diff --git a/sw/device/silicon_owner/tock/kernel/src/otbn.rs b/sw/device/silicon_owner/tock/kernel/src/acc.rs similarity index 81% rename from sw/device/silicon_owner/tock/kernel/src/otbn.rs rename to sw/device/silicon_owner/tock/kernel/src/acc.rs index 0487d6e2539..9fea823f677 100644 --- a/sw/device/silicon_owner/tock/kernel/src/otbn.rs +++ b/sw/device/silicon_owner/tock/kernel/src/acc.rs @@ -7,38 +7,38 @@ //! Usage //! ----- //! ```rust -//! let _mux_otbn = crate::otbn::AccelMuxComponent::new(&peripherals.otbn) -//! .finalize(otbn_mux_component_static!()); +//! let _mux_acc = crate::acc::AccelMuxComponent::new(&peripherals.acc) +//! .finalize(acc_mux_component_static!()); //! -//! peripherals.otbn.initialise( +//! peripherals.acc.initialise( //! dynamic_deferred_caller -//! .register(&peripherals.otbn) +//! .register(&peripherals.acc) //! .unwrap(), // Unwrap fail = dynamic deferred caller out of slots //! ); //! ``` use core::mem::MaybeUninit; use kernel::component::Component; -use lowrisc::otbn::Otbn; -use lowrisc::virtual_otbn::{MuxAccel, VirtualMuxAccel}; +use lowrisc::acc::Acc; +use lowrisc::virtual_acc::{MuxAccel, VirtualMuxAccel}; #[macro_export] -macro_rules! otbn_mux_component_static { - () => {{ kernel::static_buf!(lowrisc::virtual_otbn::MuxAccel<'static>) }}; +macro_rules! acc_mux_component_static { + () => {{ kernel::static_buf!(lowrisc::virtual_acc::MuxAccel<'static>) }}; } #[macro_export] -macro_rules! otbn_component_static { - () => {{ kernel::static_buf!(lowrisc::virtual_otbn::VirtualMuxAccel<'static>) }}; +macro_rules! acc_component_static { + () => {{ kernel::static_buf!(lowrisc::virtual_acc::VirtualMuxAccel<'static>) }}; } pub struct AccelMuxComponent { - otbn: &'static Otbn<'static>, + acc: &'static Acc<'static>, } impl AccelMuxComponent { - pub fn new(otbn: &'static Otbn<'static>) -> AccelMuxComponent { - AccelMuxComponent { otbn } + pub fn new(acc: &'static Acc<'static>) -> AccelMuxComponent { + AccelMuxComponent { acc } } } @@ -47,41 +47,41 @@ impl Component for AccelMuxComponent { type Output = &'static MuxAccel<'static>; fn finalize(self, s: Self::StaticInput) -> Self::Output { - s.write(MuxAccel::new(self.otbn)) + s.write(MuxAccel::new(self.acc)) } } -pub struct OtbnComponent { - mux_otbn: &'static MuxAccel<'static>, +pub struct AccComponent { + mux_acc: &'static MuxAccel<'static>, } -impl OtbnComponent { - pub fn new(mux_otbn: &'static MuxAccel<'static>) -> OtbnComponent { - OtbnComponent { mux_otbn } +impl AccComponent { + pub fn new(mux_acc: &'static MuxAccel<'static>) -> AccComponent { + AccComponent { mux_acc } } } -impl Component for OtbnComponent { +impl Component for AccComponent { type StaticInput = &'static mut MaybeUninit>; type Output = &'static VirtualMuxAccel<'static>; fn finalize(self, s: Self::StaticInput) -> Self::Output { - let virtual_otbn_user = s.write(VirtualMuxAccel::new(self.mux_otbn)); + let virtual_acc_user = s.write(VirtualMuxAccel::new(self.mux_acc)); - virtual_otbn_user + virtual_acc_user } } -/// Find the OTBN app in the Tock process list +/// Find the ACC app in the Tock process list /// /// This will iterate through the app list inside the `app_flash` looking /// for a disabled app with the same name as `name`. /// On success this function will return the following information: -/// * OTBN imem start address -/// * OTBN imem size -/// * OTBN dmem start address -/// * OTBN dmem size +/// * ACC imem start address +/// * ACC imem size +/// * ACC dmem start address +/// * ACC dmem size /// /// This function is based on the Tock process loading code #[allow(dead_code)] diff --git a/sw/device/silicon_owner/tock/kernel/src/main.rs b/sw/device/silicon_owner/tock/kernel/src/main.rs index 011ab9e961f..8a035b7a593 100644 --- a/sw/device/silicon_owner/tock/kernel/src/main.rs +++ b/sw/device/silicon_owner/tock/kernel/src/main.rs @@ -14,8 +14,8 @@ #![test_runner(test_runner)] #![reexport_test_harness_main = "test_main"] +use crate::acc::AccComponent; use crate::hil::symmetric_encryption::AES128_BLOCK_SIZE; -use crate::otbn::OtbnComponent; use capsules_aes_gcm::aes_gcm; use capsules_core::virtualizers::virtual_aes_ccm; use capsules_core::virtualizers::virtual_alarm::{MuxAlarm, VirtualMuxAlarm}; @@ -40,8 +40,8 @@ use kernel::{create_capability, debug, static_init}; use lowrisc::flash_ctrl::FlashMPConfig; use rv32i::csr; +mod acc; pub mod io; -mod otbn; const NUM_PROCS: usize = 4; @@ -88,7 +88,7 @@ static mut AES: Option< // Test access to SipHash static mut SIPHASH: Option<&capsules_extra::sip_hash::SipHasher24<'static>> = None; // Test access to RSA -static mut RSA_HARDWARE: Option<&lowrisc::rsa::OtbnRsa<'static>> = None; +static mut RSA_HARDWARE: Option<&lowrisc::rsa::AccRsa<'static>> = None; // Test access to a software SHA256 #[cfg(test)] @@ -611,17 +611,17 @@ unsafe fn setup() -> ( > )); - let mux_otbn = crate::otbn::AccelMuxComponent::new(&peripherals.otbn) - .finalize(otbn_mux_component_static!()); + let mux_acc = + crate::acc::AccelMuxComponent::new(&peripherals.acc).finalize(acc_mux_component_static!()); - let otbn = OtbnComponent::new(&mux_otbn).finalize(crate::otbn_component_static!()); + let acc = AccComponent::new(&mux_acc).finalize(crate::acc_component_static!()); - let otbn_rsa_internal_buf = static_init!([u8; 512], [0; 512]); + let acc_rsa_internal_buf = static_init!([u8; 512], [0; 512]); - // Use the OTBN to create an RSA engine + // Use the ACC to create an RSA engine if let Ok((rsa_imem_start, rsa_imem_length, rsa_dmem_start, rsa_dmem_length)) = - crate::otbn::find_app( - "otbn-rsa", + crate::acc::find_app( + "acc-rsa", core::slice::from_raw_parts( &_sapps as *const u8, &_eapps as *const u8 as usize - &_sapps as *const u8 as usize, @@ -629,22 +629,22 @@ unsafe fn setup() -> ( ) { let rsa_hardware = static_init!( - lowrisc::rsa::OtbnRsa<'static>, - lowrisc::rsa::OtbnRsa::new( - otbn, + lowrisc::rsa::AccRsa<'static>, + lowrisc::rsa::AccRsa::new( + acc, lowrisc::rsa::AppAddresses { imem_start: rsa_imem_start, imem_size: rsa_imem_length, dmem_start: rsa_dmem_start, dmem_size: rsa_dmem_length }, - otbn_rsa_internal_buf, + acc_rsa_internal_buf, ) ); - peripherals.otbn.set_client(rsa_hardware); + peripherals.acc.set_client(rsa_hardware); RSA_HARDWARE = Some(rsa_hardware); } else { - debug!("Unable to find otbn-rsa, disabling RSA support"); + debug!("Unable to find acc-rsa, disabling RSA support"); } // Convert hardware RNG to the Random interface. diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD index 58320c18146..4716025ea4b 100644 --- a/sw/device/tests/BUILD +++ b/sw/device/tests/BUILD @@ -402,12 +402,12 @@ opentitan_test( "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:math", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:clkmgr", "//sw/device/lib/dif:hmac", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/dif:rv_plic", "//sw/device/lib/dif:spi_host", @@ -959,13 +959,13 @@ cc_library( deps = [ "//hw/top:dt", "//sw/device/lib/base:memory", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:aon_timer", "//sw/device/lib/dif:base", "//sw/device/lib/dif:clkmgr", "//sw/device/lib/dif:hmac", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rstmgr", "//sw/device/lib/dif:rv_core_ibex", @@ -1022,8 +1022,8 @@ opentitan_test( ) opentitan_test( - name = "clkmgr_off_otbn_trans_test", - srcs = ["clkmgr_off_otbn_trans_test.c"], + name = "clkmgr_off_acc_trans_test", + srcs = ["clkmgr_off_acc_trans_test.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -1189,7 +1189,7 @@ opentitan_test( tags = ["manual"], ), deps = [ - ":otbn_randomness_impl", + ":acc_randomness_impl", "//hw/top:dt", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", @@ -1200,11 +1200,11 @@ opentitan_test( "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:csrng_testutils", "//sw/device/lib/testing:edn_testutils", "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:isr_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:rand_testutils", "//sw/device/lib/testing:rv_plic_testutils", "//sw/device/lib/testing/test_framework:ottf_main", @@ -1280,22 +1280,22 @@ opentitan_test( "//hw/top:dt", "//hw/top:edn_c_regs", "//sw/device/lib/base:mmio", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:csrng", "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:rv_core_ibex", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:aes_testutils", "//sw/device/lib/testing:edn_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:rand_testutils", "//sw/device/lib/testing/test_framework:check", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/device/tests:otbn_randomness_impl", + "//sw/device/tests:acc_randomness_impl", ], ) @@ -1317,20 +1317,20 @@ opentitan_test( "//hw/top:dt", "//hw/top:edn_c_regs", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:csrng", "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:rv_core_ibex", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:edn_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:rand_testutils", "//sw/device/lib/testing:rv_core_ibex_testutils", "//sw/device/lib/testing/test_framework:check", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/device/tests:otbn_randomness_impl", + "//sw/device/tests:acc_randomness_impl", ], ) @@ -1533,20 +1533,20 @@ opentitan_test( timeout = "long", ), deps = [ - ":otbn_randomness_impl", + ":acc_randomness_impl", "//hw/top:dt", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:base", "//sw/device/lib/dif:csrng", "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:otbn", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:csrng_testutils", "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:isr_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:rand_testutils", "//sw/device/lib/testing:rv_plic_testutils", "//sw/device/lib/testing/test_framework:ottf_main", @@ -1599,16 +1599,16 @@ opentitan_test( ), verilator = verilator_params(timeout = "long"), deps = [ - ":otbn_randomness_impl", + ":acc_randomness_impl", "//hw/top:dt", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:entropy_src", "//sw/device/lib/dif:keymgr", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rv_core_ibex", @@ -1641,16 +1641,16 @@ opentitan_test( ), verilator = verilator_params(timeout = "long"), deps = [ - ":otbn_randomness_impl", + ":acc_randomness_impl", "//hw/top:dt", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:entropy_src", "//sw/device/lib/dif:keymgr", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rv_core_ibex", @@ -1693,17 +1693,17 @@ opentitan_test( silicon = silicon_params(tags = ["flaky"]), verilator = verilator_params(timeout = "long"), deps = [ - ":otbn_randomness_impl", + ":acc_randomness_impl", "//hw/top:dt", "//sw/device/lib/base:memory", "//sw/device/lib/base:mmio", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:alert_handler", "//sw/device/lib/dif:edn", "//sw/device/lib/dif:entropy_src", "//sw/device/lib/dif:keymgr", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pwrmgr", "//sw/device/lib/dif:rv_core_ibex", @@ -2380,14 +2380,14 @@ opentitan_test( ), verilator = verilator_params(timeout = "eternal"), deps = [ + "//sw/acc/crypto:x25519_sideload", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:keymgr_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:ret_sram_testutils", "//sw/device/lib/testing:rstmgr_testutils", "//sw/device/lib/testing:sram_ctrl_testutils", "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/silicon_creator/lib/drivers:retention_sram", - "//sw/otbn/crypto:x25519_sideload", ], ) @@ -2411,14 +2411,14 @@ opentitan_test( ), verilator = verilator_params(timeout = "eternal"), deps = [ + "//sw/acc/crypto:x25519_sideload", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:keymgr_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:ret_sram_testutils", "//sw/device/lib/testing:rstmgr_testutils", "//sw/device/lib/testing:sram_ctrl_testutils", "//sw/device/lib/testing/test_framework:ottf_main", "//sw/device/silicon_creator/lib/drivers:retention_sram", - "//sw/otbn/crypto:x25519_sideload", ], ) @@ -2593,8 +2593,8 @@ opentitan_test( ) opentitan_test( - name = "keymgr_sideload_otbn_test", - srcs = ["keymgr_sideload_otbn_test.c"], + name = "keymgr_sideload_acc_test", + srcs = ["keymgr_sideload_acc_test.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -2610,25 +2610,25 @@ opentitan_test( ), verilator = verilator_params(timeout = "long"), deps = [ - "//hw/top:otbn_c_regs", + "//hw/top:acc_c_regs", + "//sw/acc/crypto:x25519_sideload", "//sw/device/lib/arch:device", "//sw/device/lib/base:macros", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:keymgr", - "//sw/device/lib/dif:otbn", "//sw/device/lib/runtime:hart", "//sw/device/lib/runtime:log", "//sw/device/lib/runtime:print", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:keymgr_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/otbn/crypto:x25519_sideload", ], ) opentitan_test( - name = "keymgr_sideload_otbn_simple_test", - srcs = ["keymgr_sideload_otbn_test.c"], + name = "keymgr_sideload_acc_simple_test", + srcs = ["keymgr_sideload_acc_test.c"], copts = ["-DTEST_SIMPLE_CASE_ONLY"], exec_env = dicts.add( EARLGREY_TEST_ENVS, @@ -2647,19 +2647,19 @@ opentitan_test( silicon = silicon_params(tags = ["broken"]), verilator = verilator_params(timeout = "long"), deps = [ - "//hw/top:otbn_c_regs", + "//hw/top:acc_c_regs", + "//sw/acc/crypto:x25519_sideload", "//sw/device/lib/arch:device", "//sw/device/lib/base:macros", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:keymgr", - "//sw/device/lib/dif:otbn", "//sw/device/lib/runtime:hart", "//sw/device/lib/runtime:log", "//sw/device/lib/runtime:print", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:keymgr_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/otbn/crypto:x25519_sideload", ], ) @@ -2969,8 +2969,8 @@ opentitan_test( ) opentitan_test( - name = "otbn_ecdsa_op_irq_test", - srcs = ["otbn_ecdsa_op_irq_test.c"], + name = "acc_ecdsa_op_irq_test", + srcs = ["acc_ecdsa_op_irq_test.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -2982,22 +2982,22 @@ opentitan_test( verilator = verilator_params(timeout = "long"), deps = [ "//hw/top:dt", - "//sw/device/lib/dif:otbn", + "//sw/acc/crypto:run_p256", + "//sw/device/lib/dif:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:irq", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:profile", "//sw/device/lib/testing:rv_plic_testutils", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/otbn/crypto:run_p256", ], ) opentitan_test( - name = "otbn_irq_test", - srcs = ["otbn_irq_test.c"], + name = "acc_irq_test", + srcs = ["acc_irq_test.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -3011,21 +3011,21 @@ opentitan_test( verilator = verilator_params(timeout = "long"), deps = [ "//hw/top:dt", - "//sw/device/lib/dif:otbn", + "//sw/acc/code-snippets:err_test", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:rv_plic", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:irq", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/otbn/code-snippets:err_test", ], ) opentitan_test( - name = "otbn_mem_scramble_test", - srcs = ["otbn_mem_scramble_test.c"], + name = "acc_mem_scramble_test", + srcs = ["acc_mem_scramble_test.c"], exec_env = dicts.add( EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, DARJEELING_TEST_ENVS, @@ -3039,33 +3039,33 @@ opentitan_test( verilator = verilator_params(timeout = "long"), deps = [ "//hw/top:dt", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:base", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:rv_core_ibex", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:otbn_testutils", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing/test_framework:ottf_main", ], ) cc_library( - name = "otbn_randomness_impl", - srcs = ["otbn_randomness_impl.c"], - hdrs = ["otbn_randomness_impl.h"], + name = "acc_randomness_impl", + srcs = ["acc_randomness_impl.c"], + hdrs = ["acc_randomness_impl.h"], target_compatible_with = [OPENTITAN_CPU], deps = [ + "//sw/acc/code-snippets:randomness", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:base", - "//sw/device/lib/dif:otbn", "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:otbn_testutils", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing/test_framework:check", - "//sw/otbn/code-snippets:randomness", ], ) opentitan_test( - name = "otbn_randomness_test", - srcs = ["otbn_randomness_test.c"], + name = "acc_randomness_test", + srcs = ["acc_randomness_test.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -3077,16 +3077,16 @@ opentitan_test( ), verilator = verilator_params(timeout = "long"), deps = [ - ":otbn_randomness_impl", + ":acc_randomness_impl", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:base", "//sw/device/lib/dif:clkmgr", - "//sw/device/lib/dif:otbn", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:irq", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:clkmgr_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing:rv_plic_testutils", "//sw/device/lib/testing/test_framework:check", "//sw/device/lib/testing/test_framework:ottf_main", @@ -3094,8 +3094,8 @@ opentitan_test( ) opentitan_test( - name = "otbn_rsa_test", - srcs = ["otbn_rsa_test.c"], + name = "acc_rsa_test", + srcs = ["acc_rsa_test.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -3107,19 +3107,19 @@ opentitan_test( verilator = verilator_params(timeout = "eternal"), deps = [ "//hw/top:dt", - "//sw/device/lib/dif:otbn", + "//sw/device/lib/dif:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils_rsa", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils_rsa", "//sw/device/lib/testing:profile", "//sw/device/lib/testing/test_framework:ottf_main", ], ) opentitan_test( - name = "otbn_smoketest", - srcs = ["otbn_smoketest.c"], + name = "acc_smoketest", + srcs = ["acc_smoketest.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -3132,20 +3132,20 @@ opentitan_test( verilator = verilator_params(timeout = "long"), deps = [ "//hw/top:dt", - "//sw/device/lib/dif:otbn", + "//sw/acc/code-snippets:barrett384", + "//sw/acc/code-snippets:err_test", + "//sw/device/lib/dif:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing/test_framework:ottf_main", - "//sw/otbn/code-snippets:barrett384", - "//sw/otbn/code-snippets:err_test", ], ) opentitan_test( - name = "otbn_isa_test", - srcs = ["otbn_isa_test.c"], + name = "acc_isa_test", + srcs = ["acc_isa_test.c"], exec_env = dicts.add( EARLGREY_TEST_ENVS, EARLGREY_SILICON_OWNER_ROM_EXT_ENVS, @@ -3156,11 +3156,11 @@ opentitan_test( }, ), deps = [ - "//hw/ip/otbn/dv/smoke:smoke_test", + "//hw/ip/acc/dv/smoke:smoke_test", "//hw/top:dt", - "//sw/device/lib/dif:otbn", + "//sw/device/lib/dif:acc", + "//sw/device/lib/testing:acc_testutils", "//sw/device/lib/testing:entropy_testutils", - "//sw/device/lib/testing:otbn_testutils", "//sw/device/lib/testing/test_framework:ottf_main", ], ) @@ -5872,6 +5872,7 @@ opentitan_test( "//hw/top_earlgrey/sw/autogen:top_earlgrey", "//sw/device/lib/base:math", "//sw/device/lib/base:multibits", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:adc_ctrl", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:csrng", @@ -5883,7 +5884,6 @@ opentitan_test( "//sw/device/lib/dif:hmac", "//sw/device/lib/dif:i2c", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:pattgen", "//sw/device/lib/dif:pinmux", "//sw/device/lib/dif:pwm", @@ -5892,12 +5892,12 @@ opentitan_test( "//sw/device/lib/dif:spi_host", "//sw/device/lib/dif:uart", "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:acc_testutils_rsa", "//sw/device/lib/testing:aes_testutils", "//sw/device/lib/testing:alert_handler_testutils", "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:hmac_testutils", "//sw/device/lib/testing:i2c_testutils", - "//sw/device/lib/testing:otbn_testutils_rsa", "//sw/device/lib/testing:pinmux_testutils", "//sw/device/lib/testing:spi_device_testutils", "//sw/device/lib/testing:spi_host_testutils", @@ -7487,7 +7487,7 @@ opentitan_test( # run manually for debugging purposes. verilator = verilator_params(tags = ["manual"]), deps = [ - ":otbn_randomness_impl", + ":acc_randomness_impl", "//hw/top:dt", "//hw/top:entropy_src_c_regs", "//sw/device/lib/base:memory", diff --git a/sw/device/tests/README.md b/sw/device/tests/README.md index 9d4c87d06b9..42eba4fe710 100644 --- a/sw/device/tests/README.md +++ b/sw/device/tests/README.md @@ -28,7 +28,7 @@ While most of these tests are top-level agnostic, some are not. * ({toplevel}-specific) **sw/device/tests/{toplevel}/** * IP Integration tests will be placed in the same folders as above. * System-level tests will be placed in the same folders as above. -* IP Integration Test data (some tests, e.g. OTBN, load data files): **sw/device/tests/{IP}\_data/** +* IP Integration Test data (some tests, e.g. ACC, load data files): **sw/device/tests/{IP}\_data/** * Target-specific tests will be subfoldered by target (see below). #### Subfoldering Target-Specific Tests diff --git a/sw/device/tests/otbn_data/otbn_ecdsa_p256_test_private_key.pem b/sw/device/tests/acc_data/acc_ecdsa_p256_test_private_key.pem similarity index 100% rename from sw/device/tests/otbn_data/otbn_ecdsa_p256_test_private_key.pem rename to sw/device/tests/acc_data/acc_ecdsa_p256_test_private_key.pem diff --git a/sw/device/tests/otbn_data/otbn_rsa_test_private_key_1024.pem b/sw/device/tests/acc_data/acc_rsa_test_private_key_1024.pem similarity index 100% rename from sw/device/tests/otbn_data/otbn_rsa_test_private_key_1024.pem rename to sw/device/tests/acc_data/acc_rsa_test_private_key_1024.pem diff --git a/sw/device/tests/otbn_data/otbn_rsa_test_private_key_2048.pem b/sw/device/tests/acc_data/acc_rsa_test_private_key_2048.pem similarity index 100% rename from sw/device/tests/otbn_data/otbn_rsa_test_private_key_2048.pem rename to sw/device/tests/acc_data/acc_rsa_test_private_key_2048.pem diff --git a/sw/device/tests/otbn_data/otbn_rsa_test_private_key_3072.pem b/sw/device/tests/acc_data/acc_rsa_test_private_key_3072.pem similarity index 100% rename from sw/device/tests/otbn_data/otbn_rsa_test_private_key_3072.pem rename to sw/device/tests/acc_data/acc_rsa_test_private_key_3072.pem diff --git a/sw/device/tests/otbn_data/otbn_rsa_test_private_key_4096.pem b/sw/device/tests/acc_data/acc_rsa_test_private_key_4096.pem similarity index 100% rename from sw/device/tests/otbn_data/otbn_rsa_test_private_key_4096.pem rename to sw/device/tests/acc_data/acc_rsa_test_private_key_4096.pem diff --git a/sw/device/tests/otbn_data/otbn_rsa_test_private_key_512.pem b/sw/device/tests/acc_data/acc_rsa_test_private_key_512.pem similarity index 100% rename from sw/device/tests/otbn_data/otbn_rsa_test_private_key_512.pem rename to sw/device/tests/acc_data/acc_rsa_test_private_key_512.pem diff --git a/sw/device/tests/otbn_data/otbn_test_params.py b/sw/device/tests/acc_data/acc_test_params.py similarity index 96% rename from sw/device/tests/otbn_data/otbn_test_params.py rename to sw/device/tests/acc_data/acc_test_params.py index ddea492775c..c3c7fdfc773 100755 --- a/sw/device/tests/otbn_data/otbn_test_params.py +++ b/sw/device/tests/acc_data/acc_test_params.py @@ -3,7 +3,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -""" Generate parameters for the OTBN end-to-end tests. +""" Generate parameters for the ACC end-to-end tests. """ from Crypto.PublicKey import RSA, ECC @@ -100,7 +100,7 @@ def main() -> int: parser = argparse.ArgumentParser() parser.add_argument('type', choices=('rsa', 'ecc')) parser.add_argument('private_key_pem_file') - parser.add_argument('message', nargs='?', default="Hello OTBN.") + parser.add_argument('message', nargs='?', default="Hello ACC.") args = parser.parse_args() diff --git a/sw/device/tests/otbn_ecdsa_op_irq_test.c b/sw/device/tests/acc_ecdsa_op_irq_test.c similarity index 54% rename from sw/device/tests/otbn_ecdsa_op_irq_test.c rename to sw/device/tests/acc_ecdsa_op_irq_test.c index 9120d2b0bad..10d14847ce4 100644 --- a/sw/device/tests/otbn_ecdsa_op_irq_test.c +++ b/sw/device/tests/acc_ecdsa_op_irq_test.c @@ -2,25 +2,25 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "hw/top/dt/dt_otbn.h" // Generated +#include "hw/top/dt/dt_acc.h" // Generated #include "hw/top/dt/dt_rv_plic.h" // Generated -#include "sw/device/lib/dif/dif_otbn.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/irq.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/profile.h" #include "sw/device/lib/testing/rv_plic_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" /** - * ECDSA sign and verify test with the NIST P-256 curve using OTBN. + * ECDSA sign and verify test with the NIST P-256 curve using ACC. * * IMPORTANT: This test is not a secure, complete, or reusable implementation of * a cryptographic algorithm; it is not even close to being production-ready. - * It is only meant as an end-to-end test for OTBN during the bringup phase. + * It is only meant as an end-to-end test for ACC during the bringup phase. * * The test contains constants and expected output, which can be independently * and conveniently verified using a Python script. @@ -28,42 +28,42 @@ * * # Optional: generate a new key * $ openssl ecparam -name prime256v1 -genkey -noout -out \ - * otbn_ecdsa_p256_test_private_key.pem + * acc_ecdsa_p256_test_private_key.pem * * # Create all constants/variables - * $ ./otbn_test_params.py ecc otbn_ecdsa_p256_test_private_key.pem + * $ ./acc_test_params.py ecc acc_ecdsa_p256_test_private_key.pem * */ -OTBN_DECLARE_APP_SYMBOLS(run_p256); - -OTBN_DECLARE_SYMBOL_ADDR(run_p256, mode); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, msg); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, r); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, s); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, x); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, y); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, d0_io); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, d1_io); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, x_r); - -static const otbn_app_t kOtbnAppP256Ecdsa = OTBN_APP_T_INIT(run_p256); - -static const otbn_addr_t kOtbnVarMode = OTBN_ADDR_T_INIT(run_p256, mode); -static const otbn_addr_t kOtbnVarMsg = OTBN_ADDR_T_INIT(run_p256, msg); -static const otbn_addr_t kOtbnVarR = OTBN_ADDR_T_INIT(run_p256, r); -static const otbn_addr_t kOtbnVarS = OTBN_ADDR_T_INIT(run_p256, s); -static const otbn_addr_t kOtbnVarX = OTBN_ADDR_T_INIT(run_p256, x); -static const otbn_addr_t kOtbnVarY = OTBN_ADDR_T_INIT(run_p256, y); -static const otbn_addr_t kOtbnVarD0 = OTBN_ADDR_T_INIT(run_p256, d0_io); -static const otbn_addr_t kOtbnVarD1 = OTBN_ADDR_T_INIT(run_p256, d1_io); -static const otbn_addr_t kOtbnVarXR = OTBN_ADDR_T_INIT(run_p256, x_r); +ACC_DECLARE_APP_SYMBOLS(run_p256); + +ACC_DECLARE_SYMBOL_ADDR(run_p256, mode); +ACC_DECLARE_SYMBOL_ADDR(run_p256, msg); +ACC_DECLARE_SYMBOL_ADDR(run_p256, r); +ACC_DECLARE_SYMBOL_ADDR(run_p256, s); +ACC_DECLARE_SYMBOL_ADDR(run_p256, x); +ACC_DECLARE_SYMBOL_ADDR(run_p256, y); +ACC_DECLARE_SYMBOL_ADDR(run_p256, d0_io); +ACC_DECLARE_SYMBOL_ADDR(run_p256, d1_io); +ACC_DECLARE_SYMBOL_ADDR(run_p256, x_r); + +static const acc_app_t kAccAppP256Ecdsa = ACC_APP_T_INIT(run_p256); + +static const acc_addr_t kAccVarMode = ACC_ADDR_T_INIT(run_p256, mode); +static const acc_addr_t kAccVarMsg = ACC_ADDR_T_INIT(run_p256, msg); +static const acc_addr_t kAccVarR = ACC_ADDR_T_INIT(run_p256, r); +static const acc_addr_t kAccVarS = ACC_ADDR_T_INIT(run_p256, s); +static const acc_addr_t kAccVarX = ACC_ADDR_T_INIT(run_p256, x); +static const acc_addr_t kAccVarY = ACC_ADDR_T_INIT(run_p256, y); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(run_p256, d0_io); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(run_p256, d1_io); +static const acc_addr_t kAccVarXR = ACC_ADDR_T_INIT(run_p256, x_r); // Declare mode constants. -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIGN); -OTBN_DECLARE_SYMBOL_ADDR(run_p256, MODE_VERIFY); -static const uint32_t kModeSign = OTBN_ADDR_T_INIT(run_p256, MODE_SIGN); -static const uint32_t kModeVerify = OTBN_ADDR_T_INIT(run_p256, MODE_VERIFY); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_SIGN); +ACC_DECLARE_SYMBOL_ADDR(run_p256, MODE_VERIFY); +static const uint32_t kModeSign = ACC_ADDR_T_INIT(run_p256, MODE_SIGN); +static const uint32_t kModeVerify = ACC_ADDR_T_INIT(run_p256, MODE_VERIFY); OTTF_DEFINE_TEST_CONFIG(); @@ -75,9 +75,9 @@ static const uint32_t kPlicTarget = 0; static dif_rv_plic_t plic; /** - * The otbn context handler. + * The acc context handler. */ -static dif_otbn_t otbn; +static dif_acc_t acc; /** * The peripheral which fired the irq to be filled by the irq handler. @@ -90,73 +90,72 @@ static volatile dt_instance_id_t plic_peripheral; static volatile dif_rv_plic_irq_id_t irq_id; /** - * The otbn irq to be filled by the irq handler. + * The acc irq to be filled by the irq handler. */ -static volatile dt_otbn_irq_t irq; +static volatile dt_acc_irq_t irq; /** - * Provides external IRQ handling for otbn tests. + * Provides external IRQ handling for acc tests. * * This function overrides the default OTTF external ISR. * * It performs the following: - * 1. Checks if the interrupt is from OTBN. - * 2. Computes the otbn irq from the PLIC ID. + * 1. Checks if the interrupt is from ACC. + * 2. Computes the acc irq from the PLIC ID. * 3. Sets volatile variables for the waiting function. * 4. Clears the IRQ at the peripheral. * 5. Returns true to indicate the interrupt was handled. */ bool ottf_handle_irq(uint32_t *exc_info, dt_instance_id_t devid, dif_rv_plic_irq_id_t plic_id) { - // Handle interrupts from OTBN - if (devid != dt_otbn_instance_id(kDtOtbn)) { + // Handle interrupts from ACC + if (devid != dt_acc_instance_id(kDtAcc)) { return false; } - // Store the peripheral and IRQ ID for otbn_wait_for_done_irq + // Store the peripheral and IRQ ID for acc_wait_for_done_irq plic_peripheral = devid; irq_id = plic_id; - irq = dt_otbn_irq_from_plic_id(kDtOtbn, plic_id); + irq = dt_acc_irq_from_plic_id(kDtAcc, plic_id); - CHECK_DIF_OK(dif_otbn_irq_acknowledge(&otbn, irq)); + CHECK_DIF_OK(dif_acc_irq_acknowledge(&acc, irq)); return true; } -static void otbn_wait_for_done_irq(dif_otbn_t *otbn) { - // Clear the otbn irq variable: we'll set it in the interrupt handler when +static void acc_wait_for_done_irq(dif_acc_t *acc) { + // Clear the acc irq variable: we'll set it in the interrupt handler when // we see the Done interrupt fire. irq = UINT32_MAX; irq_id = UINT32_MAX; plic_peripheral = kDtInstanceIdUnknown; // Enable Done interrupt. - CHECK_DIF_OK( - dif_otbn_irq_set_enabled(otbn, kDifOtbnIrqDone, kDifToggleEnabled)); + CHECK_DIF_OK(dif_acc_irq_set_enabled(acc, kDifAccIrqDone, kDifToggleEnabled)); - // At this point, OTBN should be running. Wait for an interrupt that says + // At this point, ACC should be running. Wait for an interrupt that says // it's done. ATOMIC_WAIT_FOR_INTERRUPT(plic_peripheral != kDtInstanceIdUnknown); - CHECK(plic_peripheral == dt_otbn_instance_id(kDtOtbn), + CHECK(plic_peripheral == dt_acc_instance_id(kDtAcc), "Interrupt from incorrect peripheral: (exp: %d, obs: %s)", - dt_otbn_instance_id(kDtOtbn), plic_peripheral); + dt_acc_instance_id(kDtAcc), plic_peripheral); // Check this is the interrupt we expected. - CHECK(irq == kDtOtbnIrqDone); + CHECK(irq == kDtAccIrqDone); // Disable Done interrupt. CHECK_DIF_OK( - dif_otbn_irq_set_enabled(otbn, kDifOtbnIrqDone, kDifToggleDisabled)); + dif_acc_irq_set_enabled(acc, kDifAccIrqDone, kDifToggleDisabled)); // Acknowledge Done interrupt. This clears INTR_STATE.done back to 0. - CHECK_DIF_OK(dif_otbn_irq_acknowledge(otbn, kDifOtbnIrqDone)); + CHECK_DIF_OK(dif_acc_irq_acknowledge(acc, kDifAccIrqDone)); } -static void otbn_init_irq(void) { - // Initialize PLIC and configure OTBN interrupt. +static void acc_init_irq(void) { + // Initialize PLIC and configure ACC interrupt. CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic)); // Set interrupt priority to be positive. - dif_rv_plic_irq_id_t irq_id = dt_otbn_irq_to_plic_id(kDtOtbn, kDtOtbnIrqDone); + dif_rv_plic_irq_id_t irq_id = dt_acc_irq_to_plic_id(kDtAcc, kDtAccIrqDone); CHECK_DIF_OK(dif_rv_plic_irq_set_priority(&plic, irq_id, 0x1)); CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(&plic, irq_id, kPlicTarget, @@ -171,13 +170,13 @@ static void otbn_init_irq(void) { } /** - * Securely wipes OTBN DMEM and waits for Done interrupt. + * Securely wipes ACC DMEM and waits for Done interrupt. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. */ -static void otbn_wipe_dmem(dif_otbn_t *otbn) { - CHECK_DIF_OK(dif_otbn_write_cmd(otbn, kDifOtbnCmdSecWipeDmem)); - otbn_wait_for_done_irq(otbn); +static void acc_wipe_dmem(dif_acc_t *acc) { + CHECK_DIF_OK(dif_acc_write_cmd(acc, kDifAccCmdSecWipeDmem)); + acc_wait_for_done_irq(acc); } /** @@ -199,7 +198,7 @@ static void check_data(const char *msg, const uint8_t *actual, /** * Signs a message with ECDSA using the P-256 curve. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. * @param msg The message to sign (32B). * @param private_key_d The private key (32B). * @param[out] signature_r Signature component r (the x-coordinate of R). @@ -207,45 +206,45 @@ static void check_data(const char *msg, const uint8_t *actual, * @param[out] signature_s Signature component s (the proof). * Provide a pre-allocated 32B buffer. */ -static void p256_ecdsa_sign(dif_otbn_t *otbn, const uint8_t *msg, +static void p256_ecdsa_sign(dif_acc_t *acc, const uint8_t *msg, const uint8_t *private_key_d, uint8_t *signature_r, uint8_t *signature_s) { - CHECK(otbn != NULL); + CHECK(acc != NULL); // Write input arguments. uint32_t mode = kModeSign; CHECK_STATUS_OK( - otbn_testutils_write_data(otbn, sizeof(uint32_t), &mode, kOtbnVarMode)); + acc_testutils_write_data(acc, sizeof(uint32_t), &mode, kAccVarMode)); CHECK_STATUS_OK( - otbn_testutils_write_data(otbn, /*len_bytes=*/32, msg, kOtbnVarMsg)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, /*len_bytes=*/32, - private_key_d, kOtbnVarD0)); + acc_testutils_write_data(acc, /*len_bytes=*/32, msg, kAccVarMsg)); + CHECK_STATUS_OK(acc_testutils_write_data(acc, /*len_bytes=*/32, private_key_d, + kAccVarD0)); // Write redundant upper bits of d (all-zero for this test). uint8_t d0_high[32] = {0}; - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, /*len_bytes=*/32, d0_high, - kOtbnVarD0 + 32)); + CHECK_STATUS_OK( + acc_testutils_write_data(acc, /*len_bytes=*/32, d0_high, kAccVarD0 + 32)); // Write second share of d (all-zero for this test). uint8_t d1[64] = {0}; CHECK_STATUS_OK( - otbn_testutils_write_data(otbn, /*len_bytes=*/64, d1, kOtbnVarD1)); + acc_testutils_write_data(acc, /*len_bytes=*/64, d1, kAccVarD1)); - // Call OTBN to perform operation, and wait for it to complete. - CHECK_STATUS_OK(otbn_testutils_execute(otbn)); - otbn_wait_for_done_irq(otbn); + // Call ACC to perform operation, and wait for it to complete. + CHECK_STATUS_OK(acc_testutils_execute(acc)); + acc_wait_for_done_irq(acc); // Read back results. CHECK_STATUS_OK( - otbn_testutils_read_data(otbn, /*len_bytes=*/32, kOtbnVarR, signature_r)); + acc_testutils_read_data(acc, /*len_bytes=*/32, kAccVarR, signature_r)); CHECK_STATUS_OK( - otbn_testutils_read_data(otbn, /*len_bytes=*/32, kOtbnVarS, signature_s)); + acc_testutils_read_data(acc, /*len_bytes=*/32, kAccVarS, signature_s)); } /** * Verifies a message with ECDSA using the P-256 curve. * - * @param otbn The OTBN context object. + * @param acc The ACC context object. * @param msg The message to verify (32B). * @param signature_r The signature component r (the proof) (32B). * @param signature_s The signature component s (the proof) (32B). @@ -254,46 +253,46 @@ static void p256_ecdsa_sign(dif_otbn_t *otbn, const uint8_t *msg, * @param[out] signature_x_r Recovered point x_r (== R'.x). Provide a * pre-allocated 32B buffer. */ -static void p256_ecdsa_verify(dif_otbn_t *otbn, const uint8_t *msg, +static void p256_ecdsa_verify(dif_acc_t *acc, const uint8_t *msg, const uint8_t *signature_r, const uint8_t *signature_s, const uint8_t *public_key_x, const uint8_t *public_key_y, uint8_t *signature_x_r) { - CHECK(otbn != NULL); + CHECK(acc != NULL); // Write input arguments. uint32_t mode = kModeVerify; CHECK_STATUS_OK( - otbn_testutils_write_data(otbn, sizeof(uint32_t), &mode, kOtbnVarMode)); + acc_testutils_write_data(acc, sizeof(uint32_t), &mode, kAccVarMode)); + CHECK_STATUS_OK( + acc_testutils_write_data(acc, /*len_bytes=*/32, msg, kAccVarMsg)); + CHECK_STATUS_OK( + acc_testutils_write_data(acc, /*len_bytes=*/32, signature_r, kAccVarR)); CHECK_STATUS_OK( - otbn_testutils_write_data(otbn, /*len_bytes=*/32, msg, kOtbnVarMsg)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, /*len_bytes=*/32, signature_r, - kOtbnVarR)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, /*len_bytes=*/32, signature_s, - kOtbnVarS)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, /*len_bytes=*/32, - public_key_x, kOtbnVarX)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, /*len_bytes=*/32, - public_key_y, kOtbnVarY)); - - // Call OTBN to perform operation, and wait for it to complete. - CHECK_STATUS_OK(otbn_testutils_execute(otbn)); - otbn_wait_for_done_irq(otbn); + acc_testutils_write_data(acc, /*len_bytes=*/32, signature_s, kAccVarS)); + CHECK_STATUS_OK( + acc_testutils_write_data(acc, /*len_bytes=*/32, public_key_x, kAccVarX)); + CHECK_STATUS_OK( + acc_testutils_write_data(acc, /*len_bytes=*/32, public_key_y, kAccVarY)); + + // Call ACC to perform operation, and wait for it to complete. + CHECK_STATUS_OK(acc_testutils_execute(acc)); + acc_wait_for_done_irq(acc); // Read back results. - CHECK_STATUS_OK(otbn_testutils_read_data(otbn, /*len_bytes=*/32, kOtbnVarXR, - signature_x_r)); + CHECK_STATUS_OK( + acc_testutils_read_data(acc, /*len_bytes=*/32, kAccVarXR, signature_x_r)); } /** * Performs a ECDSA roundtrip test using the NIST P-256 curve. * - * A roundtrip consists of three steps: Initialize OTBN, sign, and verify. + * A roundtrip consists of three steps: Initialize ACC, sign, and verify. */ static void test_ecdsa_p256_roundtrip(void) { // Message - static const uint8_t kIn[32] = {"Hello OTBN."}; + static const uint8_t kIn[32] = {"Hello ACC."}; // Public key x-coordinate (Q.x) static const uint8_t kPublicKeyQx[32] = { @@ -315,9 +314,9 @@ static void test_ecdsa_p256_roundtrip(void) { // Initialize uint64_t t_start_init = profile_start(); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); - otbn_init_irq(); - CHECK_STATUS_OK(otbn_testutils_load_app(&otbn, kOtbnAppP256Ecdsa)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); + acc_init_irq(); + CHECK_STATUS_OK(acc_testutils_load_app(&acc, kAccAppP256Ecdsa)); profile_end_and_print(t_start_init, "Initialization"); // Sign @@ -326,31 +325,31 @@ static void test_ecdsa_p256_roundtrip(void) { LOG_INFO("Signing"); uint64_t t_start_sign = profile_start(); - p256_ecdsa_sign(&otbn, kIn, kPrivateKeyD, signature_r, signature_s); + p256_ecdsa_sign(&acc, kIn, kPrivateKeyD, signature_r, signature_s); profile_end_and_print(t_start_sign, "Sign"); - // Securely wipe OTBN data memory and reload app - LOG_INFO("Wiping OTBN DMEM and reloading app"); - otbn_wipe_dmem(&otbn); - CHECK_STATUS_OK(otbn_testutils_load_app(&otbn, kOtbnAppP256Ecdsa)); + // Securely wipe ACC data memory and reload app + LOG_INFO("Wiping ACC DMEM and reloading app"); + acc_wipe_dmem(&acc); + CHECK_STATUS_OK(acc_testutils_load_app(&acc, kAccAppP256Ecdsa)); // Verify uint8_t signature_x_r[32] = {0}; LOG_INFO("Verifying"); uint64_t t_start_verify = profile_start(); - p256_ecdsa_verify(&otbn, kIn, signature_r, signature_s, kPublicKeyQx, + p256_ecdsa_verify(&acc, kIn, signature_r, signature_s, kPublicKeyQx, kPublicKeyQy, signature_x_r); // Include the r =? x_r comparison in the profiling as this is something - // either OTBN or the host CPU needs to do as part of the signature + // either ACC or the host CPU needs to do as part of the signature // verification. check_data("signature_x_r", signature_r, signature_x_r, 32); profile_end_and_print(t_start_verify, "Verify"); - // Securely wipe OTBN data memory - LOG_INFO("Wiping OTBN DMEM"); - otbn_wipe_dmem(&otbn); + // Securely wipe ACC data memory + LOG_INFO("Wiping ACC DMEM"); + acc_wipe_dmem(&acc); } bool test_main(void) { diff --git a/sw/device/tests/acc_irq_test.c b/sw/device/tests/acc_irq_test.c new file mode 100644 index 00000000000..47ba0b58324 --- /dev/null +++ b/sw/device/tests/acc_irq_test.c @@ -0,0 +1,160 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "hw/top/dt/dt_acc.h" +#include "hw/top/dt/dt_api.h" +#include "hw/top/dt/dt_rv_plic.h" +#include "sw/device/lib/dif/dif_acc.h" +#include "sw/device/lib/dif/dif_rv_plic.h" +#include "sw/device/lib/runtime/irq.h" +#include "sw/device/lib/testing/acc_testutils.h" +#include "sw/device/lib/testing/entropy_testutils.h" +#include "sw/device/lib/testing/test_framework/check.h" +#include "sw/device/lib/testing/test_framework/ottf_main.h" + +ACC_DECLARE_APP_SYMBOLS(err_test); + +static const acc_app_t kAppErrTest = ACC_APP_T_INIT(err_test); +static const uint32_t kPlicTarget = 0; + +OTTF_DEFINE_TEST_CONFIG(); + +static dif_rv_plic_t plic; +static dif_acc_t acc; +static dt_acc_t kAccDt = (dt_acc_t)0; + +static volatile bool acc_finished; + +/** + * Get ACC error bits; check they match expected_err_bits. + */ +static void check_acc_err_bits(dif_acc_t *acc, + dif_acc_err_bits_t expected_err_bits) { + dif_acc_err_bits_t acc_err_bits; + CHECK_DIF_OK(dif_acc_get_err_bits(acc, &acc_err_bits)); + CHECK(acc_err_bits == expected_err_bits, + "dif_acc_get_err_bits() produced unexpected error bits: %x", + acc_err_bits); +} + +/** + * Get the ACC instruction count; check that it matches expected_insn_cnt. + */ +static void check_acc_insn_cnt(dif_acc_t *acc, uint32_t expected_insn_cnt) { + uint32_t insn_cnt; + CHECK_DIF_OK(dif_acc_get_insn_cnt(acc, &insn_cnt)); + CHECK(insn_cnt == expected_insn_cnt, + "Expected to execute %d instructions, but got %d.", expected_insn_cnt, + insn_cnt); +} + +/** + * Get ACC's status; check that it matches expected_status. + */ +static void check_acc_status(dif_acc_t *acc, dif_acc_status_t expected_status) { + dif_acc_status_t status; + CHECK_DIF_OK(dif_acc_get_status(acc, &status)); + CHECK(status == expected_status, "Unexpected status: expected %d but got %d.", + expected_status, status); +} + +/** + * Run a binary on ACC, waiting for completion by interrupt. + * + * Once the binary has finished, check for expected status, error bits and + * instruction count. + */ +static void run_test_with_irqs(dif_acc_t *acc, acc_app_t app, + dif_acc_status_t expected_status, + dif_acc_err_bits_t expected_err_bits, + uint32_t expected_insn_cnt) { + // Clear the acc_finished flag: we'll set it in the interrupt handler when + // we see the Done interrupt fire. + acc_finished = false; + + CHECK_STATUS_OK(acc_testutils_load_app(acc, app)); + + // If the CTRL.SOFTWARE_ERRS_FATAL flag is set, a software error will be + // promoted to a fatal error (which, among other things, bricks ACC until + // next reset). Make sure that's not turned on. + CHECK(dif_acc_set_ctrl_software_errs_fatal(acc, false) == kDifOk); + + // Enable Done interrupt + CHECK_DIF_OK(dif_acc_irq_set_enabled(acc, kDifAccIrqDone, kDifToggleEnabled)); + + // Start ACC + CHECK_STATUS_OK(acc_testutils_execute(acc)); + + // At this point, ACC should be running. Wait for an interrupt that says + // it's done. + ATOMIC_WAIT_FOR_INTERRUPT(acc_finished); + + check_acc_status(acc, expected_status); + check_acc_err_bits(acc, expected_insn_cnt); + check_acc_insn_cnt(acc, expected_err_bits); +} + +/** + * Initialize PLIC and enable ACC interrupt. + */ +static void plic_init_with_irqs(void) { + CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic)); + + dif_rv_plic_irq_id_t irq_id = dt_acc_irq_to_plic_id(kAccDt, kDtAccIrqDone); + + // Set interrupt priority to be positive + CHECK_DIF_OK(dif_rv_plic_irq_set_priority(&plic, irq_id, 0x1)); + + // Enable the interrupt + CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(&plic, irq_id, kPlicTarget, + kDifToggleEnabled)); + + // Set the threshold for Ibex to 0. + CHECK_DIF_OK(dif_rv_plic_target_set_threshold(&plic, kPlicTarget, 0x0)); +} + +/** + * The ISR for this test. + * + * This function overrides the default OTTF external ISR. + */ +bool ottf_handle_irq(uint32_t *exc_info, dt_instance_id_t devid, + dif_rv_plic_irq_id_t irq_id) { + if (devid != dt_acc_instance_id(kAccDt)) { + return false; + } + + // Check this is the interrupt we expected + dif_acc_irq_t acc_irq = dt_acc_irq_from_plic_id(kAccDt, irq_id); + if (acc_irq != kDtAccIrqDone) { + return false; + } + + // acc_finished should currently be false (we're supposed to clear it before + // starting ACC) + CHECK(!acc_finished); + + // Set acc_finished, which we'll pick up in run_test_with_irqs. + acc_finished = true; + + CHECK_DIF_OK(dif_acc_irq_acknowledge(&acc, acc_irq)); + + return true; +} + +bool test_main(void) { + CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); + plic_init_with_irqs(); + + CHECK_DIF_OK(dif_acc_init_from_dt(kAccDt, &acc)); + + // Enable the external IRQ (so that we see the interrupt from the PLIC) + irq_global_ctrl(true); + irq_external_ctrl(true); + + run_test_with_irqs(&acc, kAppErrTest, kDifAccStatusIdle, + kDifAccErrBitsBadDataAddr, 1); + + return true; +} diff --git a/sw/device/tests/otbn_isa_test.c b/sw/device/tests/acc_isa_test.c similarity index 81% rename from sw/device/tests/otbn_isa_test.c rename to sw/device/tests/acc_isa_test.c index f1a5b0c1b58..7c68dc5fff1 100644 --- a/sw/device/tests/otbn_isa_test.c +++ b/sw/device/tests/acc_isa_test.c @@ -2,16 +2,16 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/dif/dif_otbn.h" +#include "sw/device/lib/dif/dif_acc.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" /** - * This test runs every instruction in OTBN's ISA and checks the result. + * This test runs every instruction in ACC's ISA and checks the result. * - * It reuses the `smoke_test.s` script used in OTBN's Design Verification, + * It reuses the `smoke_test.s` script used in ACC's Design Verification, * but with accesses the `RND` and `KEY_*` WSRs removed. * The result in `w1` and `w2` are downstream of the `KEY_*`, * loads and so are not checked. @@ -20,13 +20,13 @@ */ OTTF_DEFINE_TEST_CONFIG(); -OTBN_DECLARE_APP_SYMBOLS(smoke_test); -OTBN_DECLARE_SYMBOL_ADDR(smoke_test, gpr_state); -OTBN_DECLARE_SYMBOL_ADDR(smoke_test, wdr_state); +ACC_DECLARE_APP_SYMBOLS(smoke_test); +ACC_DECLARE_SYMBOL_ADDR(smoke_test, gpr_state); +ACC_DECLARE_SYMBOL_ADDR(smoke_test, wdr_state); -static const otbn_app_t kAppSmokeTest = OTBN_APP_T_INIT(smoke_test); -static const otbn_addr_t kGprState = OTBN_ADDR_T_INIT(smoke_test, gpr_state); -static const otbn_addr_t kWdrState = OTBN_ADDR_T_INIT(smoke_test, wdr_state); +static const acc_app_t kAppSmokeTest = ACC_APP_T_INIT(smoke_test); +static const acc_addr_t kGprState = ACC_ADDR_T_INIT(smoke_test, gpr_state); +static const acc_addr_t kWdrState = ACC_ADDR_T_INIT(smoke_test, wdr_state); enum { kNumExpectedGprs = 30, @@ -35,7 +35,7 @@ enum { }; // The expected values of the GPRs and WDRs are taken from -// `hw/ip/otbn/dv/smoke/smoke_expected.txt`. +// `hw/ip/acc/dv/smoke/smoke_expected.txt`. static const uint32_t kExpectedGprs[kNumExpectedGprs] = { 0xd0beb513, 0xa0be911a, 0x717d462d, 0xcfffdc07, 0xf0beb51b, 0x80be9112, 0x70002409, 0xd0beb533, 0x00000510, 0xd0beb169, 0xfad44c00, 0x000685f5, @@ -111,33 +111,33 @@ static const uint32_t kExpectedWdrs[kNumExpectedWdrs][8] = { }; bool test_main(void) { - // Initialise the entropy source and OTBN - dif_otbn_t otbn; + // Initialise the entropy source and ACC + dif_acc_t acc; CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); // Load the Smoke Test App - CHECK_STATUS_OK(otbn_testutils_load_app(&otbn, kAppSmokeTest)); - CHECK_STATUS_OK(otbn_testutils_execute(&otbn)); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(&otbn, kDifOtbnErrBitsNoError)); + CHECK_STATUS_OK(acc_testutils_load_app(&acc, kAppSmokeTest)); + CHECK_STATUS_OK(acc_testutils_execute(&acc)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(&acc, kDifAccErrBitsNoError)); // Check the instruction count is what was expected. uint32_t instruction_count; - CHECK_DIF_OK(dif_otbn_get_insn_cnt(&otbn, &instruction_count)); + CHECK_DIF_OK(dif_acc_get_insn_cnt(&acc, &instruction_count)); CHECK(kExpectedInstrCount == instruction_count, - "Expected OTBN to execute %d instructions, but it exected %d", + "Expected ACC to execute %d instructions, but it exected %d", kExpectedInstrCount, instruction_count); // Check the GPR registers of interest hold the expected values. uint32_t gpr_state[kNumExpectedGprs]; - CHECK_STATUS_OK(otbn_testutils_read_data(&otbn, sizeof(kExpectedGprs), - kGprState, &gpr_state)); + CHECK_STATUS_OK(acc_testutils_read_data(&acc, sizeof(kExpectedGprs), + kGprState, &gpr_state)); CHECK_ARRAYS_EQ(gpr_state, kExpectedGprs, kNumExpectedGprs); // Check the WDR registers of interest hold the expected values. uint32_t wdr_state[kNumExpectedWdrs][8]; - CHECK_STATUS_OK(otbn_testutils_read_data(&otbn, sizeof(kExpectedWdrs), - kWdrState, &wdr_state)); + CHECK_STATUS_OK(acc_testutils_read_data(&acc, sizeof(kExpectedWdrs), + kWdrState, &wdr_state)); CHECK_ARRAYS_EQ(wdr_state[0], kExpectedWdrs[0], 8, "w0 didn't match the expected value."); diff --git a/sw/device/tests/otbn_mem_scramble_test.c b/sw/device/tests/acc_mem_scramble_test.c similarity index 67% rename from sw/device/tests/otbn_mem_scramble_test.c rename to sw/device/tests/acc_mem_scramble_test.c index 58e82478a13..ab70626df10 100644 --- a/sw/device/tests/otbn_mem_scramble_test.c +++ b/sw/device/tests/acc_mem_scramble_test.c @@ -2,32 +2,29 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_base.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" #include "sw/device/lib/runtime/log.h" -#include "sw/device/lib/testing/otbn_testutils.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -static_assert(kDtOtbnCount >= 1, - "This test requires at least one OTBN instance"); +static_assert(kDtAccCount >= 1, "This test requires at least one ACC instance"); // rv_core_ibex wrapper around the Ibex CPU provides additional functionality. static_assert(kDtRvCoreIbexCount >= 1, "This test requires at least one rv_core_ibex instance"); -static dt_otbn_t kTestOtbn = (dt_otbn_t)0; +static dt_acc_t kTestAcc = (dt_acc_t)0; static dt_rv_core_ibex_t kTestRvCoreIbex = (dt_rv_core_ibex_t)0; OTTF_DEFINE_TEST_CONFIG(); -typedef dif_result_t (*otbn_read_t)(const dif_otbn_t *otbn, - uint32_t offset_bytes, void *dest, - size_t len_bytes); +typedef dif_result_t (*acc_read_t)(const dif_acc_t *acc, uint32_t offset_bytes, + void *dest, size_t len_bytes); -typedef dif_result_t (*otbn_write_t)(const dif_otbn_t *otbn, - uint32_t offset_bytes, const void *src, - size_t len_bytes); +typedef dif_result_t (*acc_write_t)(const dif_acc_t *acc, uint32_t offset_bytes, + const void *src, size_t len_bytes); enum { /** @@ -126,40 +123,39 @@ static void get_rand_words(dif_rv_core_ibex_t *ibex, int num, uint32_t *rnd_buf, } /** - * Write values found at `word_addrs` to OTBN memory at addresses `word_addrs`. + * Write values found at `word_addrs` to ACC memory at addresses `word_addrs`. * - * @param ctx The otbn context object. + * @param ctx The acc context object. * @param num The number of addresses to write. * @param word_addrs The data to write and the word addresses to write to. - * @param otbn_write Pointer to the function to write the memory. It can be - * either `dif_otbn_imem_write` or `dif_otbn_dmem_write`. + * @param acc_write Pointer to the function to write the memory. It can be + * either `dif_acc_imem_write` or `dif_acc_dmem_write`. */ -static void otbn_write_mem_words(const dif_otbn_t *otbn, const int num, - const uint32_t *word_addrs, - otbn_write_t otbn_write) { +static void acc_write_mem_words(const dif_acc_t *acc, const int num, + const uint32_t *word_addrs, + acc_write_t acc_write) { for (int i = 0; i < num; ++i) { - otbn_write(otbn, word_addrs[i] * sizeof(uint32_t), (void *)&word_addrs[i], - sizeof(uint32_t)); + acc_write(acc, word_addrs[i] * sizeof(uint32_t), (void *)&word_addrs[i], + sizeof(uint32_t)); } } /** - * Check whether the contents at addresses `word_addrs` of an OTBN memory match + * Check whether the contents at addresses `word_addrs` of an ACC memory match * the reference data pointed at `word_addrs`. * - * @param ctx The otbn context object. + * @param ctx The acc context object. * @param num The number of addresses to check. * @param word_addrs The word addresses to check. - * @param otbn_read Pointer to the function to read the memory. It can be - * either `dif_otbn_imem_read` or `dif_otbn_dmem_read`. + * @param acc_read Pointer to the function to read the memory. It can be + * either `dif_acc_imem_read` or `dif_acc_dmem_read`. * @param[out] num_matches Pointer to the number of observed matches. * @param[out] num_intg_errors Pointer to the number of observed integrity * errors. */ -static void otbn_check_mem_words(const dif_otbn_t *otbn, const int num, - const uint32_t *word_addrs, - otbn_read_t otbn_read, int *num_matches, - int *num_intg_errors) { +static void acc_check_mem_words(const dif_acc_t *acc, const int num, + const uint32_t *word_addrs, acc_read_t acc_read, + int *num_matches, int *num_intg_errors) { *num_matches = 0; *num_intg_errors = 0; @@ -169,8 +165,8 @@ static void otbn_check_mem_words(const dif_otbn_t *otbn, const int num, // If the memory has been scrambled we expect to receive an IRQ due to the // integrity error. has_irq_fired = false; - otbn_read(otbn, word_addrs[i] * sizeof(uint32_t), (void *)&word, - sizeof(uint32_t)); + acc_read(acc, word_addrs[i] * sizeof(uint32_t), (void *)&word, + sizeof(uint32_t)); match = (word_addrs[i] == word); if (match) { *num_matches += 1; @@ -190,9 +186,9 @@ static void otbn_check_mem_words(const dif_otbn_t *otbn, const int num, } bool test_main(void) { - // Init OTBN DIF. - dif_otbn_t otbn; - CHECK_DIF_OK(dif_otbn_init_from_dt(kTestOtbn, &otbn)); + // Init ACC DIF. + dif_acc_t acc; + CHECK_DIF_OK(dif_acc_init_from_dt(kTestAcc, &acc)); // Init Ibex DIF. dif_rv_core_ibex_t ibex; @@ -205,49 +201,49 @@ bool test_main(void) { int num_matches_dmem, num_intg_errors_dmem; // Get random address offsets to check. - max = (uint32_t)dif_otbn_get_imem_size_bytes(&otbn) / sizeof(uint32_t) - 1; + max = (uint32_t)dif_acc_get_imem_size_bytes(&acc) / sizeof(uint32_t) - 1; get_rand_words(&ibex, kNumAddrs, imem_offsets, max); - max = (uint32_t)dif_otbn_get_dmem_size_bytes(&otbn) / sizeof(uint32_t) - 1; + max = (uint32_t)dif_acc_get_dmem_size_bytes(&acc) / sizeof(uint32_t) - 1; get_rand_words(&ibex, kNumAddrs, dmem_offsets, max); - // Wait for OTBN to be idle. - CHECK_STATUS_OK(otbn_testutils_wait_for_done(&otbn, kDifOtbnErrBitsNoError)); + // Wait for ACC to be idle. + CHECK_STATUS_OK(acc_testutils_wait_for_done(&acc, kDifAccErrBitsNoError)); // Write random address offsets. - otbn_write_mem_words(&otbn, kNumAddrs, imem_offsets, dif_otbn_imem_write); - otbn_write_mem_words(&otbn, kNumAddrs, dmem_offsets, dif_otbn_dmem_write); + acc_write_mem_words(&acc, kNumAddrs, imem_offsets, dif_acc_imem_write); + acc_write_mem_words(&acc, kNumAddrs, dmem_offsets, dif_acc_dmem_write); // Read back and check random address offsets. All values must match, we must // not see any integrity errors. - otbn_check_mem_words(&otbn, kNumAddrs, imem_offsets, dif_otbn_imem_read, - &num_matches_imem, &num_intg_errors_imem); + acc_check_mem_words(&acc, kNumAddrs, imem_offsets, dif_acc_imem_read, + &num_matches_imem, &num_intg_errors_imem); CHECK(num_matches_imem == kNumAddrs, "%i unexpected IMEM mismatches", kNumAddrs - num_matches_imem); CHECK(!num_intg_errors_imem, "%i unexpected IMEM integrity errors", num_intg_errors_imem); - otbn_check_mem_words(&otbn, kNumAddrs, dmem_offsets, dif_otbn_dmem_read, - &num_matches_dmem, &num_intg_errors_dmem); + acc_check_mem_words(&acc, kNumAddrs, dmem_offsets, dif_acc_dmem_read, + &num_matches_dmem, &num_intg_errors_dmem); CHECK(num_matches_dmem == kNumAddrs, "%i unexpected DMEM mismatches", kNumAddrs - num_matches_dmem); CHECK(!num_intg_errors_dmem, "%i unexpected DMEM integrity errors", num_intg_errors_dmem); // Re-scramble IMEM and DMEM by fetching new scrambling keys from OTP. - CHECK_DIF_OK(dif_otbn_write_cmd(&otbn, kDifOtbnCmdSecWipeImem)); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(&otbn, kDifOtbnErrBitsNoError)); - CHECK_DIF_OK(dif_otbn_write_cmd(&otbn, kDifOtbnCmdSecWipeDmem)); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(&otbn, kDifOtbnErrBitsNoError)); + CHECK_DIF_OK(dif_acc_write_cmd(&acc, kDifAccCmdSecWipeImem)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(&acc, kDifAccErrBitsNoError)); + CHECK_DIF_OK(dif_acc_write_cmd(&acc, kDifAccCmdSecWipeDmem)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(&acc, kDifAccErrBitsNoError)); // Read back and check random address offsets. We don't care about the values. // "Most" reads should trigger integrity errors. - otbn_check_mem_words(&otbn, kNumAddrs, imem_offsets, dif_otbn_imem_read, - &num_matches_imem, &num_intg_errors_imem); + acc_check_mem_words(&acc, kNumAddrs, imem_offsets, dif_acc_imem_read, + &num_matches_imem, &num_intg_errors_imem); CHECK(num_intg_errors_imem >= kNumIntgErrorsThreshold, "Expecting at least %i IMEM integrity errors, got %i", kNumIntgErrorsThreshold, num_intg_errors_imem); - otbn_check_mem_words(&otbn, kNumAddrs, dmem_offsets, dif_otbn_dmem_read, - &num_matches_dmem, &num_intg_errors_dmem); + acc_check_mem_words(&acc, kNumAddrs, dmem_offsets, dif_acc_dmem_read, + &num_matches_dmem, &num_intg_errors_dmem); CHECK(num_intg_errors_dmem >= kNumIntgErrorsThreshold, "Expecting at least %i DMEM integrity errors, got %i", kNumIntgErrorsThreshold, num_intg_errors_dmem); diff --git a/sw/device/tests/acc_randomness_impl.c b/sw/device/tests/acc_randomness_impl.c new file mode 100644 index 00000000000..c97df957c66 --- /dev/null +++ b/sw/device/tests/acc_randomness_impl.c @@ -0,0 +1,72 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "sw/device/tests/acc_randomness_impl.h" + +#include "sw/device/lib/dif/dif_acc.h" +#include "sw/device/lib/dif/dif_base.h" +#include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" +#include "sw/device/lib/testing/test_framework/check.h" + +ACC_DECLARE_APP_SYMBOLS(randomness); +ACC_DECLARE_SYMBOL_ADDR(randomness, iterations); +ACC_DECLARE_SYMBOL_ADDR(randomness, rv); +ACC_DECLARE_SYMBOL_ADDR(randomness, fail_idx); +ACC_DECLARE_SYMBOL_ADDR(randomness, rnd_out); +ACC_DECLARE_SYMBOL_ADDR(randomness, urnd_out); + +static const acc_app_t kAccAppRandomnessApp = ACC_APP_T_INIT(randomness); +static const acc_addr_t kVarIters = ACC_ADDR_T_INIT(randomness, iterations); +static const acc_addr_t kVarRv = ACC_ADDR_T_INIT(randomness, rv); +static const acc_addr_t kVarFailIdx = ACC_ADDR_T_INIT(randomness, fail_idx); +static const acc_addr_t kVarRndOut = ACC_ADDR_T_INIT(randomness, rnd_out); +static const acc_addr_t kVarUrndOut = ACC_ADDR_T_INIT(randomness, urnd_out); + +/** + * LOG_INFO with a 256b unsigned integer as hexadecimal number with a prefix. + */ +static void print_uint256(dif_acc_t *acc, const acc_addr_t var, + const char *prefix) { + uint32_t data[32 / sizeof(uint32_t)]; + CHECK_STATUS_OK(acc_testutils_read_data(acc, /*len_bytes=*/32, var, &data)); + LOG_INFO("%s0x%08x%08x%08x%08x%08x%08x%08x%08x", prefix, data[7], data[6], + data[5], data[4], data[3], data[2], data[1], data[0]); +} + +void acc_randomness_test_start(dif_acc_t *acc, uint32_t iters) { + acc_randomness_test_prepare(acc, iters); + CHECK_STATUS_OK(acc_testutils_execute(acc)); +} + +void acc_randomness_test_prepare(dif_acc_t *acc, uint32_t iters) { + // Reset the `kVarRv` value to ensure the result loaded by + // `acc_randomness_test_end()` is the one generated by ACC. + uint32_t rv = UINT32_MAX; + CHECK_STATUS_OK(acc_testutils_write_data(acc, sizeof(uint32_t), &rv, kVarRv)); + CHECK_STATUS_OK(acc_testutils_load_app(acc, kAccAppRandomnessApp)); + CHECK_STATUS_OK( + acc_testutils_write_data(acc, sizeof(uint32_t), &iters, kVarIters)); +} + +bool acc_randomness_test_end(dif_acc_t *acc, bool skip_acc_done_check) { + if (!skip_acc_done_check) { + CHECK_STATUS_OK(acc_testutils_wait_for_done(acc, kDifAccErrBitsNoError)); + } + uint32_t rv; + CHECK_STATUS_OK(acc_testutils_read_data(acc, /*len_bytes=*/4, kVarRv, &rv)); + if (rv != 0) { + uint32_t fail_idx; + CHECK_STATUS_OK( + acc_testutils_read_data(acc, /*len_bytes=*/4, kVarFailIdx, &fail_idx)); + LOG_ERROR("ERROR: Test with index %d failed.", fail_idx); + return false; + } + return true; +} + +void acc_randomness_test_log_results(dif_acc_t *acc) { + print_uint256(acc, kVarRndOut, "rnd = "); + print_uint256(acc, kVarUrndOut, "urnd = "); +} diff --git a/sw/device/tests/acc_randomness_impl.h b/sw/device/tests/acc_randomness_impl.h new file mode 100644 index 00000000000..a6e97355be4 --- /dev/null +++ b/sw/device/tests/acc_randomness_impl.h @@ -0,0 +1,58 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_TESTS_ACC_RANDOMNESS_IMPL_H_ +#define OPENTITAN_SW_DEVICE_TESTS_ACC_RANDOMNESS_IMPL_H_ + +#include + +#include "sw/device/lib/dif/dif_acc.h" + +/** + * Prepares the ACC randomness test. + * + * Does the same as acc_randomness_test_start() without + * executing the test. + * + * @param acc A ACC dif handle. + * @param iters The number of entropy requests to the RND CSR. + */ +void acc_randomness_test_prepare(dif_acc_t *acc, uint32_t iters); + +/** + * Starts ACC randomness test. + * + * Requires EDN0 and EDN1 to be serving entropy, as well as an initialized + * `acc` runtime handle. A Randomness test is loaded into ACC. Use the + * `acc_randomness_test_end()` function to check the test status. This function + * is non-blocking. + * + * @param acc A ACC dif handle. + * @param iters The number of entropy requests to the RND CSR. + */ +void acc_randomness_test_start(dif_acc_t *acc, uint32_t iters); + +/** + * Checks the ACC randomness test result. + * + * This function must be called after `acc_randomness_test_start()`. + * + * @param acc A ACC dif handle. + * @param skip_acc_done_check Set to true to skip ACC done execution check. + * The check is blocking. + * @returns true on test pass, false otherwise. + */ +bool acc_randomness_test_end(dif_acc_t *acc, bool skip_acc_done_check); + +/** + * Prints the randomness data generated by the test. + * + * This function must be called after ACC is done executing the program loaded + * by the `acc_randomness_test_start()` function. + * + * @param acc A ACC dif handle. + */ +void acc_randomness_test_log_results(dif_acc_t *acc); + +#endif // OPENTITAN_SW_DEVICE_TESTS_ACC_RANDOMNESS_IMPL_H_ diff --git a/sw/device/tests/otbn_randomness_test.c b/sw/device/tests/acc_randomness_test.c similarity index 56% rename from sw/device/tests/otbn_randomness_test.c rename to sw/device/tests/acc_randomness_test.c index 79ab607c2f9..abe1a697450 100644 --- a/sw/device/tests/otbn_randomness_test.c +++ b/sw/device/tests/acc_randomness_test.c @@ -2,54 +2,54 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "hw/top/dt/dt_otbn.h" // Generated +#include "hw/top/dt/dt_acc.h" // Generated #include "hw/top/dt/dt_rv_plic.h" // Generated +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_base.h" #include "sw/device/lib/dif/dif_clkmgr.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/irq.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/clkmgr_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/rv_plic_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" OTTF_DEFINE_TEST_CONFIG(); static const uint32_t kPlicTarget = 0; static dif_clkmgr_t clkmgr; -static const dif_clkmgr_hintable_clock_t kOtbnClock = +static const dif_clkmgr_hintable_clock_t kAccClock = #if defined(OPENTITAN_IS_EARLGREY) - kTopEarlgreyHintableClocksMainOtbn + kTopEarlgreyHintableClocksMainAcc #elif defined(OPENTITAN_IS_DARJEELING) - kTopDarjeelingHintableClocksMainOtbn + kTopDarjeelingHintableClocksMainAcc #else #error Unsupported top #endif ; static dif_rv_plic_t plic; -static dif_otbn_t otbn; +static dif_acc_t acc; /** * These variables are used for ISR communication hence they are volatile. */ static volatile dt_instance_id_t plic_peripheral; -static volatile dt_otbn_irq_t irq; +static volatile dt_acc_irq_t irq; /** - * Provides external IRQ handling for otbn tests. + * Provides external IRQ handling for acc tests. * * This function overrides the default OTTF external ISR. * * It performs the following: * 1. Claims the IRQ fired (finds PLIC IRQ index). - * 2. Compute the OTBN peripheral. - * 3. Compute the otbn irq. + * 2. Compute the ACC peripheral. + * 3. Compute the acc irq. * 4. Clears the IRQ at the peripheral. * 5. Completes the IRQ service at PLIC. */ @@ -59,11 +59,11 @@ void ottf_external_isr(uint32_t *exc_info) { (dif_rv_plic_irq_id_t *)&irq_id)); plic_peripheral = dt_plic_id_to_instance_id(irq_id); - if (plic_peripheral == dt_otbn_instance_id(kDtOtbn)) { - irq = dt_otbn_irq_from_plic_id(kDtOtbn, irq_id); + if (plic_peripheral == dt_acc_instance_id(kDtAcc)) { + irq = dt_acc_irq_from_plic_id(kDtAcc, irq_id); } - // Otbn clock is disabled, so we can not acknowledge the irq. Disabling it to + // Acc clock is disabled, so we can not acknowledge the irq. Disabling it to // avoid an infinite loop here. irq_global_ctrl(false); irq_external_ctrl(false); @@ -72,30 +72,29 @@ void ottf_external_isr(uint32_t *exc_info) { CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kPlicTarget, irq_id)); } -static void otbn_wait_for_done_irq(dif_otbn_t *otbn) { - // Clear the otbn irq variable: we'll set it in the interrupt handler when +static void acc_wait_for_done_irq(dif_acc_t *acc) { + // Clear the acc irq variable: we'll set it in the interrupt handler when // we see the Done interrupt fire. irq = UINT32_MAX; plic_peripheral = kDtInstanceIdUnknown; - CHECK_DIF_OK( - dif_otbn_irq_set_enabled(otbn, kDifOtbnIrqDone, kDifToggleEnabled)); + CHECK_DIF_OK(dif_acc_irq_set_enabled(acc, kDifAccIrqDone, kDifToggleEnabled)); - // OTBN should be running. Wait for an interrupt that says + // ACC should be running. Wait for an interrupt that says // it's done. ATOMIC_WAIT_FOR_INTERRUPT(plic_peripheral != kDtInstanceIdUnknown); - CHECK(plic_peripheral == dt_otbn_instance_id(kDtOtbn), + CHECK(plic_peripheral == dt_acc_instance_id(kDtAcc), "Interrupt from incorrect peripheral: (exp: %d, obs: %s)", - dt_otbn_instance_id(kDtOtbn), plic_peripheral); + dt_acc_instance_id(kDtAcc), plic_peripheral); // Check this is the interrupt we expected. - CHECK(irq == kDtOtbnIrqDone); + CHECK(irq == kDtAccIrqDone); } -static void otbn_init_irq(void) { +static void acc_init_irq(void) { CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic)); // Set interrupt priority to be positive. - dif_rv_plic_irq_id_t irq_id = dt_otbn_irq_to_plic_id(kDtOtbn, kDtOtbnIrqDone); + dif_rv_plic_irq_id_t irq_id = dt_acc_irq_to_plic_id(kDtAcc, kDtAccIrqDone); CHECK_DIF_OK(dif_rv_plic_irq_set_priority(&plic, irq_id, 0x1)); CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(&plic, irq_id, kPlicTarget, @@ -110,49 +109,49 @@ static void otbn_init_irq(void) { status_t initialize_clkmgr(void) { CHECK_DIF_OK(dif_clkmgr_init_from_dt(kDtClkmgrAon, &clkmgr)); - // Get initial hint and enable for OTBN clock and check both are enabled. + // Get initial hint and enable for ACC clock and check both are enabled. dif_toggle_t clock_hint_state; - CHECK_DIF_OK(dif_clkmgr_hintable_clock_get_hint(&clkmgr, kOtbnClock, + CHECK_DIF_OK(dif_clkmgr_hintable_clock_get_hint(&clkmgr, kAccClock, &clock_hint_state)); CHECK(clock_hint_state == kDifToggleEnabled); - return CLKMGR_TESTUTILS_CHECK_CLOCK_HINT(clkmgr, kOtbnClock, + return CLKMGR_TESTUTILS_CHECK_CLOCK_HINT(clkmgr, kAccClock, kDifToggleEnabled); } status_t execute_test(void) { - // Write the OTBN clk hint to 0 within clkmgr to indicate OTBN clk can be - // gated and verify that the OTBN clk hint status within clkmgr reads 0 (OTBN + // Write the ACC clk hint to 0 within clkmgr to indicate ACC clk can be + // gated and verify that the ACC clk hint status within clkmgr reads 0 (ACC // is idle). CLKMGR_TESTUTILS_SET_AND_CHECK_CLOCK_HINT( - clkmgr, kOtbnClock, kDifToggleDisabled, kDifToggleDisabled); + clkmgr, kAccClock, kDifToggleDisabled, kDifToggleDisabled); - // Write the OTBN clk hint to 1 within clkmgr to indicate OTBN clk can be + // Write the ACC clk hint to 1 within clkmgr to indicate ACC clk can be // enabled. CLKMGR_TESTUTILS_SET_AND_CHECK_CLOCK_HINT( - clkmgr, kOtbnClock, kDifToggleEnabled, kDifToggleEnabled); + clkmgr, kAccClock, kDifToggleEnabled, kDifToggleEnabled); - // Start an OTBN operation, write the OTBN clk hint to 0 within clkmgr and - // verify that the OTBN clk hint status within clkmgr reads 1 (OTBN is not + // Start an ACC operation, write the ACC clk hint to 0 within clkmgr and + // verify that the ACC clk hint status within clkmgr reads 1 (ACC is not // idle). - otbn_randomness_test_start(&otbn, /*iters=*/0); + acc_randomness_test_start(&acc, /*iters=*/0); CLKMGR_TESTUTILS_SET_AND_CHECK_CLOCK_HINT( - clkmgr, kOtbnClock, kDifToggleDisabled, kDifToggleEnabled); + clkmgr, kAccClock, kDifToggleDisabled, kDifToggleEnabled); - // After the OTBN operation is complete, verify that the OTBN clk hint status - // within clkmgr now reads 0 again (OTBN is idle). - otbn_wait_for_done_irq(&otbn); - CLKMGR_TESTUTILS_CHECK_CLOCK_HINT(clkmgr, kOtbnClock, kDifToggleDisabled); + // After the ACC operation is complete, verify that the ACC clk hint status + // within clkmgr now reads 0 again (ACC is idle). + acc_wait_for_done_irq(&acc); + CLKMGR_TESTUTILS_CHECK_CLOCK_HINT(clkmgr, kAccClock, kDifToggleDisabled); - // Write the OTBN clk hint to 1, read and check the OTBN output for + // Write the ACC clk hint to 1, read and check the ACC output for // correctness. CLKMGR_TESTUTILS_SET_AND_CHECK_CLOCK_HINT( - clkmgr, kOtbnClock, kDifToggleEnabled, kDifToggleEnabled); + clkmgr, kAccClock, kDifToggleEnabled, kDifToggleEnabled); - otbn_randomness_test_log_results(&otbn); + acc_randomness_test_log_results(&acc); // Check for successful test execution (self-reported). - TRY_CHECK(otbn_randomness_test_end(&otbn, /*skip_otbn_done_check=*/true)); + TRY_CHECK(acc_randomness_test_end(&acc, /*skip_acc_done_check=*/true)); return OK_STATUS(); } @@ -161,8 +160,8 @@ bool test_main(void) { CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); CHECK_STATUS_OK(initialize_clkmgr()); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); - otbn_init_irq(); + acc_init_irq(); return status_ok(execute_test()); } diff --git a/sw/device/tests/otbn_rsa_test.c b/sw/device/tests/acc_rsa_test.c similarity index 71% rename from sw/device/tests/otbn_rsa_test.c rename to sw/device/tests/acc_rsa_test.c index c6f7bb7b50a..560c35b3a08 100644 --- a/sw/device/tests/otbn_rsa_test.c +++ b/sw/device/tests/acc_rsa_test.c @@ -2,23 +2,23 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/dif/dif_otbn.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils_rsa.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils_rsa.h" #include "sw/device/lib/testing/profile.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" /** - * End-to-end RSA encryption and decryption test using OTBN. + * End-to-end RSA encryption and decryption test using ACC. * * IMPORTANT: This test is not a secure, complete, or reusable implementation of * RSA; it is not even close to being production-ready. It is only meant as an - * end-to-end test for OTBN during the bringup phase. + * end-to-end test for ACC during the bringup phase. * - * This test loads the RSA application into OTBN, sets all required input + * This test loads the RSA application into ACC, sets all required input * arguments, and performs the encryption and decryption operations. * * To keep the test execution time reasonable some parts of the test can be @@ -29,12 +29,12 @@ * * * # Optional: generate a new key - * $ openssl genpkey -algorithm RSA -out otbn_rsa_test_private_key_1024.pem \ + * $ openssl genpkey -algorithm RSA -out acc_rsa_test_private_key_1024.pem \ * -pkeyopt rsa_keygen_bits:1024 * * # Create all constants/variables - * $ ./otbn_test_params.py rsa otbn_rsa_test_private_key_1024.pem \ - * "Hello OTBN, can you encrypt and decrypt this for me?" + * $ ./acc_test_params.py rsa acc_rsa_test_private_key_1024.pem \ + * "Hello ACC, can you encrypt and decrypt this for me?" * */ @@ -95,10 +95,10 @@ static void check_data(const uint8_t *actual, const uint8_t *expected, * Performs a RSA roundtrip test. * * A roundtrip consists of three steps: - * - Initialize OTBN. - * - Encrypt data. Check that the OTBN-produced data matches + * - Initialize ACC. + * - Encrypt data. Check that the ACC-produced data matches * `encrypted_expected`. - * - If `kTestDecrypt` is set: Decrypt the encrypted data. Check that the OTBN- + * - If `kTestDecrypt` is set: Decrypt the encrypted data. Check that the ACC- * produced plaintext matches the original plaintext in `in`. * * @param size_bytes Size of all data arguments/buffers, in bytes. @@ -106,28 +106,28 @@ static void check_data(const uint8_t *actual, const uint8_t *expected, * @param private_exponent The private exponent (d). * @param in The input data of size `size_bytes`. * @param encrypted_expected The encrypted version of `in`. - * @param out_encrypted Buffer to hold the encrypted data, as produced by OTBN. - * @param out_decrypted Buffer to hold the decrypted data, as produced by OTBN. + * @param out_encrypted Buffer to hold the encrypted data, as produced by ACC. + * @param out_decrypted Buffer to hold the decrypted data, as produced by ACC. */ static void rsa_roundtrip(uint32_t size_bytes, const uint8_t *modulus, const uint8_t *private_exponent, const uint8_t *in, const uint8_t *encrypted_expected, uint8_t *out_encrypted, uint8_t *out_decrypted) { - dif_otbn_t otbn; + dif_acc_t acc; // Initialize uint64_t t_start = profile_start(); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); - CHECK_STATUS_OK(otbn_testutils_rsa_load(&otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); + CHECK_STATUS_OK(acc_testutils_rsa_load(&acc)); profile_end_and_print(t_start, "Initialization"); // Encrypt LOG_INFO("Encrypting"); t_start = profile_start(); CHECK_STATUS_OK( - otbn_testutils_rsa_modexp_f4_start(&otbn, modulus, in, size_bytes)); + acc_testutils_rsa_modexp_f4_start(&acc, modulus, in, size_bytes)); CHECK_STATUS_OK( - otbn_testutils_rsa_modexp_f4_finalize(&otbn, out_encrypted, size_bytes)); + acc_testutils_rsa_modexp_f4_finalize(&acc, out_encrypted, size_bytes)); check_data(out_encrypted, encrypted_expected, size_bytes); profile_end_and_print(t_start, "Encryption"); @@ -135,10 +135,10 @@ static void rsa_roundtrip(uint32_t size_bytes, const uint8_t *modulus, // Decrypt LOG_INFO("Decrypting"); t_start = profile_start(); - CHECK_STATUS_OK(otbn_testutils_rsa_modexp_consttime_start( - &otbn, modulus, private_exponent, encrypted_expected, size_bytes)); - CHECK_STATUS_OK(otbn_testutils_rsa_modexp_consttime_finalize( - &otbn, out_decrypted, size_bytes)); + CHECK_STATUS_OK(acc_testutils_rsa_modexp_consttime_start( + &acc, modulus, private_exponent, encrypted_expected, size_bytes)); + CHECK_STATUS_OK(acc_testutils_rsa_modexp_consttime_finalize( + &acc, out_decrypted, size_bytes)); check_data(out_decrypted, in, size_bytes); profile_end_and_print(t_start, "Decryption"); } @@ -162,15 +162,15 @@ static void test_rsa512_roundtrip(void) { 0x5c, 0x28, 0xde, 0x76, 0x6c, 0x2f, 0xcc, 0xf3, 0x31}; static const uint8_t kEncryptedExpected[kRsa512SizeBytes] = { - 0xb7, 0x02, 0x28, 0xcb, 0x63, 0x5e, 0xa6, 0xfd, 0x55, 0x4a, 0x85, - 0x43, 0x1d, 0x26, 0x13, 0xb3, 0x78, 0x66, 0xd9, 0xe2, 0xe1, 0xbf, - 0x29, 0xc6, 0xc6, 0xdd, 0x90, 0x76, 0x3f, 0x1d, 0x43, 0xc0, 0x76, - 0x51, 0x75, 0x10, 0x66, 0x61, 0x8c, 0x3c, 0x99, 0xd9, 0x90, 0xd2, - 0x59, 0x45, 0x0a, 0x7a, 0x6d, 0x58, 0xaa, 0x75, 0xf2, 0x63, 0xb3, - 0xe1, 0x06, 0x4b, 0x82, 0x0a, 0xdd, 0x07, 0x44, 0x2a}; + 0xee, 0xa0, 0xe9, 0xda, 0x33, 0xe9, 0x11, 0xeb, 0xfd, 0x96, 0xe3, + 0xa1, 0x2e, 0x50, 0x8d, 0xbe, 0xcf, 0xb7, 0x96, 0xb0, 0x89, 0x80, + 0x1a, 0xb6, 0xa0, 0xb7, 0xce, 0x19, 0x85, 0xcb, 0xf8, 0xe0, 0x42, + 0x2c, 0x80, 0x66, 0xf5, 0xd8, 0x9b, 0x1d, 0x52, 0x15, 0xca, 0x8e, + 0x91, 0x1d, 0x41, 0x50, 0x66, 0xdc, 0xf8, 0x5f, 0x9c, 0xd0, 0xcd, + 0x78, 0x26, 0x03, 0x94, 0xdd, 0x36, 0x37, 0x87, 0x6f}; static const uint8_t kIn[kRsa512SizeBytes] = { - "Hello OTBN, can you encrypt and decrypt this for me?"}; + "Hello ACC, can you encrypt and decrypt this for me?"}; uint8_t out_encrypted[kRsa512SizeBytes] = {0}; uint8_t out_decrypted[kRsa512SizeBytes] = {0}; @@ -207,20 +207,20 @@ static void test_rsa1024_roundtrip(void) { 0xac, 0x5d, 0x4e, 0x2e, 0x7b, 0x14, 0x1f, 0x3d}; static const uint8_t kEncryptedExpected[kRsa1024SizeBytes] = { - 0x76, 0x71, 0x99, 0x16, 0x38, 0x3a, 0xe0, 0xca, 0x9e, 0xc4, 0x5e, 0x9b, - 0x68, 0xb6, 0x3f, 0x78, 0x0d, 0x6e, 0x43, 0x7c, 0xaf, 0x24, 0xcc, 0x3e, - 0x4a, 0xd0, 0x3c, 0x15, 0xc6, 0x10, 0xf8, 0x3a, 0x1a, 0x6e, 0xe8, 0x8f, - 0x9e, 0x6b, 0xdb, 0x3d, 0xd3, 0x48, 0x51, 0x20, 0x8a, 0xb9, 0x36, 0xfb, - 0x9c, 0x2a, 0xd9, 0xef, 0xfc, 0x24, 0x7f, 0xb7, 0x81, 0x7d, 0x81, 0xb2, - 0x6f, 0xd0, 0x1e, 0xdd, 0x5c, 0x70, 0x1b, 0x79, 0x3b, 0x67, 0xe5, 0xfa, - 0xaf, 0x2e, 0xf3, 0xb2, 0xc6, 0xb1, 0xb9, 0x6d, 0x18, 0x79, 0x1a, 0xed, - 0x29, 0xfd, 0xf5, 0x27, 0x8c, 0xf2, 0x6e, 0xe4, 0x48, 0x88, 0xaf, 0x75, - 0xf5, 0xed, 0x09, 0xe7, 0x92, 0xbb, 0x30, 0x97, 0x1e, 0x45, 0x68, 0x81, - 0x6d, 0x69, 0x75, 0xcb, 0xbb, 0xbc, 0xc2, 0x51, 0x6e, 0xb8, 0xc9, 0x46, - 0x57, 0xe5, 0x27, 0xf7, 0x21, 0xb8, 0xd7, 0x2f}; + 0xdf, 0xa5, 0x3c, 0x63, 0xdd, 0x01, 0x27, 0xc9, 0x5a, 0x55, 0xfc, 0xdf, + 0xf7, 0x64, 0x77, 0x99, 0xce, 0xd7, 0x22, 0xd5, 0xdb, 0x79, 0x61, 0xb3, + 0x0c, 0x5c, 0xed, 0xb9, 0xf4, 0x3a, 0x1a, 0xc7, 0x92, 0xa6, 0xbe, 0x62, + 0x9f, 0x93, 0x3c, 0x23, 0x3f, 0xef, 0x5b, 0x42, 0x1e, 0x79, 0x11, 0x39, + 0xf6, 0x48, 0xee, 0xf5, 0xcf, 0x7e, 0xb4, 0x6e, 0x5c, 0xc9, 0x9e, 0x63, + 0xad, 0xb0, 0x88, 0xa7, 0x79, 0x41, 0x49, 0xc9, 0x7d, 0x29, 0x0b, 0xbc, + 0x2c, 0x27, 0xd7, 0x11, 0xbf, 0x65, 0xcb, 0x00, 0xb8, 0xc4, 0x47, 0xb7, + 0x1d, 0xe3, 0xa6, 0xf3, 0xff, 0xcc, 0x81, 0x55, 0x11, 0x32, 0x30, 0xaa, + 0x6a, 0x8a, 0xb0, 0x7e, 0x6b, 0x99, 0x29, 0xab, 0x23, 0xb8, 0xff, 0xc4, + 0x4d, 0x07, 0xbd, 0x54, 0x16, 0xc5, 0x78, 0x1e, 0xa8, 0xec, 0x9f, 0x0d, + 0xfd, 0xaf, 0x26, 0xde, 0x14, 0x75, 0xbe, 0x55}; static const uint8_t kIn[kRsa1024SizeBytes] = { - "Hello OTBN, can you encrypt and decrypt this for me?"}; + "Hello ACC, can you encrypt and decrypt this for me?"}; uint8_t out_encrypted[kRsa1024SizeBytes] = {0}; uint8_t out_decrypted[kRsa1024SizeBytes] = {0}; @@ -279,30 +279,30 @@ static void test_rsa2048_roundtrip(void) { 0x67, 0x9a, 0x63, 0x9e}; static const uint8_t kEncryptedExpected[kRsa2048SizeBytes] = { - 0x54, 0x83, 0x7c, 0xb0, 0xd9, 0x77, 0x76, 0xb5, 0xf5, 0xc8, 0x51, 0x02, - 0x41, 0xab, 0xeb, 0xa6, 0x8e, 0x01, 0x15, 0x54, 0x30, 0x9b, 0x05, 0xb6, - 0xbf, 0x40, 0x3d, 0xd2, 0x95, 0x62, 0xf7, 0x42, 0x4d, 0xf8, 0x3b, 0xd6, - 0x0b, 0x9e, 0xef, 0x27, 0x2f, 0x95, 0x8e, 0x8a, 0xaf, 0x07, 0xe9, 0x54, - 0x66, 0xc0, 0xe9, 0x1c, 0xdd, 0x1b, 0xfb, 0x91, 0xe3, 0xa6, 0x83, 0x6f, - 0xa4, 0x74, 0x49, 0x75, 0x7f, 0x35, 0x8e, 0x40, 0x04, 0x72, 0xb9, 0xe2, - 0x78, 0x4c, 0x4a, 0x3e, 0x37, 0xe9, 0x19, 0xe8, 0x61, 0xf4, 0xaa, 0x7d, - 0x27, 0xd1, 0x55, 0x40, 0x59, 0x5b, 0x3c, 0x88, 0x70, 0x76, 0x09, 0x49, - 0x8c, 0x3c, 0x66, 0xe1, 0x85, 0x8e, 0xe9, 0x79, 0xfe, 0x8f, 0xc0, 0xfd, - 0x40, 0xbf, 0xf3, 0x87, 0xa9, 0x45, 0xb1, 0xce, 0xb2, 0xb8, 0x4b, 0xc2, - 0x60, 0xcd, 0xda, 0xe5, 0x30, 0xf3, 0xd2, 0x38, 0xfd, 0x9d, 0x6e, 0x15, - 0x5f, 0xa3, 0x24, 0x22, 0x90, 0x08, 0x09, 0x2b, 0x2d, 0x6e, 0x15, 0xe0, - 0x97, 0x31, 0x1f, 0x85, 0x47, 0x72, 0x69, 0xf9, 0xd2, 0x5a, 0xcc, 0xe4, - 0x9d, 0x17, 0xf2, 0x81, 0x73, 0x8c, 0x40, 0x61, 0x56, 0x6f, 0xbf, 0xd0, - 0xa5, 0x20, 0xed, 0x37, 0x22, 0x5a, 0xab, 0xb6, 0x8e, 0x12, 0x87, 0x1b, - 0xcd, 0x34, 0xda, 0x79, 0x0d, 0x35, 0x7c, 0xa4, 0xd1, 0xfa, 0x44, 0x09, - 0xb9, 0xf0, 0x0b, 0xb2, 0xfb, 0xd3, 0xf1, 0xfd, 0xd8, 0x2f, 0x30, 0x15, - 0xe2, 0x75, 0x18, 0x90, 0x3b, 0x33, 0xc5, 0x4a, 0x3d, 0x19, 0xd1, 0xb9, - 0x35, 0x59, 0x2d, 0x2a, 0x0a, 0x51, 0xfe, 0xad, 0x03, 0xcd, 0x05, 0x8c, - 0xb6, 0xeb, 0x5f, 0x66, 0xb9, 0x40, 0x1e, 0xd0, 0xce, 0xa5, 0xe1, 0x8e, - 0x47, 0xb7, 0xb7, 0x55, 0x06, 0x92, 0xe5, 0x6f, 0xc9, 0x92, 0xc7, 0x80, - 0x26, 0x2d, 0x3f, 0x2d}; - - static const uint8_t kIn[kRsa2048SizeBytes] = {"OTBN is great!"}; + 0xf8, 0xf7, 0xb8, 0xcc, 0x7a, 0x26, 0xc7, 0xbc, 0x30, 0xbf, 0xea, 0x6e, + 0x73, 0xbc, 0x41, 0x36, 0x81, 0x91, 0x21, 0x2a, 0xd9, 0xe7, 0x29, 0xc9, + 0xc9, 0x84, 0x75, 0x91, 0x60, 0xcb, 0x1a, 0x99, 0x1f, 0x8b, 0xd2, 0x89, + 0x8b, 0x17, 0x9a, 0x4b, 0x2c, 0x69, 0x20, 0x15, 0x97, 0x1f, 0xd1, 0xfa, + 0xdd, 0x52, 0x44, 0xf9, 0xef, 0x53, 0xad, 0x2b, 0x29, 0xb5, 0x87, 0x2e, + 0xfc, 0x89, 0xb8, 0x68, 0xd0, 0x62, 0x22, 0x79, 0x82, 0xda, 0x06, 0x32, + 0x81, 0x5c, 0x95, 0x3f, 0x2c, 0x0c, 0xea, 0xdc, 0x79, 0xf0, 0x27, 0xe6, + 0xaf, 0xc8, 0x10, 0x21, 0x08, 0xe8, 0x07, 0x79, 0x2f, 0x57, 0x97, 0x87, + 0xd0, 0x05, 0xbb, 0xfc, 0x6d, 0x94, 0x69, 0x4b, 0x30, 0xae, 0xe3, 0x3e, + 0xf9, 0x43, 0x96, 0x9f, 0x16, 0xc5, 0xa7, 0x73, 0x80, 0x00, 0x76, 0x24, + 0xdd, 0x4c, 0x6a, 0xe1, 0x41, 0x04, 0x84, 0x08, 0xee, 0x36, 0x04, 0x09, + 0xb4, 0xa6, 0xcd, 0xb9, 0x7a, 0x3a, 0xd5, 0x15, 0xeb, 0xc1, 0x06, 0x74, + 0x1a, 0x0d, 0x65, 0x82, 0x5c, 0xb5, 0xbf, 0xb2, 0x95, 0x27, 0x87, 0x2a, + 0x84, 0xa2, 0xc1, 0x6d, 0xad, 0x13, 0xb5, 0x6b, 0xed, 0x43, 0xf6, 0x08, + 0x2f, 0x6d, 0x21, 0xa3, 0xc3, 0xb5, 0x23, 0x91, 0xdd, 0xea, 0x60, 0x63, + 0xf1, 0xde, 0x5d, 0xae, 0xe8, 0x5a, 0x6e, 0xfb, 0xd7, 0xf2, 0xff, 0x58, + 0x61, 0x22, 0x9a, 0xcc, 0x82, 0xab, 0x67, 0x2a, 0xa2, 0x41, 0xc9, 0x4f, + 0x80, 0x4b, 0x52, 0xa1, 0x06, 0xc2, 0xd7, 0xe9, 0xf2, 0x7c, 0x32, 0xeb, + 0x59, 0xb6, 0xa4, 0xbd, 0x9f, 0x99, 0x76, 0x4e, 0xea, 0xff, 0x29, 0x84, + 0x9a, 0xf2, 0x32, 0xba, 0xc8, 0x4c, 0xe4, 0x12, 0xe8, 0xb5, 0xa3, 0x0d, + 0x21, 0x13, 0xe7, 0xbf, 0xd4, 0x6a, 0xc4, 0x59, 0xdf, 0x14, 0x0f, 0xd1, + 0x69, 0x4f, 0x07, 0x8c}; + + static const uint8_t kIn[kRsa2048SizeBytes] = {"ACC is great!"}; uint8_t out_encrypted[kRsa2048SizeBytes] = {0}; uint8_t out_decrypted[kRsa2048SizeBytes] = {0}; @@ -381,41 +381,41 @@ static void test_rsa3072_roundtrip(void) { 0xd2, 0x25, 0xa9, 0xb6, 0xc8, 0x8d, 0x85, 0x8c, 0x00, 0x45, 0xf9, 0x32}; static const uint8_t kEncryptedExpected[kRsa3072SizeBytes] = { - 0x45, 0x91, 0x09, 0xad, 0x6a, 0xbd, 0xc1, 0x7f, 0x68, 0xea, 0x1e, 0xad, - 0xb7, 0x59, 0xfa, 0x98, 0xa6, 0x13, 0x03, 0x35, 0x45, 0x45, 0x64, 0xca, - 0x10, 0xa3, 0x47, 0x08, 0x45, 0xc9, 0x25, 0x7a, 0xd4, 0x62, 0x77, 0xe7, - 0xfa, 0xb8, 0x03, 0x96, 0xfc, 0xb7, 0x0c, 0x20, 0x0c, 0x1f, 0xd6, 0xcc, - 0x13, 0xe0, 0x0c, 0x47, 0x11, 0x8b, 0x82, 0x77, 0x3f, 0x9b, 0x65, 0x90, - 0x54, 0x8a, 0xff, 0x83, 0xbe, 0xf4, 0xa1, 0x2a, 0xf0, 0x3c, 0xb4, 0x1b, - 0xdd, 0x03, 0xd4, 0x87, 0x20, 0xad, 0x5d, 0x1e, 0xb8, 0x74, 0xc7, 0x91, - 0x0c, 0x14, 0x56, 0x92, 0xda, 0xc4, 0x99, 0x43, 0x2d, 0x27, 0x80, 0x72, - 0x5f, 0x20, 0xfe, 0xf8, 0xcb, 0x2e, 0xd4, 0xe4, 0x47, 0x19, 0x64, 0x72, - 0xb8, 0x45, 0xd8, 0x58, 0x45, 0x60, 0x53, 0xf3, 0x81, 0xa9, 0xd9, 0xad, - 0xac, 0x02, 0xc1, 0x1a, 0xf0, 0x6d, 0x93, 0xcc, 0x42, 0xda, 0x74, 0xd9, - 0x48, 0x05, 0xde, 0xd7, 0x4e, 0x23, 0x79, 0x63, 0x81, 0x3e, 0xc9, 0x23, - 0xff, 0x24, 0x61, 0x84, 0x01, 0x65, 0xea, 0x10, 0xa9, 0xc9, 0xc1, 0x77, - 0xcd, 0x06, 0x79, 0xb9, 0xeb, 0xeb, 0x2f, 0xd6, 0x43, 0xe1, 0xa3, 0x6d, - 0xfc, 0xb7, 0x1f, 0x6d, 0x05, 0x9d, 0x8c, 0x9f, 0xd5, 0xb7, 0x73, 0xdc, - 0xf0, 0x52, 0xe9, 0x18, 0x17, 0x1d, 0x12, 0x95, 0xa8, 0xc1, 0xff, 0x99, - 0xa7, 0x93, 0x6e, 0x3b, 0x93, 0x0a, 0x9d, 0x15, 0x21, 0x19, 0xe2, 0xa8, - 0x42, 0x1c, 0x3b, 0xf5, 0x5f, 0x33, 0xa9, 0x0e, 0x74, 0x84, 0xd6, 0x4c, - 0x37, 0x92, 0x84, 0x87, 0xdb, 0xa4, 0x80, 0x65, 0x39, 0x3f, 0xf8, 0x0e, - 0xb7, 0x77, 0xd9, 0x1d, 0x7c, 0x0a, 0x7f, 0x57, 0x7e, 0xa6, 0xce, 0xc3, - 0x61, 0x3d, 0x34, 0x8c, 0x48, 0x12, 0x4c, 0x80, 0x85, 0x14, 0xa5, 0x85, - 0x6c, 0x95, 0x3e, 0xaf, 0xca, 0xd3, 0x51, 0x4b, 0xf8, 0xc9, 0x16, 0x1f, - 0xfa, 0x5c, 0x4a, 0xe5, 0x9d, 0xab, 0xc4, 0xa3, 0xf4, 0xc3, 0xe9, 0x71, - 0x81, 0x1f, 0x2e, 0x40, 0x35, 0x35, 0x24, 0xf2, 0x6d, 0x26, 0xb9, 0x0d, - 0x9e, 0x23, 0x4f, 0xfb, 0xc2, 0x9e, 0x32, 0x4e, 0x05, 0xa0, 0xee, 0x6c, - 0xe6, 0x6e, 0x94, 0x1d, 0x1c, 0xf0, 0xb8, 0x53, 0x56, 0x88, 0x36, 0x0b, - 0x78, 0x96, 0x6e, 0x3f, 0x94, 0x00, 0xe8, 0x93, 0x4a, 0x37, 0xa5, 0xf8, - 0xe6, 0x20, 0xa4, 0x56, 0x4b, 0xf2, 0x41, 0x34, 0x4e, 0x20, 0x5e, 0x65, - 0xa4, 0x0b, 0xd6, 0xe9, 0x6f, 0x1b, 0x9f, 0x4b, 0x09, 0xd7, 0x47, 0x97, - 0x99, 0xb4, 0x03, 0xbc, 0x84, 0x82, 0xc0, 0xc0, 0x34, 0x53, 0xcc, 0x29, - 0xb3, 0xe7, 0x2d, 0xf8, 0xd8, 0x4d, 0x94, 0x47, 0xb2, 0xc5, 0xef, 0x36, - 0xef, 0x65, 0x15, 0x32, 0x4f, 0x91, 0x99, 0x24, 0x15, 0x69, 0x65, 0x0c}; + 0x20, 0xae, 0x8c, 0xb7, 0x53, 0x8d, 0x3c, 0x7b, 0x34, 0xf4, 0xf7, 0x7d, + 0x9d, 0x87, 0x96, 0x9f, 0x7a, 0x2a, 0x34, 0xe1, 0xcb, 0x62, 0x44, 0x67, + 0xdc, 0x25, 0xfd, 0x74, 0xc0, 0x21, 0x5a, 0xba, 0x88, 0x78, 0x61, 0xf9, + 0x12, 0x0c, 0xb2, 0x26, 0x9c, 0x2e, 0xcf, 0x4d, 0xd5, 0xf0, 0x65, 0xa8, + 0x18, 0x70, 0x85, 0xfa, 0x3a, 0xed, 0xa8, 0xe6, 0x30, 0x85, 0x73, 0xd4, + 0x36, 0xc4, 0xc8, 0x15, 0x3f, 0xce, 0x31, 0x3d, 0x00, 0x2e, 0x9d, 0x66, + 0x2e, 0x1e, 0xb6, 0x8b, 0x35, 0x41, 0xaa, 0x2d, 0x18, 0xc9, 0x5f, 0xe2, + 0xf9, 0x83, 0x82, 0xf4, 0x38, 0x2a, 0x03, 0x70, 0x20, 0x46, 0xea, 0xa1, + 0x90, 0x8c, 0xbe, 0x78, 0x0c, 0x5e, 0xf4, 0xfc, 0x23, 0x03, 0xd8, 0xd8, + 0xa7, 0xef, 0x06, 0xca, 0xda, 0x8c, 0x27, 0x0b, 0xaf, 0x7b, 0x8c, 0x96, + 0x70, 0xbd, 0x93, 0x83, 0x0c, 0xf7, 0x9c, 0x94, 0x32, 0x17, 0x93, 0xac, + 0x99, 0x90, 0x13, 0x4f, 0xdc, 0xe2, 0x11, 0xa3, 0xc3, 0x07, 0x34, 0xca, + 0xd3, 0x6f, 0x54, 0x41, 0x16, 0xa9, 0x3b, 0x8f, 0x32, 0x0c, 0x2f, 0x2d, + 0xab, 0x22, 0xb6, 0x6a, 0x1f, 0x36, 0x05, 0x88, 0x25, 0x1d, 0xb1, 0xc4, + 0xc9, 0xf2, 0x49, 0xf6, 0x85, 0x2a, 0x3b, 0xf3, 0xb7, 0x2d, 0xda, 0x8a, + 0x01, 0x68, 0x6c, 0x02, 0xea, 0xcc, 0xe5, 0x62, 0x68, 0x6a, 0xe3, 0x0e, + 0x1e, 0xbf, 0xf2, 0xfe, 0x88, 0xe3, 0x8d, 0x0c, 0x0f, 0x19, 0x98, 0xe4, + 0x9a, 0xce, 0xa3, 0x9d, 0xa8, 0xd0, 0x7e, 0x22, 0x5f, 0x7d, 0x42, 0x6e, + 0x4a, 0xcf, 0x1b, 0x7e, 0xe2, 0x2f, 0x17, 0xe7, 0x68, 0x52, 0xdd, 0x43, + 0x60, 0x1a, 0x73, 0xd5, 0x9e, 0x8e, 0x2a, 0x05, 0x2e, 0xe7, 0xea, 0x3a, + 0x57, 0x29, 0xd5, 0x67, 0x71, 0x46, 0x89, 0x71, 0x3f, 0x35, 0x87, 0xca, + 0xf2, 0x28, 0x22, 0x43, 0x6d, 0x7d, 0xdc, 0xde, 0x55, 0xd2, 0x07, 0x25, + 0x4f, 0x1f, 0x08, 0x89, 0xac, 0x0f, 0xb0, 0xbf, 0x5b, 0x90, 0x34, 0x8c, + 0x4c, 0xc0, 0xec, 0xec, 0x9d, 0xfc, 0xe5, 0x98, 0x53, 0x5c, 0x9d, 0x3a, + 0x73, 0xfa, 0xaf, 0x79, 0x45, 0xfb, 0x25, 0x7e, 0xdd, 0x64, 0xd2, 0x11, + 0x91, 0x5f, 0xc2, 0x65, 0x61, 0xcc, 0x56, 0xea, 0x8d, 0x70, 0x9f, 0x6e, + 0x34, 0xde, 0x8c, 0xce, 0x2f, 0x47, 0xc1, 0x40, 0x11, 0x5b, 0xf0, 0x06, + 0xb0, 0x43, 0x6f, 0x88, 0x3f, 0x02, 0x36, 0x75, 0x57, 0xb0, 0xb8, 0xc5, + 0xc0, 0x13, 0x5f, 0x60, 0xa4, 0x24, 0x75, 0xda, 0xa3, 0x44, 0x4c, 0x99, + 0x0b, 0x0b, 0x3e, 0x10, 0x92, 0x13, 0xb7, 0xd5, 0xf2, 0x64, 0x63, 0x9d, + 0x5b, 0x75, 0x2e, 0xb0, 0x8d, 0x4b, 0xd6, 0x68, 0x90, 0x45, 0x06, 0xd1, + 0xd1, 0x6a, 0xb2, 0x4e, 0x04, 0x28, 0x37, 0x1d, 0xbe, 0xac, 0xd2, 0x0c}; static const uint8_t kIn[kRsa3072SizeBytes] = { - "OpenTitan proudly presents: OTBN"}; + "OpenTitan proudly presents: ACC"}; uint8_t out_encrypted[kRsa3072SizeBytes] = {0}; uint8_t out_decrypted[kRsa3072SizeBytes] = {0}; @@ -516,51 +516,51 @@ static void test_rsa4096_roundtrip(void) { 0x6f, 0x9b, 0x99, 0x46, 0x7f, 0x20, 0x4a, 0x43}; static const uint8_t kEncryptedExpected[kRsa4096SizeBytes] = { - 0x59, 0x13, 0x5c, 0x73, 0xb2, 0xee, 0xe6, 0x48, 0x24, 0x95, 0x80, 0xe3, - 0x5b, 0x54, 0x08, 0x7d, 0x81, 0x98, 0x4a, 0x64, 0xb0, 0xf4, 0x06, 0x29, - 0x6d, 0x4a, 0x51, 0x9c, 0x12, 0xcd, 0xe3, 0x4a, 0x5b, 0x48, 0x7a, 0x84, - 0x8c, 0x0c, 0x76, 0x77, 0x28, 0x23, 0xf2, 0x77, 0x62, 0x32, 0xfa, 0x03, - 0x31, 0x62, 0x83, 0x2f, 0x04, 0x97, 0x94, 0x28, 0x56, 0xa9, 0x0d, 0xaf, - 0x25, 0x85, 0xb4, 0x55, 0x87, 0x50, 0xde, 0xed, 0x1f, 0x37, 0xd4, 0xc8, - 0x39, 0x51, 0x70, 0x7a, 0x1e, 0x36, 0xd3, 0x24, 0x04, 0x94, 0x5f, 0xa3, - 0xc1, 0xf9, 0x14, 0x62, 0x1e, 0x03, 0xb6, 0x3c, 0xd6, 0x7b, 0x55, 0x1d, - 0x23, 0x64, 0x9d, 0x7e, 0xcc, 0x74, 0xba, 0x9a, 0x57, 0x29, 0xcd, 0xea, - 0x13, 0xf9, 0x41, 0xca, 0xe7, 0x31, 0x95, 0xf3, 0x78, 0x2f, 0x8f, 0x91, - 0x59, 0x36, 0x11, 0x28, 0xae, 0x01, 0x82, 0x05, 0x78, 0x68, 0xc9, 0x6a, - 0xee, 0x1c, 0x7b, 0x48, 0x4d, 0x55, 0xa5, 0x64, 0x43, 0xe2, 0x90, 0x4e, - 0x1e, 0x12, 0x4b, 0x5c, 0xa6, 0xb9, 0x12, 0x57, 0xe0, 0x9a, 0x19, 0x88, - 0xa8, 0x10, 0x8b, 0x92, 0x26, 0xf8, 0x62, 0x9e, 0x46, 0xcf, 0x65, 0xcf, - 0xdd, 0xcc, 0xb1, 0x23, 0xaf, 0x55, 0x3a, 0x8f, 0x47, 0xa6, 0x8a, 0xd9, - 0x1b, 0x19, 0x5b, 0x5e, 0x5f, 0x6c, 0xa6, 0x4e, 0xb8, 0xa7, 0x6d, 0x2f, - 0x6b, 0x0e, 0xd0, 0x0c, 0xf2, 0x01, 0xa3, 0xfd, 0x2a, 0x67, 0x5b, 0x81, - 0x21, 0x32, 0x25, 0x79, 0x95, 0x8f, 0x78, 0x05, 0x92, 0x45, 0x4a, 0x67, - 0x26, 0xd6, 0xc6, 0x5e, 0x17, 0xd3, 0xbb, 0x00, 0x14, 0x13, 0xb9, 0xa4, - 0x0d, 0x0a, 0xd4, 0x98, 0xff, 0x8f, 0x57, 0x13, 0xc2, 0x16, 0x0c, 0xc0, - 0x70, 0x67, 0x1a, 0x5d, 0xd0, 0xc7, 0xa1, 0x58, 0x28, 0x74, 0x67, 0x9c, - 0x19, 0xee, 0xef, 0x94, 0x79, 0xc4, 0x60, 0xb8, 0x6e, 0x47, 0x45, 0xe1, - 0x51, 0xd9, 0x57, 0x53, 0x24, 0x4d, 0x44, 0xc5, 0xf3, 0xbc, 0x15, 0x7e, - 0xfe, 0x7d, 0x2b, 0xb0, 0x51, 0xa3, 0x77, 0x76, 0xd4, 0x85, 0x51, 0x6d, - 0xeb, 0x6f, 0x31, 0x45, 0x63, 0x1e, 0x64, 0xac, 0x11, 0x2f, 0xbc, 0x2c, - 0xc0, 0xe8, 0x39, 0x8d, 0x8c, 0x40, 0x01, 0x41, 0x03, 0xd1, 0xce, 0xfb, - 0x68, 0x42, 0x0e, 0x63, 0xf3, 0xd0, 0x63, 0xf6, 0xc9, 0xc9, 0x84, 0xfc, - 0x90, 0x59, 0x2d, 0x7a, 0x85, 0x1a, 0x7d, 0xd6, 0x11, 0x73, 0xe2, 0x45, - 0x40, 0x72, 0x82, 0x08, 0xcd, 0x3b, 0x19, 0x26, 0x20, 0x7c, 0x86, 0x1d, - 0xde, 0xbf, 0x4f, 0xb7, 0x49, 0x2b, 0xc3, 0x2f, 0x1a, 0x8e, 0x5b, 0xeb, - 0x1e, 0xf5, 0xa9, 0xb6, 0x59, 0xdf, 0xca, 0x5a, 0x07, 0x95, 0xaf, 0x1a, - 0xbf, 0x2c, 0x2a, 0x18, 0x02, 0xeb, 0x76, 0xa3, 0xad, 0x53, 0x4e, 0xf3, - 0x18, 0xe4, 0xb9, 0xac, 0x76, 0x80, 0x8a, 0xe0, 0x37, 0x36, 0x29, 0x34, - 0x20, 0x52, 0x45, 0x81, 0x80, 0xb0, 0x1c, 0xd4, 0xac, 0x56, 0x50, 0xc6, - 0x1b, 0xe3, 0xbf, 0xa4, 0xd8, 0x55, 0xd8, 0xdd, 0xbe, 0x3a, 0x9e, 0x5f, - 0x65, 0xc7, 0xa0, 0x14, 0xb8, 0xa8, 0x75, 0x61, 0x5f, 0x50, 0xba, 0x2b, - 0x41, 0x6c, 0xf5, 0x4b, 0x9e, 0xf1, 0x66, 0xc4, 0x2a, 0xbb, 0xc5, 0xaf, - 0x10, 0x92, 0x70, 0xc9, 0x1b, 0xcd, 0x59, 0x3a, 0x17, 0xaa, 0x5e, 0xf3, - 0x6c, 0x48, 0x1b, 0xe8, 0xee, 0x8f, 0x00, 0xbb, 0xcf, 0xa6, 0x90, 0xa1, - 0xfd, 0x61, 0x19, 0x5d, 0xba, 0x55, 0xbe, 0x50, 0x77, 0xd5, 0xcc, 0xea, - 0xe8, 0x0a, 0x98, 0x48, 0x15, 0xb5, 0xee, 0x22, 0xc4, 0xab, 0x04, 0xfb, - 0xcb, 0x2c, 0x05, 0x1f, 0xef, 0x72, 0x4d, 0xf9, 0x5b, 0x29, 0x1c, 0x07, - 0x9e, 0xd4, 0x63, 0xe2, 0x9f, 0xfd, 0x04, 0x39}; - - static const uint8_t kIn[kRsa4096SizeBytes] = {"OTBN is doing RSA here"}; + 0x1c, 0xc9, 0x35, 0x1e, 0x42, 0x0b, 0x31, 0x7e, 0x41, 0x16, 0x77, 0x62, + 0x05, 0x8d, 0xfc, 0xed, 0x56, 0xca, 0xb2, 0x9c, 0xb6, 0x9c, 0x1f, 0x21, + 0xdb, 0x71, 0x0c, 0x23, 0x14, 0x45, 0x52, 0xb9, 0x0f, 0xfb, 0x90, 0xf9, + 0x4f, 0xc8, 0xec, 0xf6, 0x35, 0xf9, 0x8b, 0xd4, 0xae, 0x8a, 0x1c, 0x35, + 0x78, 0x14, 0x90, 0x2b, 0xd5, 0xaa, 0x08, 0x14, 0x88, 0xa4, 0x5f, 0x07, + 0xbf, 0xf7, 0x7c, 0x85, 0xcc, 0x2d, 0x92, 0xbc, 0x25, 0x36, 0x2e, 0xf1, + 0xa5, 0x1c, 0x7e, 0x6b, 0x3e, 0x12, 0x7f, 0x2f, 0x09, 0x97, 0x53, 0x43, + 0x0a, 0x9f, 0x44, 0x5b, 0xe9, 0x0d, 0x2d, 0x0a, 0x76, 0xe9, 0xf0, 0x79, + 0x82, 0x0f, 0x21, 0x3a, 0x00, 0x59, 0x3b, 0x03, 0x79, 0x0e, 0x38, 0x18, + 0x90, 0x53, 0x3a, 0x60, 0xa3, 0x51, 0x43, 0x6f, 0x1a, 0x64, 0x65, 0x4d, + 0x98, 0x20, 0x7d, 0xcc, 0xe3, 0x26, 0xc7, 0x61, 0x8f, 0x95, 0x69, 0xbd, + 0xa7, 0x60, 0xbf, 0x4d, 0x26, 0x61, 0x43, 0x35, 0x71, 0xba, 0xb2, 0xf6, + 0x4f, 0x8b, 0x91, 0x5d, 0x2c, 0xd6, 0xa9, 0xda, 0x69, 0xd0, 0xfc, 0x73, + 0x46, 0xae, 0x61, 0x8c, 0x70, 0x98, 0x5c, 0x35, 0x31, 0xdc, 0x1a, 0x46, + 0x1a, 0x78, 0x19, 0xd2, 0x2e, 0xbe, 0x0f, 0x89, 0xc1, 0x10, 0x85, 0x0a, + 0x02, 0xbe, 0x09, 0xd8, 0x98, 0xe4, 0x17, 0x75, 0xcd, 0x25, 0xe0, 0x55, + 0x8e, 0x21, 0xa9, 0xdd, 0xcf, 0xa1, 0x89, 0xde, 0x67, 0xc8, 0xa6, 0x6f, + 0x4f, 0x49, 0xcb, 0xa5, 0xe9, 0xc2, 0xc3, 0x1f, 0xe0, 0x72, 0xe0, 0x8e, + 0xd6, 0x88, 0xa1, 0xb9, 0x69, 0xda, 0x8e, 0xae, 0xd6, 0x59, 0x5c, 0x67, + 0xf1, 0x0f, 0x1a, 0xe5, 0xb8, 0x1f, 0x6a, 0x86, 0x8c, 0xac, 0x71, 0x01, + 0x3a, 0x2e, 0xaa, 0x58, 0x1a, 0x95, 0x6e, 0x74, 0x53, 0xf6, 0xbd, 0x5b, + 0xa6, 0xe0, 0x33, 0x1f, 0x8e, 0x4f, 0x6c, 0xbc, 0x7b, 0x59, 0x08, 0x35, + 0x76, 0x7d, 0x22, 0x5b, 0x2e, 0x6e, 0x22, 0xc0, 0xcf, 0x80, 0x85, 0xb6, + 0x58, 0x53, 0x21, 0xbd, 0xcf, 0x98, 0x1c, 0x32, 0x3b, 0x95, 0xe1, 0xfe, + 0xfb, 0x40, 0x77, 0x66, 0x48, 0x56, 0xe9, 0xaa, 0x65, 0x71, 0x60, 0x5a, + 0xfc, 0xe2, 0x0d, 0xa4, 0xea, 0xcd, 0xae, 0x05, 0x47, 0xbe, 0x2b, 0x55, + 0x07, 0x95, 0x42, 0xb5, 0x86, 0x98, 0x17, 0xe4, 0x5c, 0x04, 0x1f, 0x6a, + 0xc1, 0x06, 0xbb, 0xab, 0x74, 0x89, 0xcd, 0xda, 0xdc, 0xd7, 0x0e, 0x4a, + 0x0e, 0x6e, 0x29, 0x0a, 0xed, 0x98, 0x43, 0x91, 0x51, 0x4f, 0x0f, 0xb0, + 0x77, 0x66, 0x84, 0xa5, 0x47, 0xb3, 0x0a, 0x43, 0x4c, 0x67, 0xde, 0xc9, + 0x11, 0xf9, 0x2a, 0xab, 0x8a, 0x8b, 0xff, 0xc2, 0xe4, 0xfd, 0x59, 0x58, + 0xfc, 0xe6, 0xa2, 0x7d, 0x36, 0x31, 0x70, 0xb8, 0x71, 0x18, 0x87, 0x39, + 0x17, 0x3c, 0xc0, 0x2a, 0x64, 0x80, 0x33, 0x38, 0x8c, 0x62, 0xe3, 0x41, + 0x11, 0xa1, 0x5e, 0x9f, 0x21, 0x55, 0xd9, 0x26, 0x5c, 0xef, 0x81, 0x8c, + 0xef, 0xfb, 0xdb, 0xda, 0x70, 0x0e, 0xf2, 0x94, 0x9a, 0x9d, 0x21, 0x6e, + 0x29, 0x20, 0x52, 0x23, 0x25, 0x58, 0x2f, 0xd5, 0x96, 0xe4, 0xfb, 0x74, + 0xbc, 0x7e, 0xb3, 0x7a, 0xa5, 0x12, 0x40, 0x32, 0xa9, 0x0c, 0xa3, 0xdc, + 0x8c, 0x90, 0xac, 0xa2, 0x7c, 0x54, 0xdb, 0x76, 0xc1, 0xe5, 0x12, 0x47, + 0xaa, 0x79, 0xce, 0xc5, 0x14, 0xae, 0x86, 0xfb, 0x9a, 0xea, 0x7a, 0x29, + 0x01, 0xb7, 0xa5, 0xab, 0x2f, 0x17, 0xd8, 0x91, 0x07, 0x69, 0x4d, 0xfb, + 0x62, 0x96, 0x8c, 0xac, 0x54, 0x1b, 0xa8, 0x5a, 0x89, 0x81, 0x86, 0x8b, + 0xcc, 0xc0, 0xc1, 0xfb, 0x4b, 0x26, 0xf8, 0xfb, 0x1a, 0xd6, 0x46, 0x4f, + 0x5f, 0x96, 0xb7, 0x03, 0x6f, 0xa7, 0x11, 0x80}; + + static const uint8_t kIn[kRsa4096SizeBytes] = {"ACC is doing RSA here"}; uint8_t out_encrypted[kRsa4096SizeBytes] = {0}; uint8_t out_decrypted[kRsa4096SizeBytes] = {0}; diff --git a/sw/device/tests/acc_smoketest.c b/sw/device/tests/acc_smoketest.c new file mode 100644 index 00000000000..95c510def66 --- /dev/null +++ b/sw/device/tests/acc_smoketest.c @@ -0,0 +1,164 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "hw/top/dt/dt_acc.h" +#include "sw/device/lib/dif/dif_acc.h" +#include "sw/device/lib/runtime/ibex.h" +#include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" +#include "sw/device/lib/testing/entropy_testutils.h" +#include "sw/device/lib/testing/test_framework/check.h" +#include "sw/device/lib/testing/test_framework/ottf_main.h" + +ACC_DECLARE_APP_SYMBOLS(barrett384); +ACC_DECLARE_SYMBOL_ADDR(barrett384, inp_a); +ACC_DECLARE_SYMBOL_ADDR(barrett384, inp_b); +ACC_DECLARE_SYMBOL_ADDR(barrett384, inp_m); +ACC_DECLARE_SYMBOL_ADDR(barrett384, inp_u); +ACC_DECLARE_SYMBOL_ADDR(barrett384, oup_c); + +static const acc_app_t kAppBarrett = ACC_APP_T_INIT(barrett384); +static const acc_addr_t kInpA = ACC_ADDR_T_INIT(barrett384, inp_a); +static const acc_addr_t kInpB = ACC_ADDR_T_INIT(barrett384, inp_b); +static const acc_addr_t kInpM = ACC_ADDR_T_INIT(barrett384, inp_m); +static const acc_addr_t kInpU = ACC_ADDR_T_INIT(barrett384, inp_u); +static const acc_addr_t kOupC = ACC_ADDR_T_INIT(barrett384, oup_c); + +ACC_DECLARE_APP_SYMBOLS(err_test); + +static const acc_app_t kAppErrTest = ACC_APP_T_INIT(err_test); + +static_assert(kDtAccCount >= 1, "This test requires at least one ACC instance"); + +static dt_acc_t kTestAcc = (dt_acc_t)0; + +OTTF_DEFINE_TEST_CONFIG(); + +/** + * Gets the ACC instruction count, checks that it matches expectations. + */ +static void check_acc_insn_cnt(dif_acc_t *acc, uint32_t expected_insn_cnt) { + uint32_t insn_cnt; + CHECK_DIF_OK(dif_acc_get_insn_cnt(acc, &insn_cnt)); + CHECK(insn_cnt == expected_insn_cnt, + "Expected to execute %d instructions, but got %d.", expected_insn_cnt, + insn_cnt); +} + +/** + * Run a 384-bit Barrett Multiplication on ACC and check its result. + * + * This test is not aiming to exhaustively test the Barrett multiplication + * itself, but test the interaction between device software and ACC. As such, + * only trivial parameters are used. + * + * The code executed on ACC can be found in sw/acc/code-snippets/barrett384.s. + * The entry point wrap_barrett384() is called according to the calling + * convention described in the ACC assembly code file. + */ +static void test_barrett384(dif_acc_t *acc) { + enum { kDataSizeBytes = 48 }; + + CHECK_STATUS_OK(acc_testutils_load_app(acc, kAppBarrett)); + + // a, first operand + static const uint8_t a[kDataSizeBytes] = {10}; + + // b, second operand + static uint8_t b[kDataSizeBytes] = {20}; + + // m, modulus, max. length 384 bit with 2^384 > m > 2^383 + // We choose the modulus of P-384: m = 2**384 - 2**128 - 2**96 + 2**32 - 1 + static const uint8_t m[kDataSizeBytes] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}; + + // u, pre-computed Barrett constant (without u[384]/MSb of u which is always 1 + // for the allowed range but has to be set to 0 here). + // u has to be pre-calculated as u = floor(2^768/m). + static const uint8_t u[kDataSizeBytes] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01}; + + // c, result, max. length 384 bit. + uint8_t c[kDataSizeBytes] = {0}; + + // c = (a * b) % m = (10 * 20) % m = 200 + static const uint8_t c_expected[kDataSizeBytes] = {200}; + + CHECK_STATUS_OK(acc_testutils_write_data(acc, sizeof(a), &a, kInpA)); + CHECK_STATUS_OK(acc_testutils_write_data(acc, sizeof(b), &b, kInpB)); + CHECK_STATUS_OK(acc_testutils_write_data(acc, sizeof(m), &m, kInpM)); + CHECK_STATUS_OK(acc_testutils_write_data(acc, sizeof(u), &u, kInpU)); + + CHECK_DIF_OK(dif_acc_set_ctrl_software_errs_fatal(acc, true)); + CHECK_STATUS_OK(acc_testutils_execute(acc)); + CHECK(dif_acc_set_ctrl_software_errs_fatal(acc, false) == kDifUnavailable); + CHECK_STATUS_OK(acc_testutils_wait_for_done(acc, kDifAccErrBitsNoError)); + + // Reading back result (c). + CHECK_STATUS_OK(acc_testutils_read_data(acc, sizeof(c), kOupC, &c)); + + for (int i = 0; i < sizeof(c); ++i) { + CHECK(c[i] == c_expected[i], + "Unexpected result c at byte %d: 0x%x (actual) != 0x%x (expected)", i, + c[i], c_expected[i]); + } + + check_acc_insn_cnt(acc, 174); +} + +/** + * Run err_test on ACC and check it produces the expected error + * + * This test tries to load from an invalid address which should result in the + * kDifAccErrBitsBadDataAddr error bit being set + * + * The code executed on ACC can be found in sw/acc/code-snippets/err_test.s. + * The entry point wrap_err_test() is called, no arguments are passed or results + * returned. + */ +static void test_err_test(dif_acc_t *acc) { + CHECK_STATUS_OK(acc_testutils_load_app(acc, kAppErrTest)); + + // TODO: Turn on software_errs_fatal for err_test. Currently the model doesn't + // support this feature so turning it on leads to a failure when run with the + // model. + CHECK_DIF_OK(dif_acc_set_ctrl_software_errs_fatal(acc, false)); + CHECK_STATUS_OK(acc_testutils_execute(acc)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(acc, kDifAccErrBitsBadDataAddr)); + + check_acc_insn_cnt(acc, 1); +} + +static void test_sec_wipe(dif_acc_t *acc) { + dif_acc_status_t acc_status; + + CHECK_DIF_OK(dif_acc_write_cmd(acc, kDifAccCmdSecWipeDmem)); + CHECK_DIF_OK(dif_acc_get_status(acc, &acc_status)); + CHECK(acc_status == kDifAccStatusBusySecWipeDmem); + CHECK_STATUS_OK(acc_testutils_wait_for_done(acc, kDifAccErrBitsNoError)); + + CHECK_DIF_OK(dif_acc_write_cmd(acc, kDifAccCmdSecWipeImem)); + CHECK_DIF_OK(dif_acc_get_status(acc, &acc_status)); + CHECK(acc_status == kDifAccStatusBusySecWipeImem); + CHECK_STATUS_OK(acc_testutils_wait_for_done(acc, kDifAccErrBitsNoError)); +} + +bool test_main(void) { + CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); + + dif_acc_t acc; + CHECK_DIF_OK(dif_acc_init_from_dt(kTestAcc, &acc)); + + test_barrett384(&acc); + test_sec_wipe(&acc); + test_err_test(&acc); + + return true; +} diff --git a/sw/device/tests/alert_handler_lpg_clkoff_test.c b/sw/device/tests/alert_handler_lpg_clkoff_test.c index a0b6b453548..d4be7c447e7 100644 --- a/sw/device/tests/alert_handler_lpg_clkoff_test.c +++ b/sw/device/tests/alert_handler_lpg_clkoff_test.c @@ -9,12 +9,12 @@ #include "sw/device/lib/base/math.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_alert_handler.h" #include "sw/device/lib/dif/dif_clkmgr.h" #include "sw/device/lib/dif/dif_hmac.h" #include "sw/device/lib/dif/dif_kmac.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_rstmgr.h" #include "sw/device/lib/dif/dif_rv_plic.h" #include "sw/device/lib/dif/dif_spi_host.h" @@ -31,12 +31,12 @@ #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" +#include "hw/top/acc_regs.h" #include "hw/top/aes_regs.h" #include "hw/top/alert_handler_regs.h" #include "hw/top/hmac_regs.h" #include "hw/top/i2c_regs.h" #include "hw/top/kmac_regs.h" -#include "hw/top/otbn_regs.h" #include "hw/top/spi_host_regs.h" #include "hw/top/usbdev_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" @@ -53,7 +53,7 @@ static dif_usbdev_t usbdev; static dif_aes_t aes; static dif_hmac_t hmac; static dif_kmac_t kmac; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_rstmgr_t rstmgr; static const uint32_t kPlicTarget = kTopEarlgreyPlicTargetIbex0; @@ -109,7 +109,7 @@ static void init_peripherals(void) { dif_kmac_init(mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR), &kmac)); CHECK_DIF_OK( - dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); CHECK_DIF_OK(dif_rstmgr_init( mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr)); @@ -122,8 +122,8 @@ static const uint32_t hmac_alerts[] = {kTopEarlgreyAlertIdHmacFatalFault}; static const uint32_t kmac_alerts[] = { kTopEarlgreyAlertIdKmacFatalFaultErr, kTopEarlgreyAlertIdKmacRecovOperationErr}; -static const uint32_t otbn_alerts[] = {kTopEarlgreyAlertIdOtbnFatal, - kTopEarlgreyAlertIdOtbnRecov}; +static const uint32_t acc_alerts[] = {kTopEarlgreyAlertIdAccFatal, + kTopEarlgreyAlertIdAccRecov}; static const uint32_t spihost0_alerts[] = { kTopEarlgreyAlertIdSpiHost0FatalFault}; static const uint32_t spihost1_alerts[] = { @@ -133,14 +133,14 @@ static const uint32_t usbdev_alerts[] = {kTopEarlgreyAlertIdUsbdevFatalFault}; static const uint32_t num_aes_alerts = ARRAYSIZE(aes_alerts); static const uint32_t num_hmac_alerts = ARRAYSIZE(hmac_alerts); static const uint32_t num_kmac_alerts = ARRAYSIZE(kmac_alerts); -static const uint32_t num_otbn_alerts = ARRAYSIZE(otbn_alerts); +static const uint32_t num_acc_alerts = ARRAYSIZE(acc_alerts); static const uint32_t num_spihost0_alerts = ARRAYSIZE(spihost0_alerts); static const uint32_t num_spihost1_alerts = ARRAYSIZE(spihost1_alerts); static const uint32_t num_usbdev_alerts = ARRAYSIZE(usbdev_alerts); static const size_t num_alerts = ARRAYSIZE(aes_alerts) + ARRAYSIZE(hmac_alerts) + ARRAYSIZE(kmac_alerts) + - ARRAYSIZE(otbn_alerts) + ARRAYSIZE(spihost0_alerts) + + ARRAYSIZE(acc_alerts) + ARRAYSIZE(spihost0_alerts) + ARRAYSIZE(spihost1_alerts) + ARRAYSIZE(usbdev_alerts); /** @@ -222,14 +222,14 @@ static const test_t kPeripherals[] = { .is_hintable = true, }, { - .name = "OTBN", - .base = TOP_EARLGREY_OTBN_BASE_ADDR, - .offset = OTBN_ALERT_TEST_REG_OFFSET, - .dif = &otbn, - .fatal_alert_bit = kDifOtbnAlertFatal, - .alert_ids = otbn_alerts, - .num_alert_peri = num_otbn_alerts, - .clk_index = kTopEarlgreyHintableClocksMainOtbn, + .name = "ACC", + .base = TOP_EARLGREY_ACC_BASE_ADDR, + .offset = ACC_ALERT_TEST_REG_OFFSET, + .dif = &acc, + .fatal_alert_bit = kDifAccAlertFatal, + .alert_ids = acc_alerts, + .num_alert_peri = num_acc_alerts, + .clk_index = kTopEarlgreyHintableClocksMainAcc, .is_hintable = true, }, // Gateable clock IPs diff --git a/sw/device/tests/clkmgr_off_otbn_trans_test.c b/sw/device/tests/clkmgr_off_acc_trans_test.c similarity index 59% rename from sw/device/tests/clkmgr_off_otbn_trans_test.c rename to sw/device/tests/clkmgr_off_acc_trans_test.c index 99b61de4d07..ac69d554092 100644 --- a/sw/device/tests/clkmgr_off_otbn_trans_test.c +++ b/sw/device/tests/clkmgr_off_acc_trans_test.c @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This tests that disabling the OTBN clock causes CSR accesses to it to fail. +// This tests that disabling the ACC clock causes CSR accesses to it to fail. #include "sw/device/tests/clkmgr_off_trans_impl.h" -bool test_main(void) { return execute_off_trans_test(kTestTransOtbn); } +bool test_main(void) { return execute_off_trans_test(kTestTransAcc); } diff --git a/sw/device/tests/clkmgr_off_trans_impl.c b/sw/device/tests/clkmgr_off_trans_impl.c index 6e224e2f1a7..caf05f0d8c1 100644 --- a/sw/device/tests/clkmgr_off_trans_impl.c +++ b/sw/device/tests/clkmgr_off_trans_impl.c @@ -5,13 +5,13 @@ #include "sw/device/tests/clkmgr_off_trans_impl.h" #include "sw/device/lib/base/memory.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_aon_timer.h" #include "sw/device/lib/dif/dif_base.h" #include "sw/device/lib/dif/dif_clkmgr.h" #include "sw/device/lib/dif/dif_hmac.h" #include "sw/device/lib/dif/dif_kmac.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_pwrmgr.h" #include "sw/device/lib/dif/dif_rstmgr.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" @@ -21,10 +21,10 @@ #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" +#include "hw/top/acc_regs.h" #include "hw/top/aes_regs.h" #include "hw/top/hmac_regs.h" #include "hw/top/kmac_regs.h" -#include "hw/top/otbn_regs.h" static_assert(kDtAesCount >= 1, "This test requires at least one AES instance"); static_assert(kDtAonTimerCount >= 1, @@ -35,8 +35,7 @@ static_assert(kDtHmacCount >= 1, "This test requires at least one HMAC instance"); static_assert(kDtKmacCount >= 1, "This test requires at least one KMAC instance"); -static_assert(kDtOtbnCount >= 1, - "This test requires at least one OTBN instance"); +static_assert(kDtAccCount >= 1, "This test requires at least one ACC instance"); static_assert(kDtPwrmgrCount == 1, "this test expects exactly one pwrmgr"); static_assert(kDtRstmgrCount >= 1, "This test requires at least one Rstmgr instance"); @@ -46,7 +45,7 @@ static const dt_aon_timer_t kAonTimerDt = (dt_aon_timer_t)0; static const dt_clkmgr_t kClkmgrDt = (dt_clkmgr_t)0; static const dt_hmac_t kTestHmac = (dt_hmac_t)0; static const dt_kmac_t kTestKmac = (dt_kmac_t)0; -static const dt_otbn_t kTestOtbn = (dt_otbn_t)0; +static const dt_acc_t kTestAcc = (dt_acc_t)0; static const dt_pwrmgr_t kPwrmgrDt = (dt_pwrmgr_t)0; static const dt_rstmgr_t kRstmgrDt = (dt_rstmgr_t)0; @@ -62,7 +61,7 @@ static dif_aon_timer_t aon_timer; static dif_aes_t aes; static dif_hmac_t hmac; static dif_kmac_t kmac; -static dif_otbn_t otbn; +static dif_acc_t acc; typedef struct clock_error_info { /** @@ -127,9 +126,9 @@ OT_NOINLINE static void kmac_csr_access(void) { CHECK_DIF_OK(dif_kmac_get_status(&kmac, &status)); } -OT_NOINLINE static void otbn_csr_access(void) { - dif_otbn_err_bits_t err_bits; - CHECK_DIF_OK(dif_otbn_get_err_bits(&otbn, &err_bits)); +OT_NOINLINE static void acc_csr_access(void) { + dif_acc_err_bits_t err_bits; + CHECK_DIF_OK(dif_acc_get_err_bits(&acc, &err_bits)); } /** @@ -228,14 +227,14 @@ bool execute_off_trans_test(test_trans_block_t block) { info[trans].crash_function = kmac_csr_access; break; - case kTestTransOtbn: - // Initialize otbn. - CHECK_DIF_OK(dif_otbn_init_from_dt(kTestOtbn, &otbn)); - inst = dt_otbn_instance_id(kTestOtbn); - info[trans].name = "otbn"; + case kTestTransAcc: + // Initialize acc. + CHECK_DIF_OK(dif_acc_init_from_dt(kTestAcc, &acc)); + inst = dt_acc_instance_id(kTestAcc); + info[trans].name = "acc"; info[trans].csr_offset = - addr_as_offset(otbn.base_addr, OTBN_ERR_BITS_REG_OFFSET); - info[trans].crash_function = otbn_csr_access; + addr_as_offset(acc.base_addr, ACC_ERR_BITS_REG_OFFSET); + info[trans].crash_function = acc_csr_access; break; default: diff --git a/sw/device/tests/clkmgr_off_trans_impl.h b/sw/device/tests/clkmgr_off_trans_impl.h index 9b06c643254..806bf9edc24 100644 --- a/sw/device/tests/clkmgr_off_trans_impl.h +++ b/sw/device/tests/clkmgr_off_trans_impl.h @@ -19,10 +19,10 @@ typedef enum test_trans_block { kTestTransFirst = 0u, // List of types of IP block with hintable clocks. - kTestTransAes = kTestTransFirst, + kTestTransAcc = kTestTransFirst, + kTestTransAes, kTestTransHmac, kTestTransKmac, - kTestTransOtbn, // Number of types of IP block. kTestTransCount } test_trans_block_t; diff --git a/sw/device/tests/crypto/BUILD b/sw/device/tests/crypto/BUILD index 8ae62792e48..a50ad7d74d2 100644 --- a/sw/device/tests/crypto/BUILD +++ b/sw/device/tests/crypto/BUILD @@ -286,7 +286,7 @@ opentitan_test( timeout = "eternal", ), deps = [ - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/impl:ecc_p256", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", @@ -305,7 +305,7 @@ opentitan_test( tags = ["manual"], ), deps = [ - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/impl:ecc_p384", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", @@ -330,8 +330,8 @@ opentitan_test( tags = ["manual"], ), deps = [ + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/impl:ecc_p256", "//sw/device/lib/crypto/impl:key_transport", "//sw/device/lib/runtime:log", @@ -358,8 +358,8 @@ opentitan_test( tags = ["manual"], ), deps = [ + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/impl:ecc_p384", "//sw/device/lib/crypto/impl:key_transport", "//sw/device/lib/runtime:log", @@ -386,7 +386,7 @@ opentitan_test( timeout = "long", ), deps = [ - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/impl:ecc_p256", "//sw/device/lib/crypto/impl:keyblob", "//sw/device/lib/crypto/impl:sha2", @@ -417,7 +417,7 @@ opentitan_test( tags = ["manual"], ), deps = [ - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/impl:ecc_p384", "//sw/device/lib/crypto/impl:keyblob", "//sw/device/lib/crypto/impl:sha2", @@ -445,9 +445,9 @@ opentitan_test( tags = ["manual"], ), deps = [ + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:entropy", "//sw/device/lib/crypto/drivers:keymgr", - "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/impl:ecc_p256", "//sw/device/lib/crypto/impl:key_transport", "//sw/device/lib/crypto/impl:sha2", @@ -474,9 +474,9 @@ opentitan_test( tags = ["manual"], ), deps = [ + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:entropy", "//sw/device/lib/crypto/drivers:keymgr", - "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/impl:ecc_p384", "//sw/device/lib/crypto/impl:key_transport", "//sw/device/lib/crypto/impl:keyblob", @@ -502,8 +502,8 @@ opentitan_test( timeout = "long", ), deps = [ + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:entropy", - "//sw/device/lib/crypto/drivers:otbn", "//sw/device/lib/crypto/impl:ed25519", "//sw/device/lib/crypto/impl:integrity", "//sw/device/lib/crypto/impl:sha2", @@ -701,7 +701,7 @@ opentitan_test( ), deps = [ ":ecdsa_p256_verify_testvectors_hardcoded_header", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/impl:sha2", "//sw/device/lib/crypto/impl/ecc:p256", "//sw/device/lib/runtime:log", diff --git a/sw/device/tests/crypto/ecdh_p256_functest.c b/sw/device/tests/crypto/ecdh_p256_functest.c index 140b12a8c9b..e15d8a3c1c4 100644 --- a/sw/device/tests/crypto/ecdh_p256_functest.c +++ b/sw/device/tests/crypto/ecdh_p256_functest.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/keyblob.h" #include "sw/device/lib/crypto/include/ecc_p256.h" #include "sw/device/lib/runtime/log.h" @@ -142,9 +142,9 @@ bool test_main(void) { status_t err = key_exchange_test(); if (!status_ok(err)) { - // If there was an error, print the OTBN error bits and instruction count. - LOG_INFO("OTBN error bits: 0x%08x", otbn_err_bits_get()); - LOG_INFO("OTBN instruction count: 0x%08x", otbn_instruction_count_get()); + // If there was an error, print the ACC error bits and instruction count. + LOG_INFO("ACC error bits: 0x%08x", acc_err_bits_get()); + LOG_INFO("ACC instruction count: 0x%08x", acc_instruction_count_get()); // Print the error. CHECK_STATUS_OK(err); return false; diff --git a/sw/device/tests/crypto/ecdh_p256_sideload_functest.c b/sw/device/tests/crypto/ecdh_p256_sideload_functest.c index ff5e3541281..9211eb269e0 100644 --- a/sw/device/tests/crypto/ecdh_p256_sideload_functest.c +++ b/sw/device/tests/crypto/ecdh_p256_sideload_functest.c @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/keyblob.h" #include "sw/device/lib/crypto/include/ecc_p256.h" diff --git a/sw/device/tests/crypto/ecdh_p384_functest.c b/sw/device/tests/crypto/ecdh_p384_functest.c index 4c3d1d19300..c1e0d751e0a 100644 --- a/sw/device/tests/crypto/ecdh_p384_functest.c +++ b/sw/device/tests/crypto/ecdh_p384_functest.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/keyblob.h" #include "sw/device/lib/crypto/include/ecc_p384.h" #include "sw/device/lib/runtime/log.h" @@ -144,9 +144,9 @@ bool test_main(void) { status_t err = key_exchange_test(); if (!status_ok(err)) { - // If there was an error, print the OTBN error bits and instruction count. - LOG_INFO("OTBN error bits: 0x%08x", otbn_err_bits_get()); - LOG_INFO("OTBN instruction count: 0x%08x", otbn_instruction_count_get()); + // If there was an error, print the ACC error bits and instruction count. + LOG_INFO("ACC error bits: 0x%08x", acc_err_bits_get()); + LOG_INFO("ACC instruction count: 0x%08x", acc_instruction_count_get()); // Print the error. CHECK_STATUS_OK(err); return false; diff --git a/sw/device/tests/crypto/ecdh_p384_sideload_functest.c b/sw/device/tests/crypto/ecdh_p384_sideload_functest.c index 150a02fe002..781bf44386a 100644 --- a/sw/device/tests/crypto/ecdh_p384_sideload_functest.c +++ b/sw/device/tests/crypto/ecdh_p384_sideload_functest.c @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/keyblob.h" #include "sw/device/lib/crypto/include/ecc_p384.h" diff --git a/sw/device/tests/crypto/ecdsa_p256_functest.c b/sw/device/tests/crypto/ecdsa_p256_functest.c index 2770a32dce9..ed3a71ad36f 100644 --- a/sw/device/tests/crypto/ecdsa_p256_functest.c +++ b/sw/device/tests/crypto/ecdsa_p256_functest.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/keyblob.h" #include "sw/device/lib/crypto/include/datatypes.h" @@ -95,9 +95,9 @@ bool test_main(void) { hardened_bool_t verificationResult; status_t err = sign_then_verify_test(&verificationResult); if (!status_ok(err)) { - // If there was an error, print the OTBN error bits and instruction count. - LOG_INFO("OTBN error bits: 0x%08x", otbn_err_bits_get()); - LOG_INFO("OTBN instruction count: 0x%08x", otbn_instruction_count_get()); + // If there was an error, print the ACC error bits and instruction count. + LOG_INFO("ACC error bits: 0x%08x", acc_err_bits_get()); + LOG_INFO("ACC instruction count: 0x%08x", acc_instruction_count_get()); // Print the error. CHECK_STATUS_OK(err); return false; diff --git a/sw/device/tests/crypto/ecdsa_p256_verify_functest.c b/sw/device/tests/crypto/ecdsa_p256_verify_functest.c index 8642fa4b62b..a1779a8f104 100644 --- a/sw/device/tests/crypto/ecdsa_p256_verify_functest.c +++ b/sw/device/tests/crypto/ecdsa_p256_verify_functest.c @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/ecc/p256.h" #include "sw/device/lib/crypto/include/sha2.h" #include "sw/device/lib/runtime/log.h" @@ -34,7 +34,7 @@ status_t ecdsa_p256_verify_test( TRY(p256_ecdsa_verify_start(&testvec->signature, digest.data, &testvec->public_key)); hardened_bool_t result; - TRY(otbn_busy_wait_for_done()); + TRY(acc_busy_wait_for_done()); TRY(p256_ecdsa_verify_finalize(&testvec->signature, &result)); if (testvec->valid && result != kHardenedBoolTrue) { @@ -69,10 +69,10 @@ bool test_main(void) { } else { LOG_ERROR("Finished ecdsa_p256_verify_test on test vector %d : error %r", i + 1, err); - // For help with debugging, print the OTBN error bits, instruction + // For help with debugging, print the ACC error bits, instruction // count, and test vector notes. - LOG_INFO("OTBN error bits: 0x%08x", otbn_err_bits_get()); - LOG_INFO("OTBN instruction count: 0x%08x", otbn_instruction_count_get()); + LOG_INFO("ACC error bits: 0x%08x", acc_err_bits_get()); + LOG_INFO("ACC instruction count: 0x%08x", acc_instruction_count_get()); LOG_INFO("Test notes: %s", testvec.comment); result = false; } diff --git a/sw/device/tests/crypto/ecdsa_p384_functest.c b/sw/device/tests/crypto/ecdsa_p384_functest.c index 0ddd14b5f98..7cea13637d2 100644 --- a/sw/device/tests/crypto/ecdsa_p384_functest.c +++ b/sw/device/tests/crypto/ecdsa_p384_functest.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/keyblob.h" #include "sw/device/lib/crypto/include/datatypes.h" @@ -95,9 +95,9 @@ bool test_main(void) { hardened_bool_t verificationResult; status_t err = sign_then_verify_test(&verificationResult); if (!status_ok(err)) { - // If there was an error, print the OTBN error bits and instruction count. - LOG_INFO("OTBN error bits: 0x%08x", otbn_err_bits_get()); - LOG_INFO("OTBN instruction count: 0x%08x", otbn_instruction_count_get()); + // If there was an error, print the ACC error bits and instruction count. + LOG_INFO("ACC error bits: 0x%08x", acc_err_bits_get()); + LOG_INFO("ACC instruction count: 0x%08x", acc_instruction_count_get()); // Print the error. CHECK_STATUS_OK(err); return false; diff --git a/sw/device/tests/crypto/ed25519_functest.c b/sw/device/tests/crypto/ed25519_functest.c index be705a95db9..10aba0a5d9a 100644 --- a/sw/device/tests/crypto/ed25519_functest.c +++ b/sw/device/tests/crypto/ed25519_functest.c @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/entropy.h" -#include "sw/device/lib/crypto/drivers/otbn.h" #include "sw/device/lib/crypto/impl/integrity.h" #include "sw/device/lib/crypto/impl/status.h" #include "sw/device/lib/crypto/include/datatypes.h" @@ -121,9 +121,9 @@ bool test_main(void) { hardened_bool_t verificationResult; status_t err = sign_then_verify_test(&verificationResult); if (!status_ok(err)) { - // If there was an error, print the OTBN error bits and instruction count. - LOG_INFO("OTBN error bits: 0x%08x", otbn_err_bits_get()); - LOG_INFO("OTBN instruction count: 0x%08x", otbn_instruction_count_get()); + // If there was an error, print the ACC error bits and instruction count. + LOG_INFO("ACC error bits: 0x%08x", acc_err_bits_get()); + LOG_INFO("ACC instruction count: 0x%08x", acc_instruction_count_get()); // Print the error. CHECK_STATUS_OK(err); return false; diff --git a/sw/device/tests/crypto/rsa_2048_keygen_functest.c b/sw/device/tests/crypto/rsa_2048_keygen_functest.c index f51ccc85e00..019ce62d892 100644 --- a/sw/device/tests/crypto/rsa_2048_keygen_functest.c +++ b/sw/device/tests/crypto/rsa_2048_keygen_functest.c @@ -4,7 +4,7 @@ // SPDX-License-Identifier: Apache-2.0 #include "sw/device/lib/base/memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/rsa/rsa_datatypes.h" #include "sw/device/lib/crypto/include/datatypes.h" #include "sw/device/lib/crypto/include/rsa.h" @@ -57,7 +57,7 @@ status_t keygen_then_sign_test(void) { LOG_INFO("Starting keypair generation..."); TRY(otcrypto_rsa_keygen(kOtcryptoRsaSize2048, &public_key, &private_key)); LOG_INFO("Keypair generation complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Interpret public key using internal RSA datatype. TRY_CHECK(public_key.key_length == sizeof(rsa_2048_public_key_t)); @@ -94,7 +94,7 @@ status_t keygen_then_sign_test(void) { TRY(otcrypto_rsa_sign(&private_key, msg_digest, kOtcryptoRsaPaddingPkcs, sig_buf)); LOG_INFO("Signature generation complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Try to verify the signature. If something is wrong with the key (nonprime p // and q, incorrect CRT components of d, etc.), then this is likely to fail. @@ -103,7 +103,7 @@ status_t keygen_then_sign_test(void) { TRY(otcrypto_rsa_verify(&public_key, msg_digest, kOtcryptoRsaPaddingPkcs, const_sig_buf, &verification_result)); LOG_INFO("Signature verification complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Expect the signature to pass verification. TRY_CHECK(verification_result == kHardenedBoolTrue); diff --git a/sw/device/tests/crypto/rsa_3072_keygen_functest.c b/sw/device/tests/crypto/rsa_3072_keygen_functest.c index 2584bf7e3e8..9906232176d 100644 --- a/sw/device/tests/crypto/rsa_3072_keygen_functest.c +++ b/sw/device/tests/crypto/rsa_3072_keygen_functest.c @@ -4,7 +4,7 @@ // SPDX-License-Identifier: Apache-2.0 #include "sw/device/lib/base/memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/rsa/rsa_datatypes.h" #include "sw/device/lib/crypto/include/datatypes.h" #include "sw/device/lib/crypto/include/rsa.h" @@ -57,7 +57,7 @@ status_t keygen_then_sign_test(void) { LOG_INFO("Starting keypair generation..."); TRY(otcrypto_rsa_keygen(kOtcryptoRsaSize3072, &public_key, &private_key)); LOG_INFO("Keypair generation complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Interpret public key using internal RSA datatype. TRY_CHECK(public_key.key_length == sizeof(rsa_3072_public_key_t)); @@ -96,7 +96,7 @@ status_t keygen_then_sign_test(void) { TRY(otcrypto_rsa_sign(&private_key, msg_digest, kOtcryptoRsaPaddingPkcs, sig_buf)); LOG_INFO("Signature generation complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Try to verify the signature. If something is wrong with the key (nonprime p // and q, incorrect CRT components of d, etc.), then this is likely to fail. @@ -105,7 +105,7 @@ status_t keygen_then_sign_test(void) { TRY(otcrypto_rsa_verify(&public_key, msg_digest, kOtcryptoRsaPaddingPkcs, const_sig_buf, &verification_result)); LOG_INFO("Signature verification complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Expect the signature to pass verification. TRY_CHECK(verification_result == kHardenedBoolTrue); diff --git a/sw/device/tests/crypto/rsa_4096_keygen_functest.c b/sw/device/tests/crypto/rsa_4096_keygen_functest.c index 85312be9b00..cf3fd372096 100644 --- a/sw/device/tests/crypto/rsa_4096_keygen_functest.c +++ b/sw/device/tests/crypto/rsa_4096_keygen_functest.c @@ -4,7 +4,7 @@ // SPDX-License-Identifier: Apache-2.0 #include "sw/device/lib/base/memory.h" -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/impl/rsa/rsa_datatypes.h" #include "sw/device/lib/crypto/include/datatypes.h" #include "sw/device/lib/crypto/include/rsa.h" @@ -57,7 +57,7 @@ status_t keygen_then_sign_test(void) { LOG_INFO("Starting keypair generation..."); TRY(otcrypto_rsa_keygen(kOtcryptoRsaSize4096, &public_key, &private_key)); LOG_INFO("Keypair generation complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Interpret public key using internal RSA datatype. TRY_CHECK(public_key.key_length == sizeof(rsa_4096_public_key_t)); @@ -96,7 +96,7 @@ status_t keygen_then_sign_test(void) { TRY(otcrypto_rsa_sign(&private_key, msg_digest, kOtcryptoRsaPaddingPkcs, sig_buf)); LOG_INFO("Signature generation complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Try to verify the signature. If something is wrong with the key (nonprime p // and q, incorrect CRT components of d, etc.), then this is likely to fail. @@ -105,7 +105,7 @@ status_t keygen_then_sign_test(void) { TRY(otcrypto_rsa_verify(&public_key, msg_digest, kOtcryptoRsaPaddingPkcs, const_sig_buf, &verification_result)); LOG_INFO("Signature verification complete."); - LOG_INFO("OTBN instruction count: %u", otbn_instruction_count_get()); + LOG_INFO("ACC instruction count: %u", acc_instruction_count_get()); // Expect the signature to pass verification. TRY_CHECK(verification_result == kHardenedBoolTrue); diff --git a/sw/device/tests/crypto/testvectors/sphincsplus_kat/parse_kat.py b/sw/device/tests/crypto/testvectors/sphincsplus_kat/parse_kat.py index d691f77479c..b475f933a57 100755 --- a/sw/device/tests/crypto/testvectors/sphincsplus_kat/parse_kat.py +++ b/sw/device/tests/crypto/testvectors/sphincsplus_kat/parse_kat.py @@ -88,7 +88,7 @@ def write_split(testvecs, filename, max_tests_per_file): def main() -> int: parser = argparse.ArgumentParser( description='Analyze whether secret data affects the control flow of ' - 'an OTBN program or subroutine.') + 'an ACC program or subroutine.') parser.add_argument('src', metavar='FILE', type=argparse.FileType('r'), diff --git a/sw/device/tests/csrng_edn_concurrency_test.c b/sw/device/tests/csrng_edn_concurrency_test.c index 26dd3fad646..7d11b75b67d 100644 --- a/sw/device/tests/csrng_edn_concurrency_test.c +++ b/sw/device/tests/csrng_edn_concurrency_test.c @@ -2,11 +2,11 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_aes.h" #include "hw/top/dt/dt_csrng.h" #include "hw/top/dt/dt_edn.h" #include "hw/top/dt/dt_entropy_src.h" -#include "hw/top/dt/dt_otbn.h" #include "hw/top/dt/dt_rv_core_ibex.h" #include "hw/top/dt/dt_rv_plic.h" #include "sw/device/lib/base/macros.h" @@ -19,21 +19,21 @@ #include "sw/device/lib/dif/dif_rv_plic.h" #include "sw/device/lib/runtime/irq.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/csrng_testutils.h" #include "sw/device/lib/testing/edn_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/rand_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_macros.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; static dif_entropy_src_t entropy_src; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_rv_plic_t plic; static dif_rv_core_ibex_t rv_core_ibex; static dif_aes_t aes; @@ -54,7 +54,7 @@ enum { /** * The number of test iterations per entropy consumer. */ - kTestParamNumOtbnIterationsMax = 4, + kTestParamNumAccIterationsMax = 4, kTestParamNumIbexIterationsMax = 16, kTestParamNumAesIterationsMax = 32, kTestParamNumCsrngIterationsMax = 8, @@ -109,9 +109,9 @@ typedef enum task_id { */ kTestTaskIdMain, /** - * Assigned to `otbn_task()`. + * Assigned to `acc_task()`. */ - kTestTaskIdOtbn, + kTestTaskIdAcc, /** * Assigned to `ibex_task()`. */ @@ -150,7 +150,7 @@ static void init_peripherals(void) { CHECK_DIF_OK(dif_entropy_src_init_from_dt(kDtEntropySrc, &entropy_src)); CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic)); CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex)); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); CHECK_DIF_OK(dif_aes_init_from_dt(kDtAes, &aes)); } @@ -168,33 +168,33 @@ static void task_done_set_and_yield(task_id_t task_id) { } /** - * OTBN task. + * ACC task. * - * Executes OTBN randomness test, the test state is set to `kTestStateRun`. + * Executes ACC randomness test, the test state is set to `kTestStateRun`. * * @param task_parameters Unused. Set to NULL by ottf. */ -static void otbn_task(void *task_parameters) { +static void acc_task(void *task_parameters) { while (true) { if (execution_state == kTestStateTearDown) { break; } - if (execution_state == kTestStateSetup || task_done[kTestTaskIdOtbn]) { + if (execution_state == kTestStateSetup || task_done[kTestTaskIdAcc]) { ottf_task_yield(); continue; } - LOG_INFO("OTBN:START"); - for (size_t i = 0; i < task_iter_count_max[kTestTaskIdOtbn]; ++i) { - otbn_randomness_test_start(&otbn, /*iters=*/0); - dif_otbn_status_t status; + LOG_INFO("ACC:START"); + for (size_t i = 0; i < task_iter_count_max[kTestTaskIdAcc]; ++i) { + acc_randomness_test_start(&acc, /*iters=*/0); + dif_acc_status_t status; do { - CHECK_DIF_OK(dif_otbn_get_status(&otbn, &status)); + CHECK_DIF_OK(dif_acc_get_status(&acc, &status)); ottf_task_yield(); - } while (status != kDifOtbnStatusIdle && status != kDifOtbnStatusLocked); - CHECK(otbn_randomness_test_end(&otbn, /*skip_otbn_done_check=*/false)); + } while (status != kDifAccStatusIdle && status != kDifAccStatusLocked); + CHECK(acc_randomness_test_end(&acc, /*skip_acc_done_check=*/false)); } - LOG_INFO("OTBN:DONE"); - task_done_set_and_yield(kTestTaskIdOtbn); + LOG_INFO("ACC:DONE"); + task_done_set_and_yield(kTestTaskIdAcc); } OTTF_TASK_DELETE_SELF_OR_DIE; } @@ -373,8 +373,8 @@ static void entropy_config(void) { /*glen_val=*/0, &sw_res_seed); sw_num_reqs_between_reseeds = rand_testutils_gen32_range(1, 10); - task_iter_count_max[kTestTaskIdOtbn] = - rand_testutils_gen32_range(/*min=*/1, kTestParamNumOtbnIterationsMax); + task_iter_count_max[kTestTaskIdAcc] = + rand_testutils_gen32_range(/*min=*/1, kTestParamNumAccIterationsMax); task_iter_count_max[kTestTaskIdIbex] = rand_testutils_gen32_range(/*min=*/1, kTestParamNumIbexIterationsMax); task_iter_count_max[kTestTaskIdAes] = @@ -486,7 +486,7 @@ bool test_main(void) { execution_state_update(kTestStateSetup); CHECK(ottf_task_create(main_task, "main", kOttfFreeRtosMinStackSize, 1)); - CHECK(ottf_task_create(otbn_task, "otbn", kOttfFreeRtosMinStackSize, 1)); + CHECK(ottf_task_create(acc_task, "acc", kOttfFreeRtosMinStackSize, 1)); CHECK(ottf_task_create(ibex_task, "ibex", kOttfFreeRtosMinStackSize, 1)); CHECK(ottf_task_create(aes_task, "aes", kOttfFreeRtosMinStackSize, 1)); CHECK(ottf_task_create(csrng_task, "csrng", kOttfFreeRtosMinStackSize, 1)); diff --git a/sw/device/tests/edn_auto_mode.c b/sw/device/tests/edn_auto_mode.c index c7f8f471086..bd856905a82 100644 --- a/sw/device/tests/edn_auto_mode.c +++ b/sw/device/tests/edn_auto_mode.c @@ -3,34 +3,34 @@ // SPDX-License-Identifier: Apache-2.0 #include "hw/ip/aes/model/aes_modes.h" +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_aes.h" #include "hw/top/dt/dt_csrng.h" #include "hw/top/dt/dt_edn.h" -#include "hw/top/dt/dt_otbn.h" #include "hw/top/dt/dt_rv_core_ibex.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_edn.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/aes_testutils.h" #include "sw/device/lib/testing/edn_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/rand_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #include "hw/top/edn_regs.h" // Generated enum { kTimeout = (10 * 1000 * 1000), - kOtbnRounds = 2, - kOtbnRandomnessIterations = 1, + kAccRounds = 2, + kAccRandomnessIterations = 1, kTestProcedureRepetitions = 2, }; @@ -38,7 +38,7 @@ static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; static dif_aes_t aes; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_rv_core_ibex_t rv_core_ibex; // AES ECB encryption transaction. @@ -61,12 +61,12 @@ static void init_peripherals(void) { CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0)); CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1)); CHECK_DIF_OK(dif_aes_init_from_dt(kDtAes, &aes)); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex)); } -static void configure_otbn(void) { - otbn_randomness_test_prepare(&otbn, kOtbnRandomnessIterations); +static void configure_acc(void) { + acc_randomness_test_prepare(&acc, kAccRandomnessIterations); } // configure the entropy complex @@ -88,27 +88,27 @@ static void entropy_config(void) { } static status_t stress_test_edns(void) { - int otbn_execute_rounds = kOtbnRounds; + int acc_execute_rounds = kAccRounds; dif_rv_core_ibex_rnd_status_t ibex_rnd_status; - dif_otbn_status_t otbn_status; + dif_acc_status_t acc_status; uint32_t ibex_rnd_data; dif_aes_data_t out_data; // Start AES at least once. - LOG_INFO("aes_testutils_setup_encryption round %d", otbn_execute_rounds); + LOG_INFO("aes_testutils_setup_encryption round %d", acc_execute_rounds); CHECK_STATUS_OK(aes_testutils_setup_encryption(transaction, &aes)); - while (otbn_execute_rounds) { - LOG_INFO("dif_otbn_get_status round %d", otbn_execute_rounds); - CHECK_DIF_OK(dif_otbn_get_status(&otbn, &otbn_status)); - if (otbn_status == kDifOtbnStatusIdle) { - LOG_INFO("otbn_testutils_execute round %d", otbn_execute_rounds); - CHECK_STATUS_OK(otbn_testutils_execute(&otbn)); - otbn_execute_rounds--; + while (acc_execute_rounds) { + LOG_INFO("dif_acc_get_status round %d", acc_execute_rounds); + CHECK_DIF_OK(dif_acc_get_status(&acc, &acc_status)); + if (acc_status == kDifAccStatusIdle) { + LOG_INFO("acc_testutils_execute round %d", acc_execute_rounds); + CHECK_STATUS_OK(acc_testutils_execute(&acc)); + acc_execute_rounds--; } if (aes_testutils_get_status(&aes, kDifAesStatusOutputValid)) { - LOG_INFO("dif_aes_read_output round %d", otbn_execute_rounds); + LOG_INFO("dif_aes_read_output round %d", acc_execute_rounds); // Read out the produced cipher text. CHECK_DIF_OK(dif_aes_read_output(&aes, &out_data)); - LOG_INFO("aes_testutils_setup_encryption round %d", otbn_execute_rounds); + LOG_INFO("aes_testutils_setup_encryption round %d", acc_execute_rounds); // Start a new AES encryption. CHECK_STATUS_OK(aes_testutils_setup_encryption(transaction, &aes)); } @@ -121,7 +121,7 @@ static status_t stress_test_edns(void) { } // Verify that all entropy consuming endpoints can finish their operations // and do not hang. - CHECK_STATUS_OK(otbn_testutils_wait_for_done(&otbn, kDifOtbnErrBitsNoError)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(&acc, kDifAccErrBitsNoError)); AES_TESTUTILS_WAIT_FOR_STATUS(&aes, kDifAesStatusOutputValid, true, kTimeout); IBEX_TRY_SPIN_FOR(rv_core_ibex_testutils_is_rnd_data_valid(&rv_core_ibex), kTimeout); @@ -133,14 +133,14 @@ bool test_main(void) { int repetitions = kTestProcedureRepetitions; LOG_INFO("init_peripherals start"); init_peripherals(); - // Prepare the OTBN for execution. - configure_otbn(); + // Prepare the ACC for execution. + configure_acc(); // Start the procedure multiple times, with different EDN configurations. while (repetitions) { // Disable and restart the entropy complex. LOG_INFO("entropy_config start"); entropy_config(); - // Trigger the execution of the OTBN, AES and IBEX, consuming entropy + // Trigger the execution of the ACC, AES and IBEX, consuming entropy // to stress test the EDNs. LOG_INFO("stress_test_edns start"); stress_test_edns(); diff --git a/sw/device/tests/edn_boot_mode.c b/sw/device/tests/edn_boot_mode.c index 135afd41bf5..936bf422091 100644 --- a/sw/device/tests/edn_boot_mode.c +++ b/sw/device/tests/edn_boot_mode.c @@ -2,39 +2,39 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_csrng.h" #include "hw/top/dt/dt_edn.h" #include "hw/top/dt/dt_entropy_src.h" -#include "hw/top/dt/dt_otbn.h" #include "hw/top/dt/dt_rv_core_ibex.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_edn.h" #include "sw/device/lib/dif/dif_entropy_src.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/edn_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/rv_core_ibex_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #include "hw/top/edn_regs.h" // Generated enum { kEdnBootModeTimeout = (10 * 1000 * 1000), - kEdnBootModeOtbnRandomnessIterations = 1, + kEdnBootModeAccRandomnessIterations = 1, }; static dif_entropy_src_t entropy_src; static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_rv_core_ibex_t rv_core_ibex; dif_entropy_src_config_t entropy_src_config = { @@ -56,12 +56,12 @@ static void init_peripherals(void) { CHECK_DIF_OK(dif_csrng_init_from_dt(kDtCsrng, &csrng)); CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0)); CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1)); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex)); } -static void configure_otbn(void) { - otbn_randomness_test_prepare(&otbn, kEdnBootModeOtbnRandomnessIterations); +static void configure_acc(void) { + acc_randomness_test_prepare(&acc, kEdnBootModeAccRandomnessIterations); } // configure the entropy complex @@ -81,7 +81,7 @@ static status_t entropy_config(unsigned int round) { CHECK_DIF_OK(dif_csrng_configure(&csrng)); if (round == 1) { - // Enable EDN1 (the one connected to OTBN RND) in boot-time request mode. + // Enable EDN1 (the one connected to ACC RND) in boot-time request mode. CHECK_DIF_OK(dif_edn_set_boot_mode(&edn1)); CHECK_DIF_OK(dif_edn_configure(&edn1)); EDN_TESTUTILS_WAIT_FOR_STATUS(&edn1, kDifEdnSmStateBootGenAckWait, true, @@ -98,7 +98,7 @@ static status_t entropy_config(unsigned int round) { } if (round == 2) { - // Enable EDN1 (the one connected to OTBN RND) in auto request mode. + // Enable EDN1 (the one connected to ACC RND) in auto request mode. CHECK_DIF_OK(dif_edn_set_auto_mode(&edn1, edn_params1)); EDN_TESTUTILS_WAIT_FOR_STATUS(&edn1, kDifEdnSmStateAutoAckWait, true, kEdnBootModeTimeout); @@ -128,22 +128,21 @@ static status_t entropy_config(unsigned int round) { return OK_STATUS(); } -static void consume_entropy(unsigned int round, - dif_otbn_err_bits_t otbn_err_val, +static void consume_entropy(unsigned int round, dif_acc_err_bits_t acc_err_val, dif_rv_core_ibex_rnd_status_t ibex_rnd_fips) { uint32_t ibex_rnd_data; dif_rv_core_ibex_rnd_status_t ibex_rnd_status; - dif_otbn_irq_state_snapshot_t intr_state; + dif_acc_irq_state_snapshot_t intr_state; CHECK_STATUS_OK(entropy_config(round)); - // Launch an OTBN program consuming entropy via both + // Launch an ACC program consuming entropy via both // the RND and the URND interface. - CHECK_STATUS_OK(otbn_testutils_execute(&otbn)); - // Verify that the OTBN finishes with the expected error values + CHECK_STATUS_OK(acc_testutils_execute(&acc)); + // Verify that the ACC finishes with the expected error values // and interrupt flags. - CHECK_STATUS_OK(otbn_testutils_wait_for_done(&otbn, otbn_err_val)); - CHECK_DIF_OK(dif_otbn_irq_get_state(&otbn, &intr_state)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(&acc, acc_err_val)); + CHECK_DIF_OK(dif_acc_irq_get_state(&acc, &intr_state)); CHECK(intr_state & 0x1); - CHECK_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn)); + CHECK_DIF_OK(dif_acc_irq_acknowledge_all(&acc)); // Read rnd data through the IBEX and verify if the FIPS compliance // status is as expected. // The first read gets rid of leftover entropy from previous configurations @@ -161,15 +160,15 @@ static void consume_entropy(unsigned int round, bool test_main(void) { init_peripherals(); - // Prepare the OTBN for execution. - configure_otbn(); + // Prepare the ACC for execution. + configure_acc(); // Run the Procedure and check if EDN1 produces FIPS non-compliant entropy. - consume_entropy(/*round=*/1, kDifOtbnErrBitsRndFipsChkFail, + consume_entropy(/*round=*/1, kDifAccErrBitsRndFipsChkFail, kDifRvCoreIbexRndStatusFipsCompliant); // Run the Procedure and check if EDN0 produces FIPS non-compliant entropy. - consume_entropy(/*round=*/2, kDifOtbnErrBitsNoError, 0); + consume_entropy(/*round=*/2, kDifAccErrBitsNoError, 0); // Run the Procedure and check if both EDNs produce FIPS compliant entropy. - consume_entropy(/*round=*/3, kDifOtbnErrBitsNoError, + consume_entropy(/*round=*/3, kDifAccErrBitsNoError, kDifRvCoreIbexRndStatusFipsCompliant); return true; diff --git a/sw/device/tests/entropy_src_bypass_mode_health_test.c b/sw/device/tests/entropy_src_bypass_mode_health_test.c index c59182a6e4d..a7faa7abca0 100644 --- a/sw/device/tests/entropy_src_bypass_mode_health_test.c +++ b/sw/device/tests/entropy_src_bypass_mode_health_test.c @@ -3,33 +3,33 @@ // SPDX-License-Identifier: Apache-2.0 #include "hw/ip/aes/model/aes_modes.h" +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_aes.h" #include "hw/top/dt/dt_alert_handler.h" #include "hw/top/dt/dt_csrng.h" #include "hw/top/dt/dt_edn.h" #include "hw/top/dt/dt_entropy_src.h" -#include "hw/top/dt/dt_otbn.h" #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_alert_handler.h" #include "sw/device/lib/dif/dif_base.h" #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_edn.h" #include "sw/device/lib/dif/dif_entropy_src.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_pwrmgr.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" #include "sw/device/lib/runtime/hart.h" #include "sw/device/lib/runtime/ibex.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/aes_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #include "sw/device/lib/dif/autogen/dif_entropy_src_autogen.h" @@ -43,19 +43,19 @@ static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; static dif_aes_t aes; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_alert_handler_t alert_handler; status_t init_test_environment(void) { LOG_INFO( - "Initializing modules sntropy_src, csrng, edn0, edn1, aes, otbn and " + "Initializing modules sntropy_src, csrng, edn0, edn1, aes, acc and " "alert_handler..."); TRY(dif_entropy_src_init_from_dt(kDtEntropySrc, &entropy_src)); TRY(dif_csrng_init_from_dt(kDtCsrng, &csrng)); TRY(dif_edn_init_from_dt(kDtEdn0, &edn0)); TRY(dif_edn_init_from_dt(kDtEdn1, &edn1)); TRY(dif_aes_init_from_dt(kDtAes, &aes)); - TRY(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + TRY(dif_acc_init_from_dt(kDtAcc, &acc)); TRY(dif_alert_handler_init_from_dt(kDtAlertHandler, &alert_handler)); return OK_STATUS(); } @@ -207,78 +207,78 @@ status_t test_and_verify_aes_operation(void) { return OK_STATUS(); } -status_t start_otbn_program(void) { - LOG_INFO("Starting OTBN randomness test..."); +status_t start_acc_program(void) { + LOG_INFO("Starting ACC randomness test..."); - // Start the OTBN randomness test with one iteration - otbn_randomness_test_start(&otbn, 1); + // Start the ACC randomness test with one iteration + acc_randomness_test_start(&acc, 1); - LOG_INFO("OTBN randomness test started"); + LOG_INFO("ACC randomness test started"); return OK_STATUS(); } -status_t verify_otbn_hang(void) { - LOG_INFO("Verifying OTBN program hang..."); +status_t verify_acc_hang(void) { + LOG_INFO("Verifying ACC program hang..."); - // Wait for a timeout period to check if OTBN is still busy + // Wait for a timeout period to check if ACC is still busy const uint32_t kIterateMaxRetries = 1000000; - bool otbn_busy = true; + bool acc_busy = true; uint32_t iter_cntr = kIterateMaxRetries; - dif_otbn_status_t otbn_status; + dif_acc_status_t acc_status; while (iter_cntr > 0) { - // Check if OTBN is still busy - TRY(dif_otbn_get_status(&otbn, &otbn_status)); + // Check if ACC is still busy + TRY(dif_acc_get_status(&acc, &acc_status)); // Check if any of the busy status flags are set - otbn_busy = (otbn_status & - (kDifOtbnStatusBusyExecute | kDifOtbnStatusBusySecWipeDmem | - kDifOtbnStatusBusySecWipeImem)) != 0; - TRY_CHECK(otbn_busy, - "OTBN program completed unexpectedly; expected it to hang"); + acc_busy = + (acc_status & (kDifAccStatusBusyExecute | kDifAccStatusBusySecWipeDmem | + kDifAccStatusBusySecWipeImem)) != 0; + TRY_CHECK(acc_busy, + "ACC program completed unexpectedly; expected it to hang"); iter_cntr--; } - // After timeout, if OTBN is still busy, we shall conclude it's hanging as + // After timeout, if ACC is still busy, we shall conclude it's hanging as // expected - if (otbn_busy) { - LOG_INFO("OTBN program is still running as expected (hang detected)"); + if (acc_busy) { + LOG_INFO("ACC program is still running as expected (hang detected)"); - // Print OTBN status and error bits - dif_otbn_err_bits_t otbn_err_bits; - TRY(dif_otbn_get_err_bits(&otbn, &otbn_err_bits)); - LOG_INFO("OTBN status: 0x%x", otbn_status); - LOG_INFO("OTBN error bits: 0x%x", otbn_err_bits); + // Print ACC status and error bits + dif_acc_err_bits_t acc_err_bits; + TRY(dif_acc_get_err_bits(&acc, &acc_err_bits)); + LOG_INFO("ACC status: 0x%x", acc_status); + LOG_INFO("ACC error bits: 0x%x", acc_err_bits); // Double check to confirm no other unexpected errors are // present leading to hang - if (otbn_err_bits != kDifOtbnErrBitsNoError) { - LOG_ERROR("OTBN encountered unexpected errors"); + if (acc_err_bits != kDifAccErrBitsNoError) { + LOG_ERROR("ACC encountered unexpected errors"); // Optionally, decode and print specific error bits - if (otbn_err_bits & kDifOtbnErrBitsBadDataAddr) { + if (acc_err_bits & kDifAccErrBitsBadDataAddr) { LOG_ERROR("A BAD_DATA_ADDR error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsBadInsnAddr) { + if (acc_err_bits & kDifAccErrBitsBadInsnAddr) { LOG_ERROR("A BAD_INSN_ADDR error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsCallStack) { + if (acc_err_bits & kDifAccErrBitsCallStack) { LOG_ERROR("A CALL_STACK error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsIllegalInsn) { + if (acc_err_bits & kDifAccErrBitsIllegalInsn) { LOG_ERROR("An ILLEGAL_INSN error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsLoop) { + if (acc_err_bits & kDifAccErrBitsLoop) { LOG_ERROR("A LOOP error was observed"); } - otbn_randomness_test_end(&otbn, 1); + acc_randomness_test_end(&acc, 1); return INTERNAL(); } return OK_STATUS(); } else { - LOG_ERROR("OTBN program did not hang as expected"); + LOG_ERROR("ACC program did not hang as expected"); return INTERNAL(); } } @@ -434,12 +434,12 @@ status_t execute_test(void) { // endpoint(e.g. AES) finishes its operation CHECK_STATUS_OK(test_and_verify_aes_operation()); - // Step 8: Trigger the execution of an OTBN program requiring entropy from + // Step 8: Trigger the execution of an ACC program requiring entropy from // both EDN1 and EDN0 - CHECK_STATUS_OK(start_otbn_program()); + CHECK_STATUS_OK(start_acc_program()); - // Step 9: Verify the OTBN program hangs - CHECK_STATUS_OK(verify_otbn_hang()); + // Step 9: Verify the ACC program hangs + CHECK_STATUS_OK(verify_acc_hang()); // Step 10: Disable the entropy complex again CHECK_STATUS_OK(disable_entropy_complex()); diff --git a/sw/device/tests/entropy_src_csrng_test.c b/sw/device/tests/entropy_src_csrng_test.c index a59e1f101e6..1ce7b7edf39 100644 --- a/sw/device/tests/entropy_src_csrng_test.c +++ b/sw/device/tests/entropy_src_csrng_test.c @@ -2,32 +2,32 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_csrng.h" #include "hw/top/dt/dt_edn.h" -#include "hw/top/dt/dt_otbn.h" #include "hw/top/dt/dt_rv_plic.h" #include "sw/device/lib/base/macros.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_edn.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/runtime/irq.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/csrng_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/rand_testutils.h" #include "sw/device/lib/testing/rv_plic_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #include "sw/device/lib/testing/autogen/isr_testutils.h" static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_rv_plic_t plic; OTTF_DEFINE_TEST_CONFIG(); @@ -72,7 +72,7 @@ static void init_peripherals(void) { CHECK_DIF_OK(dif_csrng_init_from_dt(kDtCsrng, &csrng)); CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0)); CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1)); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic)); } @@ -233,7 +233,7 @@ static void edn_configure(const dif_edn_t *edn, irq_flag_id_t irq_flag_id, } /** - * Initializes EDN instances using the `SW_CMD_REQ` interface and runs the OTBN + * Initializes EDN instances using the `SW_CMD_REQ` interface and runs the ACC * randomness test to verify the entropy delivered by EDN0 and EDN1. * * @param seed_material Seed material used in EDN instantiate and reseed @@ -251,17 +251,17 @@ static void test_edn_cmd_done(const dif_edn_seed_material_t *seed_material) { plic_interrupts_enable(); // The EDN0 is connected to other peripherals that regularly request entropy - // so we keep generating entropy on the EDN0 to make sure that the OTBN - // gets enough to finish the test. The EDN1 is only connected to the OTBN + // so we keep generating entropy on the EDN0 to make sure that the ACC + // gets enough to finish the test. The EDN1 is only connected to the ACC // so we generate exactly the amount of entropy necessary for the test and not // more otherwise the Generate command will // not be fully executed, causing a hang in the `irq_block_wait()` calls - // following the end of the OTBN test. The OTBN test reads `RND` 5 times + // following the end of the ACC test. The ACC test reads `RND` 5 times // and each read consumes 256b of entropy. The EDN1 generates entropy per // blocks of 128b so we need to generate 10 blocks. - const size_t kEdnBlockSizeBits = 128; // Each EDN block contains 128b. - const size_t kOtbnRequestSizeBits = 256; // Each OTBN request requires 256b. - const size_t kOtbnTestRequestCount = + const size_t kEdnBlockSizeBits = 128; // Each EDN block contains 128b. + const size_t kAccRequestSizeBits = 256; // Each ACC request requires 256b. + const size_t kAccTestRequestCount = 5; // The number of `RND` reads in the randomness test. // Number of blocks generated on the EDN1. @@ -274,8 +274,8 @@ static void test_edn_cmd_done(const dif_edn_seed_material_t *seed_material) { edn_ready_wait(&edn1); CHECK_STATUS_OK(entropy_testutils_error_check(&csrng, &edn0, &edn1)); - LOG_INFO("OTBN:START"); - otbn_randomness_test_start(&otbn, /*iters=*/0); + LOG_INFO("ACC:START"); + acc_randomness_test_start(&acc, /*iters=*/0); bool busy = true; while (busy) { @@ -288,20 +288,20 @@ static void test_edn_cmd_done(const dif_edn_seed_material_t *seed_material) { if (irq_flags[kTestIrqFlagIdEdn1CmdDone]) { edn1_generated_blocks++; if (edn1_generated_blocks < - kOtbnTestRequestCount * kOtbnRequestSizeBits / kEdnBlockSizeBits) { + kAccTestRequestCount * kAccRequestSizeBits / kEdnBlockSizeBits) { irq_flags[kTestIrqFlagIdEdn1CmdDone] = false; // Warning: `dif_edn_generate_start` takes a length in words (32b). CHECK_DIF_OK(dif_edn_generate_start(&edn1, kEdnBlockSizeBits / 32)); } } - // Check if OTBN is still running. - dif_otbn_status_t status; - CHECK_DIF_OK(dif_otbn_get_status(&otbn, &status)); - busy = status != kDifOtbnStatusIdle && status != kDifOtbnStatusLocked; + // Check if ACC is still running. + dif_acc_status_t status; + CHECK_DIF_OK(dif_acc_get_status(&acc, &status)); + busy = status != kDifAccStatusIdle && status != kDifAccStatusLocked; } - CHECK(otbn_randomness_test_end(&otbn, /*skip_otbn_done_check=*/false)); - LOG_INFO("OTBN:END"); + CHECK(acc_randomness_test_end(&acc, /*skip_acc_done_check=*/false)); + LOG_INFO("ACC:END"); // See comment above regarding generate command length and potential test // locking issues for EDN1. diff --git a/sw/device/tests/entropy_src_edn_reqs_test.c b/sw/device/tests/entropy_src_edn_reqs_test.c index 9e758858317..f338b076008 100644 --- a/sw/device/tests/entropy_src_edn_reqs_test.c +++ b/sw/device/tests/entropy_src_edn_reqs_test.c @@ -2,6 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_aes.h" #include "hw/top/dt/dt_alert_handler.h" #include "hw/top/dt/dt_csrng.h" @@ -9,19 +10,18 @@ #include "hw/top/dt/dt_entropy_src.h" #include "hw/top/dt/dt_keymgr.h" #include "hw/top/dt/dt_kmac.h" -#include "hw/top/dt/dt_otbn.h" #include "hw/top/dt/dt_otp_ctrl.h" #include "hw/top/dt/dt_pwrmgr.h" #include "hw/top/dt/dt_rv_core_ibex.h" #include "sw/device/lib/arch/boot_stage.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_alert_handler.h" #include "sw/device/lib/dif/dif_entropy_src.h" #include "sw/device/lib/dif/dif_keymgr.h" #include "sw/device/lib/dif/dif_kmac.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_otp_ctrl.h" #include "sw/device/lib/dif/dif_pwrmgr.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" @@ -35,7 +35,7 @@ #include "sw/device/lib/testing/pwrmgr_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #include "hw/top/alert_handler_regs.h" // Generated. @@ -46,7 +46,7 @@ static dif_edn_t edn1; static dif_entropy_src_t entropy_src; static dif_kmac_t kmac; static dif_keymgr_t kmgr; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_otp_ctrl_t otp; static dif_pwrmgr_t pwrmgr; static dif_rv_core_ibex_t ibex; @@ -217,7 +217,7 @@ void test_initialize(void) { CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &ibex)); CHECK_DIF_OK(dif_pwrmgr_init_from_dt(kDtPwrmgrAon, &pwrmgr)); CHECK_DIF_OK(dif_keymgr_init_from_dt(kDtKeymgr, &kmgr)); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); CHECK_DIF_OK(dif_otp_ctrl_init_from_dt(kDtOtpCtrl, &otp)); CHECK_DIF_OK(dif_aes_init_from_dt(kDtAes, &aes)); CHECK_DIF_OK(dif_kmac_init_from_dt(kDtKmac, &kmac)); @@ -232,7 +232,7 @@ status_t execute_test(void) { LOG_INFO("Entropy src test %d/%d", i, loop); alert_handler_test(&pwrmgr); aes_test(&aes); - otbn_randomness_test_start(&otbn, /*iters=*/0); + acc_randomness_test_start(&acc, /*iters=*/0); keymgr_test(&kmgr); otp_ctrl_test(&otp); kmac_test(&kmac); @@ -240,7 +240,7 @@ status_t execute_test(void) { AES_TESTUTILS_WAIT_FOR_STATUS(&aes, kDifAesStatusIdle, /*value=*/true, /*timeout_usec=*/100000); - CHECK(otbn_randomness_test_end(&otbn, /*skip_otbn_done_check=*/false)); + CHECK(acc_randomness_test_end(&acc, /*skip_acc_done_check=*/false)); CHECK_STATUS_OK(entropy_testutils_error_check(&csrng, &edn0, &edn1)); } diff --git a/sw/device/tests/entropy_src_fips_mode_health_test.c b/sw/device/tests/entropy_src_fips_mode_health_test.c index 74d18d7726e..f95f6ed9eac 100644 --- a/sw/device/tests/entropy_src_fips_mode_health_test.c +++ b/sw/device/tests/entropy_src_fips_mode_health_test.c @@ -3,31 +3,31 @@ // SPDX-License-Identifier: Apache-2.0 #include "hw/ip/aes/model/aes_modes.h" +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_aes.h" #include "hw/top/dt/dt_alert_handler.h" #include "hw/top/dt/dt_csrng.h" #include "hw/top/dt/dt_edn.h" #include "hw/top/dt/dt_entropy_src.h" -#include "hw/top/dt/dt_otbn.h" #include "sw/device/lib/base/bitfield.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/mmio.h" #include "sw/device/lib/base/status.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_alert_handler.h" #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_edn.h" #include "sw/device/lib/dif/dif_entropy_src.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/runtime/hart.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/aes_testutils.h" #include "sw/device/lib/testing/csrng_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #include "hw/top/entropy_src_regs.h" // autogenerated @@ -45,19 +45,19 @@ static dif_csrng_t csrng; static dif_edn_t edn0; static dif_edn_t edn1; static dif_aes_t aes; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_alert_handler_t alert_handler; status_t init_test_environment(void) { LOG_INFO( - "Initializing modules entropy_src, csrng, edn0, edn1, aes, otbn and " + "Initializing modules entropy_src, csrng, edn0, edn1, aes, acc and " "alert_handler..."); TRY(dif_entropy_src_init_from_dt(kDtEntropySrc, &entropy_src)); TRY(dif_csrng_init_from_dt(kDtCsrng, &csrng)); TRY(dif_edn_init_from_dt(kDtEdn0, &edn0)); TRY(dif_edn_init_from_dt(kDtEdn1, &edn1)); TRY(dif_aes_init_from_dt(kDtAes, &aes)); - TRY(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + TRY(dif_acc_init_from_dt(kDtAcc, &acc)); TRY(dif_alert_handler_init_from_dt(kDtAlertHandler, &alert_handler)); return OK_STATUS(); } @@ -720,76 +720,76 @@ status_t test_and_verify_aes_operation_hang(void) { return OK_STATUS(); } -status_t test_and_verify_otbn_operation(void) { - LOG_INFO("Starting OTBN randomness test...(expect completion)"); +status_t test_and_verify_acc_operation(void) { + LOG_INFO("Starting ACC randomness test...(expect completion)"); - // Start the OTBN randomness test with one iteration - otbn_randomness_test_start(&otbn, 1); + // Start the ACC randomness test with one iteration + acc_randomness_test_start(&acc, 1); busy_spin_micros(9500); - // Wait for a timeout period to check if OTBN is still busy + // Wait for a timeout period to check if ACC is still busy const uint32_t kIterateMaxRetries = 10; - bool otbn_busy = true; + bool acc_busy = true; uint32_t iter_cntr = kIterateMaxRetries; - dif_otbn_status_t otbn_status; + dif_acc_status_t acc_status; while (iter_cntr > 0) { - // Check if OTBN is still busy - TRY(dif_otbn_get_status(&otbn, &otbn_status)); + // Check if ACC is still busy + TRY(dif_acc_get_status(&acc, &acc_status)); // Check if any of the busy status flags are set - otbn_busy = (otbn_status & - (kDifOtbnStatusBusyExecute | kDifOtbnStatusBusySecWipeDmem | - kDifOtbnStatusBusySecWipeImem)) != 0; - // If OTBN is no longer busy, it has completed successfully + acc_busy = + (acc_status & (kDifAccStatusBusyExecute | kDifAccStatusBusySecWipeDmem | + kDifAccStatusBusySecWipeImem)) != 0; + // If ACC is no longer busy, it has completed successfully // Break the loop - if (!otbn_busy) { + if (!acc_busy) { break; } iter_cntr--; } - // After timeout, if OTBN is not busy, we shall conclude it's + // After timeout, if ACC is not busy, we shall conclude it's // completed running, lets check final status - if (!otbn_busy) { - // Print OTBN status and error bits - dif_otbn_err_bits_t otbn_err_bits; - TRY(dif_otbn_get_err_bits(&otbn, &otbn_err_bits)); - LOG_INFO("OTBN status: 0x%x", otbn_status); - LOG_INFO("OTBN error bits: 0x%x", otbn_err_bits); + if (!acc_busy) { + // Print ACC status and error bits + dif_acc_err_bits_t acc_err_bits; + TRY(dif_acc_get_err_bits(&acc, &acc_err_bits)); + LOG_INFO("ACC status: 0x%x", acc_status); + LOG_INFO("ACC error bits: 0x%x", acc_err_bits); - LOG_INFO("OTBN program ran as expected with no hang"); + LOG_INFO("ACC program ran as expected with no hang"); // Double check to confirm no other unexpected errors are // present leading to hang - if (otbn_err_bits != kDifOtbnErrBitsNoError) { - LOG_ERROR("OTBN encountered unexpected errors"); + if (acc_err_bits != kDifAccErrBitsNoError) { + LOG_ERROR("ACC encountered unexpected errors"); // Optionally, decode and print specific error bits - if (otbn_err_bits & kDifOtbnErrBitsBadDataAddr) { + if (acc_err_bits & kDifAccErrBitsBadDataAddr) { LOG_ERROR("A BAD_DATA_ADDR error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsBadInsnAddr) { + if (acc_err_bits & kDifAccErrBitsBadInsnAddr) { LOG_ERROR("A BAD_INSN_ADDR error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsCallStack) { + if (acc_err_bits & kDifAccErrBitsCallStack) { LOG_ERROR("A CALL_STACK error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsIllegalInsn) { + if (acc_err_bits & kDifAccErrBitsIllegalInsn) { LOG_ERROR("An ILLEGAL_INSN error was observed"); } - if (otbn_err_bits & kDifOtbnErrBitsLoop) { + if (acc_err_bits & kDifAccErrBitsLoop) { LOG_ERROR("A LOOP error was observed"); } - otbn_randomness_test_end(&otbn, 1); + acc_randomness_test_end(&acc, 1); return INTERNAL(); } return OK_STATUS(); } else { - // If still busy after kIterateMaxRetries, OTBN has not completed and failed - LOG_ERROR("OTBN program did not complete run"); + // If still busy after kIterateMaxRetries, ACC has not completed and failed + LOG_ERROR("ACC program did not complete run"); return INTERNAL(); } } @@ -842,13 +842,13 @@ status_t wait_for_recoverable_alert(void) { return OK_STATUS(); } -status_t start_otbn_program(void) { - LOG_INFO("Starting OTBN randomness test..."); +status_t start_acc_program(void) { + LOG_INFO("Starting ACC randomness test..."); - // Start the OTBN randomness test with one iteration - otbn_randomness_test_start(&otbn, 1); + // Start the ACC randomness test with one iteration + acc_randomness_test_start(&acc, 1); - LOG_INFO("OTBN randomness test started"); + LOG_INFO("ACC randomness test started"); return OK_STATUS(); } @@ -876,15 +876,15 @@ status_t execute_test(void) { CHECK_STATUS_OK(enable_realistic_csrng_edns_auto_mode()); // Step 6: Trigger the execution of a cryptographic hardware block to stess - // test the entropy (e.g. AES, OTBN) to test EDN0 - // Step 7: Verify the entropy consuming endpoint(e.g. AES, OTBN) + // test the entropy (e.g. AES, ACC) to test EDN0 + // Step 7: Verify the entropy consuming endpoint(e.g. AES, ACC) // finishes its operation CHECK_STATUS_OK(test_and_verify_aes_operation()); CHECK_STATUS_OK(test_and_verify_aes_operation()); CHECK_STATUS_OK(test_and_verify_aes_operation()); - CHECK_STATUS_OK(test_and_verify_otbn_operation()); - CHECK_STATUS_OK(test_and_verify_otbn_operation()); - CHECK_STATUS_OK(test_and_verify_otbn_operation()); + CHECK_STATUS_OK(test_and_verify_acc_operation()); + CHECK_STATUS_OK(test_and_verify_acc_operation()); + CHECK_STATUS_OK(test_and_verify_acc_operation()); } LOG_INFO( "Realistic Test successfully passed with different health test window " diff --git a/sw/device/tests/entropy_src_fw_override_test.c b/sw/device/tests/entropy_src_fw_override_test.c index d78566d30a2..bb6fd29fd65 100644 --- a/sw/device/tests/entropy_src_fw_override_test.c +++ b/sw/device/tests/entropy_src_fw_override_test.c @@ -4,12 +4,12 @@ #include +#include "hw/top/dt/dt_acc.h" #include "hw/top/dt/dt_aes.h" #include "hw/top/dt/dt_csrng.h" #include "hw/top/dt/dt_edn.h" #include "hw/top/dt/dt_entropy_src.h" #include "hw/top/dt/dt_kmac.h" -#include "hw/top/dt/dt_otbn.h" #include "hw/top/dt/dt_rv_core_ibex.h" #include "hw/top/dt/dt_rv_plic.h" #include "sw/device/lib/base/memory.h" @@ -31,7 +31,7 @@ #include "sw/device/lib/testing/rv_core_ibex_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "sw/device/tests/otbn_randomness_impl.h" +#include "sw/device/tests/acc_randomness_impl.h" #include "hw/top/entropy_src_regs.h" // Generated. @@ -110,7 +110,7 @@ static dif_edn_t edn0; static dif_edn_t edn1; static dif_entropy_src_t entropy_src; static dif_kmac_t kmac; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_rv_core_ibex_t rv_core_ibex; static dif_rv_plic_t rv_plic; @@ -475,9 +475,9 @@ status_t firmware_override_extract_insert( /*message=*/"hello", /*message_len=*/6, ARRAYSIZE(output), output, /*capacity=*/NULL)); - LOG_INFO("Running OTBN..."); - otbn_randomness_test_start(&otbn, /*iters=*/10); - TRY_CHECK(otbn_randomness_test_end(&otbn, /*skip_otbn_done_check=*/false)); + LOG_INFO("Running ACC..."); + acc_randomness_test_start(&acc, /*iters=*/10); + TRY_CHECK(acc_randomness_test_end(&acc, /*skip_acc_done_check=*/false)); return OK_STATUS(); } @@ -489,7 +489,7 @@ bool test_main(void) { CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1)); CHECK_DIF_OK(dif_entropy_src_init_from_dt(kDtEntropySrc, &entropy_src)); CHECK_DIF_OK(dif_kmac_init_from_dt(kDtKmac, &kmac)); - CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn)); + CHECK_DIF_OK(dif_acc_init_from_dt(kDtAcc, &acc)); CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex)); CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &rv_plic)); diff --git a/sw/device/tests/keymgr_derive_cdi_test.c b/sw/device/tests/keymgr_derive_cdi_test.c index 6ecfcc96c41..ffa3baa7747 100644 --- a/sw/device/tests/keymgr_derive_cdi_test.c +++ b/sw/device/tests/keymgr_derive_cdi_test.c @@ -6,8 +6,8 @@ #include #include +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/keymgr_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/ret_sram_testutils.h" #include "sw/device/lib/testing/rstmgr_testutils.h" #include "sw/device/lib/testing/sram_ctrl_testutils.h" @@ -18,7 +18,7 @@ static dif_keymgr_t keymgr; static dif_kmac_t kmac; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_rstmgr_t rstmgr; static dif_sram_ctrl_t sram_ctrl; @@ -46,13 +46,13 @@ enum { /** * Grouping of the three CDI output variants that can be generated in - * each key manager state (identity, versioned software key, sideload OTBN key). + * each key manager state (identity, versioned software key, sideload ACC key). * - * Note that the sideload OTBN key is not visible to software. In order to + * Note that the sideload ACC key is not visible to software. In order to * run the same verification steps as for the identity and software keys, a - * X25519 public key is generated in the OTBN and retrieved. For the sake of + * X25519 public key is generated in the ACC and retrieved. For the sake of * simplicity, and only in the confines of this test, we can assume that the - * X25519 public key and the sideload OTBN key refer to the same thing. + * X25519 public key and the sideload ACC key refer to the same thing. */ typedef struct cdi_outputs { dif_keymgr_output_t identity; @@ -60,16 +60,15 @@ typedef struct cdi_outputs { uint32_t sideload_key[kX2551PublicKeySizeBytes]; } cdi_outputs_t; -// Symbols of the OTBN X22519 public key generation program. -// See sw/otbn/crypto/x25519_sideload.s for the source code. -OTBN_DECLARE_APP_SYMBOLS(x25519_sideload); -OTBN_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_u); -OTBN_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_result); -static const otbn_app_t kOtbnAppX25519 = OTBN_APP_T_INIT(x25519_sideload); -static const otbn_addr_t kOtbnVarEncU = - OTBN_ADDR_T_INIT(x25519_sideload, enc_u); -static const otbn_addr_t kOtbnVarEncResult = - OTBN_ADDR_T_INIT(x25519_sideload, enc_result); +// Symbols of the ACC X22519 public key generation program. +// See sw/acc/crypto/x25519_sideload.s for the source code. +ACC_DECLARE_APP_SYMBOLS(x25519_sideload); +ACC_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_u); +ACC_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_result); +static const acc_app_t kAccAppX25519 = ACC_APP_T_INIT(x25519_sideload); +static const acc_addr_t kAccVarEncU = ACC_ADDR_T_INIT(x25519_sideload, enc_u); +static const acc_addr_t kAccVarEncResult = + ACC_ADDR_T_INIT(x25519_sideload, enc_result); OTTF_DEFINE_TEST_CONFIG(); @@ -95,7 +94,7 @@ static void init_peripheral_handles(void) { mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR), &sram_ctrl)); CHECK_DIF_OK( - dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); } /** @@ -203,42 +202,42 @@ static void derive_sw_key(const char *state_name, dif_keymgr_output_t *key) { } /** - * Invoke the generation of sideload OTBN key, run the X25519 OTBN program and + * Invoke the generation of sideload ACC key, run the X25519 ACC program and * read back the resulting public key. A second generation with an invalid key * version should fail. * * @param state_name The current key manager state string. * @param The destination of the read X25519 public key. */ -static void derive_sideload_otbn_key(const char *state_name, - uint32_t key[kKeymgrOutputSizeWords]) { +static void derive_sideload_acc_key(const char *state_name, + uint32_t key[kKeymgrOutputSizeWords]) { uint32_t max_version; CHECK_STATUS_OK(keymgr_testutils_max_key_version_get(&keymgr, &max_version)); dif_keymgr_versioned_key_params_t params = kKeyVersionedParams; - params.dest = kDifKeymgrVersionedKeyDestOtbn; + params.dest = kDifKeymgrVersionedKeyDestAcc; params.version = max_version; CHECK_STATUS_OK(keymgr_testutils_generate_versioned_key(&keymgr, params)); - LOG_INFO("Keymgr generated HW output for Otbn at %s State", state_name); + LOG_INFO("Keymgr generated HW output for Acc at %s State", state_name); - // Run the X25519 public key generation. For more details, see the OTBN - // sideload test sw/device/tests/keymgr_sideload_otbn_test.c. - CHECK_STATUS_OK(otbn_testutils_load_app(&otbn, kOtbnAppX25519)); - CHECK_DIF_OK(dif_otbn_set_ctrl_software_errs_fatal(&otbn, false)); + // Run the X25519 public key generation. For more details, see the ACC + // sideload test sw/device/tests/keymgr_sideload_acc_test.c. + CHECK_STATUS_OK(acc_testutils_load_app(&acc, kAccAppX25519)); + CHECK_DIF_OK(dif_acc_set_ctrl_software_errs_fatal(&acc, false)); const uint32_t kEncodedU[8] = { // Montgomery u-Coordinate. 0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, }; - CHECK_STATUS_OK(otbn_testutils_write_data(&otbn, sizeof(kEncodedU), - &kEncodedU, kOtbnVarEncU)); - LOG_INFO("Starting OTBN program..."); - CHECK_DIF_OK(dif_otbn_set_ctrl_software_errs_fatal(&otbn, false)); - CHECK_STATUS_OK(otbn_testutils_execute(&otbn)); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(&otbn, 0)); - CHECK_STATUS_OK(otbn_testutils_read_data(&otbn, kX2551PublicKeySizeBytes, - kOtbnVarEncResult, key)); + CHECK_STATUS_OK(acc_testutils_write_data(&acc, sizeof(kEncodedU), &kEncodedU, + kAccVarEncU)); + LOG_INFO("Starting ACC program..."); + CHECK_DIF_OK(dif_acc_set_ctrl_software_errs_fatal(&acc, false)); + CHECK_STATUS_OK(acc_testutils_execute(&acc)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(&acc, 0)); + CHECK_STATUS_OK(acc_testutils_read_data(&acc, kX2551PublicKeySizeBytes, + kAccVarEncResult, key)); #ifndef DERIVE_ATTESTATION // If the key version is larger than the permitted maximum version, then @@ -249,7 +248,7 @@ static void derive_sideload_otbn_key(const char *state_name, } /** - * Derive a CDI identity, software key and sideload OTBN key. If the `write` + * Derive a CDI identity, software key and sideload ACC key. If the `write` * flag is set, then the keys are written at specific offset in the retention * SRAM. In the other case, the generated outputs are compared against outputs * from the retention SRAM (corresponding to a run before the reset). Pre- and @@ -267,7 +266,7 @@ static void derive_keys(const char *state_name, bool write, cdi_outputs_t *next_outputs) { derive_identity(state_name, &next_outputs->identity); derive_sw_key(state_name, &next_outputs->sw_key); - derive_sideload_otbn_key(state_name, next_outputs->sideload_key); + derive_sideload_acc_key(state_name, next_outputs->sideload_key); if (prev_outputs) { CHECK(!compare_outputs(&prev_outputs->identity, &next_outputs->identity)); @@ -299,10 +298,10 @@ static void derive_keys(const char *state_name, * `OwnerKey`: * - Generate identity SW output for the Attestation CDI. * - Generate SW output for the Attestation CDI. - * - Generate OTBN sideload output for the Attestation CDI. + * - Generate ACC sideload output for the Attestation CDI. * * The creation of the three outputs is handled by the `derive_identity`, - * `derive_sw_key` and `derive_sideload_otbn_key` functions, which are invoked + * `derive_sw_key` and `derive_sideload_acc_key` functions, which are invoked * by `derive_keys` through `test_derive_cdi` that traverses the three * operational states. * diff --git a/sw/device/tests/keymgr_dpe_key_derivation_test.c b/sw/device/tests/keymgr_dpe_key_derivation_test.c index 96356f87495..4bc31c85b36 100644 --- a/sw/device/tests/keymgr_dpe_key_derivation_test.c +++ b/sw/device/tests/keymgr_dpe_key_derivation_test.c @@ -70,10 +70,10 @@ bool test_main(void) { init_kmac_for_keymgr(); - // Generate OTBN output from the boot stage 0 key. + // Generate ACC output from the boot stage 0 key. gen_params.slot_src_sel = 1; gen_params.sideload_key = true; // HW key - gen_params.key_dest = kDifKeymgrDpeKeyDestOtbn; + gen_params.key_dest = kDifKeymgrDpeKeyDestAcc; gen_params.version = 0; gen_params.salt[7] = 0x49379059; gen_params.salt[6] = 0xff523992; @@ -84,7 +84,7 @@ bool test_main(void) { gen_params.salt[1] = 0x481eae40; gen_params.salt[0] = 0x45e2c7f0; generate(&keymgr_dpe, &gen_params); - LOG_INFO("KeymgrDpe generated OTBN output from boot stage 0"); + LOG_INFO("KeymgrDpe generated ACC output from boot stage 0"); // Generate SW output from boot stage 0 key. gen_params.slot_src_sel = 1; @@ -200,10 +200,10 @@ bool test_main(void) { generate(&keymgr_dpe, &gen_params); LOG_INFO("KeymgrDpe generated SW output from boot stage 1"); - // Generate OTBN output from the boot stage 1 key. + // Generate ACC output from the boot stage 1 key. gen_params.slot_src_sel = 1; gen_params.sideload_key = true; // HW key - gen_params.key_dest = kDifKeymgrDpeKeyDestOtbn; + gen_params.key_dest = kDifKeymgrDpeKeyDestAcc; gen_params.version = 3; gen_params.salt[7] = 0x564712d4; gen_params.salt[6] = 0x7ab745f5; @@ -214,7 +214,7 @@ bool test_main(void) { gen_params.salt[1] = 0x593b54d4; gen_params.salt[0] = 0xa75e231b; generate(&keymgr_dpe, &gen_params); - LOG_INFO("KeymgrDpe generated OTBN output from boot stage 1"); + LOG_INFO("KeymgrDpe generated ACC output from boot stage 1"); // Derive a boot stage 2 key from the boot stage 1 key. adv_params.slot_dst_sel = 2; @@ -285,10 +285,10 @@ bool test_main(void) { generate(&keymgr_dpe, &gen_params); LOG_INFO("KeymgrDpe generated KMAC output from boot stage 2"); - // Generate OTBN output from the boot stage 2 key. + // Generate ACC output from the boot stage 2 key. gen_params.slot_src_sel = 2; gen_params.sideload_key = true; // HW key - gen_params.key_dest = kDifKeymgrDpeKeyDestOtbn; + gen_params.key_dest = kDifKeymgrDpeKeyDestAcc; gen_params.version = 3; gen_params.salt[7] = 0x3f184f9b; gen_params.salt[6] = 0xd4af6765; @@ -299,7 +299,7 @@ bool test_main(void) { gen_params.salt[1] = 0x6a961bc2; gen_params.salt[0] = 0xec932d64; generate(&keymgr_dpe, &gen_params); - LOG_INFO("KeymgrDpe generated OTBN output from boot stage 2"); + LOG_INFO("KeymgrDpe generated ACC output from boot stage 2"); // Derive a boot stage 3 key from the boot stage 2 key. adv_params.slot_src_sel = 2; @@ -331,10 +331,10 @@ bool test_main(void) { generate(&keymgr_dpe, &gen_params); LOG_INFO("KeymgrDpe generated AES output from boot stage 3"); - // Generate OTBN output from the boot stage 3 key. + // Generate ACC output from the boot stage 3 key. gen_params.slot_src_sel = 3; gen_params.sideload_key = true; // HW key - gen_params.key_dest = kDifKeymgrDpeKeyDestOtbn; + gen_params.key_dest = kDifKeymgrDpeKeyDestAcc; gen_params.version = 0x20; gen_params.salt[7] = 0x2cd82d66; gen_params.salt[6] = 0x24275e98; @@ -345,7 +345,7 @@ bool test_main(void) { gen_params.salt[1] = 0x413a2212; gen_params.salt[0] = 0xc2dcfbc8; generate(&keymgr_dpe, &gen_params); - LOG_INFO("KeymgrDpe generated OTBN output from boot stage 3"); + LOG_INFO("KeymgrDpe generated ACC output from boot stage 3"); // Generate SW output from the boot stage 3 key. gen_params.slot_src_sel = 3; @@ -397,7 +397,7 @@ bool test_main(void) { LOG_INFO("KeymgrDpe generated SW output from boot stage 1"); gen_params.slot_src_sel = 2; gen_params.sideload_key = true; // HW key - gen_params.key_dest = kDifKeymgrDpeKeyDestOtbn; + gen_params.key_dest = kDifKeymgrDpeKeyDestAcc; gen_params.version = 7; gen_params.salt[7] = 0xfa94162c; gen_params.salt[6] = 0xd039a40f; @@ -408,7 +408,7 @@ bool test_main(void) { gen_params.salt[1] = 0xee7790c4; gen_params.salt[0] = 0x0de6bdcf; generate(&keymgr_dpe, &gen_params); - LOG_INFO("KeymgrDpe generated OTBN output from boot stage 2"); + LOG_INFO("KeymgrDpe generated ACC output from boot stage 2"); return true; } diff --git a/sw/device/tests/keymgr_key_derivation_test.c b/sw/device/tests/keymgr_key_derivation_test.c index fd8975b0cd8..f62d99821fc 100644 --- a/sw/device/tests/keymgr_key_derivation_test.c +++ b/sw/device/tests/keymgr_key_derivation_test.c @@ -46,7 +46,7 @@ bool test_main(void) { keymgr_testutils_generate_versioned_key(&keymgr, sideload_params)); LOG_INFO("Keymgr generated SW output at %s State", state_name); - // Generate sideload keys for 3 HW interfaces - Kmac, Aes, Otbn. + // Generate sideload keys for 3 HW interfaces - Kmac, Aes, Acc. sideload_params.dest = kDifKeymgrVersionedKeyDestKmac; CHECK_STATUS_OK( keymgr_testutils_generate_versioned_key(&keymgr, sideload_params)); @@ -57,10 +57,10 @@ bool test_main(void) { keymgr_testutils_generate_versioned_key(&keymgr, sideload_params)); LOG_INFO("Keymgr generated HW output for Aes at %s State", state_name); - sideload_params.dest = kDifKeymgrVersionedKeyDestOtbn; + sideload_params.dest = kDifKeymgrVersionedKeyDestAcc; CHECK_STATUS_OK( keymgr_testutils_generate_versioned_key(&keymgr, sideload_params)); - LOG_INFO("Keymgr generated HW output for Otbn at %s State", state_name); + LOG_INFO("Keymgr generated HW output for Acc at %s State", state_name); CHECK_STATUS_OK(keymgr_testutils_disable(&keymgr)); CHECK_STATUS_OK( diff --git a/sw/device/tests/keymgr_sideload_otbn_test.c b/sw/device/tests/keymgr_sideload_acc_test.c similarity index 60% rename from sw/device/tests/keymgr_sideload_otbn_test.c rename to sw/device/tests/keymgr_sideload_acc_test.c index 2c7281844c7..d977c881e99 100644 --- a/sw/device/tests/keymgr_sideload_otbn_test.c +++ b/sw/device/tests/keymgr_sideload_acc_test.c @@ -7,33 +7,32 @@ #include "sw/device/lib/arch/device.h" #include "sw/device/lib/base/macros.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_keymgr.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/runtime/hart.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/runtime/print.h" +#include "sw/device/lib/testing/acc_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" #include "sw/device/lib/testing/keymgr_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" #include "sw/device/lib/testing/test_framework/check.h" #include "sw/device/lib/testing/test_framework/ottf_main.h" -#include "hw/top/otbn_regs.h" // Generated. +#include "hw/top/acc_regs.h" // Generated. #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" static dif_keymgr_t keymgr; static dif_kmac_t kmac; -static dif_otbn_t otbn; - -/* Set up pointers to symbols in the OTBN application. */ -OTBN_DECLARE_APP_SYMBOLS(x25519_sideload); -OTBN_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_u); -OTBN_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_result); -static const otbn_app_t kOtbnAppX25519 = OTBN_APP_T_INIT(x25519_sideload); -static const otbn_addr_t kOtbnVarEncU = - OTBN_ADDR_T_INIT(x25519_sideload, enc_u); -static const otbn_addr_t kOtbnVarEncResult = - OTBN_ADDR_T_INIT(x25519_sideload, enc_result); +static dif_acc_t acc; + +/* Set up pointers to symbols in the ACC application. */ +ACC_DECLARE_APP_SYMBOLS(x25519_sideload); +ACC_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_u); +ACC_DECLARE_SYMBOL_ADDR(x25519_sideload, enc_result); +static const acc_app_t kAccAppX25519 = ACC_APP_T_INIT(x25519_sideload); +static const acc_addr_t kAccVarEncU = ACC_ADDR_T_INIT(x25519_sideload, enc_u); +static const acc_addr_t kAccVarEncResult = + ACC_ADDR_T_INIT(x25519_sideload, enc_result); OTTF_DEFINE_TEST_CONFIG(); @@ -46,7 +45,7 @@ static void init_peripheral_handles(void) { CHECK_DIF_OK(dif_keymgr_init( mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR), &keymgr)); CHECK_DIF_OK( - dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); } /** @@ -59,53 +58,51 @@ static void init_peripheral_handles(void) { static const uint32_t kEncodedU[8] = { 0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, }; -static const dif_otbn_err_bits_t kOtbnInvalidKeyErr = - 0x1 << OTBN_ERR_BITS_KEY_INVALID_BIT; -static const dif_otbn_err_bits_t kErrBitsOk = 0x0; +static const dif_acc_err_bits_t kAccInvalidKeyErr = + 0x1 << ACC_ERR_BITS_KEY_INVALID_BIT; +static const dif_acc_err_bits_t kErrBitsOk = 0x0; /** - * Runs the OTBN X25519 application. + * Runs the ACC X25519 application. * - * The X25519 app and sideloaded key should already be loaded into OTBN before - * this routine is called. Causes CHECK-fail if the OTBN error code is not as + * The X25519 app and sideloaded key should already be loaded into ACC before + * this routine is called. Causes CHECK-fail if the ACC error code is not as * expected. * - * @param otbn OTBN context object + * @param acc ACC context object * @param[out] result Resulting Montgomery u-coordinate. - * @param expect_err_bits Error code expected from OTBN ERR register. + * @param expect_err_bits Error code expected from ACC ERR register. * an unexpected error. */ -static void run_x25519_app(dif_otbn_t *otbn, uint32_t *result, - dif_otbn_err_bits_t expect_err_bits) { - CHECK_DIF_OK(dif_otbn_set_ctrl_software_errs_fatal(otbn, /*enable=*/false)); +static void run_x25519_app(dif_acc_t *acc, uint32_t *result, + dif_acc_err_bits_t expect_err_bits) { + CHECK_DIF_OK(dif_acc_set_ctrl_software_errs_fatal(acc, /*enable=*/false)); // Copy the input argument (Montgomery u-coordinate). - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, sizeof(kEncodedU), &kEncodedU, - kOtbnVarEncU)); + CHECK_STATUS_OK(acc_testutils_write_data(acc, sizeof(kEncodedU), &kEncodedU, + kAccVarEncU)); - // Run the OTBN program and wait for it to complete. Clear software + // Run the ACC program and wait for it to complete. Clear software // error fatal flag as the test expects an intermediate error state. - LOG_INFO("Starting OTBN program..."); - CHECK_DIF_OK(dif_otbn_set_ctrl_software_errs_fatal(otbn, false)); - CHECK_STATUS_OK(otbn_testutils_execute(otbn)); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(otbn, expect_err_bits)); + LOG_INFO("Starting ACC program..."); + CHECK_DIF_OK(dif_acc_set_ctrl_software_errs_fatal(acc, false)); + CHECK_STATUS_OK(acc_testutils_execute(acc)); + CHECK_STATUS_OK(acc_testutils_wait_for_done(acc, expect_err_bits)); // Copy the result (also a 256-bit Montgomery u-coordinate). - CHECK_STATUS_OK( - otbn_testutils_read_data(otbn, 32, kOtbnVarEncResult, result)); + CHECK_STATUS_OK(acc_testutils_read_data(acc, 32, kAccVarEncResult, result)); } /** - * Run an OTBN program using a sideloaded key. + * Run an ACC program using a sideloaded key. * This routine does not check the correctness of results, merely sideloads the - * key from keymgr to OTBN and then runs the X25519 program. + * key from keymgr to ACC and then runs the X25519 program. */ -static void test_otbn_with_sideloaded_key(dif_keymgr_t *keymgr, - dif_otbn_t *otbn) { +static void test_acc_with_sideloaded_key(dif_keymgr_t *keymgr, dif_acc_t *acc) { // Generate the sideloaded key. // TODO(weicai): also check in SV sequence that the key is correct. dif_keymgr_versioned_key_params_t sideload_params = kKeyVersionedParams; - sideload_params.dest = kDifKeymgrVersionedKeyDestOtbn; + sideload_params.dest = kDifKeymgrVersionedKeyDestAcc; // Get the maximum key version supported by the keymgr in its current state. uint32_t max_key_version; @@ -122,25 +119,25 @@ static void test_otbn_with_sideloaded_key(dif_keymgr_t *keymgr, CHECK_STATUS_OK( keymgr_testutils_generate_versioned_key(keymgr, sideload_params)); - LOG_INFO("Keymgr generated HW output for OTBN."); + LOG_INFO("Keymgr generated HW output for ACC."); // Load the X25519 application. - CHECK_STATUS_OK(otbn_testutils_load_app(otbn, kOtbnAppX25519)); - // Run the OTBN app and retrieve the result. + CHECK_STATUS_OK(acc_testutils_load_app(acc, kAccAppX25519)); + // Run the ACC app and retrieve the result. uint32_t result[8]; - run_x25519_app(otbn, result, kErrBitsOk); + run_x25519_app(acc, result, kErrBitsOk); #ifdef TEST_SIMPLE_CASE_ONLY return; #endif - // Clear the sideload key and check that OTBN errors with the correct error + // Clear the sideload key and check that ACC errors with the correct error // code (`KEY_INVALID` bit 5 = 1). CHECK_DIF_OK( dif_keymgr_sideload_clear_set_enabled(keymgr, kDifToggleEnabled)); LOG_INFO("Clearing the Keymgr generated sideload keys."); uint32_t at_clear_salt_result[8]; - run_x25519_app(otbn, at_clear_salt_result, kOtbnInvalidKeyErr); + run_x25519_app(acc, at_clear_salt_result, kAccInvalidKeyErr); // Disable sideload key clearing. CHECK_DIF_OK( @@ -148,23 +145,23 @@ static void test_otbn_with_sideloaded_key(dif_keymgr_t *keymgr, LOG_INFO("Disable clearing the Keymgr generated sideload keys."); // Clear the ERR bits register - mmio_region_write32(otbn->base_addr, OTBN_ERR_BITS_REG_OFFSET, 0x0); + mmio_region_write32(acc->base_addr, ACC_ERR_BITS_REG_OFFSET, 0x0); CHECK_STATUS_OK(keymgr_testutils_generate_versioned_key( keymgr, sideload_params)); // Regenerate the sideload key. - LOG_INFO("Keymgr generated HW output for OTBN."); + LOG_INFO("Keymgr generated HW output for ACC."); uint32_t post_clear_salt_result[8]; - run_x25519_app(otbn, post_clear_salt_result, kErrBitsOk); + run_x25519_app(acc, post_clear_salt_result, kErrBitsOk); CHECK_ARRAYS_EQ(result, post_clear_salt_result, ARRAYSIZE(result)); // Change the salt to generate a different key. sideload_params.salt[0] = ~sideload_params.salt[0]; CHECK_STATUS_OK( keymgr_testutils_generate_versioned_key(keymgr, sideload_params)); - LOG_INFO("Keymgr generated HW output for OTBN."); + LOG_INFO("Keymgr generated HW output for ACC."); uint32_t modified_salt_result[8]; - run_x25519_app(otbn, modified_salt_result, kErrBitsOk); + run_x25519_app(acc, modified_salt_result, kErrBitsOk); // Check that the result with the new key is different from the first // result. @@ -174,10 +171,10 @@ static void test_otbn_with_sideloaded_key(dif_keymgr_t *keymgr, sideload_params.salt[0] = ~sideload_params.salt[0]; CHECK_STATUS_OK( keymgr_testutils_generate_versioned_key(keymgr, sideload_params)); - LOG_INFO("Keymgr generated HW output for OTBN."); + LOG_INFO("Keymgr generated HW output for ACC."); uint32_t same_key_result[8]; - run_x25519_app(otbn, same_key_result, kErrBitsOk); + run_x25519_app(acc, same_key_result, kErrBitsOk); // Check that the result generated using the same key matches the first // result. @@ -188,8 +185,8 @@ bool test_main(void) { init_peripheral_handles(); CHECK_STATUS_OK(keymgr_testutils_initialize(&keymgr, &kmac)); - // Test OTBN sideloading. - test_otbn_with_sideloaded_key(&keymgr, &otbn); + // Test ACC sideloading. + test_acc_with_sideloaded_key(&keymgr, &acc); return true; } diff --git a/sw/device/tests/otbn_irq_test.c b/sw/device/tests/otbn_irq_test.c deleted file mode 100644 index 9e53b74c3b0..00000000000 --- a/sw/device/tests/otbn_irq_test.c +++ /dev/null @@ -1,162 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "hw/top/dt/dt_api.h" -#include "hw/top/dt/dt_otbn.h" -#include "hw/top/dt/dt_rv_plic.h" -#include "sw/device/lib/dif/dif_otbn.h" -#include "sw/device/lib/dif/dif_rv_plic.h" -#include "sw/device/lib/runtime/irq.h" -#include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" -#include "sw/device/lib/testing/test_framework/check.h" -#include "sw/device/lib/testing/test_framework/ottf_main.h" - -OTBN_DECLARE_APP_SYMBOLS(err_test); - -static const otbn_app_t kAppErrTest = OTBN_APP_T_INIT(err_test); -static const uint32_t kPlicTarget = 0; - -OTTF_DEFINE_TEST_CONFIG(); - -static dif_rv_plic_t plic; -static dif_otbn_t otbn; -static dt_otbn_t kOtbnDt = (dt_otbn_t)0; - -static volatile bool otbn_finished; - -/** - * Get OTBN error bits; check they match expected_err_bits. - */ -static void check_otbn_err_bits(dif_otbn_t *otbn, - dif_otbn_err_bits_t expected_err_bits) { - dif_otbn_err_bits_t otbn_err_bits; - CHECK_DIF_OK(dif_otbn_get_err_bits(otbn, &otbn_err_bits)); - CHECK(otbn_err_bits == expected_err_bits, - "dif_otbn_get_err_bits() produced unexpected error bits: %x", - otbn_err_bits); -} - -/** - * Get the OTBN instruction count; check that it matches expected_insn_cnt. - */ -static void check_otbn_insn_cnt(dif_otbn_t *otbn, uint32_t expected_insn_cnt) { - uint32_t insn_cnt; - CHECK_DIF_OK(dif_otbn_get_insn_cnt(otbn, &insn_cnt)); - CHECK(insn_cnt == expected_insn_cnt, - "Expected to execute %d instructions, but got %d.", expected_insn_cnt, - insn_cnt); -} - -/** - * Get OTBN's status; check that it matches expected_status. - */ -static void check_otbn_status(dif_otbn_t *otbn, - dif_otbn_status_t expected_status) { - dif_otbn_status_t status; - CHECK_DIF_OK(dif_otbn_get_status(otbn, &status)); - CHECK(status == expected_status, "Unexpected status: expected %d but got %d.", - expected_status, status); -} - -/** - * Run a binary on OTBN, waiting for completion by interrupt. - * - * Once the binary has finished, check for expected status, error bits and - * instruction count. - */ -static void run_test_with_irqs(dif_otbn_t *otbn, otbn_app_t app, - dif_otbn_status_t expected_status, - dif_otbn_err_bits_t expected_err_bits, - uint32_t expected_insn_cnt) { - // Clear the otbn_finished flag: we'll set it in the interrupt handler when - // we see the Done interrupt fire. - otbn_finished = false; - - CHECK_STATUS_OK(otbn_testutils_load_app(otbn, app)); - - // If the CTRL.SOFTWARE_ERRS_FATAL flag is set, a software error will be - // promoted to a fatal error (which, among other things, bricks OTBN until - // next reset). Make sure that's not turned on. - CHECK(dif_otbn_set_ctrl_software_errs_fatal(otbn, false) == kDifOk); - - // Enable Done interrupt - CHECK_DIF_OK( - dif_otbn_irq_set_enabled(otbn, kDifOtbnIrqDone, kDifToggleEnabled)); - - // Start OTBN - CHECK_STATUS_OK(otbn_testutils_execute(otbn)); - - // At this point, OTBN should be running. Wait for an interrupt that says - // it's done. - ATOMIC_WAIT_FOR_INTERRUPT(otbn_finished); - - check_otbn_status(otbn, expected_status); - check_otbn_err_bits(otbn, expected_insn_cnt); - check_otbn_insn_cnt(otbn, expected_err_bits); -} - -/** - * Initialize PLIC and enable OTBN interrupt. - */ -static void plic_init_with_irqs(void) { - CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic)); - - dif_rv_plic_irq_id_t irq_id = dt_otbn_irq_to_plic_id(kOtbnDt, kDtOtbnIrqDone); - - // Set interrupt priority to be positive - CHECK_DIF_OK(dif_rv_plic_irq_set_priority(&plic, irq_id, 0x1)); - - // Enable the interrupt - CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(&plic, irq_id, kPlicTarget, - kDifToggleEnabled)); - - // Set the threshold for Ibex to 0. - CHECK_DIF_OK(dif_rv_plic_target_set_threshold(&plic, kPlicTarget, 0x0)); -} - -/** - * The ISR for this test. - * - * This function overrides the default OTTF external ISR. - */ -bool ottf_handle_irq(uint32_t *exc_info, dt_instance_id_t devid, - dif_rv_plic_irq_id_t irq_id) { - if (devid != dt_otbn_instance_id(kOtbnDt)) { - return false; - } - - // Check this is the interrupt we expected - dif_otbn_irq_t otbn_irq = dt_otbn_irq_from_plic_id(kOtbnDt, irq_id); - if (otbn_irq != kDtOtbnIrqDone) { - return false; - } - - // otbn_finished should currently be false (we're supposed to clear it before - // starting OTBN) - CHECK(!otbn_finished); - - // Set otbn_finished, which we'll pick up in run_test_with_irqs. - otbn_finished = true; - - CHECK_DIF_OK(dif_otbn_irq_acknowledge(&otbn, otbn_irq)); - - return true; -} - -bool test_main(void) { - CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); - plic_init_with_irqs(); - - CHECK_DIF_OK(dif_otbn_init_from_dt(kOtbnDt, &otbn)); - - // Enable the external IRQ (so that we see the interrupt from the PLIC) - irq_global_ctrl(true); - irq_external_ctrl(true); - - run_test_with_irqs(&otbn, kAppErrTest, kDifOtbnStatusIdle, - kDifOtbnErrBitsBadDataAddr, 1); - - return true; -} diff --git a/sw/device/tests/otbn_randomness_impl.c b/sw/device/tests/otbn_randomness_impl.c deleted file mode 100644 index 811cd19a7b8..00000000000 --- a/sw/device/tests/otbn_randomness_impl.c +++ /dev/null @@ -1,73 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/tests/otbn_randomness_impl.h" - -#include "sw/device/lib/dif/dif_base.h" -#include "sw/device/lib/dif/dif_otbn.h" -#include "sw/device/lib/runtime/log.h" -#include "sw/device/lib/testing/otbn_testutils.h" -#include "sw/device/lib/testing/test_framework/check.h" - -OTBN_DECLARE_APP_SYMBOLS(randomness); -OTBN_DECLARE_SYMBOL_ADDR(randomness, iterations); -OTBN_DECLARE_SYMBOL_ADDR(randomness, rv); -OTBN_DECLARE_SYMBOL_ADDR(randomness, fail_idx); -OTBN_DECLARE_SYMBOL_ADDR(randomness, rnd_out); -OTBN_DECLARE_SYMBOL_ADDR(randomness, urnd_out); - -static const otbn_app_t kOtbnAppRandomnessApp = OTBN_APP_T_INIT(randomness); -static const otbn_addr_t kVarIters = OTBN_ADDR_T_INIT(randomness, iterations); -static const otbn_addr_t kVarRv = OTBN_ADDR_T_INIT(randomness, rv); -static const otbn_addr_t kVarFailIdx = OTBN_ADDR_T_INIT(randomness, fail_idx); -static const otbn_addr_t kVarRndOut = OTBN_ADDR_T_INIT(randomness, rnd_out); -static const otbn_addr_t kVarUrndOut = OTBN_ADDR_T_INIT(randomness, urnd_out); - -/** - * LOG_INFO with a 256b unsigned integer as hexadecimal number with a prefix. - */ -static void print_uint256(dif_otbn_t *otbn, const otbn_addr_t var, - const char *prefix) { - uint32_t data[32 / sizeof(uint32_t)]; - CHECK_STATUS_OK(otbn_testutils_read_data(otbn, /*len_bytes=*/32, var, &data)); - LOG_INFO("%s0x%08x%08x%08x%08x%08x%08x%08x%08x", prefix, data[7], data[6], - data[5], data[4], data[3], data[2], data[1], data[0]); -} - -void otbn_randomness_test_start(dif_otbn_t *otbn, uint32_t iters) { - otbn_randomness_test_prepare(otbn, iters); - CHECK_STATUS_OK(otbn_testutils_execute(otbn)); -} - -void otbn_randomness_test_prepare(dif_otbn_t *otbn, uint32_t iters) { - // Reset the `kVarRv` value to ensure the result loaded by - // `otbn_randomness_test_end()` is the one generated by OTBN. - uint32_t rv = UINT32_MAX; - CHECK_STATUS_OK( - otbn_testutils_write_data(otbn, sizeof(uint32_t), &rv, kVarRv)); - CHECK_STATUS_OK(otbn_testutils_load_app(otbn, kOtbnAppRandomnessApp)); - CHECK_STATUS_OK( - otbn_testutils_write_data(otbn, sizeof(uint32_t), &iters, kVarIters)); -} - -bool otbn_randomness_test_end(dif_otbn_t *otbn, bool skip_otbn_done_check) { - if (!skip_otbn_done_check) { - CHECK_STATUS_OK(otbn_testutils_wait_for_done(otbn, kDifOtbnErrBitsNoError)); - } - uint32_t rv; - CHECK_STATUS_OK(otbn_testutils_read_data(otbn, /*len_bytes=*/4, kVarRv, &rv)); - if (rv != 0) { - uint32_t fail_idx; - CHECK_STATUS_OK(otbn_testutils_read_data(otbn, /*len_bytes=*/4, kVarFailIdx, - &fail_idx)); - LOG_ERROR("ERROR: Test with index %d failed.", fail_idx); - return false; - } - return true; -} - -void otbn_randomness_test_log_results(dif_otbn_t *otbn) { - print_uint256(otbn, kVarRndOut, "rnd = "); - print_uint256(otbn, kVarUrndOut, "urnd = "); -} diff --git a/sw/device/tests/otbn_randomness_impl.h b/sw/device/tests/otbn_randomness_impl.h deleted file mode 100644 index 4470fddae25..00000000000 --- a/sw/device/tests/otbn_randomness_impl.h +++ /dev/null @@ -1,58 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef OPENTITAN_SW_DEVICE_TESTS_OTBN_RANDOMNESS_IMPL_H_ -#define OPENTITAN_SW_DEVICE_TESTS_OTBN_RANDOMNESS_IMPL_H_ - -#include - -#include "sw/device/lib/dif/dif_otbn.h" - -/** - * Prepares the OTBN randomness test. - * - * Does the same as otbn_randomness_test_start() without - * executing the test. - * - * @param otbn A OTBN dif handle. - * @param iters The number of entropy requests to the RND CSR. - */ -void otbn_randomness_test_prepare(dif_otbn_t *otbn, uint32_t iters); - -/** - * Starts OTBN randomness test. - * - * Requires EDN0 and EDN1 to be serving entropy, as well as an initialized - * `otbn` runtime handle. A Randomness test is loaded into OTBN. Use the - * `otbn_randomness_test_end()` function to check the test status. This function - * is non-blocking. - * - * @param otbn A OTBN dif handle. - * @param iters The number of entropy requests to the RND CSR. - */ -void otbn_randomness_test_start(dif_otbn_t *otbn, uint32_t iters); - -/** - * Checks the OTBN randomness test result. - * - * This function must be called after `otbn_randomness_test_start()`. - * - * @param otbn A OTBN dif handle. - * @param skip_otbn_done_check Set to true to skip OTBN done execution check. - * The check is blocking. - * @returns true on test pass, false otherwise. - */ -bool otbn_randomness_test_end(dif_otbn_t *otbn, bool skip_otbn_done_check); - -/** - * Prints the randomness data generated by the test. - * - * This function must be called after OTBN is done executing the program loaded - * by the `otbn_randomness_test_start()` function. - * - * @param otbn A OTBN dif handle. - */ -void otbn_randomness_test_log_results(dif_otbn_t *otbn); - -#endif // OPENTITAN_SW_DEVICE_TESTS_OTBN_RANDOMNESS_IMPL_H_ diff --git a/sw/device/tests/otbn_smoketest.c b/sw/device/tests/otbn_smoketest.c deleted file mode 100644 index 91b08e2b53e..00000000000 --- a/sw/device/tests/otbn_smoketest.c +++ /dev/null @@ -1,166 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "hw/top/dt/dt_otbn.h" -#include "sw/device/lib/dif/dif_otbn.h" -#include "sw/device/lib/runtime/ibex.h" -#include "sw/device/lib/runtime/log.h" -#include "sw/device/lib/testing/entropy_testutils.h" -#include "sw/device/lib/testing/otbn_testutils.h" -#include "sw/device/lib/testing/test_framework/check.h" -#include "sw/device/lib/testing/test_framework/ottf_main.h" - -OTBN_DECLARE_APP_SYMBOLS(barrett384); -OTBN_DECLARE_SYMBOL_ADDR(barrett384, inp_a); -OTBN_DECLARE_SYMBOL_ADDR(barrett384, inp_b); -OTBN_DECLARE_SYMBOL_ADDR(barrett384, inp_m); -OTBN_DECLARE_SYMBOL_ADDR(barrett384, inp_u); -OTBN_DECLARE_SYMBOL_ADDR(barrett384, oup_c); - -static const otbn_app_t kAppBarrett = OTBN_APP_T_INIT(barrett384); -static const otbn_addr_t kInpA = OTBN_ADDR_T_INIT(barrett384, inp_a); -static const otbn_addr_t kInpB = OTBN_ADDR_T_INIT(barrett384, inp_b); -static const otbn_addr_t kInpM = OTBN_ADDR_T_INIT(barrett384, inp_m); -static const otbn_addr_t kInpU = OTBN_ADDR_T_INIT(barrett384, inp_u); -static const otbn_addr_t kOupC = OTBN_ADDR_T_INIT(barrett384, oup_c); - -OTBN_DECLARE_APP_SYMBOLS(err_test); - -static const otbn_app_t kAppErrTest = OTBN_APP_T_INIT(err_test); - -static_assert(kDtOtbnCount >= 1, - "This test requires at least one OTBN instance"); - -static dt_otbn_t kTestOtbn = (dt_otbn_t)0; - -OTTF_DEFINE_TEST_CONFIG(); - -/** - * Gets the OTBN instruction count, checks that it matches expectations. - */ -static void check_otbn_insn_cnt(dif_otbn_t *otbn, uint32_t expected_insn_cnt) { - uint32_t insn_cnt; - CHECK_DIF_OK(dif_otbn_get_insn_cnt(otbn, &insn_cnt)); - CHECK(insn_cnt == expected_insn_cnt, - "Expected to execute %d instructions, but got %d.", expected_insn_cnt, - insn_cnt); -} - -/** - * Run a 384-bit Barrett Multiplication on OTBN and check its result. - * - * This test is not aiming to exhaustively test the Barrett multiplication - * itself, but test the interaction between device software and OTBN. As such, - * only trivial parameters are used. - * - * The code executed on OTBN can be found in sw/otbn/code-snippets/barrett384.s. - * The entry point wrap_barrett384() is called according to the calling - * convention described in the OTBN assembly code file. - */ -static void test_barrett384(dif_otbn_t *otbn) { - enum { kDataSizeBytes = 48 }; - - CHECK_STATUS_OK(otbn_testutils_load_app(otbn, kAppBarrett)); - - // a, first operand - static const uint8_t a[kDataSizeBytes] = {10}; - - // b, second operand - static uint8_t b[kDataSizeBytes] = {20}; - - // m, modulus, max. length 384 bit with 2^384 > m > 2^383 - // We choose the modulus of P-384: m = 2**384 - 2**128 - 2**96 + 2**32 - 1 - static const uint8_t m[kDataSizeBytes] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}; - - // u, pre-computed Barrett constant (without u[384]/MSb of u which is always 1 - // for the allowed range but has to be set to 0 here). - // u has to be pre-calculated as u = floor(2^768/m). - static const uint8_t u[kDataSizeBytes] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01}; - - // c, result, max. length 384 bit. - uint8_t c[kDataSizeBytes] = {0}; - - // c = (a * b) % m = (10 * 20) % m = 200 - static const uint8_t c_expected[kDataSizeBytes] = {200}; - - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, sizeof(a), &a, kInpA)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, sizeof(b), &b, kInpB)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, sizeof(m), &m, kInpM)); - CHECK_STATUS_OK(otbn_testutils_write_data(otbn, sizeof(u), &u, kInpU)); - - CHECK_DIF_OK(dif_otbn_set_ctrl_software_errs_fatal(otbn, true)); - CHECK_STATUS_OK(otbn_testutils_execute(otbn)); - CHECK(dif_otbn_set_ctrl_software_errs_fatal(otbn, false) == kDifUnavailable); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(otbn, kDifOtbnErrBitsNoError)); - - // Reading back result (c). - CHECK_STATUS_OK(otbn_testutils_read_data(otbn, sizeof(c), kOupC, &c)); - - for (int i = 0; i < sizeof(c); ++i) { - CHECK(c[i] == c_expected[i], - "Unexpected result c at byte %d: 0x%x (actual) != 0x%x (expected)", i, - c[i], c_expected[i]); - } - - check_otbn_insn_cnt(otbn, 174); -} - -/** - * Run err_test on OTBN and check it produces the expected error - * - * This test tries to load from an invalid address which should result in the - * kDifOtbnErrBitsBadDataAddr error bit being set - * - * The code executed on OTBN can be found in sw/otbn/code-snippets/err_test.s. - * The entry point wrap_err_test() is called, no arguments are passed or results - * returned. - */ -static void test_err_test(dif_otbn_t *otbn) { - CHECK_STATUS_OK(otbn_testutils_load_app(otbn, kAppErrTest)); - - // TODO: Turn on software_errs_fatal for err_test. Currently the model doesn't - // support this feature so turning it on leads to a failure when run with the - // model. - CHECK_DIF_OK(dif_otbn_set_ctrl_software_errs_fatal(otbn, false)); - CHECK_STATUS_OK(otbn_testutils_execute(otbn)); - CHECK_STATUS_OK( - otbn_testutils_wait_for_done(otbn, kDifOtbnErrBitsBadDataAddr)); - - check_otbn_insn_cnt(otbn, 1); -} - -static void test_sec_wipe(dif_otbn_t *otbn) { - dif_otbn_status_t otbn_status; - - CHECK_DIF_OK(dif_otbn_write_cmd(otbn, kDifOtbnCmdSecWipeDmem)); - CHECK_DIF_OK(dif_otbn_get_status(otbn, &otbn_status)); - CHECK(otbn_status == kDifOtbnStatusBusySecWipeDmem); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(otbn, kDifOtbnErrBitsNoError)); - - CHECK_DIF_OK(dif_otbn_write_cmd(otbn, kDifOtbnCmdSecWipeImem)); - CHECK_DIF_OK(dif_otbn_get_status(otbn, &otbn_status)); - CHECK(otbn_status == kDifOtbnStatusBusySecWipeImem); - CHECK_STATUS_OK(otbn_testutils_wait_for_done(otbn, kDifOtbnErrBitsNoError)); -} - -bool test_main(void) { - CHECK_STATUS_OK(entropy_testutils_auto_mode_init()); - - dif_otbn_t otbn; - CHECK_DIF_OK(dif_otbn_init_from_dt(kTestOtbn, &otbn)); - - test_barrett384(&otbn); - test_sec_wipe(&otbn); - test_err_test(&otbn); - - return true; -} diff --git a/sw/device/tests/penetrationtests/BUILD b/sw/device/tests/penetrationtests/BUILD index 7c1a8f906b5..a2e3ded2ef3 100644 --- a/sw/device/tests/penetrationtests/BUILD +++ b/sw/device/tests/penetrationtests/BUILD @@ -2,7 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load(":pentest.bzl", "pentest_cryptolib_fi_asym", "pentest_cryptolib_fi_sym", "pentest_cryptolib_sca_asym", "pentest_cryptolib_sca_sym", "pentest_fi", "pentest_fi_ibex", "pentest_fi_otbn", "pentest_sca") +load(":pentest.bzl", "pentest_cryptolib_fi_asym", "pentest_cryptolib_fi_sym", "pentest_cryptolib_sca_asym", "pentest_cryptolib_sca_sym", "pentest_fi", "pentest_fi_acc", "pentest_fi_ibex", "pentest_sca") load("@ot_python_deps//:requirements.bzl", "requirement") package(default_visibility = ["//visibility:public"]) @@ -109,21 +109,21 @@ pentest_fi( test_vectors = ROM_FI_TESTVECTOR_TARGETS, ) -OTBN_FI_TESTVECTOR_TARGETS = [ - "//sw/host/penetrationtests/testvectors/data:fi_otbn", +ACC_FI_TESTVECTOR_TARGETS = [ + "//sw/host/penetrationtests/testvectors/data:fi_acc", ] -OTBN_FI_TESTVECTOR_ARGS = " ".join([ - "--fi-otbn-json=\"$(rootpath {})\"".format(target) - for target in OTBN_FI_TESTVECTOR_TARGETS +ACC_FI_TESTVECTOR_ARGS = " ".join([ + "--fi-acc-json=\"$(rootpath {})\"".format(target) + for target in ACC_FI_TESTVECTOR_TARGETS ]) -pentest_fi_otbn( - name = "fi_otbn", +pentest_fi_acc( + name = "fi_acc", tags = [], - test_args = OTBN_FI_TESTVECTOR_ARGS, - test_harness = "//sw/host/tests/penetrationtests/fi_otbn:harness", - test_vectors = OTBN_FI_TESTVECTOR_TARGETS, + test_args = ACC_FI_TESTVECTOR_ARGS, + test_harness = "//sw/host/tests/penetrationtests/fi_acc:harness", + test_vectors = ACC_FI_TESTVECTOR_TARGETS, ) AES_SCA_TESTVECTOR_TARGETS = [ @@ -211,21 +211,21 @@ pentest_sca( test_vectors = KMAC_SCA_TESTVECTOR_TARGETS, ) -OTBN_SCA_TESTVECTOR_TARGETS = [ - "//sw/host/penetrationtests/testvectors/data:sca_otbn", +ACC_SCA_TESTVECTOR_TARGETS = [ + "//sw/host/penetrationtests/testvectors/data:sca_acc", ] -OTBN_SCA_TESTVECTOR_ARGS = " ".join([ - "--sca-otbn-json=\"$(rootpath {})\"".format(target) - for target in OTBN_SCA_TESTVECTOR_TARGETS +ACC_SCA_TESTVECTOR_ARGS = " ".join([ + "--sca-acc-json=\"$(rootpath {})\"".format(target) + for target in ACC_SCA_TESTVECTOR_TARGETS ]) pentest_sca( - name = "sca_otbn", + name = "sca_acc", tags = [], - test_args = OTBN_SCA_TESTVECTOR_ARGS, - test_harness = "//sw/host/tests/penetrationtests/sca_otbn:harness", - test_vectors = OTBN_SCA_TESTVECTOR_TARGETS, + test_args = ACC_SCA_TESTVECTOR_ARGS, + test_harness = "//sw/host/tests/penetrationtests/sca_acc:harness", + test_vectors = ACC_SCA_TESTVECTOR_TARGETS, ) SHA3_SCA_TESTVECTOR_TARGETS = [ @@ -378,10 +378,10 @@ pentest_sca( ) pentest_sca( - name = "sca_otbn_python_test", + name = "sca_acc_python_test", tags = [], test_args = "", - test_harness = "//sw/host/penetrationtests/python/sca:sca_otbn_python_test", + test_harness = "//sw/host/penetrationtests/python/sca:sca_acc_python_test", test_vectors = [], ) @@ -409,11 +409,11 @@ pentest_fi( test_vectors = [], ) -pentest_fi_otbn( - name = "fi_otbn_python_test", +pentest_fi_acc( + name = "fi_acc_python_test", tags = [], test_args = "", - test_harness = "//sw/host/penetrationtests/python/fi:fi_otbn_python_test", + test_harness = "//sw/host/penetrationtests/python/fi:fi_acc_python_test", test_vectors = [], ) diff --git a/sw/device/tests/penetrationtests/doc/README.md b/sw/device/tests/penetrationtests/doc/README.md index 514e3a1f29e..42d67c15e71 100644 --- a/sw/device/tests/penetrationtests/doc/README.md +++ b/sw/device/tests/penetrationtests/doc/README.md @@ -17,7 +17,7 @@ When contributing to the pentest framework, run the automated testing as explain ### Building Images -Due to code size memory limitations, the firmware for the chip and the FPGA is split into a SCA, general FI, IBEX FI, and OTBN FI binary. To build these binaries for the chip, run: +Due to code size memory limitations, the firmware for the chip and the FPGA is split into a SCA, general FI, IBEX FI, and ACC FI binary. To build these binaries for the chip, run: ```console cd $REPO_TOP ./bazelisk.sh build \ @@ -34,7 +34,7 @@ cd $REPO_TOP ./bazelisk.sh build \ --//signing:token=//signing/tokens:cloud_kms_sival \ - //sw/device/tests/penetrationtests/firmware:pen_test_fi_otbn_silicon_owner_sival_rom_ext + //sw/device/tests/penetrationtests/firmware:pen_test_fi_acc_silicon_owner_sival_rom_ext ./bazelisk.sh build \ --//signing:token=//signing/tokens:cloud_kms_sival \ diff --git a/sw/device/tests/penetrationtests/firmware/BUILD b/sw/device/tests/penetrationtests/firmware/BUILD index 914d070e29e..b27ea238191 100644 --- a/sw/device/tests/penetrationtests/firmware/BUILD +++ b/sw/device/tests/penetrationtests/firmware/BUILD @@ -63,8 +63,8 @@ FIRMWARE_DEPS_FI_IBEX = [ "//sw/device/tests/penetrationtests/json:commands", ] -FIRMWARE_DEPS_FI_OTBN = [ - "//sw/device/tests/penetrationtests/firmware/fi:otbn_fi", +FIRMWARE_DEPS_FI_ACC = [ + "//sw/device/tests/penetrationtests/firmware/fi:acc_fi", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", "//sw/device/lib/base:csr", "//sw/device/lib/base:status", @@ -84,7 +84,7 @@ FIRMWARE_DEPS_SCA = [ "//sw/device/tests/penetrationtests/firmware/sca:hmac_sca", "//sw/device/tests/penetrationtests/firmware/sca:ibex_sca", "//sw/device/tests/penetrationtests/firmware/sca:kmac_sca", - "//sw/device/tests/penetrationtests/firmware/sca:otbn_sca", + "//sw/device/tests/penetrationtests/firmware/sca:acc_sca", "//sw/device/tests/penetrationtests/firmware/sca:prng_sca", "//sw/device/tests/penetrationtests/firmware/sca:sha3_sca", "//sw/device/tests/penetrationtests/firmware/sca:trigger_sca", @@ -212,8 +212,8 @@ opentitan_test( # Not an actual test, only for building purposes opentitan_test( - name = "pen_test_fi_otbn", - srcs = [":firmware_fi_otbn.c"], + name = "pen_test_fi_acc", + srcs = [":firmware_fi_acc.c"], exec_env = PENTEST_EXEC_ENVS, # Tags are manual since these are not actually tests, but these create binaries to run the pentest framework fpga = fpga_params(tags = [ @@ -226,7 +226,7 @@ opentitan_test( "skip_in_ci", ], ), - deps = FIRMWARE_DEPS_FI_OTBN, + deps = FIRMWARE_DEPS_FI_ACC, ) # Not an actual test, only for building purposes diff --git a/sw/device/tests/penetrationtests/firmware/fi/BUILD b/sw/device/tests/penetrationtests/firmware/fi/BUILD index 5ab1c1d86bc..298b6fd9239 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/BUILD +++ b/sw/device/tests/penetrationtests/firmware/fi/BUILD @@ -176,40 +176,40 @@ cc_library( ) cc_library( - name = "otbn_fi", - srcs = ["otbn_fi.c"], - hdrs = ["otbn_fi.h"], + name = "acc_fi", + srcs = ["acc_fi.c"], + hdrs = ["acc_fi.h"], deps = [ "//sw/device/lib/base:memory", "//sw/device/lib/base:status", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/crypto/drivers:keymgr", - "//sw/device/lib/crypto/drivers:otbn", - "//sw/device/lib/dif:otbn", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:rv_core_ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:entropy_testutils", "//sw/device/lib/testing:keymgr_testutils", "//sw/device/lib/testing/test_framework:ujson_ottf", "//sw/device/lib/ujson", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_beq", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_bn_rshi", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_bn_sel", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_bn_wsrr", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_bne", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_dmem_access", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_dmem_write", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_hardware_dmem_op_loop", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_hardware_reg_op_loop", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_jal", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_lw", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_rf", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_unrolled_dmem_op_loop", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_char_unrolled_reg_op_loop", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_key_sideload", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_load_integrity", - "//sw/device/tests/penetrationtests/firmware/fi/otbn:otbn_pc", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_beq", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_bn_rshi", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_bn_sel", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_bn_wsrr", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_bne", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_dmem_access", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_dmem_write", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_hardware_dmem_op_loop", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_hardware_reg_op_loop", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_jal", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_lw", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_rf", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_unrolled_dmem_op_loop", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_char_unrolled_reg_op_loop", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_key_sideload", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_load_integrity", + "//sw/device/tests/penetrationtests/firmware/fi/acc:acc_pc", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/device/tests/penetrationtests/json:otbn_fi_commands", + "//sw/device/tests/penetrationtests/json:acc_fi_commands", ], ) @@ -283,6 +283,7 @@ cc_library( "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:memory", "//sw/device/lib/base:status", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:adc_ctrl", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:alert_handler", @@ -296,7 +297,6 @@ cc_library( "//sw/device/lib/dif:i2c", "//sw/device/lib/dif:keymgr", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pattgen", "//sw/device/lib/dif:pwm", diff --git a/sw/device/tests/penetrationtests/firmware/fi/acc/BUILD b/sw/device/tests/penetrationtests/firmware/fi/acc/BUILD new file mode 100644 index 00000000000..f3d07c2bc76 --- /dev/null +++ b/sw/device/tests/penetrationtests/firmware/fi/acc/BUILD @@ -0,0 +1,126 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +load("//rules:acc.bzl", "acc_binary") + +package(default_visibility = ["//visibility:public"]) + +acc_binary( + name = "acc_char_beq", + srcs = [ + "acc_char_beq.s", + ], +) + +acc_binary( + name = "acc_char_bn_rshi", + srcs = [ + "acc_char_bn_rshi.s", + ], +) + +acc_binary( + name = "acc_char_bn_sel", + srcs = [ + "acc_char_bn_sel.s", + ], +) + +acc_binary( + name = "acc_char_bn_wsrr", + srcs = [ + "acc_char_bn_wsrr.s", + ], +) + +acc_binary( + name = "acc_char_bne", + srcs = [ + "acc_char_bne.s", + ], +) + +acc_binary( + name = "acc_char_dmem_access", + srcs = [ + "acc_char_dmem_access.s", + ], +) + +acc_binary( + name = "acc_char_dmem_write", + srcs = [ + "acc_char_dmem_write.s", + ], +) + +acc_binary( + name = "acc_char_hardware_dmem_op_loop", + srcs = [ + "acc_char_hardware_dmem_op_loop.s", + ], +) + +acc_binary( + name = "acc_char_hardware_reg_op_loop", + srcs = [ + "acc_char_hardware_reg_op_loop.s", + ], +) + +acc_binary( + name = "acc_char_jal", + srcs = [ + "acc_char_jal.s", + ], +) + +acc_binary( + name = "acc_char_lw", + srcs = [ + "acc_char_lw.s", + ], +) + +acc_binary( + name = "acc_char_rf", + srcs = [ + "acc_char_rf.s", + ], +) + +acc_binary( + name = "acc_char_unrolled_dmem_op_loop", + srcs = [ + "acc_char_unrolled_dmem_op_loop.s", + ], +) + +acc_binary( + name = "acc_char_unrolled_reg_op_loop", + srcs = [ + "acc_char_unrolled_reg_op_loop.s", + ], +) + +acc_binary( + name = "acc_key_sideload", + srcs = [ + "acc_key_sideload.s", + ], +) + +acc_binary( + name = "acc_load_integrity", + srcs = [ + "acc_load_integrity.s", + ], +) + +acc_binary( + name = "acc_pc", + srcs = [ + "acc_pc.s", + ], +) diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_beq.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_beq.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_beq.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_beq.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bn_rshi.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bn_rshi.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bn_rshi.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bn_rshi.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bn_sel.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bn_sel.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bn_sel.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bn_sel.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bn_wsrr.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bn_wsrr.s similarity index 96% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bn_wsrr.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bn_wsrr.s index dd4d1b83e88..d7139e60d86 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bn_wsrr.s +++ b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bn_wsrr.s @@ -46,7 +46,7 @@ nop /* Read WDR RF into DMEM. */ - la x31, otbn_res_values_wdr + la x31, acc_res_values_wdr li x1, 0 bn.sid x1++, 0x000(x31) bn.sid x1++, 0x020(x31) @@ -85,6 +85,6 @@ .data .balign 32 - .globl otbn_res_values_wdr - otbn_res_values_wdr: + .globl acc_res_values_wdr + acc_res_values_wdr: .zero 1024 diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bne.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bne.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_bne.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_bne.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_dmem_access.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_dmem_access.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_dmem_access.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_dmem_access.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_dmem_write.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_dmem_write.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_dmem_write.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_dmem_write.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_hardware_dmem_op_loop.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_hardware_dmem_op_loop.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_hardware_dmem_op_loop.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_hardware_dmem_op_loop.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_hardware_reg_op_loop.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_hardware_reg_op_loop.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_hardware_reg_op_loop.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_hardware_reg_op_loop.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_jal.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_jal.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_jal.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_jal.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_lw.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_lw.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_lw.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_lw.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_rf.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_rf.s similarity index 93% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_rf.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_rf.s index 92e5c3401c7..86d919fed15 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_rf.s +++ b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_rf.s @@ -6,7 +6,7 @@ */ .section .text.start /* Init GPR RF. */ - la x31, otbn_ref_values + la x31, acc_ref_values lw x2, 0(x31) lw x3, 4(x31) lw x4, 8(x31) @@ -79,7 +79,7 @@ nop /* Read GPR RF into DMEM. */ - la x31, otbn_res_values_gpr + la x31, acc_res_values_gpr sw x2, 0(x31) sw x3, 4(x31) sw x4, 8(x31) @@ -111,7 +111,7 @@ sw x30, 112(x31) /* Read WDR RF into DMEM. */ - la x31, otbn_res_values_wdr + la x31, acc_res_values_wdr li x1, 0 bn.sid x1++, 0x000(x31) bn.sid x1++, 0x020(x31) @@ -150,16 +150,16 @@ .data .balign 32 - .globl otbn_ref_values - otbn_ref_values: + .globl acc_ref_values + acc_ref_values: .zero 128 .balign 32 - .globl otbn_res_values_gpr - otbn_res_values_gpr: + .globl acc_res_values_gpr + acc_res_values_gpr: .zero 128 .balign 32 - .globl otbn_res_values_wdr - otbn_res_values_wdr: + .globl acc_res_values_wdr + acc_res_values_wdr: .zero 1024 diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_unrolled_dmem_op_loop.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_unrolled_dmem_op_loop.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_unrolled_dmem_op_loop.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_unrolled_dmem_op_loop.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_unrolled_reg_op_loop.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_unrolled_reg_op_loop.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_char_unrolled_reg_op_loop.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_char_unrolled_reg_op_loop.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_key_sideload.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_key_sideload.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_key_sideload.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_key_sideload.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_load_integrity.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_load_integrity.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_load_integrity.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_load_integrity.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_pc.s b/sw/device/tests/penetrationtests/firmware/fi/acc/acc_pc.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/fi/otbn/otbn_pc.s rename to sw/device/tests/penetrationtests/firmware/fi/acc/acc_pc.s diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn_fi.c b/sw/device/tests/penetrationtests/firmware/fi/acc_fi.c similarity index 52% rename from sw/device/tests/penetrationtests/firmware/fi/otbn_fi.c rename to sw/device/tests/penetrationtests/firmware/fi/acc_fi.c index 89f41be83cc..2c53207bde0 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/otbn_fi.c +++ b/sw/device/tests/penetrationtests/firmware/fi/acc_fi.c @@ -2,13 +2,13 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/tests/penetrationtests/firmware/fi/otbn_fi.h" +#include "sw/device/tests/penetrationtests/firmware/fi/acc_fi.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/status.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/crypto/drivers/keymgr.h" -#include "sw/device/lib/crypto/drivers/otbn.h" -#include "sw/device/lib/dif/dif_otbn.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_rv_core_ibex.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/entropy_testutils.h" @@ -17,15 +17,15 @@ #include "sw/device/lib/testing/test_framework/ujson_ottf.h" #include "sw/device/lib/ujson/ujson.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "sw/device/tests/penetrationtests/json/otbn_fi_commands.h" +#include "sw/device/tests/penetrationtests/json/acc_fi_commands.h" -#include "hw/top/otbn_regs.h" +#include "hw/top/acc_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Interface to Ibex. static dif_rv_core_ibex_t rv_core_ibex; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_keymgr_t keymgr; // Indicates whether the load_integrity test is already initialized. @@ -36,41 +36,41 @@ static bool char_mem_init; static bool char_mem_test_cfg_valid; // Reference checksum for the load integrity test. static uint32_t load_checksum_ref; -// Load integrity test. Initialize OTBN app, load it, and get interface to -// OTBN data memory. -OTBN_DECLARE_APP_SYMBOLS(otbn_load_integrity); -OTBN_DECLARE_SYMBOL_ADDR(otbn_load_integrity, refval1); -OTBN_DECLARE_SYMBOL_ADDR(otbn_load_integrity, refval2); -OTBN_DECLARE_SYMBOL_ADDR(otbn_load_integrity, refval3); -static const otbn_app_t kOtbnAppLoadIntegrity = - OTBN_APP_T_INIT(otbn_load_integrity); -static const otbn_addr_t kOtbnAppLoadIntegrityRefVal1 = - OTBN_ADDR_T_INIT(otbn_load_integrity, refval1); -static const otbn_addr_t kOtbnAppLoadIntegrityRefVal2 = - OTBN_ADDR_T_INIT(otbn_load_integrity, refval2); -static const otbn_addr_t kOtbnAppLoadIntegrityRefVal3 = - OTBN_ADDR_T_INIT(otbn_load_integrity, refval3); +// Load integrity test. Initialize ACC app, load it, and get interface to +// ACC data memory. +ACC_DECLARE_APP_SYMBOLS(acc_load_integrity); +ACC_DECLARE_SYMBOL_ADDR(acc_load_integrity, refval1); +ACC_DECLARE_SYMBOL_ADDR(acc_load_integrity, refval2); +ACC_DECLARE_SYMBOL_ADDR(acc_load_integrity, refval3); +static const acc_app_t kAccAppLoadIntegrity = + ACC_APP_T_INIT(acc_load_integrity); +static const acc_addr_t kAccAppLoadIntegrityRefVal1 = + ACC_ADDR_T_INIT(acc_load_integrity, refval1); +static const acc_addr_t kAccAppLoadIntegrityRefVal2 = + ACC_ADDR_T_INIT(acc_load_integrity, refval2); +static const acc_addr_t kAccAppLoadIntegrityRefVal3 = + ACC_ADDR_T_INIT(acc_load_integrity, refval3); // Indicates whether the key sideloading test is already initialized. static bool key_sideloading_init; -// Key sideloading test. Initialize OTBN app, load it, and get interface to -// OTBN data memory. -OTBN_DECLARE_APP_SYMBOLS(otbn_key_sideload); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload, k_s0_l); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload, k_s0_h); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload, k_s1_l); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload, k_s1_h); -const otbn_app_t kOtbnAppKeySideload = OTBN_APP_T_INIT(otbn_key_sideload); -static const otbn_addr_t kOtbnAppKeySideloadks0l = - OTBN_ADDR_T_INIT(otbn_key_sideload, k_s0_l); -static const otbn_addr_t kOtbnAppKeySideloadks0h = - OTBN_ADDR_T_INIT(otbn_key_sideload, k_s0_h); -static const otbn_addr_t kOtbnAppKeySideloadks1l = - OTBN_ADDR_T_INIT(otbn_key_sideload, k_s1_l); -static const otbn_addr_t kOtbnAppKeySideloadks1h = - OTBN_ADDR_T_INIT(otbn_key_sideload, k_s1_h); - -// Config for the otbn.fi.char_mem test. +// Key sideloading test. Initialize ACC app, load it, and get interface to +// ACC data memory. +ACC_DECLARE_APP_SYMBOLS(acc_key_sideload); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload, k_s0_l); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload, k_s0_h); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload, k_s1_l); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload, k_s1_h); +const acc_app_t kAccAppKeySideload = ACC_APP_T_INIT(acc_key_sideload); +static const acc_addr_t kAccAppKeySideloadks0l = + ACC_ADDR_T_INIT(acc_key_sideload, k_s0_l); +static const acc_addr_t kAccAppKeySideloadks0h = + ACC_ADDR_T_INIT(acc_key_sideload, k_s0_h); +static const acc_addr_t kAccAppKeySideloadks1l = + ACC_ADDR_T_INIT(acc_key_sideload, k_s1_l); +static const acc_addr_t kAccAppKeySideloadks1h = + ACC_ADDR_T_INIT(acc_key_sideload, k_s1_h); + +// Config for the acc.fi.char_mem test. static bool char_mem_imem; static bool char_mem_dmem; static uint32_t char_mem_byte_offset; @@ -88,7 +88,7 @@ static const uint32_t ref_values[32] = { 0xDEADDEAD, 0xD00D2BAD, 0xEBEBEBEB, 0xFADEDEAD, 0xFDFDFDFD, 0xFEE1DEAD, 0xFEEDFACE, 0xFEEEFEEE}; -static const dif_keymgr_versioned_key_params_t kKeyVersionedParamsOTBNFI = { +static const dif_keymgr_versioned_key_params_t kKeyVersionedParamsACCFI = { .dest = kDifKeymgrVersionedKeyDestSw, .salt = // the salt doesn't really matter here. { @@ -105,249 +105,249 @@ static const dif_keymgr_versioned_key_params_t kKeyVersionedParamsOTBNFI = { }; /** - * Clears the OTBN DMEM and IMEM. + * Clears the ACC DMEM and IMEM. * * @returns OK or error. */ -static status_t clear_otbn(void) { - // Clear OTBN memory. - TRY(otbn_dmem_sec_wipe()); - TRY(otbn_imem_sec_wipe()); +static status_t clear_acc(void) { + // Clear ACC memory. + TRY(acc_dmem_sec_wipe()); + TRY(acc_imem_sec_wipe()); return OK_STATUS(); } /** - * Read the error bits of the OTBN accelerator. + * Read the error bits of the ACC accelerator. * * @returns Error bits. */ -status_t read_otbn_err_bits(dif_otbn_err_bits_t *err_otbn) { - TRY(dif_otbn_get_err_bits(&otbn, err_otbn)); +status_t read_acc_err_bits(dif_acc_err_bits_t *err_acc) { + TRY(dif_acc_get_err_bits(&acc, err_acc)); return OK_STATUS(); } /** - * Read the OTBN load checksum. + * Read the ACC load checksum. * * @returns Load checksum. */ -status_t read_otbn_load_checksum(uint32_t *checksum) { - TRY(dif_otbn_get_load_checksum(&otbn, checksum)); +status_t read_acc_load_checksum(uint32_t *checksum) { + TRY(dif_acc_get_load_checksum(&acc, checksum)); return OK_STATUS(); } /** - * Clear the OTBN load checksum. + * Clear the ACC load checksum. */ -status_t clear_otbn_load_checksum(void) { - TRY(dif_otbn_clear_load_checksum(&otbn)); +status_t clear_acc_load_checksum(void) { + TRY(dif_acc_clear_load_checksum(&acc)); return OK_STATUS(); } -status_t handle_otbn_fi_char_beq(ujson_t *uj) { +status_t handle_acc_fi_char_beq(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_beq); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_beq, res); - const otbn_app_t kOtbnAppCharBeq = OTBN_APP_T_INIT(otbn_char_beq); - static const otbn_addr_t kOtbnAppCharBeqRes = - OTBN_ADDR_T_INIT(otbn_char_beq, res); - TRY(otbn_load_app(kOtbnAppCharBeq)); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_beq); + ACC_DECLARE_SYMBOL_ADDR(acc_char_beq, res); + const acc_app_t kAccAppCharBeq = ACC_APP_T_INIT(acc_char_beq); + static const acc_addr_t kAccAppCharBeqRes = + ACC_ADDR_T_INIT(acc_char_beq, res); + TRY(acc_load_app(kAccAppCharBeq)); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read counter (x1) from OTBN data memory. - otbn_fi_result_cnt_t uj_output; + // Read counter (x1) from ACC data memory. + acc_fi_result_cnt_t uj_output; uj_output.result = 0; - TRY(otbn_dmem_read(1, kOtbnAppCharBeqRes, &uj_output.result)); + TRY(acc_dmem_read(1, kAccAppCharBeqRes, &uj_output.result)); - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send back to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_result_cnt_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_result_cnt_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_bn_rshi(ujson_t *uj) { +status_t handle_acc_fi_char_bn_rshi(ujson_t *uj) { // Get big number (2x256 bit). - otbn_fi_big_num_t uj_data; - TRY(ujson_deserialize_otbn_fi_big_num_t(uj, &uj_data)); + acc_fi_big_num_t uj_data; + TRY(ujson_deserialize_acc_fi_big_num_t(uj, &uj_data)); // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_bn_rshi); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_bn_rshi, big_num); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_bn_rshi, big_num_out); - const otbn_app_t kOtbnAppCharBnRshi = OTBN_APP_T_INIT(otbn_char_bn_rshi); - static const otbn_addr_t kOtbnAppCharBnRshiBigNum = - OTBN_ADDR_T_INIT(otbn_char_bn_rshi, big_num); - static const otbn_addr_t kOtbnAppCharBnRshiBigNumOut = - OTBN_ADDR_T_INIT(otbn_char_bn_rshi, big_num_out); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_bn_rshi); + ACC_DECLARE_SYMBOL_ADDR(acc_char_bn_rshi, big_num); + ACC_DECLARE_SYMBOL_ADDR(acc_char_bn_rshi, big_num_out); + const acc_app_t kAccAppCharBnRshi = ACC_APP_T_INIT(acc_char_bn_rshi); + static const acc_addr_t kAccAppCharBnRshiBigNum = + ACC_ADDR_T_INIT(acc_char_bn_rshi, big_num); + static const acc_addr_t kAccAppCharBnRshiBigNumOut = + ACC_ADDR_T_INIT(acc_char_bn_rshi, big_num_out); // Load app and write received big_num into DMEM. - TRY(otbn_load_app(kOtbnAppCharBnRshi)); - TRY(dif_otbn_dmem_write(&otbn, kOtbnAppCharBnRshiBigNum, uj_data.big_num, - sizeof(uj_data.big_num))); + TRY(acc_load_app(kAccAppCharBnRshi)); + TRY(dif_acc_dmem_write(&acc, kAccAppCharBnRshiBigNum, uj_data.big_num, + sizeof(uj_data.big_num))); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read big_num_out from OTBN data memory. - otbn_fi_big_num_out_t uj_output; + // Read big_num_out from ACC data memory. + acc_fi_big_num_out_t uj_output; memset(uj_output.big_num, 0, sizeof(uj_output.big_num)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnAppCharBnRshiBigNumOut, uj_output.big_num, - sizeof(uj_output.big_num))); + TRY(dif_acc_dmem_read(&acc, kAccAppCharBnRshiBigNumOut, uj_output.big_num, + sizeof(uj_output.big_num))); - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send back to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_big_num_out_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_big_num_out_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_bn_sel(ujson_t *uj) { +status_t handle_acc_fi_char_bn_sel(ujson_t *uj) { // Get big number (2x256 bit). - otbn_fi_big_num_t uj_data; - TRY(ujson_deserialize_otbn_fi_big_num_t(uj, &uj_data)); + acc_fi_big_num_t uj_data; + TRY(ujson_deserialize_acc_fi_big_num_t(uj, &uj_data)); // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_bn_sel); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_bn_sel, big_num); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_bn_sel, big_num_out); - const otbn_app_t kOtbnAppCharBnSel = OTBN_APP_T_INIT(otbn_char_bn_sel); - static const otbn_addr_t kOtbnAppCharBnSelBigNum = - OTBN_ADDR_T_INIT(otbn_char_bn_sel, big_num); - static const otbn_addr_t kOtbnAppCharBnSelBigNumOut = - OTBN_ADDR_T_INIT(otbn_char_bn_sel, big_num_out); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_bn_sel); + ACC_DECLARE_SYMBOL_ADDR(acc_char_bn_sel, big_num); + ACC_DECLARE_SYMBOL_ADDR(acc_char_bn_sel, big_num_out); + const acc_app_t kAccAppCharBnSel = ACC_APP_T_INIT(acc_char_bn_sel); + static const acc_addr_t kAccAppCharBnSelBigNum = + ACC_ADDR_T_INIT(acc_char_bn_sel, big_num); + static const acc_addr_t kAccAppCharBnSelBigNumOut = + ACC_ADDR_T_INIT(acc_char_bn_sel, big_num_out); // Load app and write received big_num into DMEM. - TRY(otbn_load_app(kOtbnAppCharBnSel)); - TRY(dif_otbn_dmem_write(&otbn, kOtbnAppCharBnSelBigNum, uj_data.big_num, - sizeof(uj_data.big_num))); + TRY(acc_load_app(kAccAppCharBnSel)); + TRY(dif_acc_dmem_write(&acc, kAccAppCharBnSelBigNum, uj_data.big_num, + sizeof(uj_data.big_num))); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read big_num_out from OTBN data memory. - otbn_fi_big_num_out_t uj_output; + // Read big_num_out from ACC data memory. + acc_fi_big_num_out_t uj_output; memset(uj_output.big_num, 0, sizeof(uj_output.big_num)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnAppCharBnSelBigNumOut, uj_output.big_num, - sizeof(uj_output.big_num))); + TRY(dif_acc_dmem_read(&acc, kAccAppCharBnSelBigNumOut, uj_output.big_num, + sizeof(uj_output.big_num))); - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send back to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_big_num_out_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_big_num_out_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_bn_wsrr(ujson_t *uj) { +status_t handle_acc_fi_char_bn_wsrr(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_bn_wsrr); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_bn_wsrr, otbn_res_values_wdr); - const otbn_app_t kOtbnAppCharBnWsrr = OTBN_APP_T_INIT(otbn_char_bn_wsrr); - static const otbn_addr_t kOtbnAppCharBnWsrrResValuesWDR = - OTBN_ADDR_T_INIT(otbn_char_bn_wsrr, otbn_res_values_wdr); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_bn_wsrr); + ACC_DECLARE_SYMBOL_ADDR(acc_char_bn_wsrr, acc_res_values_wdr); + const acc_app_t kAccAppCharBnWsrr = ACC_APP_T_INIT(acc_char_bn_wsrr); + static const acc_addr_t kAccAppCharBnWsrrResValuesWDR = + ACC_ADDR_T_INIT(acc_char_bn_wsrr, acc_res_values_wdr); // Load app and write received big_num into DMEM. - TRY(otbn_load_app(kOtbnAppCharBnWsrr)); + TRY(acc_load_app(kAccAppCharBnWsrr)); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. @@ -355,109 +355,109 @@ status_t handle_otbn_fi_char_bn_wsrr(ujson_t *uj) { // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); // Read DMEM - otbn_fi_data_t uj_output; + acc_fi_data_t uj_output; uj_output.res = 0; memset(uj_output.data, 0, sizeof(uj_output.data)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnAppCharBnWsrrResValuesWDR, uj_output.data, - sizeof(uj_output.data))); - // Read OTBN instruction counter - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + TRY(dif_acc_dmem_read(&acc, kAccAppCharBnWsrrResValuesWDR, uj_output.data, + sizeof(uj_output.data))); + // Read ACC instruction counter + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send result & ERR_STATUS to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_data_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_data_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_bne(ujson_t *uj) { +status_t handle_acc_fi_char_bne(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_bne); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_bne, res); - const otbn_app_t kOtbnAppCharBne = OTBN_APP_T_INIT(otbn_char_bne); - static const otbn_addr_t kOtbnAppCharBneRes = - OTBN_ADDR_T_INIT(otbn_char_bne, res); - TRY(otbn_load_app(kOtbnAppCharBne)); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_bne); + ACC_DECLARE_SYMBOL_ADDR(acc_char_bne, res); + const acc_app_t kAccAppCharBne = ACC_APP_T_INIT(acc_char_bne); + static const acc_addr_t kAccAppCharBneRes = + ACC_ADDR_T_INIT(acc_char_bne, res); + TRY(acc_load_app(kAccAppCharBne)); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read counter (x1) from OTBN data memory. - otbn_fi_result_cnt_t uj_output; + // Read counter (x1) from ACC data memory. + acc_fi_result_cnt_t uj_output; uj_output.result = 0; - TRY(otbn_dmem_read(1, kOtbnAppCharBneRes, &uj_output.result)); + TRY(acc_dmem_read(1, kAccAppCharBneRes, &uj_output.result)); - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send back to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_result_cnt_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_result_cnt_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_dmem_access(ujson_t *uj) { +status_t handle_acc_fi_char_dmem_access(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Config for the otbn.fi.char_dmem_access test. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_dmem_access); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_dmem_access, values); - static const otbn_app_t kOtbnAppCharDmemAccess = - OTBN_APP_T_INIT(otbn_char_dmem_access); - static const otbn_addr_t kOtbnVarCharDmemAccessValues = - OTBN_ADDR_T_INIT(otbn_char_dmem_access, values); + // Config for the acc.fi.char_dmem_access test. + ACC_DECLARE_APP_SYMBOLS(acc_char_dmem_access); + ACC_DECLARE_SYMBOL_ADDR(acc_char_dmem_access, values); + static const acc_app_t kAccAppCharDmemAccess = + ACC_APP_T_INIT(acc_char_dmem_access); + static const acc_addr_t kAccVarCharDmemAccessValues = + ACC_ADDR_T_INIT(acc_char_dmem_access, values); - TRY(otbn_load_app(kOtbnAppCharDmemAccess)); + TRY(acc_load_app(kAccAppCharDmemAccess)); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. @@ -465,412 +465,410 @@ status_t handle_otbn_fi_char_dmem_access(ujson_t *uj) { // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); // Read DMEM - otbn_fi_data_t uj_output; + acc_fi_data_t uj_output; uj_output.res = 0; memset(uj_output.data, 0, sizeof(uj_output.data)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarCharDmemAccessValues, uj_output.data, - sizeof(uj_output.data))); - // Read OTBN instruction counter - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + TRY(dif_acc_dmem_read(&acc, kAccVarCharDmemAccessValues, uj_output.data, + sizeof(uj_output.data))); + // Read ACC instruction counter + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); // Send result & ERR_STATUS to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_data_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_data_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_dmem_write(ujson_t *uj) { +status_t handle_acc_fi_char_dmem_write(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Config for the otbn.fi.char_rf test. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_dmem_write); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_dmem_write, mem); + // Config for the acc.fi.char_rf test. + ACC_DECLARE_APP_SYMBOLS(acc_char_dmem_write); + ACC_DECLARE_SYMBOL_ADDR(acc_char_dmem_write, mem); - static const otbn_app_t kOtbnAppCharDmemWrite = - OTBN_APP_T_INIT(otbn_char_dmem_write); - static const otbn_addr_t kOtbnVarCharDmemWriteMem = - OTBN_ADDR_T_INIT(otbn_char_dmem_write, mem); + static const acc_app_t kAccAppCharDmemWrite = + ACC_APP_T_INIT(acc_char_dmem_write); + static const acc_addr_t kAccVarCharDmemWriteMem = + ACC_ADDR_T_INIT(acc_char_dmem_write, mem); // Init application and load reference values into DMEM. - TRY(otbn_load_app(kOtbnAppCharDmemWrite)); + TRY(acc_load_app(kAccAppCharDmemWrite)); // FI code target. pentest_set_trigger_high(); asm volatile(NOP30); // Unrolled instruction sequence. mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem), + acc.base_addr, (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem), ref_values[0]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 4), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 4), ref_values[1]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 8), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 8), ref_values[2]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 12), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 12), ref_values[3]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 16), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 16), ref_values[4]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 20), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 20), ref_values[5]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 24), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 24), ref_values[6]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 28), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 28), ref_values[7]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 32), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 32), ref_values[8]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 36), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 36), ref_values[9]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 40), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 40), ref_values[10]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 44), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 44), ref_values[11]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 48), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 48), ref_values[12]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 52), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 52), ref_values[13]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 56), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 56), ref_values[14]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 60), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 60), ref_values[15]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 64), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 64), ref_values[16]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 68), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 68), ref_values[17]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 72), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 72), ref_values[18]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 76), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 76), ref_values[19]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 80), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 80), ref_values[20]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 84), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 84), ref_values[21]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 88), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 88), ref_values[22]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 92), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 92), ref_values[23]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 96), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 96), ref_values[24]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 100), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 100), ref_values[25]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 104), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 104), ref_values[26]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 108), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 108), ref_values[27]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 112), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 112), ref_values[28]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 116), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 116), ref_values[29]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 120), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 120), ref_values[30]); mmio_region_write32( - otbn.base_addr, - (ptrdiff_t)(OTBN_DMEM_REG_OFFSET + kOtbnVarCharDmemWriteMem + 124), + acc.base_addr, + (ptrdiff_t)(ACC_DMEM_REG_OFFSET + kAccVarCharDmemWriteMem + 124), ref_values[31]); asm volatile(NOP10); pentest_set_trigger_low(); - // Execute OTBN application. - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + // Execute ACC application. + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); // Compare reference values. - otbn_fi_result_array_t uj_output; + acc_fi_result_array_t uj_output; uint32_t res_values[ARRAYSIZE(ref_values)]; memset(res_values, 0, sizeof(res_values)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarCharDmemWriteMem, res_values, - sizeof(res_values))); + TRY(dif_acc_dmem_read(&acc, kAccVarCharDmemWriteMem, res_values, + sizeof(res_values))); for (size_t it = 0; it < ARRAYSIZE(ref_values); it++) { uj_output.result[it] = res_values[it] ^ ref_values[it]; } - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send result & ERR_STATUS to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_result_array_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_result_array_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_hardware_dmem_op_loop(ujson_t *uj) { +status_t handle_acc_fi_char_hardware_dmem_op_loop(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_hardware_dmem_op_loop); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_hardware_dmem_op_loop, lc); - const otbn_app_t kOtbnAppCharHardwareDmemOpLoop = - OTBN_APP_T_INIT(otbn_char_hardware_dmem_op_loop); - static const otbn_addr_t kOtbnAppCharHardwareDmemOpLoopLC = - OTBN_ADDR_T_INIT(otbn_char_hardware_dmem_op_loop, lc); - TRY(otbn_load_app(kOtbnAppCharHardwareDmemOpLoop)); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_hardware_dmem_op_loop); + ACC_DECLARE_SYMBOL_ADDR(acc_char_hardware_dmem_op_loop, lc); + const acc_app_t kAccAppCharHardwareDmemOpLoop = + ACC_APP_T_INIT(acc_char_hardware_dmem_op_loop); + static const acc_addr_t kAccAppCharHardwareDmemOpLoopLC = + ACC_ADDR_T_INIT(acc_char_hardware_dmem_op_loop, lc); + TRY(acc_load_app(kAccAppCharHardwareDmemOpLoop)); uint32_t loop_counter; // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read loop counter from OTBN data memory. - TRY(otbn_dmem_read(1, kOtbnAppCharHardwareDmemOpLoopLC, &loop_counter)); + // Read loop counter from ACC data memory. + TRY(acc_dmem_read(1, kAccAppCharHardwareDmemOpLoopLC, &loop_counter)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send loop counter & ERR_STATUS to host. - otbn_fi_loop_counter_t uj_output; + acc_fi_loop_counter_t uj_output; uj_output.loop_counter = loop_counter; - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_loop_counter_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_loop_counter_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_hardware_reg_op_loop(ujson_t *uj) { +status_t handle_acc_fi_char_hardware_reg_op_loop(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_hardware_reg_op_loop); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_hardware_reg_op_loop, lc); - const otbn_app_t kOtbnAppCharHardwareRegOpLoop = - OTBN_APP_T_INIT(otbn_char_hardware_reg_op_loop); - static const otbn_addr_t kOtbnAppCharHardwareRegOpLoopLC = - OTBN_ADDR_T_INIT(otbn_char_hardware_reg_op_loop, lc); - TRY(otbn_load_app(kOtbnAppCharHardwareRegOpLoop)); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_hardware_reg_op_loop); + ACC_DECLARE_SYMBOL_ADDR(acc_char_hardware_reg_op_loop, lc); + const acc_app_t kAccAppCharHardwareRegOpLoop = + ACC_APP_T_INIT(acc_char_hardware_reg_op_loop); + static const acc_addr_t kAccAppCharHardwareRegOpLoopLC = + ACC_ADDR_T_INIT(acc_char_hardware_reg_op_loop, lc); + TRY(acc_load_app(kAccAppCharHardwareRegOpLoop)); uint32_t loop_counter; // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read loop counter from OTBN data memory. - TRY(otbn_dmem_read(1, kOtbnAppCharHardwareRegOpLoopLC, &loop_counter)); + // Read loop counter from ACC data memory. + TRY(acc_dmem_read(1, kAccAppCharHardwareRegOpLoopLC, &loop_counter)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send loop counter & ERR_STATUS to host. - otbn_fi_loop_counter_t uj_output; + acc_fi_loop_counter_t uj_output; uj_output.loop_counter = loop_counter; - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_loop_counter_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_loop_counter_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_jal(ujson_t *uj) { +status_t handle_acc_fi_char_jal(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_jal); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_jal, res); - const otbn_app_t kOtbnAppCharJal = OTBN_APP_T_INIT(otbn_char_jal); - static const otbn_addr_t kOtbnAppCharJalRes = - OTBN_ADDR_T_INIT(otbn_char_jal, res); - TRY(otbn_load_app(kOtbnAppCharJal)); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_jal); + ACC_DECLARE_SYMBOL_ADDR(acc_char_jal, res); + const acc_app_t kAccAppCharJal = ACC_APP_T_INIT(acc_char_jal); + static const acc_addr_t kAccAppCharJalRes = + ACC_ADDR_T_INIT(acc_char_jal, res); + TRY(acc_load_app(kAccAppCharJal)); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read counter (x1) from OTBN data memory. - otbn_fi_result_cnt_t uj_output; + // Read counter (x1) from ACC data memory. + acc_fi_result_cnt_t uj_output; uj_output.result = 0; - TRY(otbn_dmem_read(1, kOtbnAppCharJalRes, &uj_output.result)); + TRY(acc_dmem_read(1, kAccAppCharJalRes, &uj_output.result)); - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send back to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_result_cnt_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_result_cnt_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_lw(ujson_t *uj) { +status_t handle_acc_fi_char_lw(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_lw); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_lw, mem_in); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_lw, mem_out); - const otbn_app_t kOtbnAppCharLw = OTBN_APP_T_INIT(otbn_char_lw); - static const otbn_addr_t kOtbnMemIn = OTBN_ADDR_T_INIT(otbn_char_lw, mem_in); - static const otbn_addr_t kOtbnMemOut = - OTBN_ADDR_T_INIT(otbn_char_lw, mem_out); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_lw); + ACC_DECLARE_SYMBOL_ADDR(acc_char_lw, mem_in); + ACC_DECLARE_SYMBOL_ADDR(acc_char_lw, mem_out); + const acc_app_t kAccAppCharLw = ACC_APP_T_INIT(acc_char_lw); + static const acc_addr_t kAccMemIn = ACC_ADDR_T_INIT(acc_char_lw, mem_in); + static const acc_addr_t kAccMemOut = ACC_ADDR_T_INIT(acc_char_lw, mem_out); // Load app and write reference values into mem_in DMEM. - TRY(otbn_load_app(kOtbnAppCharLw)); - TRY(dif_otbn_dmem_write(&otbn, kOtbnMemIn, ref_values, sizeof(ref_values))); + TRY(acc_load_app(kAccAppCharLw)); + TRY(dif_acc_dmem_write(&acc, kAccMemIn, ref_values, sizeof(ref_values))); // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. @@ -879,45 +877,45 @@ status_t handle_otbn_fi_char_lw(ujson_t *uj) { pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); // Compare reference values. 29 values as we are loading into 29 registers. - otbn_fi_result_array_t uj_output; + acc_fi_result_array_t uj_output; uint32_t res_values[29]; memset(res_values, 0, sizeof(res_values)); memset(uj_output.result, 0, sizeof(uj_output.result)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnMemOut, res_values, sizeof(res_values))); + TRY(dif_acc_dmem_read(&acc, kAccMemOut, res_values, sizeof(res_values))); for (size_t it = 0; it < 29; it++) { uj_output.result[it] = res_values[it] ^ ref_values[it]; } - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send back to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_result_array_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_result_array_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_mem(ujson_t *uj) { +status_t handle_acc_fi_char_mem(ujson_t *uj) { // Get the test mode. The test mode only can be set at the beginning of a // test. if (!char_mem_test_cfg_valid) { - otbn_fi_mem_cfg_t uj_cfg; - TRY(ujson_deserialize_otbn_fi_mem_cfg_t(uj, &uj_cfg)); + acc_fi_mem_cfg_t uj_cfg; + TRY(ujson_deserialize_acc_fi_mem_cfg_t(uj, &uj_cfg)); char_mem_imem = uj_cfg.imem; char_mem_dmem = uj_cfg.dmem; char_mem_byte_offset = uj_cfg.byte_offset; @@ -943,12 +941,12 @@ status_t handle_otbn_fi_char_mem(ujson_t *uj) { if (!char_mem_init) { if (char_mem_dmem) { - TRY(dif_otbn_dmem_write(&otbn, char_mem_byte_offset, dmem_array_ref, - sizeof(dmem_array_ref))); + TRY(dif_acc_dmem_write(&acc, char_mem_byte_offset, dmem_array_ref, + sizeof(dmem_array_ref))); } if (char_mem_imem) { - TRY(dif_otbn_imem_write(&otbn, char_mem_byte_offset, imem_array_ref, - sizeof(imem_array_ref))); + TRY(dif_acc_imem_write(&acc, char_mem_byte_offset, imem_array_ref, + sizeof(imem_array_ref))); } char_mem_init = true; } @@ -963,15 +961,15 @@ status_t handle_otbn_fi_char_mem(ujson_t *uj) { // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - otbn_fi_mem_t uj_output; + acc_fi_mem_t uj_output; // Init with all 0 for defaults. memset(uj_output.dmem_data, 0, sizeof(uj_output.dmem_data)); memset(uj_output.dmem_addr, 0, sizeof(uj_output.dmem_addr)); @@ -983,8 +981,8 @@ status_t handle_otbn_fi_char_mem(ujson_t *uj) { size_t fault_pos = 0; if (char_mem_dmem) { uint32_t dmem_array_res[char_mem_num_words]; - TRY(dif_otbn_dmem_read(&otbn, char_mem_byte_offset, dmem_array_res, - sizeof(dmem_array_ref))); + TRY(dif_acc_dmem_read(&acc, char_mem_byte_offset, dmem_array_res, + sizeof(dmem_array_ref))); for (size_t it = 0; it < char_mem_num_words; it++) { if (dmem_array_res[it] != dmem_array_ref[it] && fault_pos < ARRAYSIZE(uj_output.dmem_data)) { @@ -1001,8 +999,8 @@ status_t handle_otbn_fi_char_mem(ujson_t *uj) { // Check IMEM for data errors. uint32_t imem_array_res[char_mem_num_words]; if (char_mem_imem) { - TRY(dif_otbn_imem_read(&otbn, char_mem_byte_offset, imem_array_res, - sizeof(imem_array_ref))); + TRY(dif_acc_imem_read(&acc, char_mem_byte_offset, imem_array_res, + sizeof(imem_array_ref))); fault_pos = 0; for (size_t it = 0; it < char_mem_num_words; it++) { if (imem_array_res[it] != imem_array_ref[it] && @@ -1018,44 +1016,44 @@ status_t handle_otbn_fi_char_mem(ujson_t *uj) { } // Send result & ERR_STATUS to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_mem_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_mem_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_register_file(ujson_t *uj) { +status_t handle_acc_fi_char_register_file(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Config for the otbn.fi.char_rf test. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_rf); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_rf, otbn_ref_values); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_rf, otbn_res_values_gpr); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_rf, otbn_res_values_wdr); + // Config for the acc.fi.char_rf test. + ACC_DECLARE_APP_SYMBOLS(acc_char_rf); + ACC_DECLARE_SYMBOL_ADDR(acc_char_rf, acc_ref_values); + ACC_DECLARE_SYMBOL_ADDR(acc_char_rf, acc_res_values_gpr); + ACC_DECLARE_SYMBOL_ADDR(acc_char_rf, acc_res_values_wdr); - static const otbn_app_t kOtbnAppCharRF = OTBN_APP_T_INIT(otbn_char_rf); - static const otbn_addr_t kOtbnVarCharRFRefValues = - OTBN_ADDR_T_INIT(otbn_char_rf, otbn_ref_values); - static const otbn_addr_t kOtbnVarCharRFResValuesGPR = - OTBN_ADDR_T_INIT(otbn_char_rf, otbn_res_values_gpr); - static const otbn_addr_t kOtbnVarCharRFResValuesWDR = - OTBN_ADDR_T_INIT(otbn_char_rf, otbn_res_values_wdr); + static const acc_app_t kAccAppCharRF = ACC_APP_T_INIT(acc_char_rf); + static const acc_addr_t kAccVarCharRFRefValues = + ACC_ADDR_T_INIT(acc_char_rf, acc_ref_values); + static const acc_addr_t kAccVarCharRFResValuesGPR = + ACC_ADDR_T_INIT(acc_char_rf, acc_res_values_gpr); + static const acc_addr_t kAccVarCharRFResValuesWDR = + ACC_ADDR_T_INIT(acc_char_rf, acc_res_values_wdr); // Init application and load reference values into DMEM. - TRY(otbn_load_app(kOtbnAppCharRF)); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarCharRFRefValues, ref_values, - sizeof(ref_values))); + TRY(acc_load_app(kAccAppCharRF)); + TRY(dif_acc_dmem_write(&acc, kAccVarCharRFRefValues, ref_values, + sizeof(ref_values))); pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. @@ -1063,9 +1061,9 @@ status_t handle_otbn_fi_char_register_file(ujson_t *uj) { // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; @@ -1074,11 +1072,11 @@ status_t handle_otbn_fi_char_register_file(ujson_t *uj) { // Read GPR RF values from DMEM. uint32_t res_values_gpr[29]; memset(res_values_gpr, 0, sizeof(res_values_gpr)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarCharRFResValuesGPR, res_values_gpr, - sizeof(res_values_gpr))); + TRY(dif_acc_dmem_read(&acc, kAccVarCharRFResValuesGPR, res_values_gpr, + sizeof(res_values_gpr))); // Compare GPR RF values to reference values. - otbn_fi_rf_char_t uj_output; + acc_fi_rf_char_t uj_output; memset(uj_output.faulty_gpr, 0, sizeof(uj_output.faulty_gpr)); uj_output.res = 0; for (size_t it = 0; it < ARRAYSIZE(res_values_gpr); it++) { @@ -1093,8 +1091,8 @@ status_t handle_otbn_fi_char_register_file(ujson_t *uj) { // Read WDR RF values from DMEM. uint32_t res_values_wdr[256]; memset(res_values_wdr, 0, sizeof(res_values_wdr)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarCharRFResValuesWDR, res_values_wdr, - sizeof(res_values_wdr))); + TRY(dif_acc_dmem_read(&acc, kAccVarCharRFResValuesWDR, res_values_wdr, + sizeof(res_values_wdr))); // Compare WDR RF values to reference values. memset(uj_output.faulty_wdr, 0, sizeof(uj_output.faulty_wdr)); @@ -1108,123 +1106,123 @@ status_t handle_otbn_fi_char_register_file(ujson_t *uj) { } // Send result & ERR_STATUS to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_rf_char_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_rf_char_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_unrolled_dmem_op_loop(ujson_t *uj) { +status_t handle_acc_fi_char_unrolled_dmem_op_loop(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_unrolled_dmem_op_loop); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_unrolled_dmem_op_loop, lc); - const otbn_app_t kOtbnAppCharUnrolledDmemOpLoop = - OTBN_APP_T_INIT(otbn_char_unrolled_dmem_op_loop); - static const otbn_addr_t kOtbnAppCharUnrolledDmemOpLoopLC = - OTBN_ADDR_T_INIT(otbn_char_unrolled_dmem_op_loop, lc); - TRY(otbn_load_app(kOtbnAppCharUnrolledDmemOpLoop)); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_unrolled_dmem_op_loop); + ACC_DECLARE_SYMBOL_ADDR(acc_char_unrolled_dmem_op_loop, lc); + const acc_app_t kAccAppCharUnrolledDmemOpLoop = + ACC_APP_T_INIT(acc_char_unrolled_dmem_op_loop); + static const acc_addr_t kAccAppCharUnrolledDmemOpLoopLC = + ACC_ADDR_T_INIT(acc_char_unrolled_dmem_op_loop, lc); + TRY(acc_load_app(kAccAppCharUnrolledDmemOpLoop)); uint32_t loop_counter; // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read loop counter from OTBN data memory. - TRY(otbn_dmem_read(1, kOtbnAppCharUnrolledDmemOpLoopLC, &loop_counter)); + // Read loop counter from ACC data memory. + TRY(acc_dmem_read(1, kAccAppCharUnrolledDmemOpLoopLC, &loop_counter)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send loop counter & ERR_STATUS to host. - otbn_fi_loop_counter_t uj_output; + acc_fi_loop_counter_t uj_output; uj_output.loop_counter = loop_counter; - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_loop_counter_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_loop_counter_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_char_unrolled_reg_op_loop(ujson_t *uj) { +status_t handle_acc_fi_char_unrolled_reg_op_loop(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_char_unrolled_reg_op_loop); - OTBN_DECLARE_SYMBOL_ADDR(otbn_char_unrolled_reg_op_loop, lc); - const otbn_app_t kOtbnAppCharUnrolledRegOpLoop = - OTBN_APP_T_INIT(otbn_char_unrolled_reg_op_loop); - static const otbn_addr_t kOtbnAppCharUnrolledRegOpLoopLC = - OTBN_ADDR_T_INIT(otbn_char_unrolled_reg_op_loop, lc); - TRY(otbn_load_app(kOtbnAppCharUnrolledRegOpLoop)); + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_char_unrolled_reg_op_loop); + ACC_DECLARE_SYMBOL_ADDR(acc_char_unrolled_reg_op_loop, lc); + const acc_app_t kAccAppCharUnrolledRegOpLoop = + ACC_APP_T_INIT(acc_char_unrolled_reg_op_loop); + static const acc_addr_t kAccAppCharUnrolledRegOpLoopLC = + ACC_ADDR_T_INIT(acc_char_unrolled_reg_op_loop, lc); + TRY(acc_load_app(kAccAppCharUnrolledRegOpLoop)); uint32_t loop_counter; // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read loop counter from OTBN data memory. - TRY(otbn_dmem_read(1, kOtbnAppCharUnrolledRegOpLoopLC, &loop_counter)); + // Read loop counter from ACC data memory. + TRY(acc_dmem_read(1, kAccAppCharUnrolledRegOpLoopLC, &loop_counter)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send loop counter & ERR_STATUS to host. - otbn_fi_loop_counter_t uj_output; + acc_fi_loop_counter_t uj_output; uj_output.loop_counter = loop_counter; - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_loop_counter_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_loop_counter_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_init(ujson_t *uj) { +status_t handle_acc_fi_init(ujson_t *uj) { penetrationtest_cpuctrl_t uj_cpuctrl_data; TRY(ujson_deserialize_penetrationtest_cpuctrl_t(uj, &uj_cpuctrl_data)); penetrationtest_sensor_config_t uj_sensor_data; @@ -1232,16 +1230,16 @@ status_t handle_otbn_fi_init(ujson_t *uj) { penetrationtest_alert_config_t uj_alert_data; TRY(ujson_deserialize_penetrationtest_alert_config_t(uj, &uj_alert_data)); - // Configure the entropy complex for OTBN. Set the reseed interval to max + // Configure the entropy complex for ACC. Set the reseed interval to max // to avoid a non-constant trigger window. TRY(pentest_configure_entropy_source_max_reseed_interval()); pentest_select_trigger_type(kPentestTriggerTypeSw); - pentest_init(kPentestTriggerSourceOtbn, + pentest_init(kPentestTriggerSourceAcc, kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); @@ -1250,8 +1248,8 @@ status_t handle_otbn_fi_init(ujson_t *uj) { mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR), &rv_core_ibex)); - // Init the OTBN core. - TRY(dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + // Init the ACC core. + TRY(dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); // Configure the alert handler. Alerts triggered by IP blocks are captured // and reported to the test. @@ -1299,45 +1297,45 @@ status_t handle_otbn_fi_init(ujson_t *uj) { return OK_STATUS(); } -status_t handle_otbn_fi_init_keymgr(ujson_t *uj) { +status_t handle_acc_fi_init_keymgr(ujson_t *uj) { dif_kmac_t kmac; TRY(dif_kmac_init(mmio_region_from_addr(TOP_EARLGREY_KMAC_BASE_ADDR), &kmac)); TRY(dif_keymgr_init(mmio_region_from_addr(TOP_EARLGREY_KEYMGR_BASE_ADDR), &keymgr)); TRY(keymgr_testutils_initialize(&keymgr, &kmac)); - dif_keymgr_versioned_key_params_t sideload_params = kKeyVersionedParamsOTBNFI; - sideload_params.dest = kDifKeymgrVersionedKeyDestOtbn; + dif_keymgr_versioned_key_params_t sideload_params = kKeyVersionedParamsACCFI; + sideload_params.dest = kDifKeymgrVersionedKeyDestAcc; TRY(keymgr_testutils_generate_versioned_key(&keymgr, sideload_params)); return OK_STATUS(); } -status_t handle_otbn_fi_key_sideload(ujson_t *uj) { - TRY(dif_otbn_set_ctrl_software_errs_fatal(&otbn, /*enable=*/false)); +status_t handle_acc_fi_key_sideload(ujson_t *uj) { + TRY(dif_acc_set_ctrl_software_errs_fatal(&acc, /*enable=*/false)); // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); if (!key_sideloading_init) { - // Setup keymanager for sideloading key into OTBN. - TRY(otbn_load_app(kOtbnAppKeySideload)); + // Setup keymanager for sideloading key into ACC. + TRY(acc_load_app(kAccAppKeySideload)); // Get reference keys. - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks0l, &key_share_0_l_ref)); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks0h, &key_share_0_h_ref)); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks1l, &key_share_1_l_ref)); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks1h, &key_share_1_h_ref)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks0l, &key_share_0_l_ref)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks0h, &key_share_0_h_ref)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks1l, &key_share_1_l_ref)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks1h, &key_share_1_h_ref)); key_sideloading_init = true; } // FI code target. pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Get registered alerts from alert handler. @@ -1345,23 +1343,23 @@ status_t handle_otbn_fi_key_sideload(ujson_t *uj) { // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read loop counter from OTBN data memory. + // Read loop counter from ACC data memory. uint32_t key_share_0_l, key_share_0_h; uint32_t key_share_1_l, key_share_1_h; - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks0l, &key_share_0_l)); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks0h, &key_share_0_h)); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks1l, &key_share_1_l)); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks1h, &key_share_1_h)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks0l, &key_share_0_l)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks0h, &key_share_0_h)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks1l, &key_share_1_l)); + TRY(acc_dmem_read(1, kAccAppKeySideloadks1h, &key_share_1_h)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - otbn_fi_keys_t uj_output; + acc_fi_keys_t uj_output; uj_output.keys[0] = key_share_0_l; uj_output.keys[1] = key_share_0_h; uj_output.keys[2] = key_share_1_l; @@ -1376,35 +1374,35 @@ status_t handle_otbn_fi_key_sideload(ujson_t *uj) { } // Send result & ERR_STATUS to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_keys_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_keys_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_load_integrity(ujson_t *uj) { +status_t handle_acc_fi_load_integrity(ujson_t *uj) { // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); if (!load_integrity_init) { - // Load the OTBN app and read the load checksum without FI to retrieve + // Load the ACC app and read the load checksum without FI to retrieve // reference value. - clear_otbn_load_checksum(); - TRY(otbn_load_app(kOtbnAppLoadIntegrity)); - read_otbn_load_checksum(&load_checksum_ref); - clear_otbn_load_checksum(); + clear_acc_load_checksum(); + TRY(acc_load_app(kAccAppLoadIntegrity)); + read_acc_load_checksum(&load_checksum_ref); + clear_acc_load_checksum(); load_integrity_init = true; } // FI code target. pentest_set_trigger_high(); - TRY(otbn_load_app(kOtbnAppLoadIntegrity)); + TRY(acc_load_app(kAccAppLoadIntegrity)); pentest_set_trigger_low(); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); @@ -1413,14 +1411,14 @@ status_t handle_otbn_fi_load_integrity(ujson_t *uj) { // Read back checksum. uint32_t load_checksum; - read_otbn_load_checksum(&load_checksum); - clear_otbn_load_checksum(); + read_acc_load_checksum(&load_checksum); + clear_acc_load_checksum(); - // Read loop counter from OTBN data memory. + // Read loop counter from ACC data memory. uint32_t ref_val1, ref_val2, ref_val3; - TRY(otbn_dmem_read(1, kOtbnAppLoadIntegrityRefVal1, &ref_val1)); - TRY(otbn_dmem_read(1, kOtbnAppLoadIntegrityRefVal2, &ref_val2)); - TRY(otbn_dmem_read(1, kOtbnAppLoadIntegrityRefVal3, &ref_val3)); + TRY(acc_dmem_read(1, kAccAppLoadIntegrityRefVal1, &ref_val1)); + TRY(acc_dmem_read(1, kAccAppLoadIntegrityRefVal2, &ref_val2)); + TRY(acc_dmem_read(1, kAccAppLoadIntegrityRefVal3, &ref_val3)); // Check if DMEM is corrupted. bool dmem_corrupted = false; @@ -1436,147 +1434,147 @@ status_t handle_otbn_fi_load_integrity(ujson_t *uj) { res = 1; } - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send result & ERR_STATUS to host. - otbn_fi_result_t uj_output; + acc_fi_result_t uj_output; uj_output.result = res; - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_result_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_result_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi_pc(ujson_t *uj) { - // Get OTBN program counter from host. - otbn_fi_pc_t uj_data; - TRY(ujson_deserialize_otbn_fi_pc_t(uj, &uj_data)); +status_t handle_acc_fi_pc(ujson_t *uj) { + // Get ACC program counter from host. + acc_fi_pc_t uj_data; + TRY(ujson_deserialize_acc_fi_pc_t(uj, &uj_data)); // Clear registered alerts in alert handler. pentest_registered_alerts_t reg_alerts = pentest_get_triggered_alerts(); // Clear the AST recoverable alerts. pentest_clear_sensor_recov_alerts(); - // Initialize OTBN app, load it, and get interface to OTBN data memory. - OTBN_DECLARE_APP_SYMBOLS(otbn_pc); - OTBN_DECLARE_SYMBOL_ADDR(otbn_pc, pc); - OTBN_DECLARE_SYMBOL_ADDR(otbn_pc, pc_out); - const otbn_app_t kOtbnAppPc = OTBN_APP_T_INIT(otbn_pc); - static const otbn_addr_t kOtbnPc = OTBN_ADDR_T_INIT(otbn_pc, pc); - static const otbn_addr_t kOtbnPcOut = OTBN_ADDR_T_INIT(otbn_pc, pc_out); - dif_otbn_status_t otbn_status; + // Initialize ACC app, load it, and get interface to ACC data memory. + ACC_DECLARE_APP_SYMBOLS(acc_pc); + ACC_DECLARE_SYMBOL_ADDR(acc_pc, pc); + ACC_DECLARE_SYMBOL_ADDR(acc_pc, pc_out); + const acc_app_t kAccAppPc = ACC_APP_T_INIT(acc_pc); + static const acc_addr_t kAccPc = ACC_ADDR_T_INIT(acc_pc, pc); + static const acc_addr_t kAccPcOut = ACC_ADDR_T_INIT(acc_pc, pc_out); + dif_acc_status_t acc_status; // Load app. - TRY(otbn_load_app(kOtbnAppPc)); + TRY(acc_load_app(kAccAppPc)); // FI code target. pentest_set_trigger_high(); - TRY(dif_otbn_dmem_write(&otbn, kOtbnPc, &uj_data.pc, sizeof(uj_data.pc))); - TRY(otbn_execute()); + TRY(dif_acc_dmem_write(&acc, kAccPc, &uj_data.pc, sizeof(uj_data.pc))); + TRY(acc_execute()); // Wait until is started before deasserting the trigger. bool is_running = false; while (!is_running) { - TRY(dif_otbn_get_status(&otbn, &otbn_status)); - if (otbn_status != kDifOtbnStatusIdle) { + TRY(dif_acc_get_status(&acc, &acc_status)); + if (acc_status != kDifAccStatusIdle) { is_running = true; } } pentest_set_trigger_low(); - TRY(otbn_busy_wait_for_done()); + TRY(acc_busy_wait_for_done()); // Get registered alerts from alert handler. reg_alerts = pentest_get_triggered_alerts(); // Get fatal and recoverable AST alerts from sensor controller. pentest_sensor_alerts_t sensor_alerts = pentest_get_sensor_alerts(); - // Read pc_out from OTBN data memory. - otbn_fi_pc_out_t uj_output; - TRY(dif_otbn_dmem_read(&otbn, kOtbnPcOut, &uj_output.pc_otbn, - sizeof(uj_output.pc_otbn))); - TRY(dif_otbn_dmem_read(&otbn, kOtbnPc, &uj_output.pc_dmem, - sizeof(uj_output.pc_dmem))); + // Read pc_out from ACC data memory. + acc_fi_pc_out_t uj_output; + TRY(dif_acc_dmem_read(&acc, kAccPcOut, &uj_output.pc_acc, + sizeof(uj_output.pc_acc))); + TRY(dif_acc_dmem_read(&acc, kAccPc, &uj_output.pc_dmem, + sizeof(uj_output.pc_dmem))); - // Read OTBN instruction counter. - TRY(dif_otbn_get_insn_cnt(&otbn, &uj_output.insn_cnt)); + // Read ACC instruction counter. + TRY(dif_acc_get_insn_cnt(&acc, &uj_output.insn_cnt)); - // Read ERR_STATUS register from OTBN. - dif_otbn_err_bits_t err_otbn; - read_otbn_err_bits(&err_otbn); + // Read ERR_STATUS register from ACC. + dif_acc_err_bits_t err_acc; + read_acc_err_bits(&err_acc); // Read ERR_STATUS register from Ibex. dif_rv_core_ibex_error_status_t err_ibx; TRY(dif_rv_core_ibex_get_error_status(&rv_core_ibex, &err_ibx)); - // Clear OTBN memory. - TRY(clear_otbn()); + // Clear ACC memory. + TRY(clear_acc()); // Send back to host. - uj_output.err_otbn = err_otbn; + uj_output.err_acc = err_acc; uj_output.err_ibx = err_ibx; memcpy(uj_output.alerts, reg_alerts.alerts, sizeof(reg_alerts.alerts)); memcpy(uj_output.ast_alerts, sensor_alerts.alerts, sizeof(sensor_alerts.alerts)); - RESP_OK(ujson_serialize_otbn_fi_pc_out_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_fi_pc_out_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_fi(ujson_t *uj) { - otbn_fi_subcommand_t cmd; - TRY(ujson_deserialize_otbn_fi_subcommand_t(uj, &cmd)); +status_t handle_acc_fi(ujson_t *uj) { + acc_fi_subcommand_t cmd; + TRY(ujson_deserialize_acc_fi_subcommand_t(uj, &cmd)); switch (cmd) { - case kOtbnFiSubcommandCharBeq: - return handle_otbn_fi_char_beq(uj); - case kOtbnFiSubcommandCharBnRshi: - return handle_otbn_fi_char_bn_rshi(uj); - case kOtbnFiSubcommandCharBnSel: - return handle_otbn_fi_char_bn_sel(uj); - case kOtbnFiSubcommandCharBnWsrr: - return handle_otbn_fi_char_bn_wsrr(uj); - case kOtbnFiSubcommandCharBne: - return handle_otbn_fi_char_bne(uj); - case kOtbnFiSubcommandCharDmemAccess: - return handle_otbn_fi_char_dmem_access(uj); - case kOtbnFiSubcommandCharDmemWrite: - return handle_otbn_fi_char_dmem_write(uj); - case kOtbnFiSubcommandCharHardwareDmemOpLoop: - return handle_otbn_fi_char_hardware_dmem_op_loop(uj); - case kOtbnFiSubcommandCharHardwareRegOpLoop: - return handle_otbn_fi_char_hardware_reg_op_loop(uj); - case kOtbnFiSubcommandCharJal: - return handle_otbn_fi_char_jal(uj); - case kOtbnFiSubcommandCharLw: - return handle_otbn_fi_char_lw(uj); - case kOtbnFiSubcommandCharMem: - return handle_otbn_fi_char_mem(uj); - case kOtbnFiSubcommandCharRF: - return handle_otbn_fi_char_register_file(uj); - case kOtbnFiSubcommandCharUnrolledDmemOpLoop: - return handle_otbn_fi_char_unrolled_dmem_op_loop(uj); - case kOtbnFiSubcommandCharUnrolledRegOpLoop: - return handle_otbn_fi_char_unrolled_reg_op_loop(uj); - case kOtbnFiSubcommandInit: - return handle_otbn_fi_init(uj); - case kOtbnFiSubcommandInitKeyMgr: - return handle_otbn_fi_init_keymgr(uj); - case kOtbnFiSubcommandKeySideload: - return handle_otbn_fi_key_sideload(uj); - case kOtbnFiSubcommandLoadIntegrity: - return handle_otbn_fi_load_integrity(uj); - case kOtbnFiSubcommandPC: - return handle_otbn_fi_pc(uj); + case kAccFiSubcommandCharBeq: + return handle_acc_fi_char_beq(uj); + case kAccFiSubcommandCharBnRshi: + return handle_acc_fi_char_bn_rshi(uj); + case kAccFiSubcommandCharBnSel: + return handle_acc_fi_char_bn_sel(uj); + case kAccFiSubcommandCharBnWsrr: + return handle_acc_fi_char_bn_wsrr(uj); + case kAccFiSubcommandCharBne: + return handle_acc_fi_char_bne(uj); + case kAccFiSubcommandCharDmemAccess: + return handle_acc_fi_char_dmem_access(uj); + case kAccFiSubcommandCharDmemWrite: + return handle_acc_fi_char_dmem_write(uj); + case kAccFiSubcommandCharHardwareDmemOpLoop: + return handle_acc_fi_char_hardware_dmem_op_loop(uj); + case kAccFiSubcommandCharHardwareRegOpLoop: + return handle_acc_fi_char_hardware_reg_op_loop(uj); + case kAccFiSubcommandCharJal: + return handle_acc_fi_char_jal(uj); + case kAccFiSubcommandCharLw: + return handle_acc_fi_char_lw(uj); + case kAccFiSubcommandCharMem: + return handle_acc_fi_char_mem(uj); + case kAccFiSubcommandCharRF: + return handle_acc_fi_char_register_file(uj); + case kAccFiSubcommandCharUnrolledDmemOpLoop: + return handle_acc_fi_char_unrolled_dmem_op_loop(uj); + case kAccFiSubcommandCharUnrolledRegOpLoop: + return handle_acc_fi_char_unrolled_reg_op_loop(uj); + case kAccFiSubcommandInit: + return handle_acc_fi_init(uj); + case kAccFiSubcommandInitKeyMgr: + return handle_acc_fi_init_keymgr(uj); + case kAccFiSubcommandKeySideload: + return handle_acc_fi_key_sideload(uj); + case kAccFiSubcommandLoadIntegrity: + return handle_acc_fi_load_integrity(uj); + case kAccFiSubcommandPC: + return handle_acc_fi_pc(uj); default: - LOG_ERROR("Unrecognized OTBN FI subcommand: %d", cmd); + LOG_ERROR("Unrecognized ACC FI subcommand: %d", cmd); return INVALID_ARGUMENT(); } return OK_STATUS(); diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn_fi.h b/sw/device/tests/penetrationtests/firmware/fi/acc_fi.h similarity index 68% rename from sw/device/tests/penetrationtests/firmware/fi/otbn_fi.h rename to sw/device/tests/penetrationtests/firmware/fi/acc_fi.h index 3c013a70c56..d575a7fac2c 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/otbn_fi.h +++ b/sw/device/tests/penetrationtests/firmware/fi/acc_fi.h @@ -2,14 +2,14 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_FI_OTBN_FI_H_ -#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_FI_OTBN_FI_H_ +#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_FI_ACC_FI_H_ +#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_FI_ACC_FI_H_ #include "sw/device/lib/base/status.h" #include "sw/device/lib/ujson/ujson.h" /** - * otbn.fi.char.beq command handler. + * acc.fi.char.beq command handler. * * The goal of this test is to fault to BEQ instruction such that the jump is * not performed. Then, a counter gets incremented. When no effective fault @@ -20,10 +20,10 @@ * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_char_beq(ujson_t *uj); +status_t handle_acc_fi_char_beq(ujson_t *uj); /** - * otbn.fi.char.bn_rshi command handler. + * acc.fi.char.bn_rshi command handler. * * The goal of this test is to manipulate the BN.RSHI instruction. * @@ -32,10 +32,10 @@ status_t handle_otbn_fi_char_beq(ujson_t *uj); * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_char_bn_rshi(ujson_t *uj); +status_t handle_acc_fi_char_bn_rshi(ujson_t *uj); /** - * otbn.fi.char.bn_sel command handler. + * acc.fi.char.bn_sel command handler. * * The goal of this test is to manipulate the carry flag or the BN.SEL * instruction. @@ -45,10 +45,10 @@ status_t handle_otbn_fi_char_bn_rshi(ujson_t *uj); * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_char_bn_sel(ujson_t *uj); +status_t handle_acc_fi_char_bn_sel(ujson_t *uj); /** - * otbn.fi.char.bn_wsrr command handler. + * acc.fi.char.bn_wsrr command handler. * * The goal of this test is to manipulate the BN.WSRR instruction or the content * of the registers. @@ -58,10 +58,10 @@ status_t handle_otbn_fi_char_bn_sel(ujson_t *uj); * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_char_bn_wsrr(ujson_t *uj); +status_t handle_acc_fi_char_bn_wsrr(ujson_t *uj); /** - * otbn.fi.char.bne command handler. + * acc.fi.char.bne command handler. * * The goal of this test is to fault to BNE instruction such that the jump is * not performed. Then, a counter gets incremented. When no effective fault @@ -72,12 +72,12 @@ status_t handle_otbn_fi_char_bn_wsrr(ujson_t *uj); * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_char_bne(ujson_t *uj); +status_t handle_acc_fi_char_bne(ujson_t *uj); /** - * otbn.fi.char_dmem_access command handler. + * acc.fi.char_dmem_access command handler. * - * OTBN loads WDRs with words from DMEM. These values are stored in different + * ACC loads WDRs with words from DMEM. These values are stored in different * data sections. * * Faults are injected during the trigger_high & trigger_low. @@ -85,10 +85,10 @@ status_t handle_otbn_fi_char_bne(ujson_t *uj); * @param uj The received uJSON data. * @return OK or error. */ -status_t handle_otbn_fi_char_dmem_access(ujson_t *uj); +status_t handle_acc_fi_char_dmem_access(ujson_t *uj); /** - * otbn.fi.char_dmem_write command handler. + * acc.fi.char_dmem_write command handler. * * Inject faults during Ibex writes data to DMEM. * @@ -96,12 +96,12 @@ status_t handle_otbn_fi_char_dmem_access(ujson_t *uj); * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_char_dmem_write(ujson_t *uj); +status_t handle_acc_fi_char_dmem_write(ujson_t *uj); /** - * otbn.fi.char.hardware.dmem.op.loop command handler. + * acc.fi.char.hardware.dmem.op.loop command handler. * - * This FI penetration tests executes the following instructions on OTBN: + * This FI penetration tests executes the following instructions on ACC: * - Initialize register x3=0 * - Perform 10000 x3 = x3 + 1 additions using hardware loop instructions. * Load loop counter from memory and write back after increment. @@ -113,12 +113,12 @@ status_t handle_otbn_fi_char_dmem_write(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_char_hardware_dmem_op_loop(ujson_t *uj); +status_t handle_acc_fi_char_hardware_dmem_op_loop(ujson_t *uj); /** - * otbn.fi.char.hardware.reg.op.loop command handler. + * acc.fi.char.hardware.reg.op.loop command handler. * - * This FI penetration tests executes the following instructions on OTBN: + * This FI penetration tests executes the following instructions on ACC: * - Initialize register x3=0 * - Perform 10000 x3 = x3 + 1 additions using hardware loop instructions * - Return the value over UART. @@ -129,10 +129,10 @@ status_t handle_otbn_fi_char_hardware_dmem_op_loop(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_char_hardware_reg_op_loop(ujson_t *uj); +status_t handle_acc_fi_char_hardware_reg_op_loop(ujson_t *uj); /** - * otbn.fi.char.jal command handler. + * acc.fi.char.jal command handler. * * The goal of this test is to fault to JAL instruction such that the jump is * not performed. Then, a counter gets incremented. When no effective fault @@ -144,21 +144,21 @@ status_t handle_otbn_fi_char_hardware_reg_op_loop(ujson_t *uj); * @param uj The received uJSON data. * @return OK or error. */ -status_t handle_otbn_fi_char_jal(ujson_t *uj); +status_t handle_acc_fi_char_jal(ujson_t *uj); /** - * otbn.fi.char.lw command handler. + * acc.fi.char.lw command handler. * * The goal of this test is to manipulate LW instructions using FI. * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_char_lw(ujson_t *uj); +status_t handle_acc_fi_char_lw(ujson_t *uj); /** - * otbn.fi.char_mem command handler. + * acc.fi.char_mem command handler. * - * Initializes IMEM and DMEM of OTBN with a fixed pattern. Inject a fault and + * Initializes IMEM and DMEM of ACC with a fixed pattern. Inject a fault and * check whether the data in memory got corrupted. * * Faults are injected during the trigger_high & trigger_low. @@ -166,24 +166,24 @@ status_t handle_otbn_fi_char_lw(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_char_mem(ujson_t *uj); +status_t handle_acc_fi_char_mem(ujson_t *uj); /** - * otbn.fi.char_rf command handler. + * acc.fi.char_rf command handler. * - * Init GPRs and WDRs of OTBN with reference values. Inject faults during 10000 + * Init GPRs and WDRs of ACC with reference values. Inject faults during 10000 * NOPS. Read back GPRs and WDRs and compare against reference values. Report * faulty values back to host. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_char_register_file(ujson_t *uj); +status_t handle_acc_fi_char_register_file(ujson_t *uj); /** - * otbn.fi.char.unrolled.dmem.op.loop command handler. + * acc.fi.char.unrolled.dmem.op.loop command handler. * - * This FI penetration tests executes the following instructions on OTBN: + * This FI penetration tests executes the following instructions on ACC: * - Perform 100 times: * - Load loop counter from memory * - Increment loop counter @@ -196,12 +196,12 @@ status_t handle_otbn_fi_char_register_file(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_char_unrolled_dmem_op_loop(ujson_t *uj); +status_t handle_acc_fi_char_unrolled_dmem_op_loop(ujson_t *uj); /** - * otbn.char.unrolled.reg.op.loop command handler. + * acc.char.unrolled.reg.op.loop command handler. * - * This FI penetration tests executes the following instructions on OTBN: + * This FI penetration tests executes the following instructions on ACC: * - Initialize register x2=0 * - Perform 100 x2 = x2 + 1 additions * - Return the value over UART. @@ -212,10 +212,10 @@ status_t handle_otbn_fi_char_unrolled_dmem_op_loop(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_char_unrolled_reg_op_loop(ujson_t *uj); +status_t handle_acc_fi_char_unrolled_reg_op_loop(ujson_t *uj); /** - * Initializes the OTBN FI test. + * Initializes the ACC FI test. * * Setup the trigger and alert handler. Disable dummy instructions and the * iCache. @@ -223,7 +223,7 @@ status_t handle_otbn_fi_char_unrolled_reg_op_loop(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_init(ujson_t *uj); +status_t handle_acc_init(ujson_t *uj); /** * Initializes the key manager. @@ -231,28 +231,28 @@ status_t handle_otbn_init(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_init_keymgr(ujson_t *uj); +status_t handle_acc_fi_init_keymgr(ujson_t *uj); /** - * otbn.fi.key_sideload command handler. + * acc.fi.key_sideload command handler. * - * Injects a fault when a key is sideloaded from the key manager into OTBN. + * Injects a fault when a key is sideloaded from the key manager into ACC. * * Faults are injected during the trigger_high & trigger_low. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_key_sideload(ujson_t *uj); +status_t handle_acc_fi_key_sideload(ujson_t *uj); /** - * otbn.fi.load_integrity command handler. + * acc.fi.load_integrity command handler. * - * Tests, whether a fault during loading the OTBN app can manipulate data in + * Tests, whether a fault during loading the ACC app can manipulate data in * DMEM without changing the CRC-32 checksum that is used to check the * integrity of the DMEM and IMEM. * - * As the OTBN app itself is not the target of this FI analysis, it only + * As the ACC app itself is not the target of this FI analysis, it only * consists of NOPs. The DMEM is initialized with reference values that * are checked. * @@ -261,27 +261,27 @@ status_t handle_otbn_fi_key_sideload(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi_load_integrity(ujson_t *uj); +status_t handle_acc_fi_load_integrity(ujson_t *uj); /** - * otbn.fi.pc command handler. + * acc.fi.pc command handler. * - * The goal of this test is to fault the OTBN program counter that is passed - * from Ibex into OTBN. OTBN jumps to this PC. Manipulation can be detected by + * The goal of this test is to fault the ACC program counter that is passed + * from Ibex into ACC. ACC jumps to this PC. Manipulation can be detected by * reading the instruction counter. * * @param uj The received uJSON data. */ -status_t handle_otbn_fi_pc(ujson_t *uj); +status_t handle_acc_fi_pc(ujson_t *uj); /** - * OTBN FI command handler. + * ACC FI command handler. * - * Command handler for the OTBN FI command. + * Command handler for the ACC FI command. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_fi(ujson_t *uj); +status_t handle_acc_fi(ujson_t *uj); -#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_FI_OTBN_FI_H_ +#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_FI_ACC_FI_H_ diff --git a/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c b/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c index 4362cb3b8cf..ee8d4f3a65f 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c +++ b/sw/device/tests/penetrationtests/firmware/fi/alert_fi.c @@ -7,6 +7,7 @@ #include "sw/device/lib/base/abs_mmio.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/status.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_adc_ctrl.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_alert_handler.h" @@ -22,7 +23,6 @@ #include "sw/device/lib/dif/dif_keymgr.h" #include "sw/device/lib/dif/dif_kmac.h" #include "sw/device/lib/dif/dif_lc_ctrl.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_otp_ctrl.h" #include "sw/device/lib/dif/dif_pattgen.h" #include "sw/device/lib/dif/dif_pinmux.h" @@ -70,7 +70,7 @@ static dif_i2c_t i2c2; static dif_keymgr_t keymgr; static dif_kmac_t kmac; static dif_lc_ctrl_t lc_ctrl; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_otp_ctrl_t otp_ctrl; static dif_pattgen_t pattgen; static dif_pinmux_t pinmux_aon; @@ -152,8 +152,8 @@ static status_t init_peripherals(void) { base_addr = mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR); TRY(dif_lc_ctrl_init(base_addr, &lc_ctrl)); - base_addr = mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR); - TRY(dif_otbn_init(base_addr, &otbn)); + base_addr = mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR); + TRY(dif_acc_init(base_addr, &acc)); base_addr = mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR); TRY(dif_otp_ctrl_init(base_addr, &otp_ctrl)); @@ -341,10 +341,10 @@ status_t handle_alert_fi_trigger(ujson_t *uj) { TRY(dif_lc_ctrl_alert_force(&lc_ctrl, kDifLcCtrlAlertFatalBusIntegError)); break; case 30: - TRY(dif_otbn_alert_force(&otbn, kDifOtbnAlertFatal)); + TRY(dif_acc_alert_force(&acc, kDifAccAlertFatal)); break; case 31: - TRY(dif_otbn_alert_force(&otbn, kDifOtbnAlertRecov)); + TRY(dif_acc_alert_force(&acc, kDifAccAlertRecov)); break; case 32: TRY(dif_otp_ctrl_alert_force(&otp_ctrl, kDifOtpCtrlAlertFatalMacroError)); @@ -618,7 +618,7 @@ status_t handle_alert_fi_init(ujson_t *uj) { kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); diff --git a/sw/device/tests/penetrationtests/firmware/fi/alert_fi.h b/sw/device/tests/penetrationtests/firmware/fi/alert_fi.h index 646c6137967..02277870990 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/alert_fi.h +++ b/sw/device/tests/penetrationtests/firmware/fi/alert_fi.h @@ -62,7 +62,7 @@ * - FatalProgError [Case 27] * - FatalStateError [Case 28] * - FatalBusIntegError [Case 29] - * OTBN: recoverable and fatal alerts for the OpenTitan Big Number accelerator. + * ACC: recoverable and fatal alerts for the OpenTitan Big Number accelerator. * - FatalAlert [Case 30] * - RecovAlert [Case 30] * OTP_CTRL: fatal macro, check, bus integrity errors, and primary OTP alerts diff --git a/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_asym.c b/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_asym.c index 92e6b57f59a..a2147dbf69f 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_asym.c +++ b/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_asym.c @@ -470,7 +470,7 @@ status_t handle_cryptolib_fi_asym_init(ujson_t *uj) { kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); diff --git a/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_sym.c b/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_sym.c index 31e3887223d..4f8937cbfe1 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_sym.c +++ b/sw/device/tests/penetrationtests/firmware/fi/cryptolib_fi_sym.c @@ -182,7 +182,7 @@ status_t handle_cryptolib_fi_sym_init(ujson_t *uj) { kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); diff --git a/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c b/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c index ab9aed0bf23..a42287f6b4b 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c +++ b/sw/device/tests/penetrationtests/firmware/fi/ibex_fi.c @@ -4241,7 +4241,7 @@ status_t handle_ibex_fi_init(ujson_t *uj) { kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); diff --git a/sw/device/tests/penetrationtests/firmware/fi/otbn/BUILD b/sw/device/tests/penetrationtests/firmware/fi/otbn/BUILD deleted file mode 100644 index 846c290c449..00000000000 --- a/sw/device/tests/penetrationtests/firmware/fi/otbn/BUILD +++ /dev/null @@ -1,126 +0,0 @@ -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -load("//rules:otbn.bzl", "otbn_binary") - -package(default_visibility = ["//visibility:public"]) - -otbn_binary( - name = "otbn_char_beq", - srcs = [ - "otbn_char_beq.s", - ], -) - -otbn_binary( - name = "otbn_char_bn_rshi", - srcs = [ - "otbn_char_bn_rshi.s", - ], -) - -otbn_binary( - name = "otbn_char_bn_sel", - srcs = [ - "otbn_char_bn_sel.s", - ], -) - -otbn_binary( - name = "otbn_char_bn_wsrr", - srcs = [ - "otbn_char_bn_wsrr.s", - ], -) - -otbn_binary( - name = "otbn_char_bne", - srcs = [ - "otbn_char_bne.s", - ], -) - -otbn_binary( - name = "otbn_char_dmem_access", - srcs = [ - "otbn_char_dmem_access.s", - ], -) - -otbn_binary( - name = "otbn_char_dmem_write", - srcs = [ - "otbn_char_dmem_write.s", - ], -) - -otbn_binary( - name = "otbn_char_hardware_dmem_op_loop", - srcs = [ - "otbn_char_hardware_dmem_op_loop.s", - ], -) - -otbn_binary( - name = "otbn_char_hardware_reg_op_loop", - srcs = [ - "otbn_char_hardware_reg_op_loop.s", - ], -) - -otbn_binary( - name = "otbn_char_jal", - srcs = [ - "otbn_char_jal.s", - ], -) - -otbn_binary( - name = "otbn_char_lw", - srcs = [ - "otbn_char_lw.s", - ], -) - -otbn_binary( - name = "otbn_char_rf", - srcs = [ - "otbn_char_rf.s", - ], -) - -otbn_binary( - name = "otbn_char_unrolled_dmem_op_loop", - srcs = [ - "otbn_char_unrolled_dmem_op_loop.s", - ], -) - -otbn_binary( - name = "otbn_char_unrolled_reg_op_loop", - srcs = [ - "otbn_char_unrolled_reg_op_loop.s", - ], -) - -otbn_binary( - name = "otbn_key_sideload", - srcs = [ - "otbn_key_sideload.s", - ], -) - -otbn_binary( - name = "otbn_load_integrity", - srcs = [ - "otbn_load_integrity.s", - ], -) - -otbn_binary( - name = "otbn_pc", - srcs = [ - "otbn_pc.s", - ], -) diff --git a/sw/device/tests/penetrationtests/firmware/fi/otp_fi.c b/sw/device/tests/penetrationtests/firmware/fi/otp_fi.c index 6b92aa699a1..cbe374e0892 100644 --- a/sw/device/tests/penetrationtests/firmware/fi/otp_fi.c +++ b/sw/device/tests/penetrationtests/firmware/fi/otp_fi.c @@ -170,7 +170,7 @@ status_t handle_otp_fi_init(ujson_t *uj) { kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); diff --git a/sw/device/tests/penetrationtests/firmware/firmware_fi_otbn.c b/sw/device/tests/penetrationtests/firmware/firmware_fi_acc.c similarity index 86% rename from sw/device/tests/penetrationtests/firmware/firmware_fi_otbn.c rename to sw/device/tests/penetrationtests/firmware/firmware_fi_acc.c index 26315906c3e..d4210fd13f2 100644 --- a/sw/device/tests/penetrationtests/firmware/firmware_fi_otbn.c +++ b/sw/device/tests/penetrationtests/firmware/firmware_fi_acc.c @@ -11,12 +11,12 @@ #include "sw/device/lib/ujson/ujson.h" // Include commands +#include "sw/device/tests/penetrationtests/json/acc_fi_commands.h" #include "sw/device/tests/penetrationtests/json/commands.h" -#include "sw/device/tests/penetrationtests/json/otbn_fi_commands.h" #include "sw/device/tests/penetrationtests/json/pentest_lib_commands.h" // Include handlers -#include "sw/device/tests/penetrationtests/firmware/fi/otbn_fi.h" +#include "sw/device/tests/penetrationtests/firmware/fi/acc_fi.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" OTTF_DEFINE_TEST_CONFIG(.enable_uart_flow_control = true); @@ -26,8 +26,8 @@ status_t process_cmd(ujson_t *uj) { penetrationtest_cmd_t cmd; TRY(ujson_deserialize_penetrationtest_cmd_t(uj, &cmd)); switch (cmd) { - case kPenetrationtestCommandOtbnFi: - RESP_ERR(uj, handle_otbn_fi(uj)); + case kPenetrationtestCommandAccFi: + RESP_ERR(uj, handle_acc_fi(uj)); break; case kPenetrationtestCommandAlertInfo: RESP_ERR(uj, pentest_read_rstmgr_alert_info(uj)); diff --git a/sw/device/tests/penetrationtests/firmware/firmware_sca.c b/sw/device/tests/penetrationtests/firmware/firmware_sca.c index 9747749e98d..5d5ff69d35b 100644 --- a/sw/device/tests/penetrationtests/firmware/firmware_sca.c +++ b/sw/device/tests/penetrationtests/firmware/firmware_sca.c @@ -11,13 +11,13 @@ #include "sw/device/lib/ujson/ujson.h" // Include commands +#include "sw/device/tests/penetrationtests/json/acc_sca_commands.h" #include "sw/device/tests/penetrationtests/json/aes_sca_commands.h" #include "sw/device/tests/penetrationtests/json/commands.h" #include "sw/device/tests/penetrationtests/json/edn_sca_commands.h" #include "sw/device/tests/penetrationtests/json/hmac_sca_commands.h" #include "sw/device/tests/penetrationtests/json/ibex_sca_commands.h" #include "sw/device/tests/penetrationtests/json/kmac_sca_commands.h" -#include "sw/device/tests/penetrationtests/json/otbn_sca_commands.h" #include "sw/device/tests/penetrationtests/json/pentest_lib_commands.h" #include "sw/device/tests/penetrationtests/json/prng_sca_commands.h" #include "sw/device/tests/penetrationtests/json/sha3_sca_commands.h" @@ -26,12 +26,12 @@ // Include handlers #include "sw/device/tests/penetrationtests/firmware/lib/extclk_sca_fi.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" +#include "sw/device/tests/penetrationtests/firmware/sca/acc_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/aes_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/edn_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/hmac_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/ibex_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/kmac_sca.h" -#include "sw/device/tests/penetrationtests/firmware/sca/otbn_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/rng_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/sha3_sca.h" #include "sw/device/tests/penetrationtests/firmware/sca/trigger_sca.h" @@ -64,8 +64,8 @@ status_t process_cmd(ujson_t *uj) { case kPenetrationtestCommandKmacSca: RESP_ERR(uj, handle_kmac_sca(uj)); break; - case kPenetrationtestCommandOtbnSca: - RESP_ERR(uj, handle_otbn_sca(uj)); + case kPenetrationtestCommandAccSca: + RESP_ERR(uj, handle_acc_sca(uj)); break; case kPenetrationtestCommandPrngSca: RESP_ERR(uj, handle_prng_sca(uj)); diff --git a/sw/device/tests/penetrationtests/firmware/lib/BUILD b/sw/device/tests/penetrationtests/firmware/lib/BUILD index d4c08b41681..0f3f01bb07d 100644 --- a/sw/device/tests/penetrationtests/firmware/lib/BUILD +++ b/sw/device/tests/penetrationtests/firmware/lib/BUILD @@ -73,7 +73,7 @@ cc_library( ] + select({ "//sw/device:is_english_breakfast": [], "//conditions:default": [ - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/testing:entropy_testutils", ], }), diff --git a/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.c b/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.c index 1159fdcf00c..f143381847e 100644 --- a/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.c +++ b/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.c @@ -43,16 +43,16 @@ #include "sw/device/silicon_creator/lib/drivers/retention_sram.h" #include "sw/device/silicon_creator/lib/ownership/ownership.h" +#include "hw/top/acc_regs.h" // Generated. #include "hw/top/clkmgr_regs.h" // Generated #include "hw/top/csrng_regs.h" // Generated -#include "hw/top/otbn_regs.h" // Generated. #include "hw/top/rv_core_ibex_regs.h" // Generated #include "hw/top/sensor_ctrl_regs.h" // Generated. #include "hw/top/sram_ctrl_regs.h" // Generated #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #if !OT_IS_ENGLISH_BREAKFAST -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" #include "sw/device/lib/dif/dif_csrng.h" #include "sw/device/lib/dif/dif_edn.h" #include "sw/device/lib/dif/dif_entropy_src.h" @@ -833,7 +833,7 @@ void sca_disable_peripherals(pentest_peripherals_t disable) { } #endif - // Disable HMAC, KMAC, OTBN and USB clocks through CLKMGR DIF. + // Disable HMAC, KMAC, ACC and USB clocks through CLKMGR DIF. dif_clkmgr_t clkmgr; OT_DISCARD(dif_clkmgr_init( mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR), &clkmgr)); @@ -872,9 +872,9 @@ void sca_disable_peripherals(pentest_peripherals_t disable) { OT_DISCARD(dif_clkmgr_hintable_clock_set_hint( &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT, kDifToggleDisabled)); } - if (disable & kPentestPeripheralOtbn) { + if (disable & kPentestPeripheralAcc) { OT_DISCARD(dif_clkmgr_hintable_clock_set_hint( - &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT, kDifToggleDisabled)); + &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_ACC_HINT_BIT, kDifToggleDisabled)); } #endif } @@ -938,7 +938,7 @@ void pentest_set_trigger_low(void) { } void pentest_call_and_sleep(sca_callee callee, uint32_t sleep_cycles, - bool sw_trigger, bool otbn) { + bool sw_trigger, bool acc) { // Disable the IO_DIV4_PERI clock to reduce noise during the actual capture. // This also disables the UART(s) and GPIO modules required for // communication with the scope. Therefore, it has to be re-enabled after @@ -966,8 +966,8 @@ void pentest_call_and_sleep(sca_callee callee, uint32_t sleep_cycles, wait_for_interrupt(); #if !OT_IS_ENGLISH_BREAKFAST - if (otbn) { - OT_DISCARD((otbn_busy_wait_for_done()).value); + if (acc) { + OT_DISCARD((acc_busy_wait_for_done()).value); } #endif diff --git a/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h b/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h index 9b5dbeb0bb9..72877b8b64d 100644 --- a/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h +++ b/sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h @@ -81,9 +81,9 @@ typedef enum pentest_trigger_source { */ kPentestTriggerSourceKmac = 2, /** - * Use OTBN for capture trigger. + * Use ACC for capture trigger. */ - kPentestTriggerSourceOtbn = 3, + kPentestTriggerSourceAcc = 3, } pentest_trigger_source_t; /** @@ -153,9 +153,9 @@ typedef enum pentest_peripheral { */ kPentestPeripheralKmac = 1 << 5, /** - * OTBN. + * ACC. */ - kPentestPeripheralOtbn = 1 << 6, + kPentestPeripheralAcc = 1 << 6, /** * Peripherals using the IO_DIV4_PERI clock (UART, GPIO, I2C, SPI Dev, ...) */ @@ -204,12 +204,12 @@ typedef enum pentest_lfsr_context { } pentest_lfsr_context_t; /** - * Configures the entropy complex for OTBN tests. + * Configures the entropy complex for ACC tests. * * Similar to entropy_testutils_auto_mode_init(), this function inits the * entropy complex. However, in comparison to the function available in the * testutils, this function maximizes the reseed intervall to 0xffffffff. - * This is necessary to guarantee a fixed trigger window for OTBN tests. + * This is necessary to guarantee a fixed trigger window for ACC tests. * * @return OK or error. */ @@ -474,11 +474,11 @@ typedef void (*sca_callee)(void); * @param callee Function to call before putting Ibex to sleep. * @param sleep_cycles Number of cycles to sleep. * @param sw_trigger Raise trigger before calling the target function. - * @param otbn Wait until OTBN execution has finished. Not supported in + * @param acc Wait until ACC execution has finished. Not supported in * ENGLISH_BREAKFAST. */ void pentest_call_and_sleep(sca_callee callee, uint32_t sleep_cycles, - bool sw_trigger, bool otbn); + bool sw_trigger, bool acc); /** * Seeds the software LFSR usable e.g. for key masking. diff --git a/sw/device/tests/penetrationtests/firmware/sca/BUILD b/sw/device/tests/penetrationtests/firmware/sca/BUILD index 1df62c2de75..7ea6a95fb4f 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/BUILD +++ b/sw/device/tests/penetrationtests/firmware/sca/BUILD @@ -121,9 +121,10 @@ cc_library( hdrs = ["ecc256_keygen_sca.h"], deps = [ "//hw/top_earlgrey/sw/autogen:top_earlgrey", + "//sw/acc/crypto:p256_key_from_seed_sca", "//sw/device/lib/base:abs_mmio", "//sw/device/lib/base:memory", - "//sw/device/lib/crypto/drivers:otbn", + "//sw/device/lib/crypto/drivers:acc", "//sw/device/lib/runtime:ibex", "//sw/device/lib/runtime:log", "//sw/device/lib/testing/test_framework:ottf_main", @@ -131,8 +132,7 @@ cc_library( "//sw/device/lib/ujson", "//sw/device/sca/lib:prng", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/device/tests/penetrationtests/json:otbn_sca_commands", - "//sw/otbn/crypto:p256_key_from_seed_sca", + "//sw/device/tests/penetrationtests/json:acc_sca_commands", ], ) @@ -184,10 +184,10 @@ cc_library( ":ecc256_keygen_sca", "//sw/device/lib/base:memory", "//sw/device/lib/base:status", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:aes", "//sw/device/lib/dif:keymgr", "//sw/device/lib/dif:kmac", - "//sw/device/lib/dif:otbn", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:hmac_testutils", "//sw/device/lib/testing:keymgr_testutils", @@ -218,29 +218,29 @@ cc_library( ) cc_library( - name = "otbn_sca", - srcs = ["otbn_sca.c"], - hdrs = ["otbn_sca.h"], + name = "acc_sca", + srcs = ["acc_sca.c"], + hdrs = ["acc_sca.h"], deps = [ ":ecc256_keygen_sca", + "//sw/acc/crypto:p256_ecdsa_sca", + "//sw/acc/crypto:rsa", "//sw/device/lib/base:memory", "//sw/device/lib/base:status", "//sw/device/lib/crypto/drivers:keymgr", "//sw/device/lib/crypto/impl:keyblob", "//sw/device/lib/crypto/impl:status", - "//sw/device/lib/dif:otbn", + "//sw/device/lib/dif:acc", "//sw/device/lib/runtime:log", "//sw/device/lib/testing:keymgr_testutils", "//sw/device/lib/testing/test_framework:ujson_ottf", "//sw/device/lib/ujson", "//sw/device/sca/lib:prng", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", - "//sw/device/tests/penetrationtests/firmware/sca/otbn:otbn_insn_carry_flag", - "//sw/device/tests/penetrationtests/firmware/sca/otbn:otbn_insn_combi_ops", - "//sw/device/tests/penetrationtests/firmware/sca/otbn:otbn_key_sideload_sca", - "//sw/device/tests/penetrationtests/json:otbn_sca_commands", - "//sw/otbn/crypto:p256_ecdsa_sca", - "//sw/otbn/crypto:rsa", + "//sw/device/tests/penetrationtests/firmware/sca/acc:acc_insn_carry_flag", + "//sw/device/tests/penetrationtests/firmware/sca/acc:acc_insn_combi_ops", + "//sw/device/tests/penetrationtests/firmware/sca/acc:acc_key_sideload_sca", + "//sw/device/tests/penetrationtests/json:acc_sca_commands", ], ) diff --git a/sw/device/tests/penetrationtests/firmware/sca/otbn/BUILD b/sw/device/tests/penetrationtests/firmware/sca/acc/BUILD similarity index 50% rename from sw/device/tests/penetrationtests/firmware/sca/otbn/BUILD rename to sw/device/tests/penetrationtests/firmware/sca/acc/BUILD index 33645aea1e4..1d06f5733a8 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/otbn/BUILD +++ b/sw/device/tests/penetrationtests/firmware/sca/acc/BUILD @@ -2,27 +2,27 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -load("//rules:otbn.bzl", "otbn_binary") +load("//rules:acc.bzl", "acc_binary") package(default_visibility = ["//visibility:public"]) -otbn_binary( - name = "otbn_insn_carry_flag", +acc_binary( + name = "acc_insn_carry_flag", srcs = [ - "otbn_insn_carry_flag.s", + "acc_insn_carry_flag.s", ], ) -otbn_binary( - name = "otbn_key_sideload_sca", +acc_binary( + name = "acc_key_sideload_sca", srcs = [ - "otbn_key_sideload_sca.s", + "acc_key_sideload_sca.s", ], ) -otbn_binary( - name = "otbn_insn_combi_ops", +acc_binary( + name = "acc_insn_combi_ops", srcs = [ - "otbn_insn_combi_ops.s", + "acc_insn_combi_ops.s", ], ) diff --git a/sw/device/tests/penetrationtests/firmware/sca/otbn/otbn_insn_carry_flag.s b/sw/device/tests/penetrationtests/firmware/sca/acc/acc_insn_carry_flag.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/sca/otbn/otbn_insn_carry_flag.s rename to sw/device/tests/penetrationtests/firmware/sca/acc/acc_insn_carry_flag.s diff --git a/sw/device/tests/penetrationtests/firmware/sca/otbn/otbn_insn_combi_ops.s b/sw/device/tests/penetrationtests/firmware/sca/acc/acc_insn_combi_ops.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/sca/otbn/otbn_insn_combi_ops.s rename to sw/device/tests/penetrationtests/firmware/sca/acc/acc_insn_combi_ops.s diff --git a/sw/device/tests/penetrationtests/firmware/sca/otbn/otbn_key_sideload_sca.s b/sw/device/tests/penetrationtests/firmware/sca/acc/acc_key_sideload_sca.s similarity index 100% rename from sw/device/tests/penetrationtests/firmware/sca/otbn/otbn_key_sideload_sca.s rename to sw/device/tests/penetrationtests/firmware/sca/acc/acc_key_sideload_sca.s diff --git a/sw/device/tests/penetrationtests/firmware/sca/otbn_sca.c b/sw/device/tests/penetrationtests/firmware/sca/acc_sca.c similarity index 54% rename from sw/device/tests/penetrationtests/firmware/sca/otbn_sca.c rename to sw/device/tests/penetrationtests/firmware/sca/acc_sca.c index 291c37fba6e..6ce1f7e801b 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/otbn_sca.c +++ b/sw/device/tests/penetrationtests/firmware/sca/acc_sca.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#include "sw/device/tests/penetrationtests/firmware/sca/otbn_sca.h" +#include "sw/device/tests/penetrationtests/firmware/sca/acc_sca.h" #include "ecc256_keygen_sca.h" #include "sw/device/lib/arch/boot_stage.h" @@ -11,7 +11,7 @@ #include "sw/device/lib/crypto/drivers/keymgr.h" #include "sw/device/lib/crypto/impl/keyblob.h" #include "sw/device/lib/crypto/impl/status.h" -#include "sw/device/lib/dif/dif_otbn.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/entropy_testutils.h" #include "sw/device/lib/testing/keymgr_testutils.h" @@ -21,15 +21,15 @@ #include "sw/device/lib/ujson/ujson.h" #include "sw/device/sca/lib/prng.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "sw/device/tests/penetrationtests/json/otbn_sca_commands.h" +#include "sw/device/tests/penetrationtests/json/acc_sca_commands.h" -#include "hw/top/otbn_regs.h" // Generated. +#include "hw/top/acc_regs.h" // Generated. #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" #define MAX_BATCH_SIZE 256 #define BYTES_IN_WDR 32 -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_keymgr_t keymgr; static dif_kmac_t kmac; @@ -52,78 +52,77 @@ enum { }; // Data structs for key sideloading test. -OTBN_DECLARE_APP_SYMBOLS(otbn_key_sideload_sca); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload_sca, k_s0_l); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload_sca, k_s0_h); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload_sca, k_s1_l); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload_sca, k_s1_h); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload_sca, k_l); -OTBN_DECLARE_SYMBOL_ADDR(otbn_key_sideload_sca, k_h); -const otbn_app_t kOtbnAppKeySideloadSca = - OTBN_APP_T_INIT(otbn_key_sideload_sca); -static const otbn_addr_t kOtbnAppKeySideloadks0l = - OTBN_ADDR_T_INIT(otbn_key_sideload_sca, k_s0_l); -static const otbn_addr_t kOtbnAppKeySideloadks0h = - OTBN_ADDR_T_INIT(otbn_key_sideload_sca, k_s0_h); -static const otbn_addr_t kOtbnAppKeySideloadks1l = - OTBN_ADDR_T_INIT(otbn_key_sideload_sca, k_s1_l); -static const otbn_addr_t kOtbnAppKeySideloadks1h = - OTBN_ADDR_T_INIT(otbn_key_sideload_sca, k_s1_h); -static const otbn_addr_t kOtbnAppKeySideloadkl = - OTBN_ADDR_T_INIT(otbn_key_sideload_sca, k_l); -static const otbn_addr_t kOtbnAppKeySideloadkh = - OTBN_ADDR_T_INIT(otbn_key_sideload_sca, k_h); - -// RSA OTBN App. -OTBN_DECLARE_APP_SYMBOLS(rsa); -OTBN_DECLARE_SYMBOL_ADDR(rsa, mode); -OTBN_DECLARE_SYMBOL_ADDR(rsa, n_limbs); -OTBN_DECLARE_SYMBOL_ADDR(rsa, inout); -OTBN_DECLARE_SYMBOL_ADDR(rsa, modulus); -OTBN_DECLARE_SYMBOL_ADDR(rsa, exp); - -static const otbn_app_t kOtbnAppRsa = OTBN_APP_T_INIT(rsa); -static const otbn_addr_t kOtbnVarRsaMode = OTBN_ADDR_T_INIT(rsa, mode); -static const otbn_addr_t kOtbnVarRsaNLimbs = OTBN_ADDR_T_INIT(rsa, n_limbs); -static const otbn_addr_t kOtbnVarRsaInOut = OTBN_ADDR_T_INIT(rsa, inout); -static const otbn_addr_t kOtbnVarRsaModulus = OTBN_ADDR_T_INIT(rsa, modulus); -static const otbn_addr_t kOtbnVarRsaExp = OTBN_ADDR_T_INIT(rsa, exp); +ACC_DECLARE_APP_SYMBOLS(acc_key_sideload_sca); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload_sca, k_s0_l); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload_sca, k_s0_h); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload_sca, k_s1_l); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload_sca, k_s1_h); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload_sca, k_l); +ACC_DECLARE_SYMBOL_ADDR(acc_key_sideload_sca, k_h); +const acc_app_t kAccAppKeySideloadSca = ACC_APP_T_INIT(acc_key_sideload_sca); +static const acc_addr_t kAccAppKeySideloadks0l = + ACC_ADDR_T_INIT(acc_key_sideload_sca, k_s0_l); +static const acc_addr_t kAccAppKeySideloadks0h = + ACC_ADDR_T_INIT(acc_key_sideload_sca, k_s0_h); +static const acc_addr_t kAccAppKeySideloadks1l = + ACC_ADDR_T_INIT(acc_key_sideload_sca, k_s1_l); +static const acc_addr_t kAccAppKeySideloadks1h = + ACC_ADDR_T_INIT(acc_key_sideload_sca, k_s1_h); +static const acc_addr_t kAccAppKeySideloadkl = + ACC_ADDR_T_INIT(acc_key_sideload_sca, k_l); +static const acc_addr_t kAccAppKeySideloadkh = + ACC_ADDR_T_INIT(acc_key_sideload_sca, k_h); + +// RSA ACC App. +ACC_DECLARE_APP_SYMBOLS(rsa); +ACC_DECLARE_SYMBOL_ADDR(rsa, mode); +ACC_DECLARE_SYMBOL_ADDR(rsa, n_limbs); +ACC_DECLARE_SYMBOL_ADDR(rsa, inout); +ACC_DECLARE_SYMBOL_ADDR(rsa, modulus); +ACC_DECLARE_SYMBOL_ADDR(rsa, exp); + +static const acc_app_t kAccAppRsa = ACC_APP_T_INIT(rsa); +static const acc_addr_t kAccVarRsaMode = ACC_ADDR_T_INIT(rsa, mode); +static const acc_addr_t kAccVarRsaNLimbs = ACC_ADDR_T_INIT(rsa, n_limbs); +static const acc_addr_t kAccVarRsaInOut = ACC_ADDR_T_INIT(rsa, inout); +static const acc_addr_t kAccVarRsaModulus = ACC_ADDR_T_INIT(rsa, modulus); +static const acc_addr_t kAccVarRsaExp = ACC_ADDR_T_INIT(rsa, exp); // p256_ecdsa_sca has randomization removed. -OTBN_DECLARE_APP_SYMBOLS(p256_ecdsa_sca); - -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, mode); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, msg); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, r); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, s); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, y); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d0); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d1); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k0); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k1); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x_r); - -static const otbn_app_t kOtbnAppP256Ecdsa = OTBN_APP_T_INIT(p256_ecdsa_sca); - -static const otbn_addr_t kOtbnVarMode = OTBN_ADDR_T_INIT(p256_ecdsa_sca, mode); -static const otbn_addr_t kOtbnVarMsg = OTBN_ADDR_T_INIT(p256_ecdsa_sca, msg); -static const otbn_addr_t kOtbnVarR = OTBN_ADDR_T_INIT(p256_ecdsa_sca, r); -static const otbn_addr_t kOtbnVarS = OTBN_ADDR_T_INIT(p256_ecdsa_sca, s); -static const otbn_addr_t kOtbnVarD0 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, d0); -static const otbn_addr_t kOtbnVarD1 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, d1); -static const otbn_addr_t kOtbnVarK0 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, k0); -static const otbn_addr_t kOtbnVarK1 = OTBN_ADDR_T_INIT(p256_ecdsa_sca, k1); +ACC_DECLARE_APP_SYMBOLS(p256_ecdsa_sca); + +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, mode); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, msg); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, r); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, s); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, y); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d0); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, d1); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k0); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, k1); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, x_r); + +static const acc_app_t kAccAppP256Ecdsa = ACC_APP_T_INIT(p256_ecdsa_sca); + +static const acc_addr_t kAccVarMode = ACC_ADDR_T_INIT(p256_ecdsa_sca, mode); +static const acc_addr_t kAccVarMsg = ACC_ADDR_T_INIT(p256_ecdsa_sca, msg); +static const acc_addr_t kAccVarR = ACC_ADDR_T_INIT(p256_ecdsa_sca, r); +static const acc_addr_t kAccVarS = ACC_ADDR_T_INIT(p256_ecdsa_sca, s); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(p256_ecdsa_sca, d0); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(p256_ecdsa_sca, d1); +static const acc_addr_t kAccVarK0 = ACC_ADDR_T_INIT(p256_ecdsa_sca, k0); +static const acc_addr_t kAccVarK1 = ACC_ADDR_T_INIT(p256_ecdsa_sca, k1); /** - * Clears the OTBN DMEM and IMEM. + * Clears the ACC DMEM and IMEM. * * @returns OK or error. */ -static status_t clear_otbn(void) { - // Clear OTBN memory. - TRY(otbn_dmem_sec_wipe()); - TRY(otbn_imem_sec_wipe()); +static status_t clear_acc(void) { + // Clear ACC memory. + TRY(acc_dmem_sec_wipe()); + TRY(acc_imem_sec_wipe()); return OK_STATUS(); } @@ -177,7 +176,7 @@ void gen_fvsr_data(uint32_t *dest_array, bool fixed, uint32_t *src_fixed_array, * r = x-coordinate of R * s = k^(-1)(msg + r*d) mod n * - * @param otbn_ctx The OTBN context object. + * @param acc_ctx The ACC context object. * @param msg The message to sign, msg (32B). * @param private_key_d The private key, d (32B). * @param k The ephemeral key, k (random scalar) (32B). @@ -191,43 +190,42 @@ static status_t p256_ecdsa_sign(const uint32_t *msg, uint32_t *signature_r, uint32_t *signature_s, const uint32_t *k) { uint32_t mode = 1; // mode 1 => sign - // Send operation mode to OTBN - TRY(otbn_dmem_write(/*num_words=*/1, &mode, kOtbnVarMode)); - // Send Msg to OTBN - TRY(otbn_dmem_write(kEcc256NumWords, msg, kOtbnVarMsg)); - // Send two shares of private_key_d to OTBN - TRY(otbn_dmem_write(kEcc256NumWords, private_key_d, kOtbnVarD0)); - TRY(otbn_dmem_write(kEcc256NumWords, private_key_d + kEcc256NumWords, - kOtbnVarD1)); - // Send two shares of secret_k to OTBN - TRY(otbn_dmem_write(kEcc256NumWords, k, kOtbnVarK0)); - TRY(otbn_dmem_write(kEcc256NumWords, k + kEcc256NumWords, kOtbnVarK1)); - - // Start OTBN execution + // Send operation mode to ACC + TRY(acc_dmem_write(/*num_words=*/1, &mode, kAccVarMode)); + // Send Msg to ACC + TRY(acc_dmem_write(kEcc256NumWords, msg, kAccVarMsg)); + // Send two shares of private_key_d to ACC + TRY(acc_dmem_write(kEcc256NumWords, private_key_d, kAccVarD0)); + TRY(acc_dmem_write(kEcc256NumWords, private_key_d + kEcc256NumWords, + kAccVarD1)); + // Send two shares of secret_k to ACC + TRY(acc_dmem_write(kEcc256NumWords, k, kAccVarK0)); + TRY(acc_dmem_write(kEcc256NumWords, k + kEcc256NumWords, kAccVarK1)); + + // Start ACC execution pentest_set_trigger_high(); // Give the trigger time to rise. asm volatile(NOP30); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Read the results back (sig_r, sig_s) - TRY(otbn_dmem_read(kEcc256NumWords, kOtbnVarR, signature_r)); - TRY(otbn_dmem_read(kEcc256NumWords, kOtbnVarS, signature_s)); + TRY(acc_dmem_read(kEcc256NumWords, kAccVarR, signature_r)); + TRY(acc_dmem_read(kEcc256NumWords, kAccVarS, signature_s)); return OK_STATUS(); } -status_t handle_otbn_sca_ecdsa_p256_sign(ujson_t *uj) { +status_t handle_acc_sca_ecdsa_p256_sign(ujson_t *uj) { // Get masks off or on. - penetrationtest_otbn_sca_en_masks_t uj_data_masks; - TRY(ujson_deserialize_penetrationtest_otbn_sca_en_masks_t(uj, - &uj_data_masks)); + penetrationtest_acc_sca_en_masks_t uj_data_masks; + TRY(ujson_deserialize_penetrationtest_acc_sca_en_masks_t(uj, &uj_data_masks)); // Get message and key. - penetrationtest_otbn_sca_ecdsa_p256_sign_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_ecdsa_p256_sign_t(uj, - &uj_data)); + penetrationtest_acc_sca_ecdsa_p256_sign_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_ecdsa_p256_sign_t(uj, + &uj_data)); // Set of share d1 for masking. uint32_t ecc256_private_key_d1[kEcc256NumWords]; @@ -263,7 +261,7 @@ status_t handle_otbn_sca_ecdsa_p256_sign(ujson_t *uj) { memcpy(ecc256_secret_k + kEcc256NumWords, ecc256_secret_k1, sizeof(ecc256_secret_k1)); - TRY(otbn_load_app(kOtbnAppP256Ecdsa)); + TRY(acc_load_app(kAccAppP256Ecdsa)); // Signature output. uint32_t ecc256_signature_r[kEcc256NumWords]; @@ -274,22 +272,22 @@ status_t handle_otbn_sca_ecdsa_p256_sign(ujson_t *uj) { ecc256_signature_s, ecc256_secret_k); // Send back signature to host. - penetrationtest_otbn_sca_ecdsa_p256_signature_t uj_output; + penetrationtest_acc_sca_ecdsa_p256_signature_t uj_output; memcpy(uj_output.r, ecc256_signature_r, sizeof(ecc256_signature_r)); memcpy(uj_output.s, ecc256_signature_s, sizeof(ecc256_signature_s)); - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_ecdsa_p256_signature_t, uj, + RESP_OK(ujson_serialize_penetrationtest_acc_sca_ecdsa_p256_signature_t, uj, &uj_output); - // Clear OTBN memory - TRY(clear_otbn()); + // Clear ACC memory + TRY(clear_acc()); return OK_STATUS(); } -status_t handle_otbn_sca_ecdsa_p256_sign_batch(ujson_t *uj) { +status_t handle_acc_sca_ecdsa_p256_sign_batch(ujson_t *uj) { // Get number of traces. - penetrationtest_otbn_sca_num_traces_t uj_data_num_traces; - TRY(ujson_deserialize_penetrationtest_otbn_sca_num_traces_t( + penetrationtest_acc_sca_num_traces_t uj_data_num_traces; + TRY(ujson_deserialize_penetrationtest_acc_sca_num_traces_t( uj, &uj_data_num_traces)); if (uj_data_num_traces.num_traces > kNumBatchOpsMax) { @@ -297,9 +295,8 @@ status_t handle_otbn_sca_ecdsa_p256_sign_batch(ujson_t *uj) { } // Get masks off or on. - penetrationtest_otbn_sca_en_masks_t uj_data_masks; - TRY(ujson_deserialize_penetrationtest_otbn_sca_en_masks_t(uj, - &uj_data_masks)); + penetrationtest_acc_sca_en_masks_t uj_data_masks; + TRY(ujson_deserialize_penetrationtest_acc_sca_en_masks_t(uj, &uj_data_masks)); // Create random message, k, and d. uint32_t ecc256_message_batch[kNumBatchOpsMax][kEcc256NumWords]; @@ -351,7 +348,7 @@ status_t handle_otbn_sca_ecdsa_p256_sign_batch(ujson_t *uj) { uint32_t ecc256_signature_s[kEcc256NumWords]; // Run num_traces ECDSA operations. for (size_t i = 0; i < uj_data_num_traces.num_traces; ++i) { - TRY(otbn_load_app(kOtbnAppP256Ecdsa)); + TRY(acc_load_app(kAccAppP256Ecdsa)); // Start the operation. p256_ecdsa_sign(ecc256_message_batch[i], ecc256_private_key_d_batch[i], @@ -360,22 +357,22 @@ status_t handle_otbn_sca_ecdsa_p256_sign_batch(ujson_t *uj) { } // Send back the last signature to host. - penetrationtest_otbn_sca_ecdsa_p256_signature_t uj_output; + penetrationtest_acc_sca_ecdsa_p256_signature_t uj_output; memcpy(uj_output.r, ecc256_signature_r, sizeof(ecc256_signature_r)); memcpy(uj_output.s, ecc256_signature_s, sizeof(ecc256_signature_s)); - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_ecdsa_p256_signature_t, uj, + RESP_OK(ujson_serialize_penetrationtest_acc_sca_ecdsa_p256_signature_t, uj, &uj_output); - // Clear OTBN memory - TRY(clear_otbn()); + // Clear ACC memory + TRY(clear_acc()); return OK_STATUS(); } -status_t handle_otbn_sca_ecdsa_p256_sign_fvsr_batch(ujson_t *uj) { +status_t handle_acc_sca_ecdsa_p256_sign_fvsr_batch(ujson_t *uj) { // Get number of traces. - penetrationtest_otbn_sca_num_traces_t uj_data_num_traces; - TRY(ujson_deserialize_penetrationtest_otbn_sca_num_traces_t( + penetrationtest_acc_sca_num_traces_t uj_data_num_traces; + TRY(ujson_deserialize_penetrationtest_acc_sca_num_traces_t( uj, &uj_data_num_traces)); if (uj_data_num_traces.num_traces > kNumBatchOpsMax) { @@ -383,14 +380,13 @@ status_t handle_otbn_sca_ecdsa_p256_sign_fvsr_batch(ujson_t *uj) { } // Get masks off or on. - penetrationtest_otbn_sca_en_masks_t uj_data_masks; - TRY(ujson_deserialize_penetrationtest_otbn_sca_en_masks_t(uj, - &uj_data_masks)); + penetrationtest_acc_sca_en_masks_t uj_data_masks; + TRY(ujson_deserialize_penetrationtest_acc_sca_en_masks_t(uj, &uj_data_masks)); // Get fixed message and key. - penetrationtest_otbn_sca_ecdsa_p256_sign_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_ecdsa_p256_sign_t(uj, - &uj_data)); + penetrationtest_acc_sca_ecdsa_p256_sign_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_ecdsa_p256_sign_t(uj, + &uj_data)); uint32_t ecc256_message_batch[kNumBatchOpsMax][kEcc256NumWords]; @@ -452,7 +448,7 @@ status_t handle_otbn_sca_ecdsa_p256_sign_fvsr_batch(ujson_t *uj) { uint32_t ecc256_signature_s[kEcc256NumWords]; // Run num_traces ECDSA operations. for (size_t i = 0; i < uj_data_num_traces.num_traces; ++i) { - TRY(otbn_load_app(kOtbnAppP256Ecdsa)); + TRY(acc_load_app(kAccAppP256Ecdsa)); // Start the operation. p256_ecdsa_sign(uj_data.msg, ecc256_private_key_d_batch[i], @@ -461,33 +457,33 @@ status_t handle_otbn_sca_ecdsa_p256_sign_fvsr_batch(ujson_t *uj) { } // Send back the last signature to host. - penetrationtest_otbn_sca_ecdsa_p256_signature_t uj_output; + penetrationtest_acc_sca_ecdsa_p256_signature_t uj_output; memcpy(uj_output.r, ecc256_signature_r, sizeof(ecc256_signature_r)); memcpy(uj_output.s, ecc256_signature_s, sizeof(ecc256_signature_s)); - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_ecdsa_p256_signature_t, uj, + RESP_OK(ujson_serialize_penetrationtest_acc_sca_ecdsa_p256_signature_t, uj, &uj_output); - // Clear OTBN memory - TRY(clear_otbn()); + // Clear ACC memory + TRY(clear_acc()); return OK_STATUS(); } -status_t handle_otbn_pentest_init(ujson_t *uj) { +status_t handle_acc_pentest_init(ujson_t *uj) { penetrationtest_cpuctrl_t uj_cpuctrl_data; TRY(ujson_deserialize_penetrationtest_cpuctrl_t(uj, &uj_cpuctrl_data)); penetrationtest_sensor_config_t uj_sensor_data; TRY(ujson_deserialize_penetrationtest_sensor_config_t(uj, &uj_sensor_data)); - // Configure the entropy complex for OTBN. Set the reseed interval to max + // Configure the entropy complex for ACC. Set the reseed interval to max // to avoid a non-constant trigger window. TRY(pentest_configure_entropy_source_max_reseed_interval()); - // Init the OTBN core. - TRY(dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + // Init the ACC core. + TRY(dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); - // Load p256 keygen from seed app into OTBN. - if (otbn_load_app(kOtbnAppP256KeyFromSeed).value != OTCRYPTO_OK.value) { + // Load p256 keygen from seed app into ACC. + if (acc_load_app(kAccAppP256KeyFromSeed).value != OTCRYPTO_OK.value) { return ABORTED(); } @@ -503,9 +499,9 @@ status_t handle_otbn_pentest_init(ujson_t *uj) { &uj_output.sram_ret_readback_en, uj_cpuctrl_data.enable_data_ind_timing, &uj_output.data_ind_timing_en)); - pentest_init(kPentestTriggerSourceOtbn, + pentest_init(kPentestTriggerSourceAcc, kPentestPeripheralEntropy | kPentestPeripheralIoDiv4 | - kPentestPeripheralOtbn | kPentestPeripheralCsrng | + kPentestPeripheralAcc | kPentestPeripheralCsrng | kPentestPeripheralEdn, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); @@ -523,7 +519,7 @@ status_t handle_otbn_pentest_init(ujson_t *uj) { return OK_STATUS(); } -status_t handle_otbn_pentest_init_keymgr(ujson_t *uj) { +status_t handle_acc_pentest_init_keymgr(ujson_t *uj) { if (kBootStage != kBootStageOwner) { TRY(keymgr_testutils_startup(&keymgr, &kmac)); // Advance to OwnerIntermediateKey state. @@ -537,137 +533,137 @@ status_t handle_otbn_pentest_init_keymgr(ujson_t *uj) { TRY(keymgr_testutils_check_state(&keymgr, kDifKeymgrStateOwnerRootKey)); } - dif_otbn_t otbn; - TRY(dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + dif_acc_t acc; + TRY(dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); return OK_STATUS(); } -status_t handle_otbn_sca_insn_carry_flag(ujson_t *uj) { +status_t handle_acc_sca_insn_carry_flag(ujson_t *uj) { // Get big number (256 bit). - penetrationtest_otbn_sca_big_num_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_big_num_t(uj, &uj_data)); + penetrationtest_acc_sca_big_num_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_big_num_t(uj, &uj_data)); - // INSN Carry Flag OTBN App. - OTBN_DECLARE_APP_SYMBOLS(otbn_insn_carry_flag); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_carry_flag, big_num); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_carry_flag, big_num_out); + // INSN Carry Flag ACC App. + ACC_DECLARE_APP_SYMBOLS(acc_insn_carry_flag); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_carry_flag, big_num); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_carry_flag, big_num_out); - static const otbn_app_t kOtbnAppInsnCarryFlag = - OTBN_APP_T_INIT(otbn_insn_carry_flag); - static const otbn_addr_t kOtbnVarInsnCarryFlagBigNum = - OTBN_ADDR_T_INIT(otbn_insn_carry_flag, big_num); - static const otbn_addr_t kOtbnVarInsnCarryFlagBigNumOut = - OTBN_ADDR_T_INIT(otbn_insn_carry_flag, big_num_out); + static const acc_app_t kAccAppInsnCarryFlag = + ACC_APP_T_INIT(acc_insn_carry_flag); + static const acc_addr_t kAccVarInsnCarryFlagBigNum = + ACC_ADDR_T_INIT(acc_insn_carry_flag, big_num); + static const acc_addr_t kAccVarInsnCarryFlagBigNumOut = + ACC_ADDR_T_INIT(acc_insn_carry_flag, big_num_out); // Load app and write received big_num into DMEM. - TRY(otbn_load_app(kOtbnAppInsnCarryFlag)); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarInsnCarryFlagBigNum, uj_data.big_num, - sizeof(uj_data.big_num))); + TRY(acc_load_app(kAccAppInsnCarryFlag)); + TRY(dif_acc_dmem_write(&acc, kAccVarInsnCarryFlagBigNum, uj_data.big_num, + sizeof(uj_data.big_num))); pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); - penetrationtest_otbn_sca_big_num_t uj_output; + penetrationtest_acc_sca_big_num_t uj_output; memset(uj_output.big_num, 0, sizeof(uj_output.big_num)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCarryFlagBigNumOut, - uj_output.big_num, sizeof(uj_output.big_num))); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCarryFlagBigNumOut, uj_output.big_num, + sizeof(uj_output.big_num))); - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_big_num_t, uj, &uj_output); + RESP_OK(ujson_serialize_penetrationtest_acc_sca_big_num_t, uj, &uj_output); return OK_STATUS(); } -status_t trigger_otbn_sca_combi_operations( +status_t trigger_acc_sca_combi_operations( uint32_t value1, uint32_t value2, uint32_t result1[8], uint32_t result2[8], uint32_t result3[8], uint32_t result4[8], uint32_t result5[8], uint32_t result6[8], uint32_t result7[8], uint32_t *result8, uint32_t trigger) { - // INSN Combi Ops OTBN App. - OTBN_DECLARE_APP_SYMBOLS(otbn_insn_combi_ops); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, big_input_1); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, big_input_2); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_1); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_2); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_3); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_4); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_5); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_6); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_7); - OTBN_DECLARE_SYMBOL_ADDR(otbn_insn_combi_ops, result_8); - - static const otbn_app_t kOtbnAppInsnCombiOps = - OTBN_APP_T_INIT(otbn_insn_combi_ops); - static const otbn_addr_t kOtbnVarInsnCombiOpsValue1 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, big_input_1); - static const otbn_addr_t kOtbnVarInsnCombiOpsValue2 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, big_input_2); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult1 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_1); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult2 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_2); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult3 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_3); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult4 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_4); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult5 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_5); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult6 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_6); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult7 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_7); - static const otbn_addr_t kOtbnVarInsnCombiOpsResult8 = - OTBN_ADDR_T_INIT(otbn_insn_combi_ops, result_8); + // INSN Combi Ops ACC App. + ACC_DECLARE_APP_SYMBOLS(acc_insn_combi_ops); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, big_input_1); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, big_input_2); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_1); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_2); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_3); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_4); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_5); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_6); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_7); + ACC_DECLARE_SYMBOL_ADDR(acc_insn_combi_ops, result_8); + + static const acc_app_t kAccAppInsnCombiOps = + ACC_APP_T_INIT(acc_insn_combi_ops); + static const acc_addr_t kAccVarInsnCombiOpsValue1 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, big_input_1); + static const acc_addr_t kAccVarInsnCombiOpsValue2 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, big_input_2); + static const acc_addr_t kAccVarInsnCombiOpsResult1 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_1); + static const acc_addr_t kAccVarInsnCombiOpsResult2 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_2); + static const acc_addr_t kAccVarInsnCombiOpsResult3 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_3); + static const acc_addr_t kAccVarInsnCombiOpsResult4 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_4); + static const acc_addr_t kAccVarInsnCombiOpsResult5 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_5); + static const acc_addr_t kAccVarInsnCombiOpsResult6 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_6); + static const acc_addr_t kAccVarInsnCombiOpsResult7 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_7); + static const acc_addr_t kAccVarInsnCombiOpsResult8 = + ACC_ADDR_T_INIT(acc_insn_combi_ops, result_8); // Load app and write received big_num into DMEM. - TRY(otbn_load_app(kOtbnAppInsnCombiOps)); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarInsnCombiOpsValue1, &value1, - sizeof(value1))); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarInsnCombiOpsValue2, &value2, - sizeof(value2))); + TRY(acc_load_app(kAccAppInsnCombiOps)); + TRY(dif_acc_dmem_write(&acc, kAccVarInsnCombiOpsValue1, &value1, + sizeof(value1))); + TRY(dif_acc_dmem_write(&acc, kAccVarInsnCombiOpsValue2, &value2, + sizeof(value2))); if (trigger & 0x1) pentest_set_trigger_high(); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); if (trigger & 0x1) pentest_set_trigger_low(); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult1, &result1[0], - BYTES_IN_WDR)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult2, &result2[0], - BYTES_IN_WDR)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult3, &result3[0], - BYTES_IN_WDR)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult4, &result4[0], - BYTES_IN_WDR)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult5, &result5[0], - BYTES_IN_WDR)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult6, &result6[0], - BYTES_IN_WDR)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult7, &result7[0], - BYTES_IN_WDR)); - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarInsnCombiOpsResult8, &result8[0], - sizeof(*result8))); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult1, &result1[0], + BYTES_IN_WDR)); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult2, &result2[0], + BYTES_IN_WDR)); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult3, &result3[0], + BYTES_IN_WDR)); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult4, &result4[0], + BYTES_IN_WDR)); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult5, &result5[0], + BYTES_IN_WDR)); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult6, &result6[0], + BYTES_IN_WDR)); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult7, &result7[0], + BYTES_IN_WDR)); + TRY(dif_acc_dmem_read(&acc, kAccVarInsnCombiOpsResult8, &result8[0], + sizeof(*result8))); if (trigger & 0x2) pentest_set_trigger_high(); - TRY(otbn_dmem_sec_wipe()); + TRY(acc_dmem_sec_wipe()); if (trigger & 0x2) pentest_set_trigger_low(); return OK_STATUS(); } -status_t handle_otbn_sca_combi_operations_batch(ujson_t *uj) { +status_t handle_acc_sca_combi_operations_batch(ujson_t *uj) { // Get number of iterations and fixed data. - otbn_sca_test_batch_ops_t uj_data; - TRY(ujson_deserialize_otbn_sca_test_batch_ops_t(uj, &uj_data)); + acc_sca_test_batch_ops_t uj_data; + TRY(ujson_deserialize_acc_sca_test_batch_ops_t(uj, &uj_data)); TRY_CHECK(uj_data.num_iterations < MAX_BATCH_SIZE); - otbn_sca_ops_result_t uj_output; + acc_sca_ops_result_t uj_output; // SCA code target. for (size_t it = 0; it < uj_data.num_iterations; it++) { @@ -681,7 +677,7 @@ status_t handle_otbn_sca_combi_operations_batch(ujson_t *uj) { memset(uj_output.result7, 0, sizeof(uj_output.result7)); uj_output.result8 = 0; // Call the target code sequence. - TRY(trigger_otbn_sca_combi_operations( + TRY(trigger_acc_sca_combi_operations( uj_data.fixed_data1, uj_data.fixed_data2, uj_output.result1, uj_output.result2, uj_output.result3, uj_output.result4, uj_output.result5, uj_output.result6, uj_output.result7, @@ -690,19 +686,19 @@ status_t handle_otbn_sca_combi_operations_batch(ujson_t *uj) { // Write back last values to validate generated data if asked for. if (uj_data.print_flag) { - RESP_OK(ujson_serialize_otbn_sca_ops_result_t, uj, &uj_output); + RESP_OK(ujson_serialize_acc_sca_ops_result_t, uj, &uj_output); } else { - otbn_sca_empty_t uj_empty; + acc_sca_empty_t uj_empty; uj_empty.success = true; - RESP_OK(ujson_serialize_otbn_sca_empty_t, uj, &uj_empty); + RESP_OK(ujson_serialize_acc_sca_empty_t, uj, &uj_empty); } return OK_STATUS(); } -status_t handle_otbn_sca_key_sideload_fvsr(ujson_t *uj) { +status_t handle_acc_sca_key_sideload_fvsr(ujson_t *uj) { // Get fixed seed. - penetrationtest_otbn_sca_fixed_seed_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_fixed_seed_t(uj, &uj_data)); + penetrationtest_acc_sca_fixed_seed_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_fixed_seed_t(uj, &uj_data)); // Key generation parameters. dif_keymgr_versioned_key_params_t sideload_params[kKeySideloadNumIt]; @@ -711,7 +707,7 @@ status_t handle_otbn_sca_key_sideload_fvsr(ujson_t *uj) { bool sample_fixed = true; for (size_t it = 0; it < kKeySideloadNumIt; it++) { sideload_params[it].version = 0x0; - sideload_params[it].dest = kDifKeymgrVersionedKeyDestOtbn; + sideload_params[it].dest = kDifKeymgrVersionedKeyDestAcc; memset(sideload_params[it].salt, 0, sizeof(sideload_params[it].salt)); if (sample_fixed) { sideload_params[it].salt[0] = uj_data.fixed_seed; @@ -721,7 +717,7 @@ status_t handle_otbn_sca_key_sideload_fvsr(ujson_t *uj) { sample_fixed = prng_rand_uint32() & 0x1; } - TRY(otbn_load_app(kOtbnAppKeySideloadSca)); + TRY(acc_load_app(kAccAppKeySideloadSca)); uint32_t key_share_0_l[kKeySideloadNumIt], key_share_0_h[kKeySideloadNumIt]; uint32_t key_share_1_l[16], key_share_1_h[kKeySideloadNumIt]; @@ -731,26 +727,26 @@ status_t handle_otbn_sca_key_sideload_fvsr(ujson_t *uj) { for (size_t it = 0; it < kKeySideloadNumIt; it++) { TRY(keymgr_testutils_generate_versioned_key(&keymgr, sideload_params[it])); - TRY(dif_otbn_set_ctrl_software_errs_fatal(&otbn, /*enable=*/false)); + TRY(dif_acc_set_ctrl_software_errs_fatal(&acc, /*enable=*/false)); pentest_set_trigger_high(); // Give the trigger time to rise. asm volatile(NOP30); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); asm volatile(NOP30); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks0l, &key_share_0_l[it])); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks0h, &key_share_0_h[it])); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks1l, &key_share_1_l[it])); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadks1h, &key_share_1_h[it])); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadkl, &key_l[it])); - TRY(otbn_dmem_read(1, kOtbnAppKeySideloadkh, &key_h[it])); + TRY(acc_dmem_read(1, kAccAppKeySideloadks0l, &key_share_0_l[it])); + TRY(acc_dmem_read(1, kAccAppKeySideloadks0h, &key_share_0_h[it])); + TRY(acc_dmem_read(1, kAccAppKeySideloadks1l, &key_share_1_l[it])); + TRY(acc_dmem_read(1, kAccAppKeySideloadks1h, &key_share_1_h[it])); + TRY(acc_dmem_read(1, kAccAppKeySideloadkl, &key_l[it])); + TRY(acc_dmem_read(1, kAccAppKeySideloadkh, &key_h[it])); } // Write back shares and keys to host. - penetrationtest_otbn_sca_key_t uj_output; + penetrationtest_acc_sca_key_t uj_output; for (size_t it = 0; it < kKeySideloadNumIt; it++) { uj_output.shares[0] = key_share_0_l[it]; uj_output.shares[1] = key_share_0_h[it]; @@ -758,82 +754,82 @@ status_t handle_otbn_sca_key_sideload_fvsr(ujson_t *uj) { uj_output.shares[3] = key_share_1_h[it]; uj_output.keys[0] = key_l[it]; uj_output.keys[1] = key_h[it]; - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_key_t, uj, &uj_output); + RESP_OK(ujson_serialize_penetrationtest_acc_sca_key_t, uj, &uj_output); } return OK_STATUS(); } -status_t handle_otbn_sca_rsa512_decrypt(ujson_t *uj) { +status_t handle_acc_sca_rsa512_decrypt(ujson_t *uj) { // Get RSA256 parameters. - penetrationtest_otbn_sca_rsa512_dec_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_rsa512_dec_t(uj, &uj_data)); - TRY(otbn_load_app(kOtbnAppRsa)); + penetrationtest_acc_sca_rsa512_dec_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_rsa512_dec_t(uj, &uj_data)); + TRY(acc_load_app(kAccAppRsa)); uint32_t mode = 2; // Decrypt. // RSA512 configuration. uint32_t n_limbs = 2; - // Write data into OTBN DMEM. - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarRsaMode, &mode, sizeof(mode))); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarRsaNLimbs, &n_limbs, sizeof(n_limbs))); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarRsaModulus, uj_data.modu, - sizeof(uj_data.modu))); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarRsaExp, uj_data.exp, - sizeof(uj_data.exp))); - TRY(dif_otbn_dmem_write(&otbn, kOtbnVarRsaInOut, uj_data.msg, - sizeof(uj_data.msg))); + // Write data into ACC DMEM. + TRY(dif_acc_dmem_write(&acc, kAccVarRsaMode, &mode, sizeof(mode))); + TRY(dif_acc_dmem_write(&acc, kAccVarRsaNLimbs, &n_limbs, sizeof(n_limbs))); + TRY(dif_acc_dmem_write(&acc, kAccVarRsaModulus, uj_data.modu, + sizeof(uj_data.modu))); + TRY(dif_acc_dmem_write(&acc, kAccVarRsaExp, uj_data.exp, + sizeof(uj_data.exp))); + TRY(dif_acc_dmem_write(&acc, kAccVarRsaInOut, uj_data.msg, + sizeof(uj_data.msg))); pentest_set_trigger_high(); // Give the trigger time to rise. asm volatile(NOP30); - TRY(otbn_execute()); - TRY(otbn_busy_wait_for_done()); + TRY(acc_execute()); + TRY(acc_busy_wait_for_done()); pentest_set_trigger_low(); // Send back decryption result to host. - penetrationtest_otbn_sca_rsa512_dec_out_t uj_output; - TRY(dif_otbn_dmem_read(&otbn, kOtbnVarRsaInOut, uj_output.out, - sizeof(uj_output.out))); - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_rsa512_dec_out_t, uj, + penetrationtest_acc_sca_rsa512_dec_out_t uj_output; + TRY(dif_acc_dmem_read(&acc, kAccVarRsaInOut, uj_output.out, + sizeof(uj_output.out))); + RESP_OK(ujson_serialize_penetrationtest_acc_sca_rsa512_dec_out_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_sca(ujson_t *uj) { - otbn_sca_subcommand_t cmd; - TRY(ujson_deserialize_otbn_sca_subcommand_t(uj, &cmd)); +status_t handle_acc_sca(ujson_t *uj) { + acc_sca_subcommand_t cmd; + TRY(ujson_deserialize_acc_sca_subcommand_t(uj, &cmd)); switch (cmd) { - case kOtbnScaSubcommandEcc256EcdsaKeygenFvsrKeyBatch: - return handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_key_batch(uj); - case kOtbnScaSubcommandEcc256EcdsaKeygenFvsrSeedBatch: - return handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(uj); - case kOtbnScaSubcommandEcc256EnMasks: - return handle_otbn_sca_ecc256_en_masks(uj); - case kOtbnScaSubcommandEcc256SetC: - return handle_otbn_sca_ecc256_set_c(uj); - case kOtbnScaSubcommandEcc256SetSeed: - return handle_otbn_sca_ecc256_set_seed(uj); - case kOtbnScaSubcommandEcdsaP256Sign: - return handle_otbn_sca_ecdsa_p256_sign(uj); - case kOtbnScaSubcommandEcdsaP256SignBatch: - return handle_otbn_sca_ecdsa_p256_sign_batch(uj); - case kOtbnScaSubcommandEcdsaP256SignFvsrBatch: - return handle_otbn_sca_ecdsa_p256_sign_fvsr_batch(uj); - case kOtbnScaSubcommandInit: - return handle_otbn_pentest_init(uj); - case kOtbnScaSubcommandInitKeyMgr: - return handle_otbn_pentest_init_keymgr(uj); - case kOtbnScaSubcommandInsnCarryFlag: - return handle_otbn_sca_insn_carry_flag(uj); - case kOtbnScaSubcommandCombiOps: - return handle_otbn_sca_combi_operations_batch(uj); - case kOtbnScaSubcommandKeySideloadFvsr: - return handle_otbn_sca_key_sideload_fvsr(uj); - case kOtbnScaSubcommandRsa512Decrypt: - return handle_otbn_sca_rsa512_decrypt(uj); + case kAccScaSubcommandEcc256EcdsaKeygenFvsrKeyBatch: + return handle_acc_sca_ecc256_ecdsa_keygen_fvsr_key_batch(uj); + case kAccScaSubcommandEcc256EcdsaKeygenFvsrSeedBatch: + return handle_acc_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(uj); + case kAccScaSubcommandEcc256EnMasks: + return handle_acc_sca_ecc256_en_masks(uj); + case kAccScaSubcommandEcc256SetC: + return handle_acc_sca_ecc256_set_c(uj); + case kAccScaSubcommandEcc256SetSeed: + return handle_acc_sca_ecc256_set_seed(uj); + case kAccScaSubcommandEcdsaP256Sign: + return handle_acc_sca_ecdsa_p256_sign(uj); + case kAccScaSubcommandEcdsaP256SignBatch: + return handle_acc_sca_ecdsa_p256_sign_batch(uj); + case kAccScaSubcommandEcdsaP256SignFvsrBatch: + return handle_acc_sca_ecdsa_p256_sign_fvsr_batch(uj); + case kAccScaSubcommandInit: + return handle_acc_pentest_init(uj); + case kAccScaSubcommandInitKeyMgr: + return handle_acc_pentest_init_keymgr(uj); + case kAccScaSubcommandInsnCarryFlag: + return handle_acc_sca_insn_carry_flag(uj); + case kAccScaSubcommandCombiOps: + return handle_acc_sca_combi_operations_batch(uj); + case kAccScaSubcommandKeySideloadFvsr: + return handle_acc_sca_key_sideload_fvsr(uj); + case kAccScaSubcommandRsa512Decrypt: + return handle_acc_sca_rsa512_decrypt(uj); default: - LOG_ERROR("Unrecognized OTBN SCA subcommand: %d", cmd); + LOG_ERROR("Unrecognized ACC SCA subcommand: %d", cmd); return INVALID_ARGUMENT(); } return OK_STATUS(); diff --git a/sw/device/tests/penetrationtests/firmware/sca/otbn_sca.h b/sw/device/tests/penetrationtests/firmware/sca/acc_sca.h similarity index 65% rename from sw/device/tests/penetrationtests/firmware/sca/otbn_sca.h rename to sw/device/tests/penetrationtests/firmware/sca/acc_sca.h index 5e904734143..7e86d3ca1d6 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/otbn_sca.h +++ b/sw/device/tests/penetrationtests/firmware/sca/acc_sca.h @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_OTBN_SCA_H_ -#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_OTBN_SCA_H_ +#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_ACC_SCA_H_ +#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_ACC_SCA_H_ #include "sw/device/lib/base/status.h" #include "sw/device/lib/ujson/ujson.h" @@ -12,23 +12,23 @@ * Starts the P-256 ECDSA Key Generation from a key in batch mode. * * Num_traces fixed vs random keys are generated using the SCA PRNG and - * for each key the key generation operation on OTBN is started. + * for each key the key generation operation on ACC is started. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_key_batch(ujson_t *uj); +status_t handle_acc_sca_ecc256_ecdsa_keygen_fvsr_key_batch(ujson_t *uj); /** * Starts the P-256 ECDSA Key Generation from a seed in batch mode. * * Num_traces fixed vs random seeds are generated using the SCA PRNG and - * for each seed the key generation operation on OTBN is started. + * for each seed the key generation operation on ACC is started. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(ujson_t *uj); +status_t handle_acc_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(ujson_t *uj); /** * Enable or disable masking. @@ -40,7 +40,7 @@ status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecc256_en_masks(ujson_t *uj); +status_t handle_acc_sca_ecc256_en_masks(ujson_t *uj); /** * Set the constant C. @@ -51,7 +51,7 @@ status_t handle_otbn_sca_ecc256_en_masks(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecc256_set_c(ujson_t *uj); +status_t handle_acc_sca_ecc256_set_c(ujson_t *uj); /** * Set the seed share 0. @@ -62,10 +62,10 @@ status_t handle_otbn_sca_ecc256_set_c(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecc256_set_seed(ujson_t *uj); +status_t handle_acc_sca_ecc256_set_seed(ujson_t *uj); /** - * otbn.sca.ecdsa256.sign command handler. + * acc.sca.ecdsa256.sign command handler. * * Runs a ECDSA 256 sign operation, used to measure whether the operation * leakes secret information. @@ -73,70 +73,70 @@ status_t handle_otbn_sca_ecc256_set_seed(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecdsa_p256_sign(ujson_t *uj); +status_t handle_acc_sca_ecdsa_p256_sign(ujson_t *uj); /** - * otbn.sca.ecdsa256.sign_batch command handler. + * acc.sca.ecdsa256.sign_batch command handler. * - * Same as otbn.sca.ecdsa256.sign but in batch mode. Random message, random + * Same as acc.sca.ecdsa256.sign but in batch mode. Random message, random * key, and random secret is used. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecdsa_p256_sign_batch(ujson_t *uj); +status_t handle_acc_sca_ecdsa_p256_sign_batch(ujson_t *uj); /** - * otbn.sca.ecdsa256.sign_fvsr_batch command handler. + * acc.sca.ecdsa256.sign_fvsr_batch command handler. * - * Same as otbn.sca.ecdsa256.sign but in batch mode. Fixed or random message, + * Same as acc.sca.ecdsa256.sign but in batch mode. Fixed or random message, * fixed or random key, and fixed or random secret is used. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_ecdsa_p256_sign_fvsr_batch(ujson_t *uj); +status_t handle_acc_sca_ecdsa_p256_sign_fvsr_batch(ujson_t *uj); /** - * Initializes the OTBN SCA test on the device. + * Initializes the ACC SCA test on the device. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_pentest_init(ujson_t *uj); +status_t handle_acc_pentest_init(ujson_t *uj); /** - * Initializes the Keymanager used for the OTBN SCA tests. + * Initializes the Keymanager used for the ACC SCA tests. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_pentest_init_keymgr(ujson_t *uj); +status_t handle_acc_pentest_init_keymgr(ujson_t *uj); /** - * otbn.sca.insn.carry_flag command handler. + * acc.sca.insn.carry_flag command handler. * - * Receive big_num from host. On OTBN, add big_num + big_num and get the + * Receive big_num from host. On ACC, add big_num + big_num and get the * carry flag. If the carry flag is not set, return the result. If the carry * flag is set, return random number. Checks whether carry flag is leaking. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_insn_carry_flag(ujson_t *uj); +status_t handle_acc_sca_insn_carry_flag(ujson_t *uj); /** - * Command handler for the otbn.sca.key_sideload_fvsr test. + * Command handler for the acc.sca.key_sideload_fvsr test. * - * Side-load 16 fixed vs. random keys from keymanager to OTBN. + * Side-load 16 fixed vs. random keys from keymanager to ACC. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_key_sideload_fvsr(ujson_t *uj); +status_t handle_acc_sca_key_sideload_fvsr(ujson_t *uj); /** - * Command handler for the otbn.sca.rsa512_decrypt test. + * Command handler for the acc.sca.rsa512_decrypt test. * * RSA512 decryption side-channel test. Get mod, exp, and msg from uJSON. * Perform RSA512 decryption and send back the message. @@ -144,12 +144,12 @@ status_t handle_otbn_sca_key_sideload_fvsr(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_rsa512_decrypt(ujson_t *uj); +status_t handle_acc_sca_rsa512_decrypt(ujson_t *uj); /** - * Command handler for the otbn.sca.combi_ops test. + * Command handler for the acc.sca.combi_ops test. * - * Loads two fixed values to the OTBN and performs several operations. + * Loads two fixed values to the ACC and performs several operations. * Each operation also has an output that the test sends back. * Each 32-bit fixed value is copied eight times to fill a 256-bit register. * @@ -165,7 +165,7 @@ status_t handle_otbn_sca_rsa512_decrypt(ujson_t *uj); * - the comparison of the two inputs (8 means the comparison was succesful and * 4 means it was not) The above is done under a trigger signal. * - * A second trigger window can be chosen which is over the wiping of the OTBN. + * A second trigger window can be chosen which is over the wiping of the ACC. * * The print_flag can be set to false to print a small success value instead of * the full response. @@ -173,16 +173,16 @@ status_t handle_otbn_sca_rsa512_decrypt(ujson_t *uj); * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca_combi_operations_batch(ujson_t *uj); +status_t handle_acc_sca_combi_operations_batch(ujson_t *uj); /** - * OTBN SCA command handler. + * ACC SCA command handler. * - * Command handler for the OTBN SCA command. + * Command handler for the ACC SCA command. * * @param uj An initialized uJSON context. * @return OK or error. */ -status_t handle_otbn_sca(ujson_t *uj); +status_t handle_acc_sca(ujson_t *uj); -#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_OTBN_SCA_H_ +#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_ACC_SCA_H_ diff --git a/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_asym.c b/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_asym.c index fddb589b9b5..7c36f908e9c 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_asym.c +++ b/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_asym.c @@ -879,7 +879,7 @@ status_t handle_cryptolib_sca_asym_init(ujson_t *uj) { kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); diff --git a/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_sym.c b/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_sym.c index e6612f46dc6..0876d1a538a 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_sym.c +++ b/sw/device/tests/penetrationtests/firmware/sca/cryptolib_sca_sym.c @@ -890,7 +890,7 @@ status_t handle_cryptolib_sca_sym_init(ujson_t *uj) { kPentestPeripheralIoDiv4 | kPentestPeripheralEdn | kPentestPeripheralCsrng | kPentestPeripheralEntropy | kPentestPeripheralAes | kPentestPeripheralHmac | - kPentestPeripheralKmac | kPentestPeripheralOtbn, + kPentestPeripheralKmac | kPentestPeripheralAcc, uj_sensor_data.sensor_ctrl_enable, uj_sensor_data.sensor_ctrl_en_fatal); diff --git a/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.c b/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.c index 012285b7870..7181b77c8f0 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.c +++ b/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.c @@ -14,9 +14,9 @@ #include "sw/device/lib/ujson/ujson.h" #include "sw/device/sca/lib/prng.h" #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" -#include "sw/device/tests/penetrationtests/json/otbn_sca_commands.h" +#include "sw/device/tests/penetrationtests/json/acc_sca_commands.h" -#include "hw/top/otbn_regs.h" +#include "hw/top/acc_regs.h" #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" enum { @@ -49,31 +49,28 @@ enum { */ kNumBatchOpsMax = 256, /** - * Number of cycles that Ibex should sleep to minimize noise during OTBN + * Number of cycles that Ibex should sleep to minimize noise during ACC * operations. Caution: This number should be chosen to provide enough time - * to complete the operation. Otherwise, Ibex might wake up while OTBN is + * to complete the operation. Otherwise, Ibex might wake up while ACC is * still busy and disturb the capture. This was measured using mcycle_read - * when otbn_manual_trigger and otbn_busy_wait_for_done get executed. + * when acc_manual_trigger and acc_busy_wait_for_done get executed. */ - kIbexOtbnSleepCycles = 1100, + kIbexAccSleepCycles = 1100, }; /** * App configuration for p256_key_from_seed_sca */ -const otbn_app_t kOtbnAppP256KeyFromSeed = - OTBN_APP_T_INIT(p256_key_from_seed_sca); - -static const otbn_addr_t kOtbnVarMode = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, mode); -static const otbn_addr_t kOtbnVarSeed0 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, seed0); -static const otbn_addr_t kOtbnVarSeed1 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, seed1); -static const otbn_addr_t kOtbnVarD0 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, d0); -static const otbn_addr_t kOtbnVarD1 = - OTBN_ADDR_T_INIT(p256_key_from_seed_sca, d1); +const acc_app_t kAccAppP256KeyFromSeed = ACC_APP_T_INIT(p256_key_from_seed_sca); + +static const acc_addr_t kAccVarMode = + ACC_ADDR_T_INIT(p256_key_from_seed_sca, mode); +static const acc_addr_t kAccVarSeed0 = + ACC_ADDR_T_INIT(p256_key_from_seed_sca, seed0); +static const acc_addr_t kAccVarSeed1 = + ACC_ADDR_T_INIT(p256_key_from_seed_sca, seed1); +static const acc_addr_t kAccVarD0 = ACC_ADDR_T_INIT(p256_key_from_seed_sca, d0); +static const acc_addr_t kAccVarD1 = ACC_ADDR_T_INIT(p256_key_from_seed_sca, d1); /** * An array of seeds to be used in a batch @@ -146,12 +143,12 @@ static void add_arrays(uint8_t *dest, uint8_t *source, size_t dest_len, } /** - * Callback wrapper for OTBN manual trigger function. + * Callback wrapper for ACC manual trigger function. */ -static void otbn_manual_trigger(void) { OT_DISCARD(otbn_execute().value); } +static void acc_manual_trigger(void) { OT_DISCARD(acc_execute().value); } /** - * Runs the OTBN key generation program. + * Runs the ACC key generation program. * * The seed shares must be `kEcc256SeedNumWords` words long. * @@ -163,24 +160,24 @@ static void otbn_manual_trigger(void) { OT_DISCARD(otbn_execute().value); } static status_t p256_run_keygen(uint32_t mode, const uint32_t *share0, const uint32_t *share1) { // Secure wipe to scramble DMEM. - TRY(otbn_load_app(kOtbnAppP256KeyFromSeed)); + TRY(acc_load_app(kAccAppP256KeyFromSeed)); // Write mode. - TRY(otbn_dmem_write(/*num_words=*/1, &mode, kOtbnVarMode)); + TRY(acc_dmem_write(/*num_words=*/1, &mode, kAccVarMode)); // Write seed shares. - TRY(otbn_dmem_write(kEcc256SeedNumWords, share0, kOtbnVarSeed0)); - TRY(otbn_dmem_write(kEcc256SeedNumWords, share1, kOtbnVarSeed1)); + TRY(acc_dmem_write(kEcc256SeedNumWords, share0, kAccVarSeed0)); + TRY(acc_dmem_write(kEcc256SeedNumWords, share1, kAccVarSeed1)); // Execute program. Trigger is set inside this function. - pentest_call_and_sleep(otbn_manual_trigger, kIbexOtbnSleepCycles, true, true); + pentest_call_and_sleep(acc_manual_trigger, kIbexAccSleepCycles, true, true); return OK_STATUS(); } -status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_key_batch(ujson_t *uj) { - penetrationtest_otbn_sca_num_traces_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_num_traces_t(uj, &uj_data)); +status_t handle_acc_sca_ecc256_ecdsa_keygen_fvsr_key_batch(ujson_t *uj) { + penetrationtest_acc_sca_num_traces_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_num_traces_t(uj, &uj_data)); uint32_t num_traces = uj_data.num_traces; uint32_t batch_digest[kEcc256SeedNumWords]; @@ -232,8 +229,8 @@ status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_key_batch(ujson_t *uj) { TRY(p256_run_keygen(kEcc256ModeKeypair, batch_share0[i], batch_share1[i])); // Read results. - TRY(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD0, d0_batch)); - TRY(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD1, d1_batch)); + TRY(acc_dmem_read(kEcc256SeedNumWords, kAccVarD0, d0_batch)); + TRY(acc_dmem_read(kEcc256SeedNumWords, kAccVarD1, d1_batch)); // The correctness of each batch is verified by computing and sending // the batch digest. This digest is computed by XORing all d0 shares of @@ -243,18 +240,18 @@ status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_key_batch(ujson_t *uj) { } } // Send the batch digest to the host for verification. - penetrationtest_otbn_sca_batch_digest_t uj_output; + penetrationtest_acc_sca_batch_digest_t uj_output; memcpy(uj_output.batch_digest, (uint8_t *)batch_digest, kEcc256SeedNumWords * 4); - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_batch_digest_t, uj, + RESP_OK(ujson_serialize_penetrationtest_acc_sca_batch_digest_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(ujson_t *uj) { - penetrationtest_otbn_sca_num_traces_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_num_traces_t(uj, &uj_data)); +status_t handle_acc_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(ujson_t *uj) { + penetrationtest_acc_sca_num_traces_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_num_traces_t(uj, &uj_data)); uint32_t num_traces = uj_data.num_traces; uint32_t batch_digest[kEcc256SeedNumWords]; @@ -300,8 +297,8 @@ status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(ujson_t *uj) { TRY(p256_run_keygen(kEcc256ModeKeypair, batch_share0[i], batch_share1[i])); // Read results. - TRY(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD0, d0_batch)); - TRY(otbn_dmem_read(kEcc256SeedNumWords, kOtbnVarD1, d1_batch)); + TRY(acc_dmem_read(kEcc256SeedNumWords, kAccVarD0, d0_batch)); + TRY(acc_dmem_read(kEcc256SeedNumWords, kAccVarD1, d1_batch)); // The correctness of each batch is verified by computing and sending // the batch digest. This digest is computed by XORing all d0 shares of @@ -312,18 +309,18 @@ status_t handle_otbn_sca_ecc256_ecdsa_keygen_fvsr_seed_batch(ujson_t *uj) { } // Send the batch digest to the host for verification. - penetrationtest_otbn_sca_batch_digest_t uj_output; + penetrationtest_acc_sca_batch_digest_t uj_output; memcpy(uj_output.batch_digest, (uint8_t *)batch_digest, kEcc256SeedNumWords * 4); - RESP_OK(ujson_serialize_penetrationtest_otbn_sca_batch_digest_t, uj, + RESP_OK(ujson_serialize_penetrationtest_acc_sca_batch_digest_t, uj, &uj_output); return OK_STATUS(); } -status_t handle_otbn_sca_ecc256_en_masks(ujson_t *uj) { - penetrationtest_otbn_sca_en_masks_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_en_masks_t(uj, &uj_data)); +status_t handle_acc_sca_ecc256_en_masks(ujson_t *uj) { + penetrationtest_acc_sca_en_masks_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_en_masks_t(uj, &uj_data)); if (uj_data.en_masks) { en_masks = true; } else { @@ -332,18 +329,18 @@ status_t handle_otbn_sca_ecc256_en_masks(ujson_t *uj) { return OK_STATUS(); } -status_t handle_otbn_sca_ecc256_set_c(ujson_t *uj) { - penetrationtest_otbn_sca_constant_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_constant_t(uj, &uj_data)); +status_t handle_acc_sca_ecc256_set_c(ujson_t *uj) { + penetrationtest_acc_sca_constant_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_constant_t(uj, &uj_data)); memcpy(ecc256_C, uj_data.constant, kEcc256SeedNumBytes); return OK_STATUS(); } -status_t handle_otbn_sca_ecc256_set_seed(ujson_t *uj) { - penetrationtest_otbn_sca_seed_t uj_data; - TRY(ujson_deserialize_penetrationtest_otbn_sca_seed_t(uj, &uj_data)); +status_t handle_acc_sca_ecc256_set_seed(ujson_t *uj) { + penetrationtest_acc_sca_seed_t uj_data; + TRY(ujson_deserialize_penetrationtest_acc_sca_seed_t(uj, &uj_data)); memcpy(ecc256_seed, uj_data.seed, kEcc256SeedNumBytes); diff --git a/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.h b/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.h index 70e7d076ad3..0fb601e1ceb 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.h +++ b/sw/device/tests/penetrationtests/firmware/sca/ecc256_keygen_sca.h @@ -5,27 +5,27 @@ #ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_ECC256_KEYGEN_SCA_H_ #define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_ECC256_KEYGEN_SCA_H_ -#include "sw/device/lib/crypto/drivers/otbn.h" +#include "sw/device/lib/crypto/drivers/acc.h" /** * App configuration for p256_key_from_seed_sca */ -OTBN_DECLARE_APP_SYMBOLS(p256_key_from_seed_sca); +ACC_DECLARE_APP_SYMBOLS(p256_key_from_seed_sca); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, mode); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed0); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed1); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d0); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d1); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, x); -OTBN_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, y); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, mode); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed0); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, seed1); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d0); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, d1); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, x); +ACC_DECLARE_SYMBOL_ADDR(p256_key_from_seed_sca, y); -extern const otbn_app_t kOtbnAppP256KeyFromSeed; +extern const acc_app_t kAccAppP256KeyFromSeed; -static const otbn_addr_t kOtbnVarMode; -static const otbn_addr_t kOtbnVarSeed0; -static const otbn_addr_t kOtbnVarSeed1; -static const otbn_addr_t kOtbnVarD0; -static const otbn_addr_t kOtbnVarD1; +static const acc_addr_t kAccVarMode; +static const acc_addr_t kAccVarSeed0; +static const acc_addr_t kAccVarSeed1; +static const acc_addr_t kAccVarD0; +static const acc_addr_t kAccVarD1; #endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_FIRMWARE_SCA_ECC256_KEYGEN_SCA_H_ diff --git a/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.c b/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.c index 4de5bb91bd2..86f25e9024c 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.c +++ b/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.c @@ -7,10 +7,10 @@ #include "ecc256_keygen_sca.h" #include "sw/device/lib/base/memory.h" #include "sw/device/lib/base/status.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_keymgr.h" #include "sw/device/lib/dif/dif_kmac.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/runtime/log.h" #include "sw/device/lib/testing/hmac_testutils.h" #include "sw/device/lib/testing/keymgr_testutils.h" @@ -22,22 +22,22 @@ #include "sw/device/tests/penetrationtests/firmware/lib/pentest_lib.h" #include "sw/device/tests/penetrationtests/json/ibex_sca_commands.h" -#include "hw/top/otbn_regs.h" // Generated. +#include "hw/top/acc_regs.h" // Generated. #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" static dif_keymgr_t keymgr; static dif_kmac_t kmac; static dif_aes_t aes; static dif_hmac_t hmac; -static dif_otbn_t otbn; +static dif_acc_t acc; #define MAX_BATCH_SIZE 256 -// OTBN symbols used by the combinatorial test. -OTBN_DECLARE_APP_SYMBOLS(p256_ecdsa_sca); -OTBN_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, msg); -static const otbn_app_t kOtbnAppP256Ecdsa = OTBN_APP_T_INIT(p256_ecdsa_sca); -static const otbn_addr_t kOtbnVarMsg = OTBN_ADDR_T_INIT(p256_ecdsa_sca, msg); +// ACC symbols used by the combinatorial test. +ACC_DECLARE_APP_SYMBOLS(p256_ecdsa_sca); +ACC_DECLARE_SYMBOL_ADDR(p256_ecdsa_sca, msg); +static const acc_app_t kAccAppP256Ecdsa = ACC_APP_T_INIT(p256_ecdsa_sca); +static const acc_addr_t kAccVarMsg = ACC_ADDR_T_INIT(p256_ecdsa_sca, msg); // Enum for the triggers of the combinatorial test. typedef enum combi_operations_trigger_t { @@ -52,7 +52,7 @@ typedef enum combi_operations_trigger_t { kCombiOpsTriggerCp = 256, kCombiOpsTriggerAes = 512, kCombiOpsTriggerHmac = 1024, - kCombiOpsTriggerOtbn = 2048, + kCombiOpsTriggerAcc = 2048, kCombiOpsNumResults = 12, } combi_operations_trigger_t; @@ -143,7 +143,7 @@ status_t handle_ibex_pentest_init(ujson_t *uj) { pentest_select_trigger_type(kPentestTriggerTypeSw); pentest_init(kPentestTriggerSourceAes, kPentestPeripheralEntropy | kPentestPeripheralIoDiv4 | - kPentestPeripheralOtbn | kPentestPeripheralCsrng | + kPentestPeripheralAcc | kPentestPeripheralCsrng | kPentestPeripheralEdn | kPentestPeripheralHmac | kPentestPeripheralKmac | kPentestPeripheralAes, uj_sensor_data.sensor_ctrl_enable, @@ -172,12 +172,12 @@ status_t handle_ibex_pentest_init(ujson_t *uj) { TRY(dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes)); TRY(dif_aes_reset(&aes)); - // Init OTBN. - TRY(dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + // Init ACC. + TRY(dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); - // Load p256 keygen from seed app into OTBN. + // Load p256 keygen from seed app into ACC. // This is not used, but just set so it receives input, - TRY(otbn_load_app(kOtbnAppP256Ecdsa)); + TRY(acc_load_app(kAccAppP256Ecdsa)); // Read rom digest. TRY(pentest_read_rom_digest(uj_output.rom_digest)); @@ -408,12 +408,12 @@ static status_t trigger_ibex_sca_combi_operations(uint32_t value1, result[10] = value1; } - if (trigger & kCombiOpsTriggerOtbn) { - // Write to the OTBN. + if (trigger & kCombiOpsTriggerAcc) { + // Write to the ACC. uint32_t msg[8]; memset(msg, (int)value1, sizeof(msg)); pentest_set_trigger_high(); - TRY(otbn_dmem_write(8, msg, kOtbnVarMsg)); + TRY(acc_dmem_write(8, msg, kAccVarMsg)); pentest_set_trigger_low(); result[11] = value1; } diff --git a/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.h b/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.h index 97ec8ca7b88..caa75c05fbb 100644 --- a/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.h +++ b/sw/device/tests/penetrationtests/firmware/sca/ibex_sca.h @@ -34,7 +34,7 @@ status_t handle_ibex_pentest_init(ujson_t *uj); * - Copy values from SRAM to another address * - Send data to the AES * - Send data to the HMAC - * - Send data to the OTBN + * - Send data to the ACC * * @param uj An initialized uJSON context. * @return OK or error. @@ -60,7 +60,7 @@ status_t handle_ibex_sca_combi_operations_batch(ujson_t *uj); * - Copy values from SRAM to another address * - Send data to the AES * - Send data to the HMAC - * - Send data to the OTBN + * - Send data to the ACC * * @param uj An initialized uJSON context. * @return OK or error. diff --git a/sw/device/tests/penetrationtests/json/BUILD b/sw/device/tests/penetrationtests/json/BUILD index 3a1153d4973..15153f2028f 100644 --- a/sw/device/tests/penetrationtests/json/BUILD +++ b/sw/device/tests/penetrationtests/json/BUILD @@ -9,6 +9,8 @@ cc_library( srcs = ["commands.c"], hdrs = ["commands.h"], deps = [ + ":acc_fi_commands", + ":acc_sca_commands", ":aes_sca_commands", ":alert_fi_commands", ":crypto_fi_commands", @@ -22,8 +24,6 @@ cc_library( ":ibex_fi_commands", ":kmac_sca_commands", ":lc_ctrl_fi_commands", - ":otbn_fi_commands", - ":otbn_sca_commands", ":otp_fi_commands", ":prng_sca_commands", ":rom_fi_commands", @@ -147,16 +147,16 @@ cc_library( ) cc_library( - name = "otbn_fi_commands", - srcs = ["otbn_fi_commands.c"], - hdrs = ["otbn_fi_commands.h"], + name = "acc_fi_commands", + srcs = ["acc_fi_commands.c"], + hdrs = ["acc_fi_commands.h"], deps = ["//sw/device/lib/ujson"], ) cc_library( - name = "otbn_sca_commands", - srcs = ["otbn_sca_commands.c"], - hdrs = ["otbn_sca_commands.h"], + name = "acc_sca_commands", + srcs = ["acc_sca_commands.c"], + hdrs = ["acc_sca_commands.h"], deps = ["//sw/device/lib/ujson"], ) diff --git a/sw/device/tests/penetrationtests/json/otbn_fi_commands.c b/sw/device/tests/penetrationtests/json/acc_fi_commands.c similarity index 86% rename from sw/device/tests/penetrationtests/json/otbn_fi_commands.c rename to sw/device/tests/penetrationtests/json/acc_fi_commands.c index f24663a6125..d870329c5e9 100644 --- a/sw/device/tests/penetrationtests/json/otbn_fi_commands.c +++ b/sw/device/tests/penetrationtests/json/acc_fi_commands.c @@ -3,4 +3,4 @@ // SPDX-License-Identifier: Apache-2.0 #define UJSON_SERDE_IMPL 1 -#include "otbn_fi_commands.h" +#include "acc_fi_commands.h" diff --git a/sw/device/tests/penetrationtests/json/otbn_fi_commands.h b/sw/device/tests/penetrationtests/json/acc_fi_commands.h similarity index 53% rename from sw/device/tests/penetrationtests/json/otbn_fi_commands.h rename to sw/device/tests/penetrationtests/json/acc_fi_commands.h index cfbf3fded97..449bd750eac 100644 --- a/sw/device/tests/penetrationtests/json/otbn_fi_commands.h +++ b/sw/device/tests/penetrationtests/json/acc_fi_commands.h @@ -2,8 +2,8 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_OTBN_FI_COMMANDS_H_ -#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_OTBN_FI_COMMANDS_H_ +#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_ACC_FI_COMMANDS_H_ +#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_ACC_FI_COMMANDS_H_ #include "sw/device/lib/ujson/ujson_derive.h" #ifdef __cplusplus extern "C" { @@ -11,7 +11,7 @@ extern "C" { // clang-format off -#define OTBNFI_SUBCOMMAND(_, value) \ +#define ACCFI_SUBCOMMAND(_, value) \ value(_, CharBeq) \ value(_, CharBnRshi) \ value(_, CharBnSel) \ @@ -32,121 +32,121 @@ extern "C" { value(_, KeySideload) \ value(_, LoadIntegrity) \ value(_, PC) -C_ONLY(UJSON_SERDE_ENUM(OtbnFiSubcommand, otbn_fi_subcommand_t, OTBNFI_SUBCOMMAND)); -RUST_ONLY(UJSON_SERDE_ENUM(OtbnFiSubcommand, otbn_fi_subcommand_t, OTBNFI_SUBCOMMAND, RUST_DEFAULT_DERIVE, strum::EnumString)); +C_ONLY(UJSON_SERDE_ENUM(AccFiSubcommand, acc_fi_subcommand_t, ACCFI_SUBCOMMAND)); +RUST_ONLY(UJSON_SERDE_ENUM(AccFiSubcommand, acc_fi_subcommand_t, ACCFI_SUBCOMMAND, RUST_DEFAULT_DERIVE, strum::EnumString)); -#define OTBNFI_LOOP_COUNTER_OUTPUT(field, string) \ +#define ACCFI_LOOP_COUNTER_OUTPUT(field, string) \ field(loop_counter, uint32_t) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiLoopCounterOutput, otbn_fi_loop_counter_t, OTBNFI_LOOP_COUNTER_OUTPUT); +UJSON_SERDE_STRUCT(AccFiLoopCounterOutput, acc_fi_loop_counter_t, ACCFI_LOOP_COUNTER_OUTPUT); -#define OTBNFI_RESULT_OUTPUT(field, string) \ +#define ACCFI_RESULT_OUTPUT(field, string) \ field(result, uint32_t) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiResultOutput, otbn_fi_result_t, OTBNFI_RESULT_OUTPUT); +UJSON_SERDE_STRUCT(AccFiResultOutput, acc_fi_result_t, ACCFI_RESULT_OUTPUT); -#define OTBNFI_KEY_OUTPUT(field, string) \ +#define ACCFI_KEY_OUTPUT(field, string) \ field(res, uint32_t) \ field(keys, uint32_t, 4) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiKeyOutput, otbn_fi_keys_t, OTBNFI_KEY_OUTPUT); +UJSON_SERDE_STRUCT(AccFiKeyOutput, acc_fi_keys_t, ACCFI_KEY_OUTPUT); -#define OTBNFI_MEM_CFG(field, string) \ +#define ACCFI_MEM_CFG(field, string) \ field(byte_offset, uint32_t) \ field(num_words, uint32_t) \ field(imem, bool) \ field(dmem, bool) -UJSON_SERDE_STRUCT(OtbnFiMemCfg, otbn_fi_mem_cfg_t, OTBNFI_MEM_CFG); +UJSON_SERDE_STRUCT(AccFiMemCfg, acc_fi_mem_cfg_t, ACCFI_MEM_CFG); -#define OTBNFI_MEM_OUTPUT(field, string) \ +#define ACCFI_MEM_OUTPUT(field, string) \ field(res, uint32_t) \ field(imem_data, uint32_t, 8) \ field(imem_addr, uint32_t, 8) \ field(dmem_data, uint32_t, 8) \ field(dmem_addr, uint32_t, 8) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiMemOutput, otbn_fi_mem_t, OTBNFI_MEM_OUTPUT); +UJSON_SERDE_STRUCT(AccFiMemOutput, acc_fi_mem_t, ACCFI_MEM_OUTPUT); -#define OTBNFI_DATA_OUTPUT(field, string) \ +#define ACCFI_DATA_OUTPUT(field, string) \ field(res, uint32_t) \ field(data, uint32_t, 256) \ field(insn_cnt, uint32_t) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiDataOutput, otbn_fi_data_t, OTBNFI_DATA_OUTPUT); +UJSON_SERDE_STRUCT(AccFiDataOutput, acc_fi_data_t, ACCFI_DATA_OUTPUT); -#define OTBNFI_RF_CHAR_OUTPUT(field, string) \ +#define ACCFI_RF_CHAR_OUTPUT(field, string) \ field(res, uint32_t) \ field(faulty_gpr, uint32_t, 29) \ field(faulty_wdr, uint32_t, 256) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiRfCharOutput, otbn_fi_rf_char_t, OTBNFI_RF_CHAR_OUTPUT); +UJSON_SERDE_STRUCT(AccFiRfCharOutput, acc_fi_rf_char_t, ACCFI_RF_CHAR_OUTPUT); -#define OTBNFI_RESULT_CNT_OUTPUT(field, string) \ +#define ACCFI_RESULT_CNT_OUTPUT(field, string) \ field(result, uint32_t) \ field(insn_cnt, uint32_t) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiResultCntOutput, otbn_fi_result_cnt_t, OTBNFI_RESULT_CNT_OUTPUT); +UJSON_SERDE_STRUCT(AccFiResultCntOutput, acc_fi_result_cnt_t, ACCFI_RESULT_CNT_OUTPUT); -#define OTBNFI_RESULT_ARRAY(field, string) \ +#define ACCFI_RESULT_ARRAY(field, string) \ field(result, uint32_t, 32) \ field(insn_cnt, uint32_t) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiResultArray, otbn_fi_result_array_t, OTBNFI_RESULT_ARRAY); +UJSON_SERDE_STRUCT(AccFiResultArray, acc_fi_result_array_t, ACCFI_RESULT_ARRAY); -#define OTBNFI_BIG_NUM(field, string) \ +#define ACCFI_BIG_NUM(field, string) \ field(big_num, uint32_t, 16) -UJSON_SERDE_STRUCT(OtbnFiBigNum, otbn_fi_big_num_t, OTBNFI_BIG_NUM); +UJSON_SERDE_STRUCT(AccFiBigNum, acc_fi_big_num_t, ACCFI_BIG_NUM); -#define OTBNFI_BIG_NUM_OUTPUT(field, string) \ +#define ACCFI_BIG_NUM_OUTPUT(field, string) \ field(big_num, uint32_t, 16) \ field(insn_cnt, uint32_t) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiBigNumOutput, otbn_fi_big_num_out_t, OTBNFI_BIG_NUM_OUTPUT); +UJSON_SERDE_STRUCT(AccFiBigNumOutput, acc_fi_big_num_out_t, ACCFI_BIG_NUM_OUTPUT); -#define OTBNFI_PC(field, string) \ +#define ACCFI_PC(field, string) \ field(pc, uint32_t) -UJSON_SERDE_STRUCT(OtbnFiPc, otbn_fi_pc_t, OTBNFI_PC); +UJSON_SERDE_STRUCT(AccFiPc, acc_fi_pc_t, ACCFI_PC); -#define OTBNFI_PC_OUTPUT(field, string) \ +#define ACCFI_PC_OUTPUT(field, string) \ field(pc_dmem, uint32_t) \ - field(pc_otbn, uint32_t) \ + field(pc_acc, uint32_t) \ field(insn_cnt, uint32_t) \ - field(err_otbn, uint32_t) \ + field(err_acc, uint32_t) \ field(err_ibx, uint32_t) \ field(alerts, uint32_t, 3) \ field(ast_alerts, uint32_t, 2) -UJSON_SERDE_STRUCT(OtbnFiPcOutput, otbn_fi_pc_out_t, OTBNFI_PC_OUTPUT); +UJSON_SERDE_STRUCT(AccFiPcOutput, acc_fi_pc_out_t, ACCFI_PC_OUTPUT); // clang-format on #ifdef __cplusplus } #endif -#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_OTBN_FI_COMMANDS_H_ +#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_ACC_FI_COMMANDS_H_ diff --git a/sw/device/tests/penetrationtests/json/otbn_sca_commands.c b/sw/device/tests/penetrationtests/json/acc_sca_commands.c similarity index 86% rename from sw/device/tests/penetrationtests/json/otbn_sca_commands.c rename to sw/device/tests/penetrationtests/json/acc_sca_commands.c index 3647bf0cc04..e765f149c58 100644 --- a/sw/device/tests/penetrationtests/json/otbn_sca_commands.c +++ b/sw/device/tests/penetrationtests/json/acc_sca_commands.c @@ -3,4 +3,4 @@ // SPDX-License-Identifier: Apache-2.0 #define UJSON_SERDE_IMPL 1 -#include "otbn_sca_commands.h" +#include "acc_sca_commands.h" diff --git a/sw/device/tests/penetrationtests/json/acc_sca_commands.h b/sw/device/tests/penetrationtests/json/acc_sca_commands.h new file mode 100644 index 00000000000..7229116ab9f --- /dev/null +++ b/sw/device/tests/penetrationtests/json/acc_sca_commands.h @@ -0,0 +1,119 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_ACC_SCA_COMMANDS_H_ +#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_ACC_SCA_COMMANDS_H_ +#include "sw/device/lib/ujson/ujson_derive.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define ACCSCA_CMD_MAX_BATCH_DIGEST_BYTES 40 +#define ACCSCA_CMD_MAX_SEED_BYTES 40 + +// clang-format off + +// ACC SCA arguments + +#define ACCSCA_SUBCOMMAND(_, value) \ + value(_, Ecc256EcdsaKeygenFvsrKeyBatch) \ + value(_, Ecc256EcdsaKeygenFvsrSeedBatch) \ + value(_, Ecc256EnMasks) \ + value(_, Ecc256SetC) \ + value(_, Ecc256SetSeed) \ + value(_, EcdsaP256Sign) \ + value(_, EcdsaP256SignBatch) \ + value(_, EcdsaP256SignFvsrBatch) \ + value(_, Init) \ + value(_, InitKeyMgr) \ + value(_, InsnCarryFlag) \ + value(_, CombiOps) \ + value(_, KeySideloadFvsr) \ + value(_, Rsa512Decrypt) +C_ONLY(UJSON_SERDE_ENUM(AccScaSubcommand, acc_sca_subcommand_t, ACCSCA_SUBCOMMAND)); +RUST_ONLY(UJSON_SERDE_ENUM(AccScaSubcommand, acc_sca_subcommand_t, ACCSCA_SUBCOMMAND, RUST_DEFAULT_DERIVE, strum::EnumString)); + +#define ACC_SCA_EN_MASKS(field, string) \ + field(en_masks, bool) +UJSON_SERDE_STRUCT(PenetrationtestAccScaEnMasks, penetrationtest_acc_sca_en_masks_t, ACC_SCA_EN_MASKS); + +#define ACC_SCA_NUM_TRACES(field, string) \ + field(num_traces, uint32_t) +UJSON_SERDE_STRUCT(PenetrationtestAccScaNumTraces, penetrationtest_acc_sca_num_traces_t, ACC_SCA_NUM_TRACES); + +#define ACC_SCA_BATCH_DIGEST(field, string) \ + field(batch_digest, uint8_t, ACCSCA_CMD_MAX_BATCH_DIGEST_BYTES) +UJSON_SERDE_STRUCT(PenetrationtestAccScaBatchDigest, penetrationtest_acc_sca_batch_digest_t, ACC_SCA_BATCH_DIGEST); + +#define ACC_SCA_SEED(field, string) \ + field(seed, uint8_t, ACCSCA_CMD_MAX_SEED_BYTES) +UJSON_SERDE_STRUCT(PenetrationtestAccScaSeed, penetrationtest_acc_sca_seed_t, ACC_SCA_SEED); + +#define ACC_SCA_CONSTANT(field, string) \ + field(constant, uint8_t, ACCSCA_CMD_MAX_SEED_BYTES) +UJSON_SERDE_STRUCT(PenetrationtestAccScaConstant, penetrationtest_acc_sca_constant_t, ACC_SCA_CONSTANT); + +#define ACC_SCA_KEY(field, string) \ + field(shares, uint32_t, 4) \ + field(keys, uint32_t, 2) +UJSON_SERDE_STRUCT(PenetrationtestAccScaKey, penetrationtest_acc_sca_key_t, ACC_SCA_KEY); + +#define ACC_SCA_FIXED_SEED(field, string) \ + field(fixed_seed, uint32_t) +UJSON_SERDE_STRUCT(PenetrationtestAccScaFixedKey, penetrationtest_acc_sca_fixed_seed_t, ACC_SCA_FIXED_SEED); + +#define ACC_SCA_RSA512_DEC(field, string) \ + field(modu, uint8_t, 64) \ + field(exp, uint8_t, 64) \ + field(msg, uint8_t, 64) +UJSON_SERDE_STRUCT(PenetrationtestAccScaRsa512Dec, penetrationtest_acc_sca_rsa512_dec_t, ACC_SCA_RSA512_DEC); + +#define ACC_SCA_RSA512_DEC_OUT(field, string) \ + field(out, uint8_t, 64) +UJSON_SERDE_STRUCT(PenetrationtestAccScaRsa512DecOut, penetrationtest_acc_sca_rsa512_dec_out_t, ACC_SCA_RSA512_DEC_OUT); + +#define ACC_SCA_BIG_NUM(field, string) \ + field(big_num, uint32_t, 8) +UJSON_SERDE_STRUCT(PenetrationtestAccScaBigNum, penetrationtest_acc_sca_big_num_t, ACC_SCA_BIG_NUM); + +#define ACC_SCA_ECDSA_P256_SIGN(field, string) \ + field(msg, uint32_t, 8) \ + field(d0, uint32_t, 10) \ + field(k0, uint32_t, 10) +UJSON_SERDE_STRUCT(PenetrationtestAccScaEcdsaP256Sign, penetrationtest_acc_sca_ecdsa_p256_sign_t, ACC_SCA_ECDSA_P256_SIGN); + +#define ACC_SCA_ECDSA_P256_SIGNATURE(field, string) \ + field(r, uint8_t, 32) \ + field(s, uint8_t, 32) +UJSON_SERDE_STRUCT(PenetrationtestAccScaEcdsaP256Signature, penetrationtest_acc_sca_ecdsa_p256_signature_t, ACC_SCA_ECDSA_P256_SIGNATURE); + +#define ACC_SCA_TEST_BATCH_OPS(field, string) \ + field(num_iterations, uint32_t) \ + field(fixed_data1, uint32_t) \ + field(fixed_data2, uint32_t) \ + field(print_flag, bool) \ + field(trigger, uint32_t) +UJSON_SERDE_STRUCT(AccScaTestBatchOps, acc_sca_test_batch_ops_t, ACC_SCA_TEST_BATCH_OPS); + +#define ACC_SCA_OPS_RESULT(field, string) \ + field(result1, uint32_t, 8) \ + field(result2, uint32_t, 8) \ + field(result3, uint32_t, 8) \ + field(result4, uint32_t, 8) \ + field(result5, uint32_t, 8) \ + field(result6, uint32_t, 8) \ + field(result7, uint32_t, 8) \ + field(result8, uint32_t) +UJSON_SERDE_STRUCT(AccScaOpsResult, acc_sca_ops_result_t, ACC_SCA_OPS_RESULT); + +#define ACC_SCA_EMPTY(field, string) \ + field(success, bool) +UJSON_SERDE_STRUCT(AccScaEmpty, acc_sca_empty_t, ACC_SCA_EMPTY); + +// clang-format on + +#ifdef __cplusplus +} +#endif +#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_ACC_SCA_COMMANDS_H_ diff --git a/sw/device/tests/penetrationtests/json/commands.h b/sw/device/tests/penetrationtests/json/commands.h index fdd4fdc1682..e6d0ba6da1f 100644 --- a/sw/device/tests/penetrationtests/json/commands.h +++ b/sw/device/tests/penetrationtests/json/commands.h @@ -26,8 +26,8 @@ extern "C" { value(_, IbexSca) \ value(_, KmacSca) \ value(_, LCCtrlFi) \ - value(_, OtbnFi) \ - value(_, OtbnSca) \ + value(_, AccFi) \ + value(_, AccSca) \ value(_, OtpFi) \ value(_, PrngSca) \ value(_, RngFi) \ diff --git a/sw/device/tests/penetrationtests/json/otbn_sca_commands.h b/sw/device/tests/penetrationtests/json/otbn_sca_commands.h deleted file mode 100644 index c118b490248..00000000000 --- a/sw/device/tests/penetrationtests/json/otbn_sca_commands.h +++ /dev/null @@ -1,119 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_OTBN_SCA_COMMANDS_H_ -#define OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_OTBN_SCA_COMMANDS_H_ -#include "sw/device/lib/ujson/ujson_derive.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define OTBNSCA_CMD_MAX_BATCH_DIGEST_BYTES 40 -#define OTBNSCA_CMD_MAX_SEED_BYTES 40 - -// clang-format off - -// OTBN SCA arguments - -#define OTBNSCA_SUBCOMMAND(_, value) \ - value(_, Ecc256EcdsaKeygenFvsrKeyBatch) \ - value(_, Ecc256EcdsaKeygenFvsrSeedBatch) \ - value(_, Ecc256EnMasks) \ - value(_, Ecc256SetC) \ - value(_, Ecc256SetSeed) \ - value(_, EcdsaP256Sign) \ - value(_, EcdsaP256SignBatch) \ - value(_, EcdsaP256SignFvsrBatch) \ - value(_, Init) \ - value(_, InitKeyMgr) \ - value(_, InsnCarryFlag) \ - value(_, CombiOps) \ - value(_, KeySideloadFvsr) \ - value(_, Rsa512Decrypt) -C_ONLY(UJSON_SERDE_ENUM(OtbnScaSubcommand, otbn_sca_subcommand_t, OTBNSCA_SUBCOMMAND)); -RUST_ONLY(UJSON_SERDE_ENUM(OtbnScaSubcommand, otbn_sca_subcommand_t, OTBNSCA_SUBCOMMAND, RUST_DEFAULT_DERIVE, strum::EnumString)); - -#define OTBN_SCA_EN_MASKS(field, string) \ - field(en_masks, bool) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaEnMasks, penetrationtest_otbn_sca_en_masks_t, OTBN_SCA_EN_MASKS); - -#define OTBN_SCA_NUM_TRACES(field, string) \ - field(num_traces, uint32_t) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaNumTraces, penetrationtest_otbn_sca_num_traces_t, OTBN_SCA_NUM_TRACES); - -#define OTBN_SCA_BATCH_DIGEST(field, string) \ - field(batch_digest, uint8_t, OTBNSCA_CMD_MAX_BATCH_DIGEST_BYTES) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaBatchDigest, penetrationtest_otbn_sca_batch_digest_t, OTBN_SCA_BATCH_DIGEST); - -#define OTBN_SCA_SEED(field, string) \ - field(seed, uint8_t, OTBNSCA_CMD_MAX_SEED_BYTES) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaSeed, penetrationtest_otbn_sca_seed_t, OTBN_SCA_SEED); - -#define OTBN_SCA_CONSTANT(field, string) \ - field(constant, uint8_t, OTBNSCA_CMD_MAX_SEED_BYTES) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaConstant, penetrationtest_otbn_sca_constant_t, OTBN_SCA_CONSTANT); - -#define OTBN_SCA_KEY(field, string) \ - field(shares, uint32_t, 4) \ - field(keys, uint32_t, 2) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaKey, penetrationtest_otbn_sca_key_t, OTBN_SCA_KEY); - -#define OTBN_SCA_FIXED_SEED(field, string) \ - field(fixed_seed, uint32_t) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaFixedKey, penetrationtest_otbn_sca_fixed_seed_t, OTBN_SCA_FIXED_SEED); - -#define OTBN_SCA_RSA512_DEC(field, string) \ - field(modu, uint8_t, 64) \ - field(exp, uint8_t, 64) \ - field(msg, uint8_t, 64) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaRsa512Dec, penetrationtest_otbn_sca_rsa512_dec_t, OTBN_SCA_RSA512_DEC); - -#define OTBN_SCA_RSA512_DEC_OUT(field, string) \ - field(out, uint8_t, 64) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaRsa512DecOut, penetrationtest_otbn_sca_rsa512_dec_out_t, OTBN_SCA_RSA512_DEC_OUT); - -#define OTBN_SCA_BIG_NUM(field, string) \ - field(big_num, uint32_t, 8) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaBigNum, penetrationtest_otbn_sca_big_num_t, OTBN_SCA_BIG_NUM); - -#define OTBN_SCA_ECDSA_P256_SIGN(field, string) \ - field(msg, uint32_t, 8) \ - field(d0, uint32_t, 10) \ - field(k0, uint32_t, 10) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaEcdsaP256Sign, penetrationtest_otbn_sca_ecdsa_p256_sign_t, OTBN_SCA_ECDSA_P256_SIGN); - -#define OTBN_SCA_ECDSA_P256_SIGNATURE(field, string) \ - field(r, uint8_t, 32) \ - field(s, uint8_t, 32) -UJSON_SERDE_STRUCT(PenetrationtestOtbnScaEcdsaP256Signature, penetrationtest_otbn_sca_ecdsa_p256_signature_t, OTBN_SCA_ECDSA_P256_SIGNATURE); - -#define OTBN_SCA_TEST_BATCH_OPS(field, string) \ - field(num_iterations, uint32_t) \ - field(fixed_data1, uint32_t) \ - field(fixed_data2, uint32_t) \ - field(print_flag, bool) \ - field(trigger, uint32_t) -UJSON_SERDE_STRUCT(OtbnScaTestBatchOps, otbn_sca_test_batch_ops_t, OTBN_SCA_TEST_BATCH_OPS); - -#define OTBN_SCA_OPS_RESULT(field, string) \ - field(result1, uint32_t, 8) \ - field(result2, uint32_t, 8) \ - field(result3, uint32_t, 8) \ - field(result4, uint32_t, 8) \ - field(result5, uint32_t, 8) \ - field(result6, uint32_t, 8) \ - field(result7, uint32_t, 8) \ - field(result8, uint32_t) -UJSON_SERDE_STRUCT(OtbnScaOpsResult, otbn_sca_ops_result_t, OTBN_SCA_OPS_RESULT); - -#define OTBN_SCA_EMPTY(field, string) \ - field(success, bool) -UJSON_SERDE_STRUCT(OtbnScaEmpty, otbn_sca_empty_t, OTBN_SCA_EMPTY); - -// clang-format on - -#ifdef __cplusplus -} -#endif -#endif // OPENTITAN_SW_DEVICE_TESTS_PENETRATIONTESTS_JSON_OTBN_SCA_COMMANDS_H_ diff --git a/sw/device/tests/penetrationtests/pentest.bzl b/sw/device/tests/penetrationtests/pentest.bzl index 1b6b96d0a25..47dd1032e0a 100644 --- a/sw/device/tests/penetrationtests/pentest.bzl +++ b/sw/device/tests/penetrationtests/pentest.bzl @@ -60,8 +60,8 @@ FIRMWARE_DEPS_FI_IBEX = [ "//sw/device/tests/penetrationtests/json:commands", ] -FIRMWARE_DEPS_FI_OTBN = [ - "//sw/device/tests/penetrationtests/firmware/fi:otbn_fi", +FIRMWARE_DEPS_FI_ACC = [ + "//sw/device/tests/penetrationtests/firmware/fi:acc_fi", "//sw/device/tests/penetrationtests/firmware/lib:pentest_lib", "//sw/device/lib/base:csr", "//sw/device/lib/base:status", @@ -81,7 +81,7 @@ FIRMWARE_DEPS_SCA = [ "//sw/device/tests/penetrationtests/firmware/sca:hmac_sca", "//sw/device/tests/penetrationtests/firmware/sca:ibex_sca", "//sw/device/tests/penetrationtests/firmware/sca:kmac_sca", - "//sw/device/tests/penetrationtests/firmware/sca:otbn_sca", + "//sw/device/tests/penetrationtests/firmware/sca:acc_sca", "//sw/device/tests/penetrationtests/firmware/sca:prng_sca", "//sw/device/tests/penetrationtests/firmware/sca:sha3_sca", "//sw/device/tests/penetrationtests/firmware/sca:trigger_sca", @@ -255,7 +255,7 @@ def pentest_fi_ibex(name, test_vectors, test_args, test_harness, tags): deps = FIRMWARE_DEPS_FI_IBEX, ) -def pentest_fi_otbn(name, test_vectors, test_args, test_harness, tags): +def pentest_fi_acc(name, test_vectors, test_args, test_harness, tags): """A macro for defining a CryptoTest test case. Args: @@ -267,7 +267,7 @@ def pentest_fi_otbn(name, test_vectors, test_args, test_harness, tags): """ opentitan_test( name = name, - srcs = ["//sw/device/tests/penetrationtests/firmware:firmware_fi_otbn.c"], + srcs = ["//sw/device/tests/penetrationtests/firmware:firmware_fi_acc.c"], fpga = fpga_params( timeout = "moderate", data = test_vectors, @@ -296,7 +296,7 @@ def pentest_fi_otbn(name, test_vectors, test_args, test_harness, tags): """ + test_args, test_harness = test_harness, ), - deps = FIRMWARE_DEPS_FI_OTBN, + deps = FIRMWARE_DEPS_FI_ACC, ) def pentest_sca(name, test_vectors, test_args, test_harness, tags): diff --git a/sw/device/tests/power_virus_systemtest.c b/sw/device/tests/power_virus_systemtest.c index b28c368ea8a..498f29b82fe 100644 --- a/sw/device/tests/power_virus_systemtest.c +++ b/sw/device/tests/power_virus_systemtest.c @@ -6,6 +6,7 @@ #include "hw/top/dt/dt_api.h" // Generated #include "sw/device/lib/base/math.h" #include "sw/device/lib/base/multibits.h" +#include "sw/device/lib/dif/dif_acc.h" #include "sw/device/lib/dif/dif_adc_ctrl.h" #include "sw/device/lib/dif/dif_aes.h" #include "sw/device/lib/dif/dif_csrng.h" @@ -17,7 +18,6 @@ #include "sw/device/lib/dif/dif_hmac.h" #include "sw/device/lib/dif/dif_i2c.h" #include "sw/device/lib/dif/dif_kmac.h" -#include "sw/device/lib/dif/dif_otbn.h" #include "sw/device/lib/dif/dif_pattgen.h" #include "sw/device/lib/dif/dif_pinmux.h" #include "sw/device/lib/dif/dif_pwm.h" @@ -26,12 +26,12 @@ #include "sw/device/lib/dif/dif_spi_host.h" #include "sw/device/lib/dif/dif_uart.h" #include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/acc_testutils_rsa.h" #include "sw/device/lib/testing/aes_testutils.h" #include "sw/device/lib/testing/alert_handler_testutils.h" #include "sw/device/lib/testing/entropy_testutils.h" #include "sw/device/lib/testing/hmac_testutils.h" #include "sw/device/lib/testing/i2c_testutils.h" -#include "sw/device/lib/testing/otbn_testutils_rsa.h" #include "sw/device/lib/testing/pinmux_testutils.h" #include "sw/device/lib/testing/spi_device_testutils.h" #include "sw/device/lib/testing/spi_host_testutils.h" @@ -73,7 +73,7 @@ static dif_i2c_t i2c_0; static dif_i2c_t i2c_1; static dif_i2c_t i2c_2; static dif_kmac_t kmac; -static dif_otbn_t otbn; +static dif_acc_t acc; static dif_pattgen_t pattgen; static dif_pinmux_t pinmux; static dif_pwm_t pwm; @@ -392,7 +392,7 @@ static void init_peripheral_handles(void) { CHECK_DIF_OK(dif_spi_host_init( mmio_region_from_addr(TOP_EARLGREY_SPI_HOST1_BASE_ADDR), &spi_host_1)); CHECK_DIF_OK( - dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn)); + dif_acc_init(mmio_region_from_addr(TOP_EARLGREY_ACC_BASE_ADDR), &acc)); CHECK_DIF_OK(dif_pattgen_init( mmio_region_from_addr(TOP_EARLGREY_PATTGEN_BASE_ADDR), &pattgen)); CHECK_DIF_OK(dif_pwm_init( @@ -1031,8 +1031,8 @@ void configure_pwm(void) { /*channels*/ (1u << PWM_PARAM_N_OUTPUTS) - 1, kDifToggleEnabled)); } -static void configure_otbn(void) { - CHECK_STATUS_OK(otbn_testutils_rsa_load(&otbn)); +static void configure_acc(void) { + CHECK_STATUS_OK(acc_testutils_rsa_load(&acc)); } static void check_crypto_blocks_idle(void) { @@ -1046,10 +1046,10 @@ static void check_crypto_blocks_idle(void) { dif_kmac_status_t kmac_status; CHECK_DIF_OK(dif_kmac_get_status(&kmac, &kmac_status)); CHECK(kmac_status.sha3_state == kDifKmacSha3StateAbsorbing); - // OTBN - dif_otbn_status_t otbn_status; - CHECK_DIF_OK(dif_otbn_get_status(&otbn, &otbn_status)); - CHECK(otbn_status == kDifOtbnStatusIdle); + // ACC + dif_acc_status_t acc_status; + CHECK_DIF_OK(dif_acc_get_status(&acc, &acc_status)); + CHECK(acc_status == kDifAccStatusIdle); } static void complete_kmac_operations(uint32_t *digest) { @@ -1278,9 +1278,9 @@ static void max_power(void) { mmio_region_write32(i2c_1.base_addr, I2C_CTRL_REG_OFFSET, i2c_ctrl_reg); mmio_region_write32(i2c_2.base_addr, I2C_CTRL_REG_OFFSET, i2c_ctrl_reg); - // Issue OTBN start command. - CHECK_STATUS_OK(otbn_testutils_rsa_modexp_f4_start( - &otbn, (unsigned char *)kRsa2KModulus, (unsigned char *)kRsa2KSignature, + // Issue ACC start command. + CHECK_STATUS_OK(acc_testutils_rsa_modexp_f4_start( + &acc, (unsigned char *)kRsa2KModulus, (unsigned char *)kRsa2KSignature, sizeof(kRsa2KModulus))); // Enable pattgen. @@ -1351,10 +1351,10 @@ static void max_power(void) { CHECK(kKmacDigestLength == ARRAYSIZE(kKmacDigest)); CHECK_ARRAYS_EQ(kmac_digest, kKmacDigest, ARRAYSIZE(kKmacDigest)); - // Check OTBN operations. + // Check ACC operations. uint32_t rsa_recovered_message[ARRAYSIZE(kRsa2KEncodedMessage)]; - CHECK_STATUS_OK(otbn_testutils_rsa_modexp_f4_finalize( - &otbn, (unsigned char *)rsa_recovered_message, + CHECK_STATUS_OK(acc_testutils_rsa_modexp_f4_finalize( + &acc, (unsigned char *)rsa_recovered_message, sizeof(rsa_recovered_message))); CHECK_ARRAYS_EQ(rsa_recovered_message, kRsa2KEncodedMessage, ARRAYSIZE(kRsa2KEncodedMessage)); @@ -1475,7 +1475,7 @@ bool test_main(void) { dif_gpio_output_set_enabled(&gpio, /*pin=*/0, kDifToggleEnabled)); configure_adc_ctrl_to_continuously_sample(); configure_entropy_complex(); - configure_otbn(); + configure_acc(); configure_uart(&uart_1); configure_uart(&uart_2); configure_uart(&uart_3); diff --git a/sw/device/tests/sim_dv/all_escalation_resets_test.c b/sw/device/tests/sim_dv/all_escalation_resets_test.c index a580d350eda..9cacabf59fb 100644 --- a/sw/device/tests/sim_dv/all_escalation_resets_test.c +++ b/sw/device/tests/sim_dv/all_escalation_resets_test.c @@ -46,6 +46,7 @@ #error "all_escalation_resets_test does not support this top" #endif +#include "hw/top/dt/dt_acc.h" // Generated #include "hw/top/dt/dt_aes.h" // Generated #include "hw/top/dt/dt_alert_handler.h" // Generated #include "hw/top/dt/dt_aon_timer.h" // Generated @@ -58,7 +59,6 @@ #include "hw/top/dt/dt_i2c.h" // Generated #include "hw/top/dt/dt_kmac.h" // Generated #include "hw/top/dt/dt_lc_ctrl.h" // Generated -#include "hw/top/dt/dt_otbn.h" // Generated #include "hw/top/dt/dt_otp_ctrl.h" // Generated #include "hw/top/dt/dt_pinmux.h" // Generated #include "hw/top/dt/dt_pwrmgr.h" // Generated @@ -314,7 +314,7 @@ static const char *i2c0_inst_name = "i2c0"; static const char *kmac_inst_name = "kmac"; // TODO: test lc_ctrl fatal_state, alert 17. static const char *lc_ctrl_inst_name = "lc_ctrl"; -static const char *otbn_inst_name = "otbn"; +static const char *acc_inst_name = "acc"; static const char *otp_ctrl_inst_name = "otp_ctrl"; static const char *pinmux_inst_name = "pinmux"; static const char *pwrmgr_inst_name = "pwrmgr"; @@ -524,25 +524,25 @@ static void lc_ctrl_fault_checker(bool enable, const char *ip_inst, } /* -// TODO(#14518) otbn cannot read fault_status register. -static void otbn_ctrl_fault_checker(bool enable) { - // Check the otbn integrity fatal error code. - dif_otbn_err_bits_t codes; +// TODO(#14518) acc cannot read fault_status register. +static void acc_ctrl_fault_checker(bool enable) { + // Check the acc integrity fatal error code. + dif_acc_err_bits_t codes; // TODO we seem to be missing a dif to read FATAL_ALERT_CAUSE. - CHECK_DIF_OK(dif_otbn_get_err_bits(&otbn, &codes)); + CHECK_DIF_OK(dif_acc_get_err_bits(&acc, &codes)); if (enable) { - CHECK(status.codes == kDifOtbn??, "Got codes 0x%x", codes); + CHECK(status.codes == kDifAcc??, "Got codes 0x%x", codes); } else { CHECK(codes == 0, "Got codes 0x%x", codes); } } */ -static void otbn_fault_checker(bool enable, const char *ip_inst, - const char *type) { +static void acc_fault_checker(bool enable, const char *ip_inst, + const char *type) { // TODO(#14518) - LOG_INFO("Expected alert %d otbn fault check is yet unimplemented", - kDtOtbnAlertFatal); + LOG_INFO("Expected alert %d acc fault check is yet unimplemented", + kDtAccAlertFatal); trivial_fault_checker(enable, ip_inst, type); } @@ -1017,9 +1017,9 @@ static void init_fault_checkers(fault_checker_t *checkers) { kDtLcCtrlAlertFatalBusIntegError)] = (fault_checker_t){lc_ctrl_fault_checker, lc_ctrl_inst_name, we_check}; - checkers[dt_otbn_alert_to_alert_id((dt_otbn_t)0, kDtOtbnAlertFatal)] = - (fault_checker_t){otbn_fault_checker, otbn_inst_name, we_check}; - static_assert(kDtOtbnCount >= 1, "This test needs at least 1 OTBN instance"); + checkers[dt_acc_alert_to_alert_id((dt_acc_t)0, kDtAccAlertFatal)] = + (fault_checker_t){acc_fault_checker, acc_inst_name, we_check}; + static_assert(kDtAccCount >= 1, "This test needs at least 1 ACC instance"); // TODO add mechanism to inject: // forcing otp_prog_err_o from lc_ctrl_fsm and diff --git a/sw/device/tests/sival/BUILD b/sw/device/tests/sival/BUILD index 46707b3dc01..5b3f62f9c6e 100644 --- a/sw/device/tests/sival/BUILD +++ b/sw/device/tests/sival/BUILD @@ -22,7 +22,8 @@ test_suite( "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_0", "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_10", "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_20", - "//sw/device/silicon_creator/lib:otbn_boot_services_functest", + "//sw/device/silicon_creator/lib:acc_boot_services_functest", + "//sw/device/tests:acc_smoketest", "//sw/device/tests:aes_smoketest", "//sw/device/tests:aon_timer_irq_test", "//sw/device/tests:aon_timer_smoketest", @@ -39,11 +40,10 @@ test_suite( "//sw/device/tests:hmac_enc_test", "//sw/device/tests:hmac_smoketest", "//sw/device/tests:i2c_target_test", - "//sw/device/tests:keymgr_sideload_otbn_simple_test", - "//sw/device/tests:keymgr_sideload_otbn_test", + "//sw/device/tests:keymgr_sideload_acc_simple_test", + "//sw/device/tests:keymgr_sideload_acc_test", "//sw/device/tests:kmac_mode_kmac_test", "//sw/device/tests:kmac_smoketest", - "//sw/device/tests:otbn_smoketest", "//sw/device/tests:otp_ctrl_smoketest", "//sw/device/tests:pattgen_ios_test", "//sw/device/tests:pmp_smoketest_napot", @@ -81,6 +81,13 @@ test_suite( "//hw/top_earlgrey/sw/autogen/tests:alert_test", "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_0", "//sw/device/silicon_creator/rom/e2e:rom_e2e_smoke", + "//sw/device/tests:acc_ecdsa_op_irq_test", + "//sw/device/tests:acc_irq_test", + "//sw/device/tests:acc_isa_test", + "//sw/device/tests:acc_mem_scramble_test", + "//sw/device/tests:acc_randomness_test", + "//sw/device/tests:acc_rsa_test", + "//sw/device/tests:acc_smoketest", "//sw/device/tests:aes_entropy_test", "//sw/device/tests:aes_idle_test", "//sw/device/tests:alert_handler_lpg_clkoff_test", @@ -96,10 +103,10 @@ test_suite( "//sw/device/tests:chip_power_idle_load_test", "//sw/device/tests:clkmgr_jitter_frequency_test", "//sw/device/tests:clkmgr_jitter_test", + "//sw/device/tests:clkmgr_off_acc_trans_test", "//sw/device/tests:clkmgr_off_aes_trans_test", "//sw/device/tests:clkmgr_off_hmac_trans_test", "//sw/device/tests:clkmgr_off_kmac_trans_test", - "//sw/device/tests:clkmgr_off_otbn_trans_test", "//sw/device/tests:clkmgr_off_peri_test", "//sw/device/tests:clkmgr_reset_frequency_test", "//sw/device/tests:clkmgr_sleep_frequency_test", @@ -136,13 +143,6 @@ test_suite( "//sw/device/tests:kmac_idle_test", "//sw/device/tests:kmac_kmac_key_sideload_test", "//sw/device/tests:kmac_mode_cshake_test", - "//sw/device/tests:otbn_ecdsa_op_irq_test", - "//sw/device/tests:otbn_irq_test", - "//sw/device/tests:otbn_isa_test", - "//sw/device/tests:otbn_mem_scramble_test", - "//sw/device/tests:otbn_randomness_test", - "//sw/device/tests:otbn_rsa_test", - "//sw/device/tests:otbn_smoketest", "//sw/device/tests:plic_sw_irq_test", "//sw/device/tests:pwrmgr_all_reset_reqs_test", "//sw/device/tests:pwrmgr_deep_sleep_all_reset_reqs_test", diff --git a/sw/device/tock/BUILD b/sw/device/tock/BUILD index b184ade70da..0cfbbe70d88 100644 --- a/sw/device/tock/BUILD +++ b/sw/device/tock/BUILD @@ -9,6 +9,7 @@ package(default_visibility = ["//visibility:public"]) filegroup( name = "lowrisc_defs", srcs = [ + "//hw/top:acc_rust_regs", "//hw/top:adc_ctrl_rust_regs", "//hw/top:aes_rust_regs", "//hw/top:aon_timer_rust_regs", @@ -21,7 +22,6 @@ filegroup( "//hw/top:keymgr_rust_regs", "//hw/top:kmac_rust_regs", "//hw/top:lc_ctrl_rust_regs", - "//hw/top:otbn_rust_regs", "//hw/top:otp_ctrl_rust_regs", "//hw/top:pattgen_rust_regs", "//hw/top:pwm_rust_regs", diff --git a/sw/host/opentitanlib/src/crypto/rsa.rs b/sw/host/opentitanlib/src/crypto/rsa.rs index c43c9443511..37a9efa6eaf 100644 --- a/sw/host/opentitanlib/src/crypto/rsa.rs +++ b/sw/host/opentitanlib/src/crypto/rsa.rs @@ -27,13 +27,13 @@ const MODULUS_BIT_LEN: usize = 3072; const EXPONENT_BIT_LEN: usize = 17; const SIGNATURE_BIT_LEN: usize = 3072; const RR_BIT_LEN: usize = 3072; -const OTBN_BITS: usize = 256; +const ACC_BITS: usize = 256; fixed_size_bigint!(Modulus, MODULUS_BIT_LEN); fixed_size_bigint!(Exponent, EXPONENT_BIT_LEN); fixed_size_bigint!(Signature, at_most SIGNATURE_BIT_LEN); fixed_size_bigint!(RR, at_most RR_BIT_LEN); -fixed_size_bigint!(N0Inv, at_most OTBN_BITS); +fixed_size_bigint!(N0Inv, at_most ACC_BITS); /// Ensure the components of `key` have the correct bit length. fn validate_key(key: &impl PublicKeyParts) -> Result<()> { @@ -117,9 +117,9 @@ impl RsaPublicKey { Exponent::from_le_bytes(self.key.e().to_bytes_le()).unwrap() } - /// Computes the OTBN montgomery parameter: -1 / n\[0\] mod 2^256. + /// Computes the ACC montgomery parameter: -1 / n\[0\] mod 2^256. pub fn n0_inv(&self) -> Result { - let base = BigInt::from(1u8) << OTBN_BITS; + let base = BigInt::from(1u8) << ACC_BITS; let n_neg = BigInt::from_biguint(Minus, self.key.n().to_owned()); let n0_inv = n_neg .mod_inverse(&base) diff --git a/sw/host/ot_hal/bindgen/BUILD b/sw/host/ot_hal/bindgen/BUILD index 806ce0fa6fa..a43a632659c 100644 --- a/sw/host/ot_hal/bindgen/BUILD +++ b/sw/host/ot_hal/bindgen/BUILD @@ -36,7 +36,7 @@ _EARLGREY_DEPS = [ "//sw/device/lib/dif:keymgr", "//sw/device/lib/dif:kmac", "//sw/device/lib/dif:lc_ctrl", - "//sw/device/lib/dif:otbn", + "//sw/device/lib/dif:acc", "//sw/device/lib/dif:otp_ctrl", "//sw/device/lib/dif:pattgen", "//sw/device/lib/dif:pinmux", @@ -101,8 +101,8 @@ rust_bindgen_library( "--allowlist-var=KMAC_.*_REG_OFFSET", "--allowlist-var=LC_CTRL_.*_BIT", "--allowlist-var=LC_CTRL_.*_REG_OFFSET", - "--allowlist-var=OTBN_.*_REG_OFFSET", - "--allowlist-var=OTBN_.*_SIZE_BYTES", + "--allowlist-var=ACC_.*_REG_OFFSET", + "--allowlist-var=ACC_.*_SIZE_BYTES", "--allowlist-var=OTP_CTRL_.*_BIT", "--allowlist-var=OTP_CTRL_.*_OFFSET", "--allowlist-var=OTP_CTRL_.*_SIZE", diff --git a/sw/host/ot_hal/bindgen/difs.h b/sw/host/ot_hal/bindgen/difs.h index efebf969ea2..ba35ee8ba51 100644 --- a/sw/host/ot_hal/bindgen/difs.h +++ b/sw/host/ot_hal/bindgen/difs.h @@ -21,6 +21,7 @@ #else +#include "hw/top/acc_regs.h" // Generated. #include "hw/top/adc_ctrl_regs.h" // Generated. #include "hw/top/aes_regs.h" // Generated. #include "hw/top/alert_handler_regs.h" // Generated. @@ -36,7 +37,6 @@ #include "hw/top/keymgr_regs.h" // Generated. #include "hw/top/kmac_regs.h" // Generated. #include "hw/top/lc_ctrl_regs.h" // Generated. -#include "hw/top/otbn_regs.h" // Generated. #include "hw/top/otp_ctrl_regs.h" // Generated. #include "hw/top/pattgen_regs.h" // Generated. #include "hw/top/pinmux_regs.h" // Generated. diff --git a/sw/host/penetrationtests/python/fi/BUILD b/sw/host/penetrationtests/python/fi/BUILD index c9af46cfdf9..fdf0fa69ca1 100644 --- a/sw/host/penetrationtests/python/fi/BUILD +++ b/sw/host/penetrationtests/python/fi/BUILD @@ -44,16 +44,16 @@ py_binary( ) py_binary( - name = "fi_otbn_python_test", + name = "fi_acc_python_test", testonly = True, - srcs = ["test_scripts/fi_otbn_python_test.py"], + srcs = ["test_scripts/fi_acc_python_test.py"], data = [ "//sw/host/opentitantool", - "//sw/host/penetrationtests/python/fi/gold_responses:fi_otbn", + "//sw/host/penetrationtests/python/fi/gold_responses:fi_acc", ], deps = [ - "//sw/host/penetrationtests/python/fi:fi_otbn_commands", - "//sw/host/penetrationtests/python/fi:fi_otbn_functions", + "//sw/host/penetrationtests/python/fi:fi_acc_commands", + "//sw/host/penetrationtests/python/fi:fi_acc_functions", "//sw/host/penetrationtests/python/util:common_library", "//sw/host/penetrationtests/python/util:targets", "//sw/host/penetrationtests/python/util:utils", @@ -189,10 +189,10 @@ py_library( ) py_library( - name = "fi_otbn_functions", - srcs = ["host_scripts/fi_otbn_functions.py"], + name = "fi_acc_functions", + srcs = ["host_scripts/fi_acc_functions.py"], deps = [ - ":fi_otbn_commands", + ":fi_acc_commands", "//sw/host/penetrationtests/python/util:common_library", "//sw/host/penetrationtests/python/util:targets", ], @@ -271,8 +271,8 @@ py_library( ) py_library( - name = "fi_otbn_commands", - srcs = ["communication/fi_otbn_commands.py"], + name = "fi_acc_commands", + srcs = ["communication/fi_acc_commands.py"], deps = ["//sw/host/penetrationtests/python/util:common_library"], ) diff --git a/sw/host/penetrationtests/python/fi/communication/fi_otbn_commands.py b/sw/host/penetrationtests/python/fi/communication/fi_acc_commands.py similarity index 61% rename from sw/host/penetrationtests/python/fi/communication/fi_otbn_commands.py rename to sw/host/penetrationtests/python/fi/communication/fi_acc_commands.py index a9325b1480b..a7d40909825 100644 --- a/sw/host/penetrationtests/python/fi/communication/fi_otbn_commands.py +++ b/sw/host/penetrationtests/python/fi/communication/fi_acc_commands.py @@ -1,7 +1,7 @@ # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -"""Communication interface for OpenTitan OTBN FI framework. +"""Communication interface for OpenTitan ACC FI framework. Communication with OpenTitan happens over the uJSON command interface. """ @@ -10,53 +10,53 @@ from sw.host.penetrationtests.python.util import common_library -class OTFIOtbn: +class OTFIAcc: def __init__(self, target) -> None: self.target = target - def _ujson_otbn_fi_cmd(self) -> None: - self.target.write(json.dumps("OtbnFi").encode("ascii")) + def _ujson_acc_fi_cmd(self) -> None: + self.target.write(json.dumps("AccFi").encode("ascii")) time.sleep(0.003) - def otbn_char_dmem_access(self) -> None: - """Starts the otbn.fi.char.dmem.access test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_dmem_access(self) -> None: + """Starts the acc.fi.char.dmem.access test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharDmemAccess command. self.target.write(json.dumps("CharDmemAccess").encode("ascii")) - def otbn_char_dmem_write(self) -> None: - """Starts the otbn.fi.char.dmem.write test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_dmem_write(self) -> None: + """Starts the acc.fi.char.dmem.write test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharDmemWrite command. self.target.write(json.dumps("CharDmemWrite").encode("ascii")) - def otbn_char_rf(self) -> None: - """Starts the otbn.fi.char.rf test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_rf(self) -> None: + """Starts the acc.fi.char.rf test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharRF command. self.target.write(json.dumps("CharRF").encode("ascii")) - def otbn_char_beq(self) -> None: - """Starts the otbn.fi.char.beq test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_beq(self) -> None: + """Starts the acc.fi.char.beq test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharBeq command. self.target.write(json.dumps("CharBeq").encode("ascii")) - def otbn_char_jal(self) -> None: - """Starts the otbn.fi.char.jal test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_jal(self) -> None: + """Starts the acc.fi.char.jal test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharJal command. self.target.write(json.dumps("CharJal").encode("ascii")) - def otbn_char_mem(self, byte_offset, num_words, imem, dmem, first_call) -> None: - """Starts the otbn.fi.char.mem test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_mem(self, byte_offset, num_words, imem, dmem, first_call) -> None: + """Starts the acc.fi.char.mem test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharMem command. self.target.write(json.dumps("CharMem").encode("ascii")) if first_call: @@ -68,91 +68,91 @@ def otbn_char_mem(self, byte_offset, num_words, imem, dmem, first_call) -> None: } self.target.write(json.dumps(parameters).encode("ascii")) - def otbn_char_bn_sel(self, data) -> None: - """Starts the otbn.fi.char.bn.sel test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_bn_sel(self, data) -> None: + """Starts the acc.fi.char.bn.sel test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharBnSel command. self.target.write(json.dumps("CharBnSel").encode("ascii")) parameters = {"big_num": data} self.target.write(json.dumps(parameters).encode("ascii")) - def otbn_char_bne(self) -> None: - """Starts the otbn.fi.char.bne test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_bne(self) -> None: + """Starts the acc.fi.char.bne test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharBne command. self.target.write(json.dumps("CharBne").encode("ascii")) - def otbn_char_bn_rshi(self, data) -> None: - """Starts the otbn.fi.char.bn.rshi test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_bn_rshi(self, data) -> None: + """Starts the acc.fi.char.bn.rshi test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharBnRshi command. self.target.write(json.dumps("CharBnRshi").encode("ascii")) parameters = {"big_num": data} self.target.write(json.dumps(parameters).encode("ascii")) - def otbn_char_bn_wsrr(self) -> None: - """Starts the otbn.fi.char.bn.wsrr test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_bn_wsrr(self) -> None: + """Starts the acc.fi.char.bn.wsrr test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharBnWsrr command. self.target.write(json.dumps("CharBnWsrr").encode("ascii")) - def otbn_char_lw(self) -> None: - """Starts the otbn.fi.char.lw test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_lw(self) -> None: + """Starts the acc.fi.char.lw test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharLw command. self.target.write(json.dumps("CharLw").encode("ascii")) - def otbn_char_unrolled_reg_op_loop(self) -> None: - """Starts the otbn.fi.char.unrolled.reg.op.loop test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_unrolled_reg_op_loop(self) -> None: + """Starts the acc.fi.char.unrolled.reg.op.loop test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharUnrolledRegOpLoop command. self.target.write(json.dumps("CharUnrolledRegOpLoop").encode("ascii")) - def otbn_char_unrolled_dmem_op_loop(self) -> None: - """Starts the otbn.fi.char.unrolled.dmem.op.loop test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_unrolled_dmem_op_loop(self) -> None: + """Starts the acc.fi.char.unrolled.dmem.op.loop test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharUnrolledDmemOpLoop command. self.target.write(json.dumps("CharUnrolledDmemOpLoop").encode("ascii")) - def otbn_char_hardware_reg_op_loop(self) -> None: - """Starts the otbn.fi.char.hardware.reg.op.loop test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_hardware_reg_op_loop(self) -> None: + """Starts the acc.fi.char.hardware.reg.op.loop test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharHardwareRegOpLoop command. self.target.write(json.dumps("CharHardwareRegOpLoop").encode("ascii")) - def otbn_char_hardware_dmem_op_loop(self) -> None: - """Starts the otbn.fi.char.hardware.dmem.op.loop test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_char_hardware_dmem_op_loop(self) -> None: + """Starts the acc.fi.char.hardware.dmem.op.loop test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # CharMemOpLoop command. self.target.write(json.dumps("CharHardwareDmemOpLoop").encode("ascii")) - def otbn_key_sideload(self) -> None: - """Starts the otbn.fi.key_sideload test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_key_sideload(self) -> None: + """Starts the acc.fi.key_sideload test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # KeySideload command. self.target.write(json.dumps("KeySideload").encode("ascii")) - def otbn_load_integrity(self) -> None: - """Starts the otbn.fi.load_integrity test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_load_integrity(self) -> None: + """Starts the acc.fi.load_integrity test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # LoadIntegrity command. self.target.write(json.dumps("LoadIntegrity").encode("ascii")) - def otbn_pc(self, pc) -> None: - """Starts the otbn.pc test.""" - # OtbnFi command. - self._ujson_otbn_fi_cmd() + def acc_pc(self, pc) -> None: + """Starts the acc.pc test.""" + # AccFi command. + self._ujson_acc_fi_cmd() # PC command. self.target.write(json.dumps("PC").encode("ascii")) parameters = {"pc": pc} @@ -165,8 +165,8 @@ def init_keymgr(self, test: str) -> None: needed. """ if "key_sideload" in test: - # OtbnFi command. - self._ujson_otbn_fi_cmd() + # AccFi command. + self._ujson_acc_fi_cmd() # InitTrigger command. self.target.write(json.dumps("InitKeyMgr").encode("ascii")) @@ -176,7 +176,7 @@ def init( sensor_config: dict = common_library.default_sensor_config, alert_config: dict = common_library.default_alert_config, ) -> tuple: - """Initialize the OTBN FI code on the chip. + """Initialize the ACC FI code on the chip. Returns: Device id @@ -188,8 +188,8 @@ def init( The testOS version """ - # OtbnFi command. - self._ujson_otbn_fi_cmd() + # AccFi command. + self._ujson_acc_fi_cmd() # Init command. self.target.write(json.dumps("Init").encode("ascii")) diff --git a/sw/host/penetrationtests/python/fi/gold_responses/BUILD b/sw/host/penetrationtests/python/fi/gold_responses/BUILD index 9d2105967de..6fffcbff12a 100644 --- a/sw/host/penetrationtests/python/fi/gold_responses/BUILD +++ b/sw/host/penetrationtests/python/fi/gold_responses/BUILD @@ -15,8 +15,8 @@ filegroup( ) filegroup( - name = "fi_otbn", - srcs = ["fi_otbn.json"], + name = "fi_acc", + srcs = ["fi_acc.json"], ) filegroup( diff --git a/sw/host/penetrationtests/python/fi/gold_responses/fi_otbn.json b/sw/host/penetrationtests/python/fi/gold_responses/fi_acc.json similarity index 91% rename from sw/host/penetrationtests/python/fi/gold_responses/fi_otbn.json rename to sw/host/penetrationtests/python/fi/gold_responses/fi_acc.json index 31b0c7ec81b..732633e53e4 100644 --- a/sw/host/penetrationtests/python/fi/gold_responses/fi_otbn.json +++ b/sw/host/penetrationtests/python/fi/gold_responses/fi_acc.json @@ -2,7 +2,7 @@ "char_beq": { "result": 0, "insn_cnt": 509, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -10,7 +10,7 @@ "char_bn_rshi": { "big_num": [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], "insn_cnt": 109, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -18,7 +18,7 @@ "char_bn_sel": { "big_num": [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], "insn_cnt": 1014, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -26,7 +26,7 @@ "char_bn_wsrr": { "res": 0, "insn_cnt": 1089, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -34,7 +34,7 @@ "char_bne": { "result": 0, "insn_cnt": 509, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -42,7 +42,7 @@ "char_dmem_access": { "res": 0, "insn_cnt": 271, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -52,21 +52,21 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "insn_cnt": 1, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] }, "char_dmem_op_loop": { "loop_counter": 10000, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] }, "char_reg_op_loop": { "loop_counter": 10000, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -74,7 +74,7 @@ "char_jal": { "result": 0, "insn_cnt": 505, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -84,7 +84,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "insn_cnt": 1084, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -95,7 +95,7 @@ "imem_addr": [0, 0, 0, 0, 0, 0, 0, 0], "dmem_data": [0, 0, 0, 0, 0, 0, 0, 0], "dmem_addr": [0, 0, 0, 0, 0, 0, 0, 0], - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] @@ -108,37 +108,37 @@ "faulty_wdr": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] }, "char_unrolled_dmem_op_loop": { "loop_counter": 100, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] }, "char_unrolled_reg_op_loop": { "loop_counter": 100, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] }, "char_load_integrity": { "result": 0, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] }, "char_pc": { "pc_dmem": 2224, - "pc_otbn": 2224, + "pc_acc": 2224, "insn_cnt": 472, - "err_otbn": 0, + "err_acc": 0, "err_ibx": 0, "alerts": [0, 0, 0], "ast_alerts": [0, 0] diff --git a/sw/host/penetrationtests/python/fi/host_scripts/fi_otbn_functions.py b/sw/host/penetrationtests/python/fi/host_scripts/fi_acc_functions.py similarity index 74% rename from sw/host/penetrationtests/python/fi/host_scripts/fi_otbn_functions.py rename to sw/host/penetrationtests/python/fi/host_scripts/fi_acc_functions.py index 6f9ecb1b171..186fa6cc095 100644 --- a/sw/host/penetrationtests/python/fi/host_scripts/fi_otbn_functions.py +++ b/sw/host/penetrationtests/python/fi/host_scripts/fi_acc_functions.py @@ -2,211 +2,211 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -from sw.host.penetrationtests.python.fi.communication.fi_otbn_commands import OTFIOtbn +from sw.host.penetrationtests.python.fi.communication.fi_acc_commands import OTFIAcc from sw.host.penetrationtests.python.util import common_library def char_beq(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_beq() + accfi.acc_char_beq() response = target.read_response() # Return the result that is read out return response def char_bn_rshi(target, iterations, data, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_bn_rshi(data) + accfi.acc_char_bn_rshi(data) response = target.read_response() # Return the result that is read out return response def char_bn_sel(target, iterations, data, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_bn_sel(data) + accfi.acc_char_bn_sel(data) response = target.read_response() # Return the result that is read out return response def char_bn_wsrr(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_bn_wsrr() + accfi.acc_char_bn_wsrr() response = target.read_response() # Return the result that is read out return response def char_bne(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_bne() + accfi.acc_char_bne() response = target.read_response() # Return the result that is read out return response def char_dmem_access(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_dmem_access() + accfi.acc_char_dmem_access() response = target.read_response() # Return the result that is read out return response def char_dmem_write(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_dmem_write() + accfi.acc_char_dmem_write() response = target.read_response() # Return the result that is read out return response def char_dmem_op_loop(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_hardware_dmem_op_loop() + accfi.acc_char_hardware_dmem_op_loop() response = target.read_response() # Return the result that is read out return response def char_reg_op_loop(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_hardware_reg_op_loop() + accfi.acc_char_hardware_reg_op_loop() response = target.read_response() # Return the result that is read out return response def char_jal(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_jal() + accfi.acc_char_jal() response = target.read_response() # Return the result that is read out return response def char_lw(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_lw() + accfi.acc_char_lw() response = target.read_response() # Return the result that is read out return response def char_mem(target, iterations, byte_offset, num_words, imem, dmem, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) # The config is only set in the first call first_call = True for _ in range(iterations): - otbnfi.otbn_char_mem(byte_offset, num_words, imem, dmem, first_call) + accfi.acc_char_mem(byte_offset, num_words, imem, dmem, first_call) first_call = False response = target.read_response() # Return the result that is read out @@ -214,85 +214,85 @@ def char_mem(target, iterations, byte_offset, num_words, imem, dmem, reset = Fal def char_rf(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_rf() + accfi.acc_char_rf() response = target.read_response() # Return the result that is read out return response def char_unrolled_dmem_op_loop(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_unrolled_dmem_op_loop() + accfi.acc_char_unrolled_dmem_op_loop() response = target.read_response() # Return the result that is read out return response def char_unrolled_reg_op_loop(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_char_unrolled_reg_op_loop() + accfi.acc_char_unrolled_reg_op_loop() response = target.read_response() # Return the result that is read out return response def char_load_integrity(target, iterations, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_load_integrity() + accfi.acc_load_integrity() response = target.read_response() # Return the result that is read out return response def char_pc(target, iterations, pc, reset = False): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) for _ in range(iterations): - otbnfi.otbn_pc(pc) + accfi.acc_pc(pc) response = target.read_response() # Return the result that is read out return response diff --git a/sw/host/penetrationtests/python/fi/test_scripts/fi_otbn_python_test.py b/sw/host/penetrationtests/python/fi/test_scripts/fi_acc_python_test.py similarity index 86% rename from sw/host/penetrationtests/python/fi/test_scripts/fi_otbn_python_test.py rename to sw/host/penetrationtests/python/fi/test_scripts/fi_acc_python_test.py index dfd8175d33c..d374e5cccde 100644 --- a/sw/host/penetrationtests/python/fi/test_scripts/fi_otbn_python_test.py +++ b/sw/host/penetrationtests/python/fi/test_scripts/fi_acc_python_test.py @@ -2,8 +2,8 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -from sw.host.penetrationtests.python.fi.host_scripts import fi_otbn_functions -from sw.host.penetrationtests.python.fi.communication.fi_otbn_commands import OTFIOtbn +from sw.host.penetrationtests.python.fi.host_scripts import fi_acc_functions +from sw.host.penetrationtests.python.fi.communication.fi_acc_commands import OTFIAcc from python.runfiles import Runfiles from sw.host.penetrationtests.python.util import targets from sw.host.penetrationtests.python.util import utils @@ -32,7 +32,7 @@ def load_test_data(test_name): data_path = r.Rlocation( - "lowrisc_opentitan/sw/host/penetrationtests/python/fi/gold_responses/fi_otbn.json" + "lowrisc_opentitan/sw/host/penetrationtests/python/fi/gold_responses/fi_acc.json" ) with open(data_path, 'r') as f: @@ -40,12 +40,12 @@ def load_test_data(test_name): return data[test_name] -class OtbnFiTest(unittest.TestCase): +class AccFiTest(unittest.TestCase): def test_init(self): - otbnfi = OTFIOtbn(target) + accfi = OTFIAcc(target) device_id, sensors, alerts, owner_page, boot_log, boot_measurements, version = ( - otbnfi.init(alert_config=common_library.default_fpga_friendly_alert_config) + accfi.init(alert_config=common_library.default_fpga_friendly_alert_config) ) device_id_json = json.loads(device_id) sensors_json = json.loads(sensors) @@ -149,7 +149,7 @@ def test_init(self): self.assertIn("PENTEST", version) def test_char_beq(self): - actual_result = fi_otbn_functions.char_beq(target, iterations) + actual_result = fi_acc_functions.char_beq(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_beq') utils.compare_json_data( @@ -158,7 +158,7 @@ def test_char_beq(self): def test_char_bn_rshi(self): data = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] - actual_result = fi_otbn_functions.char_bn_rshi(target, iterations, data) + actual_result = fi_acc_functions.char_bn_rshi(target, iterations, data) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_bn_rshi') utils.compare_json_data( @@ -167,7 +167,7 @@ def test_char_bn_rshi(self): def test_char_bn_sel(self): data = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] - actual_result = fi_otbn_functions.char_bn_sel(target, iterations, data) + actual_result = fi_acc_functions.char_bn_sel(target, iterations, data) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_bn_sel') utils.compare_json_data( @@ -175,7 +175,7 @@ def test_char_bn_sel(self): ) def test_char_bn_wsrr(self): - actual_result = fi_otbn_functions.char_bn_wsrr(target, iterations) + actual_result = fi_acc_functions.char_bn_wsrr(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_bn_wsrr') utils.compare_json_data( @@ -183,7 +183,7 @@ def test_char_bn_wsrr(self): ) def test_char_bne(self): - actual_result = fi_otbn_functions.char_bne(target, iterations) + actual_result = fi_acc_functions.char_bne(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_bne') utils.compare_json_data( @@ -191,7 +191,7 @@ def test_char_bne(self): ) def test_char_dmem_access(self): - actual_result = fi_otbn_functions.char_dmem_access(target, iterations) + actual_result = fi_acc_functions.char_dmem_access(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_dmem_access') utils.compare_json_data( @@ -199,7 +199,7 @@ def test_char_dmem_access(self): ) def test_char_dmem_write(self): - actual_result = fi_otbn_functions.char_dmem_write(target, iterations) + actual_result = fi_acc_functions.char_dmem_write(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_dmem_write') utils.compare_json_data( @@ -207,7 +207,7 @@ def test_char_dmem_write(self): ) def test_char_dmem_op_loop(self): - actual_result = fi_otbn_functions.char_dmem_op_loop(target, iterations) + actual_result = fi_acc_functions.char_dmem_op_loop(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_dmem_op_loop') utils.compare_json_data( @@ -215,7 +215,7 @@ def test_char_dmem_op_loop(self): ) def test_char_reg_op_loop(self): - actual_result = fi_otbn_functions.char_reg_op_loop(target, iterations) + actual_result = fi_acc_functions.char_reg_op_loop(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_reg_op_loop') utils.compare_json_data( @@ -223,7 +223,7 @@ def test_char_reg_op_loop(self): ) def test_char_jal(self): - actual_result = fi_otbn_functions.char_jal(target, iterations) + actual_result = fi_acc_functions.char_jal(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_jal') utils.compare_json_data( @@ -231,7 +231,7 @@ def test_char_jal(self): ) def test_char_lw(self): - actual_result = fi_otbn_functions.char_lw(target, iterations) + actual_result = fi_acc_functions.char_lw(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_lw') utils.compare_json_data( @@ -243,7 +243,7 @@ def test_char_mem(self): num_words = 4 imem = False dmem = True - actual_result = fi_otbn_functions.char_mem( + actual_result = fi_acc_functions.char_mem( target, iterations, byte_offset, num_words, imem, dmem ) actual_result_json = json.loads(actual_result) @@ -253,7 +253,7 @@ def test_char_mem(self): ) def test_char_rf(self): - actual_result = fi_otbn_functions.char_rf(target, iterations) + actual_result = fi_acc_functions.char_rf(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_rf') utils.compare_json_data( @@ -261,7 +261,7 @@ def test_char_rf(self): ) def test_char_unrolled_dmem_op_loop(self): - actual_result = fi_otbn_functions.char_unrolled_dmem_op_loop(target, iterations) + actual_result = fi_acc_functions.char_unrolled_dmem_op_loop(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_unrolled_dmem_op_loop') utils.compare_json_data( @@ -269,7 +269,7 @@ def test_char_unrolled_dmem_op_loop(self): ) def test_char_unrolled_reg_op_loop(self): - actual_result = fi_otbn_functions.char_unrolled_reg_op_loop(target, iterations) + actual_result = fi_acc_functions.char_unrolled_reg_op_loop(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_unrolled_reg_op_loop') utils.compare_json_data( @@ -277,7 +277,7 @@ def test_char_unrolled_reg_op_loop(self): ) def test_char_load_integrity(self): - actual_result = fi_otbn_functions.char_load_integrity(target, iterations) + actual_result = fi_acc_functions.char_load_integrity(target, iterations) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_load_integrity') utils.compare_json_data( @@ -286,7 +286,7 @@ def test_char_load_integrity(self): def test_char_pc(self): pc = 2224 - actual_result = fi_otbn_functions.char_pc(target, iterations, pc) + actual_result = fi_acc_functions.char_pc(target, iterations, pc) actual_result_json = json.loads(actual_result) expected_result_json = load_test_data('char_pc') utils.compare_json_data( diff --git a/sw/host/penetrationtests/python/fi/test_scripts/fi_alert_python_test.py b/sw/host/penetrationtests/python/fi/test_scripts/fi_alert_python_test.py index 8f90f281058..cda487fc598 100644 --- a/sw/host/penetrationtests/python/fi/test_scripts/fi_alert_python_test.py +++ b/sw/host/penetrationtests/python/fi/test_scripts/fi_alert_python_test.py @@ -60,8 +60,8 @@ 16, # Case 27 maps to alert_list index 16 ("lc_ctrl_fatal_prog_error") 17, # Case 28 maps to alert_list index 17 ("lc_ctrl_fatal_state_error") 18, # Case 29 maps to alert_list index 18 ("lc_ctrl_fatal_bus_integ_error") - 47, # Case 30 maps to alert_list index 47 ("otbn_fatal") - 48, # Case 31 maps to alert_list index 48 ("otbn_recov") + 47, # Case 30 maps to alert_list index 47 ("acc_fatal") + 48, # Case 31 maps to alert_list index 48 ("acc_recov") 11, # Case 32 maps to alert_list index 11 ("otp_ctrl_fatal_macro_error") 12, # Case 33 maps to alert_list index 12 ("otp_ctrl_fatal_check_error") 13, # Case 34 maps to alert_list index 13 ("otp_ctrl_fatal_bus_integ_error") diff --git a/sw/host/penetrationtests/python/sca/BUILD b/sw/host/penetrationtests/python/sca/BUILD index 39959148aa0..bdc44089a16 100644 --- a/sw/host/penetrationtests/python/sca/BUILD +++ b/sw/host/penetrationtests/python/sca/BUILD @@ -75,15 +75,15 @@ py_binary( ) py_binary( - name = "sca_otbn_python_test", + name = "sca_acc_python_test", testonly = True, - srcs = ["test_scripts/sca_otbn_python_test.py"], + srcs = ["test_scripts/sca_acc_python_test.py"], data = [ "//sw/host/opentitantool", ], deps = [ - "//sw/host/penetrationtests/python/sca:sca_otbn_commands", - "//sw/host/penetrationtests/python/sca:sca_otbn_functions", + "//sw/host/penetrationtests/python/sca:sca_acc_commands", + "//sw/host/penetrationtests/python/sca:sca_acc_functions", "//sw/host/penetrationtests/python/util:targets", "//sw/host/penetrationtests/python/util:utils", "@rules_python//python/runfiles", @@ -185,10 +185,10 @@ py_library( ) py_library( - name = "sca_otbn_functions", - srcs = ["host_scripts/sca_otbn_functions.py"], + name = "sca_acc_functions", + srcs = ["host_scripts/sca_acc_functions.py"], deps = [ - ":sca_otbn_commands", + ":sca_acc_commands", "//sw/host/penetrationtests/python/util:targets", ], ) @@ -249,8 +249,8 @@ py_library( ) py_library( - name = "sca_otbn_commands", - srcs = ["communication/sca_otbn_commands.py"], + name = "sca_acc_commands", + srcs = ["communication/sca_acc_commands.py"], deps = ["//sw/host/penetrationtests/python/util:common_library"], ) diff --git a/sw/host/penetrationtests/python/sca/communication/sca_otbn_commands.py b/sw/host/penetrationtests/python/sca/communication/sca_acc_commands.py similarity index 84% rename from sw/host/penetrationtests/python/sca/communication/sca_otbn_commands.py rename to sw/host/penetrationtests/python/sca/communication/sca_acc_commands.py index 301744deee0..4352766e866 100644 --- a/sw/host/penetrationtests/python/sca/communication/sca_otbn_commands.py +++ b/sw/host/penetrationtests/python/sca/communication/sca_acc_commands.py @@ -1,7 +1,7 @@ # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -"""Communication interface for the OTBN SCA application on OpenTitan. +"""Communication interface for the ACC SCA application on OpenTitan. Communication with OpenTitan happens the uJson command interface. @@ -11,12 +11,12 @@ from sw.host.penetrationtests.python.util import common_library -class OTOTBN: +class OTACC: def __init__(self, target) -> None: self.target = target - def _ujson_otbn_sca_cmd(self): - self.target.write(json.dumps("OtbnSca").encode("ascii")) + def _ujson_acc_sca_cmd(self): + self.target.write(json.dumps("AccSca").encode("ascii")) time.sleep(0.003) def init( @@ -24,7 +24,7 @@ def init( core_config: dict = common_library.default_core_config, sensor_config: dict = common_library.default_sensor_config, ) -> tuple: - """Initializes the Otbn SCA tests on the target. + """Initializes the Acc SCA tests on the target. Returns: Device id @@ -34,8 +34,8 @@ def init( The testOS version """ - # OtbnSca command. - self._ujson_otbn_sca_cmd() + # AccSca command. + self._ujson_acc_sca_cmd() # Init command. self.target.write(json.dumps("Init").encode("ascii")) @@ -51,34 +51,34 @@ def init( return device_id, owner_page, boot_log, boot_measurements, version def init_keymgr(self): - """Initializes the key manager for OTBN on the target.""" - # OtbnSca command. - self._ujson_otbn_sca_cmd() + """Initializes the key manager for ACC on the target.""" + # AccSca command. + self._ujson_acc_sca_cmd() # Init the key manager. self.target.write(json.dumps("InitKeyMgr").encode("ascii")) def key_sideload_fvsr(self, seed: int): - """Starts the key sidloading FvsR test on OTBN. + """Starts the key sidloading FvsR test on ACC. Args: seed: The fixed seed used by the key manager. """ - # OtbnSca command. - self._ujson_otbn_sca_cmd() + # AccSca command. + self._ujson_acc_sca_cmd() # Start the KeySideloadFvsr test. self.target.write(json.dumps("KeySideloadFvsr").encode("ascii")) seed_data = {"fixed_seed": seed} self.target.write(json.dumps(seed_data).encode("ascii")) def ecdsa_p256_sign(self, masking_on: bool, msg, d0, k0): - """Starts the EcdsaP256Sign test on OTBN. + """Starts the EcdsaP256Sign test on ACC. Args: masking_on: Turn on/off masking. msg: Message array (8xuint32_t) d0: Message array (10xuint32_t) k0: Message array (10xuint32_t) """ - # OtbnSca command. - self._ujson_otbn_sca_cmd() + # AccSca command. + self._ujson_acc_sca_cmd() # Start the EcdsaP256Sign test. self.target.write(json.dumps("EcdsaP256Sign").encode("ascii")) # Configure masking. @@ -89,7 +89,7 @@ def ecdsa_p256_sign(self, masking_on: bool, msg, d0, k0): self.target.write(json.dumps(data).encode("ascii")) def ecdsa_p256_sign_batch(self, num_traces: int, masking_on: bool, msg, d0, k0): - """Starts the EcdsaP256SignBatch test on OTBN. + """Starts the EcdsaP256SignBatch test on ACC. Args: num_traces: Number of batch operations. masking_on: Turn on/off masking. @@ -97,8 +97,8 @@ def ecdsa_p256_sign_batch(self, num_traces: int, masking_on: bool, msg, d0, k0): d0: Message array (10xuint32_t) k0: Message array (10xuint32_t) """ - # OtbnSca command. - self._ujson_otbn_sca_cmd() + # AccSca command. + self._ujson_acc_sca_cmd() # Start the EcdsaP256SignBatch test. self.target.write(json.dumps("EcdsaP256Sign").encode("ascii")) # Configure number of traces. @@ -114,7 +114,7 @@ def ecdsa_p256_sign_batch(self, num_traces: int, masking_on: bool, msg, d0, k0): def ecdsa_p256_sign_batch_fvsr( self, num_traces: int, masking_on: bool, msg, d0, k0 ): - """Starts the EcdsaP256SignFvsrBatch test on OTBN. + """Starts the EcdsaP256SignFvsrBatch test on ACC. Args: num_traces: Number of batch operations. masking_on: Turn on/off masking. @@ -122,8 +122,8 @@ def ecdsa_p256_sign_batch_fvsr( d0: Message array (10xuint32_t) k0: Message array (10xuint32_t) """ - # OtbnSca command. - self._ujson_otbn_sca_cmd() + # AccSca command. + self._ujson_acc_sca_cmd() # Start the EcdsaP256SignBatch test. self.target.write(json.dumps("EcdsaP256SignFvsrBatch").encode("ascii")) # Configure number of traces. @@ -147,8 +147,8 @@ def start_combi_ops_batch( print_flag: Whether to print an output or an empty RESP_OK. trigger: Which triggers to raise. """ - # OtbnSca command. - self._ujson_otbn_sca_cmd() + # AccSca command. + self._ujson_acc_sca_cmd() # Start the CombiOps test. self.target.write(json.dumps("CombiOps").encode("ascii")) data = { diff --git a/sw/host/penetrationtests/python/sca/host_scripts/sca_otbn_functions.py b/sw/host/penetrationtests/python/sca/host_scripts/sca_acc_functions.py similarity index 80% rename from sw/host/penetrationtests/python/sca/host_scripts/sca_otbn_functions.py rename to sw/host/penetrationtests/python/sca/host_scripts/sca_acc_functions.py index d1b650ded90..59c24c83271 100644 --- a/sw/host/penetrationtests/python/sca/host_scripts/sca_otbn_functions.py +++ b/sw/host/penetrationtests/python/sca/host_scripts/sca_acc_functions.py @@ -2,7 +2,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -from sw.host.penetrationtests.python.sca.communication.sca_otbn_commands import OTOTBN +from sw.host.penetrationtests.python.sca.communication.sca_acc_commands import OTACC def char_combi_operations_batch( @@ -15,15 +15,15 @@ def char_combi_operations_batch( trigger, reset = False ): - otbnsca = OTOTBN(target) + accsca = OTACC(target) if reset: target.reset_target() # Clear the output from the reset target.dump_all() # Initialize our chip and catch its output - device_id, owner_page, boot_log, boot_measurements, version = otbnsca.init() + device_id, owner_page, boot_log, boot_measurements, version = accsca.init() for _ in range(iterations): - otbnsca.start_combi_ops_batch( + accsca.start_combi_ops_batch( num_segments, fixed_data1, fixed_data2, print_flag, trigger ) response = target.read_response() diff --git a/sw/host/penetrationtests/python/sca/test_scripts/sca_otbn_python_test.py b/sw/host/penetrationtests/python/sca/test_scripts/sca_acc_python_test.py similarity index 96% rename from sw/host/penetrationtests/python/sca/test_scripts/sca_otbn_python_test.py rename to sw/host/penetrationtests/python/sca/test_scripts/sca_acc_python_test.py index accb1513b00..e97578a4b68 100644 --- a/sw/host/penetrationtests/python/sca/test_scripts/sca_otbn_python_test.py +++ b/sw/host/penetrationtests/python/sca/test_scripts/sca_acc_python_test.py @@ -2,8 +2,8 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -from sw.host.penetrationtests.python.sca.host_scripts import sca_otbn_functions -from sw.host.penetrationtests.python.sca.communication.sca_otbn_commands import OTOTBN +from sw.host.penetrationtests.python.sca.host_scripts import sca_acc_functions +from sw.host.penetrationtests.python.sca.communication.sca_acc_commands import OTACC from python.runfiles import Runfiles from sw.host.penetrationtests.python.util import targets from sw.host.penetrationtests.python.util import utils @@ -31,11 +31,11 @@ BOOTSTRAP = args.bootstrap -class OtbnScaTest(unittest.TestCase): +class AccScaTest(unittest.TestCase): def test_init(self): - otbnsca = OTOTBN(target) - device_id, owner_page, boot_log, boot_measurements, version = otbnsca.init() + accsca = OTACC(target) + device_id, owner_page, boot_log, boot_measurements, version = accsca.init() device_id_json = json.loads(device_id) owner_page_json = json.loads(owner_page) boot_log_json = json.loads(boot_log) @@ -118,7 +118,7 @@ def test_char_combi_operations_batch(self): fixed_data1 = 0 fixed_data2 = 0 print_flag = True - actual_result = sca_otbn_functions.char_combi_operations_batch( + actual_result = sca_acc_functions.char_combi_operations_batch( target, iterations, num_segments, @@ -196,7 +196,7 @@ def test_char_combi_operations_batch(self): fixed_data1 = 1 fixed_data2 = 1 print_flag = True - actual_result = sca_otbn_functions.char_combi_operations_batch( + actual_result = sca_acc_functions.char_combi_operations_batch( target, iterations, num_segments, @@ -274,7 +274,7 @@ def test_char_combi_operations_batch(self): fixed_data1 = random.getrandbits(32) fixed_data2 = random.getrandbits(32) print_flag = True - actual_result = sca_otbn_functions.char_combi_operations_batch( + actual_result = sca_acc_functions.char_combi_operations_batch( target, iterations, num_segments, diff --git a/sw/host/penetrationtests/python/util/common_library.py b/sw/host/penetrationtests/python/util/common_library.py index 54515894b46..07a653c3f6c 100644 --- a/sw/host/penetrationtests/python/util/common_library.py +++ b/sw/host/penetrationtests/python/util/common_library.py @@ -75,8 +75,8 @@ 0, # "hmac_fatal_fault", 1, # "kmac_recov_operation_err", 0, # "kmac_fatal_fault_err", - 0, # "otbn_fatal", - 1, # "otbn_recov", + 0, # "acc_fatal", + 1, # "acc_recov", 1, # "keymgr_recov_operation_err", 0, # "keymgr_fatal_fault_err", 1, # "csrng_recov_alert", @@ -142,8 +142,8 @@ True, # "hmac_fatal_fault", True, # "kmac_recov_operation_err", True, # "kmac_fatal_fault_err", - True, # "otbn_fatal", - True, # "otbn_recov", + True, # "acc_fatal", + True, # "acc_recov", True, # "keymgr_recov_operation_err", True, # "keymgr_fatal_fault_err", True, # "csrng_recov_alert", @@ -217,8 +217,8 @@ 0, # "hmac_fatal_fault", 1, # "kmac_recov_operation_err", 0, # "kmac_fatal_fault_err", - 0, # "otbn_fatal", - 1, # "otbn_recov", + 0, # "acc_fatal", + 1, # "acc_recov", 1, # "keymgr_recov_operation_err", 0, # "keymgr_fatal_fault_err", 1, # "csrng_recov_alert", @@ -285,8 +285,8 @@ True, # "hmac_fatal_fault", True, # "kmac_recov_operation_err", True, # "kmac_fatal_fault_err", - True, # "otbn_fatal", - True, # "otbn_recov", + True, # "acc_fatal", + True, # "acc_recov", True, # "keymgr_recov_operation_err", True, # "keymgr_fatal_fault_err", True, # "csrng_recov_alert", diff --git a/sw/host/penetrationtests/testvectors/data/BUILD b/sw/host/penetrationtests/testvectors/data/BUILD index bbddf130efe..87ce3ea8225 100644 --- a/sw/host/penetrationtests/testvectors/data/BUILD +++ b/sw/host/penetrationtests/testvectors/data/BUILD @@ -30,8 +30,8 @@ filegroup( ) filegroup( - name = "fi_otbn", - srcs = ["fi_otbn.json"], + name = "fi_acc", + srcs = ["fi_acc.json"], ) filegroup( @@ -85,8 +85,8 @@ filegroup( ) filegroup( - name = "sca_otbn", - srcs = ["sca_otbn.json"], + name = "sca_acc", + srcs = ["sca_acc.json"], ) filegroup( diff --git a/sw/host/penetrationtests/testvectors/data/fi_otbn.json b/sw/host/penetrationtests/testvectors/data/fi_acc.json similarity index 73% rename from sw/host/penetrationtests/testvectors/data/fi_otbn.json rename to sw/host/penetrationtests/testvectors/data/fi_acc.json index dae206cb317..856e32606ba 100644 --- a/sw/host/penetrationtests/testvectors/data/fi_otbn.json +++ b/sw/host/penetrationtests/testvectors/data/fi_acc.json @@ -17,90 +17,90 @@ { "test_case_id": 2, "command": "CharBeq", - "expected_output": ["{\"result\":0,\"insn_cnt\":509,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"result\":0,\"insn_cnt\":509,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 3, "command": "CharBnRshi", "input": "{\"big_num\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]}", - "expected_output": ["{\"big_num\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":109,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"big_num\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":109,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 4, "command": "CharBnSel", "input": "{\"big_num\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]}", - "expected_output": ["{\"big_num\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":1014,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"big_num\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":1014,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 5, "command": "CharBnWsrr", - "expected_output": ["{\"res\":0,\"insn_cnt\":1089,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"res\":0,\"insn_cnt\":1089,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 6, "command": "CharBne", - "expected_output": ["{\"result\":0,\"insn_cnt\":509,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"result\":0,\"insn_cnt\":509,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 7, "command": "CharDmemAccess", - "expected_output": ["{\"res\":0,\"insn_cnt\":271,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"res\":0,\"insn_cnt\":271,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 8, "command": "CharDmemWrite", - "expected_output": ["{\"result\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":1,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"result\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":1,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 9, "command": "CharHardwareDmemOpLoop", - "expected_output": ["{\"loop_counter\":10000,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"loop_counter\":10000,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 10, "command": "CharHardwareRegOpLoop", - "expected_output": ["{\"loop_counter\":10000,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"loop_counter\":10000,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 11, "command": "CharJal", - "expected_output": ["{\"result\":0,\"insn_cnt\":505,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"result\":0,\"insn_cnt\":505,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 12, "command": "CharLw", - "expected_output": ["{\"result\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":1084,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"result\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"insn_cnt\":1084,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 13, "command": "CharMem", "input": "{\"byte_offset\":0,\"num_words\":4,\"imem\":false,\"dmem\":true}", - "expected_output": ["{\"res\":0,\"imem_data\":[0,0,0,0,0,0,0,0],\"imem_addr\":[0,0,0,0,0,0,0,0],\"dmem_data\":[0,0,0,0,0,0,0,0],\"dmem_addr\":[0,0,0,0,0,0,0,0],\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"res\":0,\"imem_data\":[0,0,0,0,0,0,0,0],\"imem_addr\":[0,0,0,0,0,0,0,0],\"dmem_data\":[0,0,0,0,0,0,0,0],\"dmem_addr\":[0,0,0,0,0,0,0,0],\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 14, "command": "CharRF", - "expected_output": ["{\"res\":0,\"faulty_gpr\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"faulty_wdr\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"res\":0,\"faulty_gpr\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"faulty_wdr\":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 15, "command": "CharUnrolledDmemOpLoop", - "expected_output": ["{\"loop_counter\":100,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"loop_counter\":100,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 16, "command": "CharUnrolledRegOpLoop", - "expected_output": ["{\"loop_counter\":100,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"loop_counter\":100,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 17, "command": "LoadIntegrity", - "expected_output": ["{\"result\":0,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"result\":0,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] }, { "test_case_id": 18, "command": "PC", "input": "{\"pc\":2224}", - "expected_output": ["{\"pc_dmem\":2224,\"pc_otbn\":2224,\"insn_cnt\":472,\"err_otbn\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] + "expected_output": ["{\"pc_dmem\":2224,\"pc_acc\":2224,\"insn_cnt\":472,\"err_acc\":0,\"err_ibx\":0,\"alerts\":[0,0,0],\"ast_alerts\":[0,0]}"] } ] diff --git a/sw/host/penetrationtests/testvectors/data/sca_otbn.json b/sw/host/penetrationtests/testvectors/data/sca_acc.json similarity index 100% rename from sw/host/penetrationtests/testvectors/data/sca_otbn.json rename to sw/host/penetrationtests/testvectors/data/sca_acc.json diff --git a/sw/host/penetrationtests/ujson_lib/BUILD b/sw/host/penetrationtests/ujson_lib/BUILD index 47a86169c8b..cb0299afceb 100644 --- a/sw/host/penetrationtests/ujson_lib/BUILD +++ b/sw/host/penetrationtests/ujson_lib/BUILD @@ -38,8 +38,8 @@ ujson_rust( ) ujson_rust( - name = "fi_otbn_commands_rust", - srcs = ["//sw/device/tests/penetrationtests/json:otbn_fi_commands"], + name = "fi_acc_commands_rust", + srcs = ["//sw/device/tests/penetrationtests/json:acc_fi_commands"], ) ujson_rust( @@ -98,8 +98,8 @@ ujson_rust( ) ujson_rust( - name = "sca_otbn_commands_rust", - srcs = ["//sw/device/tests/penetrationtests/json:otbn_sca_commands"], + name = "sca_acc_commands_rust", + srcs = ["//sw/device/tests/penetrationtests/json:acc_sca_commands"], ) ujson_rust( @@ -111,24 +111,24 @@ rust_library( name = "pentest_commands", srcs = [ "src/commands.rs", + "src/fi_acc_commands.rs", "src/fi_asym_cryptolib_commands.rs", "src/fi_crypto_commands.rs", "src/fi_ibex_commands.rs", "src/fi_lc_ctrl_commands.rs", - "src/fi_otbn_commands.rs", "src/fi_otp_commands.rs", "src/fi_rng_commands.rs", "src/fi_rom_commands.rs", "src/fi_sym_cryptolib_commands.rs", "src/lib.rs", "src/pentest_lib_commands.rs", + "src/sca_acc_commands.rs", "src/sca_aes_commands.rs", "src/sca_asym_cryptolib_commands.rs", "src/sca_edn_commands.rs", "src/sca_hmac_commands.rs", "src/sca_ibex_commands.rs", "src/sca_kmac_commands.rs", - "src/sca_otbn_commands.rs", "src/sca_sha3_commands.rs", "src/sca_sym_cryptolib_commands.rs", ], @@ -139,7 +139,7 @@ rust_library( ":fi_asym_cryptolib_commands_rust", ":fi_ibex_commands_rust", ":fi_lc_ctrl_commands_rust", - ":fi_otbn_commands_rust", + ":fi_acc_commands_rust", ":fi_otp_commands_rust", ":fi_rng_commands_rust", ":fi_rom_commands_rust", @@ -151,7 +151,7 @@ rust_library( ":sca_hmac_commands_rust", ":sca_ibex_commands_rust", ":sca_kmac_commands_rust", - ":sca_otbn_commands_rust", + ":sca_acc_commands_rust", ":sca_sha3_commands_rust", ], rustc_env = { @@ -161,7 +161,7 @@ rust_library( "fi_asym_cryptolib_commands_loc": "$(execpath :fi_asym_cryptolib_commands_rust)", "fi_ibex_commands_loc": "$(execpath :fi_ibex_commands_rust)", "fi_lc_ctrl_commands_loc": "$(execpath :fi_lc_ctrl_commands_rust)", - "fi_otbn_commands_loc": "$(execpath :fi_otbn_commands_rust)", + "fi_acc_commands_loc": "$(execpath :fi_acc_commands_rust)", "fi_otp_commands_loc": "$(execpath :fi_otp_commands_rust)", "fi_rng_commands_loc": "$(execpath :fi_rng_commands_rust)", "fi_rom_commands_loc": "$(execpath :fi_rom_commands_rust)", @@ -173,7 +173,7 @@ rust_library( "sca_hmac_commands_loc": "$(execpath :sca_hmac_commands_rust)", "sca_ibex_commands_loc": "$(execpath :sca_ibex_commands_rust)", "sca_kmac_commands_loc": "$(execpath :sca_kmac_commands_rust)", - "sca_otbn_commands_loc": "$(execpath :sca_otbn_commands_rust)", + "sca_acc_commands_loc": "$(execpath :sca_acc_commands_rust)", "sca_sha3_commands_loc": "$(execpath :sca_sha3_commands_rust)", }, deps = [ diff --git a/sw/host/penetrationtests/ujson_lib/src/fi_otbn_commands.rs b/sw/host/penetrationtests/ujson_lib/src/fi_acc_commands.rs similarity index 80% rename from sw/host/penetrationtests/ujson_lib/src/fi_otbn_commands.rs rename to sw/host/penetrationtests/ujson_lib/src/fi_acc_commands.rs index 5cee3c6d3f2..c9483c25ef1 100644 --- a/sw/host/penetrationtests/ujson_lib/src/fi_otbn_commands.rs +++ b/sw/host/penetrationtests/ujson_lib/src/fi_acc_commands.rs @@ -1,4 +1,4 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -include!(env!("fi_otbn_commands_loc")); +include!(env!("fi_acc_commands_loc")); diff --git a/sw/host/penetrationtests/ujson_lib/src/lib.rs b/sw/host/penetrationtests/ujson_lib/src/lib.rs index 2e497f2a1f2..f4a4fbba02e 100644 --- a/sw/host/penetrationtests/ujson_lib/src/lib.rs +++ b/sw/host/penetrationtests/ujson_lib/src/lib.rs @@ -2,22 +2,22 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 pub mod commands; +pub mod fi_acc_commands; pub mod fi_asym_cryptolib_commands; pub mod fi_crypto_commands; pub mod fi_ibex_commands; pub mod fi_lc_ctrl_commands; -pub mod fi_otbn_commands; pub mod fi_otp_commands; pub mod fi_rng_commands; pub mod fi_rom_commands; pub mod fi_sym_cryptolib_commands; pub mod pentest_lib_commands; +pub mod sca_acc_commands; pub mod sca_aes_commands; pub mod sca_asym_cryptolib_commands; pub mod sca_edn_commands; pub mod sca_hmac_commands; pub mod sca_ibex_commands; pub mod sca_kmac_commands; -pub mod sca_otbn_commands; pub mod sca_sha3_commands; pub mod sca_sym_cryptolib_commands; diff --git a/sw/host/penetrationtests/ujson_lib/src/sca_otbn_commands.rs b/sw/host/penetrationtests/ujson_lib/src/sca_acc_commands.rs similarity index 80% rename from sw/host/penetrationtests/ujson_lib/src/sca_otbn_commands.rs rename to sw/host/penetrationtests/ujson_lib/src/sca_acc_commands.rs index fc10d4f4115..cdad395b9b8 100644 --- a/sw/host/penetrationtests/ujson_lib/src/sca_otbn_commands.rs +++ b/sw/host/penetrationtests/ujson_lib/src/sca_acc_commands.rs @@ -1,4 +1,4 @@ // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -include!(env!("sca_otbn_commands_loc")); +include!(env!("sca_acc_commands_loc")); diff --git a/sw/host/tests/chip/rv_dm/src/csr_rw.rs b/sw/host/tests/chip/rv_dm/src/csr_rw.rs index 769d15ee06d..3d4b8f9bdd0 100644 --- a/sw/host/tests/chip/rv_dm/src/csr_rw.rs +++ b/sw/host/tests/chip/rv_dm/src/csr_rw.rs @@ -155,9 +155,9 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> { dif::KMAC_INTR_ENABLE_REG_OFFSET, ), ( - "otbn", - top_earlgrey::OTBN_BASE_ADDR, - dif::OTBN_INTR_ENABLE_REG_OFFSET, + "acc", + top_earlgrey::ACC_BASE_ADDR, + dif::ACC_INTR_ENABLE_REG_OFFSET, ), ( "otp_ctrl", diff --git a/sw/host/tests/chip/rv_dm/src/mem_access.rs b/sw/host/tests/chip/rv_dm/src/mem_access.rs index e666b58cde0..f20a9141bad 100644 --- a/sw/host/tests/chip/rv_dm/src/mem_access.rs +++ b/sw/host/tests/chip/rv_dm/src/mem_access.rs @@ -85,14 +85,14 @@ fn test_mem_access(opts: &Opts, transport: &TransportWrapper) -> Result<()> { top_earlgrey::SRAM_CTRL_MAIN_RAM_SIZE_BYTES as u32, ), ( - "otbn_imem", - top_earlgrey::OTBN_BASE_ADDR as u32 + dif::OTBN_IMEM_REG_OFFSET, - dif::OTBN_IMEM_SIZE_BYTES, + "acc_imem", + top_earlgrey::ACC_BASE_ADDR as u32 + dif::ACC_IMEM_REG_OFFSET, + dif::ACC_IMEM_SIZE_BYTES, ), ( - "otbn_dmem", - top_earlgrey::OTBN_BASE_ADDR as u32 + dif::OTBN_DMEM_REG_OFFSET, - dif::OTBN_DMEM_SIZE_BYTES, + "acc_dmem", + top_earlgrey::ACC_BASE_ADDR as u32 + dif::ACC_DMEM_REG_OFFSET, + dif::ACC_DMEM_SIZE_BYTES, ), ]; diff --git a/sw/host/tests/penetrationtests/fi_otbn/BUILD b/sw/host/tests/penetrationtests/fi_acc/BUILD similarity index 100% rename from sw/host/tests/penetrationtests/fi_otbn/BUILD rename to sw/host/tests/penetrationtests/fi_acc/BUILD diff --git a/sw/host/tests/penetrationtests/fi_otbn/src/main.rs b/sw/host/tests/penetrationtests/fi_acc/src/main.rs similarity index 83% rename from sw/host/tests/penetrationtests/fi_otbn/src/main.rs rename to sw/host/tests/penetrationtests/fi_acc/src/main.rs index 2ab4847f454..feae09ce3f8 100644 --- a/sw/host/tests/penetrationtests/fi_otbn/src/main.rs +++ b/sw/host/tests/penetrationtests/fi_acc/src/main.rs @@ -11,7 +11,7 @@ use clap::Parser; use serde::Deserialize; use pentest_commands::commands::PenetrationtestCommand; -use pentest_commands::fi_otbn_commands::OtbnFiSubcommand; +use pentest_commands::fi_acc_commands::AccFiSubcommand; use opentitanlib::app::TransportWrapper; use opentitanlib::execute_test; @@ -31,11 +31,11 @@ struct Opts { timeout: Duration, #[arg(long, num_args = 1..)] - fi_otbn_json: Vec, + fi_acc_json: Vec, } #[derive(Debug, Deserialize)] -struct FiOtbnTestCase { +struct FiAccTestCase { test_case_id: usize, command: String, #[serde(default)] @@ -52,16 +52,16 @@ fn filter_response(response: serde_json::Value) -> serde_json::Map = response_common_filtered.clone(); - // OTBN instruction counter should be const. + // ACC instruction counter should be const. map.remove("insn_cnt"); - // Filter as the CharBnWsrr returns random data from OTBN. + // Filter as the CharBnWsrr returns random data from ACC. map.remove("data"); map } -fn run_fi_otbn_testcase( - test_case: &FiOtbnTestCase, +fn run_fi_acc_testcase( + test_case: &FiAccTestCase, opts: &Opts, uart: &dyn Uart, fail_counter: &mut u32, @@ -71,11 +71,11 @@ fn run_fi_otbn_testcase( test_case.test_case_id, test_case.command ); - PenetrationtestCommand::OtbnFi.send(uart)?; + PenetrationtestCommand::AccFi.send(uart)?; // Send test subcommand. - OtbnFiSubcommand::from_str(test_case.command.as_str()) - .context("unsupported OTBN FI subcommand")? + AccFiSubcommand::from_str(test_case.command.as_str()) + .context("unsupported ACC FI subcommand")? .send(uart)?; // Check if we need to send an input. @@ -128,21 +128,21 @@ fn run_fi_otbn_testcase( Ok(()) } -fn test_fi_otbn(opts: &Opts, transport: &TransportWrapper) -> Result<()> { +fn test_fi_acc(opts: &Opts, transport: &TransportWrapper) -> Result<()> { let uart = transport.uart("console")?; uart.set_flow_control(true)?; let _ = UartConsole::wait_for(&*uart, r"Running ", opts.timeout)?; let mut test_counter = 0u32; let mut fail_counter = 0u32; - let test_vector_files = &opts.fi_otbn_json; + let test_vector_files = &opts.fi_acc_json; for file in test_vector_files { let raw_json = fs::read_to_string(file)?; - let fi_otbn_tests: Vec = serde_json::from_str(&raw_json)?; - for fi_otbn_test in &fi_otbn_tests { + let fi_acc_tests: Vec = serde_json::from_str(&raw_json)?; + for fi_acc_test in &fi_acc_tests { test_counter += 1; log::info!("Test counter: {}", test_counter); - run_fi_otbn_testcase(fi_otbn_test, opts, &*uart, &mut fail_counter)?; + run_fi_acc_testcase(fi_acc_test, opts, &*uart, &mut fail_counter)?; } } assert_eq!( @@ -158,6 +158,6 @@ fn main() -> Result<()> { opts.init.init_logging(); let transport = opts.init.init_target()?; - execute_test!(test_fi_otbn, &opts, &transport); + execute_test!(test_fi_acc, &opts, &transport); Ok(()) } diff --git a/sw/host/tests/penetrationtests/sca_otbn/BUILD b/sw/host/tests/penetrationtests/sca_acc/BUILD similarity index 100% rename from sw/host/tests/penetrationtests/sca_otbn/BUILD rename to sw/host/tests/penetrationtests/sca_acc/BUILD diff --git a/sw/host/tests/penetrationtests/sca_otbn/src/main.rs b/sw/host/tests/penetrationtests/sca_acc/src/main.rs similarity index 85% rename from sw/host/tests/penetrationtests/sca_otbn/src/main.rs rename to sw/host/tests/penetrationtests/sca_acc/src/main.rs index a14f8b4ff16..f8c57cfb1ab 100644 --- a/sw/host/tests/penetrationtests/sca_otbn/src/main.rs +++ b/sw/host/tests/penetrationtests/sca_acc/src/main.rs @@ -11,7 +11,7 @@ use clap::Parser; use serde::Deserialize; use pentest_commands::commands::PenetrationtestCommand; -use pentest_commands::sca_otbn_commands::OtbnScaSubcommand; +use pentest_commands::sca_acc_commands::AccScaSubcommand; use opentitanlib::app::TransportWrapper; use opentitanlib::execute_test; @@ -31,11 +31,11 @@ struct Opts { timeout: Duration, #[arg(long, num_args = 1..)] - sca_otbn_json: Vec, + sca_acc_json: Vec, } #[derive(Debug, Deserialize)] -struct ScaOtbnTestCase { +struct ScaAccTestCase { test_case_id: usize, command: String, #[serde(default)] @@ -50,8 +50,8 @@ struct ScaOtbnTestCase { expected_output: Vec, } -fn run_sca_otbn_testcase( - test_case: &ScaOtbnTestCase, +fn run_sca_acc_testcase( + test_case: &ScaAccTestCase, opts: &Opts, uart: &dyn Uart, fail_counter: &mut u32, @@ -61,11 +61,11 @@ fn run_sca_otbn_testcase( test_case.test_case_id, test_case.command ); - PenetrationtestCommand::OtbnSca.send(uart)?; + PenetrationtestCommand::AccSca.send(uart)?; // Send test subcommand. - OtbnScaSubcommand::from_str(test_case.command.as_str()) - .context("unsupported OTBN SCA subcommand")? + AccScaSubcommand::from_str(test_case.command.as_str()) + .context("unsupported ACC SCA subcommand")? .send(uart)?; // Check if we need to send an input. @@ -123,21 +123,21 @@ fn run_sca_otbn_testcase( Ok(()) } -fn test_sca_otbn(opts: &Opts, transport: &TransportWrapper) -> Result<()> { +fn test_sca_acc(opts: &Opts, transport: &TransportWrapper) -> Result<()> { let uart = transport.uart("console")?; uart.set_flow_control(true)?; let _ = UartConsole::wait_for(&*uart, r"Running ", opts.timeout)?; let mut test_counter = 0u32; let mut fail_counter = 0u32; - let test_vector_files = &opts.sca_otbn_json; + let test_vector_files = &opts.sca_acc_json; for file in test_vector_files { let raw_json = fs::read_to_string(file)?; - let sca_otbn_tests: Vec = serde_json::from_str(&raw_json)?; - for sca_otbn_test in &sca_otbn_tests { + let sca_acc_tests: Vec = serde_json::from_str(&raw_json)?; + for sca_acc_test in &sca_acc_tests { test_counter += 1; log::info!("Test counter: {}", test_counter); - run_sca_otbn_testcase(sca_otbn_test, opts, &*uart, &mut fail_counter)?; + run_sca_acc_testcase(sca_acc_test, opts, &*uart, &mut fail_counter)?; } } assert_eq!( @@ -153,6 +153,6 @@ fn main() -> Result<()> { opts.init.init_logging(); let transport = opts.init.init_target()?; - execute_test!(test_sca_otbn, &opts, &transport); + execute_test!(test_sca_acc, &opts, &transport); Ok(()) } diff --git a/util/BUILD b/util/BUILD index c5f0d9cb560..04de3e57fa7 100644 --- a/util/BUILD +++ b/util/BUILD @@ -26,13 +26,13 @@ filegroup( ) py_binary( - name = "otbn_build", - srcs = ["otbn_build.py"], - imports = ["../hw/ip/otbn/util/"], + name = "acc_build", + srcs = ["acc_build.py"], + imports = ["../hw/ip/acc/util/"], deps = [ requirement("pyelftools"), - "//hw/ip/otbn/util:otbn_as", - "//hw/ip/otbn/util:otbn_ld", + "//hw/ip/acc/util:acc_as", + "//hw/ip/acc/util:acc_ld", ], ) @@ -159,7 +159,7 @@ cc_library( "code_snippet", "dashboard", "doxygen", - "otbn", + "acc", "readme2index", "reggen", "testplan", diff --git a/util/otbn_build.py b/util/acc_build.py similarity index 87% rename from util/otbn_build.py rename to util/acc_build.py index 33590490d02..57f8c3cf65e 100755 --- a/util/otbn_build.py +++ b/util/acc_build.py @@ -2,12 +2,12 @@ # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -"""Build software running on OTBN +"""Build software running on ACC -Each assembly source file is first assembled with otbn_as.py. All resulting -objects are then linked with otbn_ld.py. The resulting ELF file is converted +Each assembly source file is first assembled with acc_as.py. All resulting +objects are then linked with acc_ld.py. The resulting ELF file is converted into an embeddable RV32 object file using objcopy. In this object, all symbols -are prefixed with `_otbn_app__` (only global symbols are included). +are prefixed with `_acc_app__` (only global symbols are included). environment variables: This script, and the tools called from it, rely on the following environment @@ -15,20 +15,20 @@ sensible default values are provided (tools are generally expected to be in the $PATH). - OTBN_TOOLS path to the OTBN linker and assembler tools + ACC_TOOLS path to the ACC linker and assembler tools RV32_TOOL_LD path to RV32 ld RV32_TOOL_AS path to RV32 as RV32_TOOL_AR path to RV32 ar RV32_TOOL_OBJCOPY path to RV32 objcopy - The RV32* environment variables are used by both this script and the OTBN - wrappers (otbn_as.py and otbn_ld.py) to find tools in a RV32 toolchain. + The RV32* environment variables are used by both this script and the ACC + wrappers (acc_as.py and acc_ld.py) to find tools in a RV32 toolchain. outputs: The build process produces multiple files inside the output directory. .o the compiled source files - .elf the compiled and linked application targeting OTBN + .elf the compiled and linked application targeting ACC .rv32embed.o the application as embeddable object for RV32 """ @@ -44,8 +44,8 @@ from pathlib import Path from typing import List, Optional, Tuple -import otbn_as -import otbn_ld +import acc_as +import acc_ld from elftools.elf.elffile import ELFFile, SymbolTableSection # type: ignore @@ -73,7 +73,7 @@ def run_tool(tool, out_file: Path, args) -> None: This works by writing to a temporary file (in the same directory) and then atomically replacing any existing destination file when done. This is - needed if we need to run multiple otbn_build processes that generate the + needed if we need to run multiple acc_build processes that generate the same files in parallel (this was a requirement of our old Meson-based infrastructure; it may not be needed now that we use Bazel). @@ -103,18 +103,18 @@ def run_tool(tool, out_file: Path, args) -> None: pass -def call_otbn_as(src_file: Path, out_file: Path): - run_tool(otbn_as.main, out_file, [src_file]) +def call_acc_as(src_file: Path, out_file: Path): + run_tool(acc_as.main, out_file, [src_file]) -def call_otbn_ld(src_files: List[Path], out_file: Path, - linker_script: Optional[Path]): +def call_acc_ld(src_files: List[Path], out_file: Path, + linker_script: Optional[Path]): args = ['-gc-sections', '-gc-keep-exported'] if linker_script: args += ['-T', linker_script] args += src_files - run_tool(otbn_ld.main, out_file, args) + run_tool(acc_ld.main, out_file, args) def call_rv32_objcopy(args: List[str]): @@ -129,12 +129,12 @@ def call_rv32_ar(args: List[str]): def get_app_checksum(elf_path: str) -> int: - '''Get the CRC32 checksum of an OTBN app. + '''Get the CRC32 checksum of an ACC app. The checksum is computed over first the `.text` (IMEM) section, then the `.data` section, in order. Each 32-bit word of IMEM or DMEM becomes a 48-bit value: {imem, addr, value}, where `imem` is 1 or 0 depending on if - the value is for IMEM or DMEM, `addr` is the word-offset within OTBN's + the value is for IMEM or DMEM, `addr` is the word-offset within ACC's memory zero-extended to 15 bits. The checksum is computed over this value in little-endian order. ''' @@ -175,7 +175,7 @@ def get_app_checksum(elf_path: str) -> int: return checksum -def get_otbn_syms(elf_path: str) -> List[Tuple[str, int]]: +def get_acc_syms(elf_path: str) -> List[Tuple[str, int]]: '''Get externally-visible symbols from an ELF Symbols are returned as a list of triples: (name, address). This @@ -275,52 +275,52 @@ def main() -> int: try: if not args.no_assembler: for src_file, obj_file in zip(src_files, obj_files): - call_otbn_as(src_file, obj_file) + call_acc_as(src_file, obj_file) out_elf = out_dir / (app_name + '.elf') - call_otbn_ld(obj_files, out_elf, linker_script=args.linker_script) + call_acc_ld(obj_files, out_elf, linker_script=args.linker_script) - # out_elf is a fully-linked OTBN binary, but we want to be able to use + # out_elf is a fully-linked ACC binary, but we want to be able to use # it from Ibex, the host processor. To make this work, we generate an # ELF file that can be linked into the Ibex image. # # This ELF contains all initialised data (the .text and .data # sections). We change the flags to treat them like rodata (since # they're not executable on Ibex, nor does it make sense for Ibex code - # to manipulate OTBN data sections "in place") and add a .rodata.otbn + # to manipulate ACC data sections "in place") and add a .rodata.acc # prefix to the section names. # # The symbols exposed by the binary will be relocated as part of the # link, so they'll point into the Ibex address space. To allow linking - # against multiple OTBN applications, we give the symbols an + # against multiple ACC applications, we give the symbols an # application-specific prefix. (Note: This prefix is used in driver # code: so needs to be kept in sync with that). # # As well as the initialised data and relocated symbols, we also want - # to add (absolute) symbols that have the OTBN addresses of the symbols + # to add (absolute) symbols that have the ACC addresses of the symbols # in question. Unfortunately, objcopy doesn't seem to have a "make all # symbols absolute" command, so we have to do it by hand. This also # means constructing an enormous objcopy command line :-/ If we run out # of space, we might have to use elftools to inject the addresses after # the objcopy. - host_side_pfx = '_otbn_local_app_{}_'.format(app_name) - otbn_side_pfx = '_otbn_remote_app_{}_'.format(app_name) + host_side_pfx = '_acc_local_app_{}_'.format(app_name) + acc_side_pfx = '_acc_remote_app_{}_'.format(app_name) out_embedded_obj = out_dir / (app_name + '.rv32embed.o') args = [ '-O', 'elf32-littleriscv', '--set-section-flags=*=alloc,load,readonly', '--remove-section=.scratchpad', '--remove-section=.bss', '--remove-section=.debug*', - '--prefix-sections=.rodata.otbn', '--prefix-symbols', host_side_pfx + '--prefix-sections=.rodata.acc', '--prefix-symbols', host_side_pfx ] - for name, addr in get_otbn_syms(out_elf): - args += ['--add-symbol', f'{otbn_side_pfx}{name}=0x{addr:x}'] + for name, addr in get_acc_syms(out_elf): + args += ['--add-symbol', f'{acc_side_pfx}{name}=0x{addr:x}'] # Compute the CRC32 checksum and add it as a constant. Ibex can use # this with the LOAD_CHECKSUM register to ensure the app was loaded # correctly. checksum = get_app_checksum(out_elf) - args += ['--add-symbol', f'{otbn_side_pfx}_checksum={checksum:#x}'] + args += ['--add-symbol', f'{acc_side_pfx}_checksum={checksum:#x}'] call_rv32_objcopy(args + [out_elf, out_embedded_obj]) diff --git a/util/mdbook_otbn.py b/util/mdbook_acc.py similarity index 59% rename from util/mdbook_otbn.py rename to util/mdbook_acc.py index f76c2148252..bcc9b051281 100755 --- a/util/mdbook_otbn.py +++ b/util/mdbook_acc.py @@ -2,9 +2,9 @@ # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -"""mdbook preprocessor that generates ISA tables for the OTBN. +"""mdbook preprocessor that generates ISA tables for the ACC. -The preprocessor also handles `{{#otbn-insn-ref ... }}` links to the ISA Table. +The preprocessor also handles `{{#acc-insn-ref ... }}` links to the ISA Table. """ import json @@ -19,16 +19,16 @@ REPO_TOP = Path(__file__).resolve().parents[1] # We are looking to match on the following example strings -# {{#otbn-isa base }} -OTBN_ISA_BASE_PATTERN = re.compile(r'\{\{#otbn-isa\s+base\s*\}\}') -OTBN_ISA_BIGNUM_PATTERN = re.compile(r'\{\{#otbn-isa\s+bignum\s*\}\}') +# {{#acc-isa base }} +ACC_ISA_BASE_PATTERN = re.compile(r'\{\{#acc-isa\s+base\s*\}\}') +ACC_ISA_BIGNUM_PATTERN = re.compile(r'\{\{#acc-isa\s+bignum\s*\}\}') -# {{#otbn-insn-ref insn }} -OTBN_INSNREF_PATTERN = re.compile(r'\{\{#otbn-insn-ref\s+?(.+?)\s*?\}\}') +# {{#acc-insn-ref insn }} +ACC_INSNREF_PATTERN = re.compile(r'\{\{#acc-insn-ref\s+?(.+?)\s*?\}\}') -OTBN_SCRIPT = REPO_TOP / 'hw/ip/otbn/util/yaml_to_doc.py' -OTBN_CFG = REPO_TOP / 'hw/ip/otbn/data/insns.yml' -OTBN_IMPL = REPO_TOP / 'hw/ip/otbn/dv/otbnsim/sim/insn.py' +ACC_SCRIPT = REPO_TOP / 'hw/ip/acc/util/yaml_to_doc.py' +ACC_CFG = REPO_TOP / 'hw/ip/acc/data/insns.yml' +ACC_IMPL = REPO_TOP / 'hw/ip/acc/dv/accsim/sim/insn.py' def main() -> None: @@ -44,17 +44,17 @@ def main() -> None: if chapter["source_path"] is None: continue - if OTBN_ISA_BASE_PATTERN.search(chapter["content"]) \ - and OTBN_ISA_BIGNUM_PATTERN.search(chapter["content"]): + if ACC_ISA_BASE_PATTERN.search(chapter["content"]) \ + and ACC_ISA_BIGNUM_PATTERN.search(chapter["content"]): - chapter["content"] = OTBN_ISA_BASE_PATTERN.sub(base_content, chapter["content"]) - chapter["content"] = OTBN_ISA_BIGNUM_PATTERN.sub(bignum_content, chapter["content"]) + chapter["content"] = ACC_ISA_BASE_PATTERN.sub(base_content, chapter["content"]) + chapter["content"] = ACC_ISA_BIGNUM_PATTERN.sub(bignum_content, chapter["content"]) isa_book_path = chapter["source_path"] break if isa_book_path is None: - sys.exit("No file was found with both {{#otbn-isa base}} and {{#otbn-isa bignum}}") + sys.exit("No file was found with both {{#acc-isa base}} and {{#acc-isa bignum}}") def ref_to_link(m: re.Match): instr = m.group(1) @@ -63,7 +63,7 @@ def ref_to_link(m: re.Match): for chapter in md_utils.chapters(book["sections"]): chapter["content"] = \ - OTBN_INSNREF_PATTERN.sub( + ACC_INSNREF_PATTERN.sub( ref_to_link, chapter["content"], ) @@ -73,10 +73,10 @@ def ref_to_link(m: re.Match): def get_listings() -> (str, str): - """Use the otbn utility scripts to generate the ISA listings.""" + """Use the acc utility scripts to generate the ISA listings.""" with tempfile.TemporaryDirectory() as tmpdir: subprocess.run( - [str(OTBN_SCRIPT), str(OTBN_CFG), str(OTBN_IMPL), tmpdir], + [str(ACC_SCRIPT), str(ACC_CFG), str(ACC_IMPL), tmpdir], check=True, ) tmpdir = Path(tmpdir) diff --git a/util/mdbook_dashboard.py b/util/mdbook_dashboard.py index 79a3df2e141..8f7defea18a 100755 --- a/util/mdbook_dashboard.py +++ b/util/mdbook_dashboard.py @@ -32,7 +32,7 @@ REPO_TOP / "hw/ip/keymgr/data/keymgr.hjson", REPO_TOP / "hw/ip/kmac/data/kmac.hjson", REPO_TOP / "hw/ip/lc_ctrl/data/lc_ctrl.hjson", - REPO_TOP / "hw/ip/otbn/data/otbn.hjson", + REPO_TOP / "hw/ip/acc/data/acc.hjson", REPO_TOP / "hw/ip/pattgen/data/pattgen.hjson", REPO_TOP / "hw/ip/rom_ctrl/data/rom_ctrl.hjson", REPO_TOP / "hw/ip/rv_dm/data/rv_dm.hjson", diff --git a/util/reggen/ip_block.py b/util/reggen/ip_block.py index 15b740eb7aa..c9936810476 100644 --- a/util/reggen/ip_block.py +++ b/util/reggen/ip_block.py @@ -39,7 +39,7 @@ 12: 'keymgr', 13: 'kmac', 14: 'lc_ctrl', - 15: 'otbn', + 15: 'acc', 16: 'otp_ctrl', 17: 'pattgen', 18: 'pinmux', diff --git a/util/site/blocks.json b/util/site/blocks.json index 94a3ea590d2..997abbb171a 100644 --- a/util/site/blocks.json +++ b/util/site/blocks.json @@ -34,10 +34,10 @@ "data_file": "hw/ip/keymgr/data/keymgr.hjson", "report": "/hw/ip/keymgr/dv" }, - "otbn": { - "name": "OTBN", - "data_file": "hw/ip/otbn/data/otbn.hjson", - "report": "/hw/ip/otbn/dv/uvm" + "acc": { + "name": "ACC", + "data_file": "hw/ip/acc/data/acc.hjson", + "report": "/hw/ip/acc/dv/uvm" }, "aes": { "name": "AES", diff --git a/util/site/build-docs.sh b/util/site/build-docs.sh index 6efc6ffc74b..8d6a07f7e6e 100755 --- a/util/site/build-docs.sh +++ b/util/site/build-docs.sh @@ -88,7 +88,7 @@ getURLs book_env="env" book_env+=" MDBOOK_PREPROCESSOR__TESTPLAN__COMMAND=${proj_root}/util/mdbook_testplan.py" book_env+=" MDBOOK_PREPROCESSOR__TOOLVERSION__COMMAND=${proj_root}/util/mdbook_toolversion.py" -book_env+=" MDBOOK_PREPROCESSOR__OTBN__COMMAND=${proj_root}/util/mdbook_otbn.py" +book_env+=" MDBOOK_PREPROCESSOR__ACC__COMMAND=${proj_root}/util/mdbook_acc.py" book_env+=" MDBOOK_PREPROCESSOR__CODE_SNIPPET__COMMAND=${proj_root}/util/mdbook_code_snippet.py" book_env+=" MDBOOK_PREPROCESSOR__DOXYGEN__COMMAND=${proj_root}/util/mdbook_doxygen.py" book_env+=" MDBOOK_PREPROCESSOR__REGGEN__COMMAND=${proj_root}/util/mdbook_reggen.py" diff --git a/util/site/fetch_block_stats.py b/util/site/fetch_block_stats.py index 16273d82d75..5c82eed1931 100755 --- a/util/site/fetch_block_stats.py +++ b/util/site/fetch_block_stats.py @@ -35,7 +35,7 @@ "key-manager": "hw/ip/keymgr/dv/latest/", "kmac": "hw/ip/kmac_masked/dv/latest/", "life-cycle": "hw/ip/lc_ctrl/dv/latest/", - "otbn": "hw/ip/otbn/dv/uvm/latest/", + "acc": "hw/ip/acc/dv/uvm/latest/", "otp-fuse-controller": "hw/top_earlgrey/ip_autogen/otp_ctrl/dv/latest/", "pattern-generators": "hw/ip/pattgen/dv/latest/", "pwm": "hw/top_earlgrey/ip_autogen/pwm/dv/latest/", diff --git a/util/topgen.py b/util/topgen.py index 6bc8385b3f6..5dde53f66e9 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -1844,7 +1844,7 @@ def render_template(template_path: str, rendered_path: Path, "sram_ctrl": ["lowrisc:ip:sram_ctrl_pkg"], "aes": ["lowrisc:ip:aes"], "kmac": ["lowrisc:ip:kmac_pkg"], - "otbn": ["lowrisc:ip:otbn_pkg"], + "acc": ["lowrisc:ip:acc_pkg"], "keymgr": ["lowrisc:ip:keymgr_pkg"], "csrng": ["lowrisc:ip:csrng_pkg"], } diff --git a/util/verible-format-allowlist.txt b/util/verible-format-allowlist.txt index 45e02fe3a94..5f7cd25eaa5 100644 --- a/util/verible-format-allowlist.txt +++ b/util/verible-format-allowlist.txt @@ -114,10 +114,10 @@ hw/ip/kmac/dv/tests/kmac_test_pkg.sv hw/ip/lc_ctrl/dv/env/seq_lib/lc_ctrl_errors_vseq.sv hw/ip/lc_ctrl/dv/env/seq_lib/lc_ctrl_vseq_list.sv hw/ip/lc_ctrl/dv/tests/lc_ctrl_test_pkg.sv -hw/ip/otbn/dv/uvm/env/seq_lib/otbn_reset_vseq.sv -hw/ip/otbn/dv/uvm/env/seq_lib/otbn_vseq_list.sv -hw/ip/otbn/dv/uvm/tests/otbn_test_pkg.sv -hw/ip/otbn/dv/verilator/otbn_mock_edn.sv +hw/ip/acc/dv/uvm/env/seq_lib/acc_reset_vseq.sv +hw/ip/acc/dv/uvm/env/seq_lib/acc_vseq_list.sv +hw/ip/acc/dv/uvm/tests/acc_test_pkg.sv +hw/ip/acc/dv/verilator/acc_mock_edn.sv hw/ip/pattgen/dv/cov/pattgen_cov_bind.sv hw/ip/pattgen/dv/env/seq_lib/pattgen_error_vseq.sv hw/ip/pattgen/dv/env/seq_lib/pattgen_smoke_vseq.sv