Computer.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2023  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
# Date created = 12:05:37  March 30, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		Computer_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY Computer
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:05:37  MARCH 30, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH SHEF -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME SHEF -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id SHEF
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME SHEFT -section_id SHEF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE SHEFT.vt -section_id SHEF
set_global_assignment -name SYSTEMVERILOG_FILE SHEFT.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU_74181.sv
set_global_assignment -name VECTOR_WAVEFORM_FILE ALU.vwf
set_global_assignment -name SYSTEMVERILOG_FILE FLAG_helper.sv
set_global_assignment -name SYSTEMVERILOG_FILE Timing.sv
set_global_assignment -name VECTOR_WAVEFORM_FILE Timing.vwf
set_global_assignment -name SYSTEMVERILOG_FILE Computer.sv
set_global_assignment -name QIP_FILE decode4_16.qip
set_global_assignment -name QIP_FILE lpm_mux4.qip
set_global_assignment -name SYSTEMVERILOG_FILE reg_group.sv
set_global_assignment -name SYSTEMVERILOG_FILE flag_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE RAM.sv
set_global_assignment -name QIP_FILE PC_counter.qip
set_global_assignment -name SYSTEMVERILOG_FILE LED_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE IR_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE common_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE uControl.sv
set_global_assignment -name VECTOR_WAVEFORM_FILE Computer.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE uControl.vwf
set_global_assignment -name QIP_FILE decode5_32.qip
set_global_assignment -name QIP_FILE lpm_mux5.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE Computer2.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top