Currently, the docs state:
If the IRQ line is asserted on the same cycle that the CPU attempts to clear MIP.MEIP, the IRQ line takes priority to avoid lost interrupts.
RISC-V mandates MEIP be read-only (Version 20240326, page 37):
MEIP is read-only in mip, and is set and cleared by a platform-specific interrupt controller.
When I wrote the docs, I was probably describing how interrupt clear bits within the platform-specific interrupt controller should be implemented, and conflated that MEIP behavior.
Currently, the docs state:
RISC-V mandates MEIP be read-only (Version 20240326, page 37):
When I wrote the docs, I was probably describing how interrupt clear bits within the platform-specific interrupt controller should be implemented, and conflated that MEIP behavior.