bl net not found in timing paths for byte-write SRAM on sky130 #283
Description
Characterization fails with Could not find bl net in timing paths when generating a byte-write enabled SRAM on sky130. The SRAM layout and routing complete successfully, but the characterizer fails during .lib generation. Any insights into the root cause is appreciated.
Version Commit ea15a81 (stable), OpenRAM v1.2.49
To Reproduce
Use the following configuration:
word_size = 64
num_words = 128
human_byte_size = "{:.0f}kbytes".format((word_size * num_words) / 1024 / 8)
write_size = 8
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
num_spare_rows = 1
num_spare_cols = 1
ports_human = '1rw'
words_per_row = 2
num_threads = 8
import os
exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())
Run:
python3
sram_compiler.py -n -v \
-o sky130_sram_1kbytes_1rw_64x128_8 \
-p macros/sky130_sram_1kbytes_1rw_64x128_8 \
macros/sram_configs/sky130_sram_1kbytes_1rw_64x128_8.py
Expected behavior
Characterization should complete successfully and generate a .lib file with timing information for the byte-write enabled SRAM.
Logs
python3 sram_compiler.py -n -v -o sky130_sram_1kbytes_1rw_64x128_8 -p macros/sky130_sram_1kbytes_1rw_64x128_8 macros/sram_configs/sky130_sram_1kbytes_1rw_64x128_8.py
[openram.globals/init_openram]: Initializing OpenRAM...
[openram.globals/setup_paths]: OpenRAM source code found in /var/tmp/OpenRAM/compiler
[openram.globals/setup_paths]: Temporary files saved in /tmp/openram_lannanjiang_10261_temp/
[openram.globals/read_config]: Configuration file is /var/tmp/OpenRAM/macros/sram_configs/sky130_sram_1kbytes_1rw_64x128_8.py
[openram.globals/read_config]: Output saved in /var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/
[openram.globals/install_conda]: Creating conda setup...
[openram.globals/import_tech]: Tech directory found in /var/tmp/OpenRAM/technology:/var/tmp/OpenRAM/miniconda/lib/python3.8/site-packages/openram/technology
[openram.globals/import_tech]: Adding technology path: /var/tmp/OpenRAM/technology
[openram.globals/import_tech]: Adding technology path: /var/tmp/OpenRAM/miniconda/lib/python3.8/site-packages/openram/technology
[openram.globals/init_paths]: Creating temp directory: /tmp/openram_lannanjiang_10261_temp/
[openram.globals/setup_bitcell]: Using bitcell: bitcell_1port
[openram.characterizer/]: Initializing characterizer...
[openram.characterizer/]: Analytical model enabled.
[openram.verify/]: Initializing verify...
[openram.verify/]: LVS/DRC/PEX disabled.
[openram.globals/setup_bitcell]: Using bitcell: bitcell_1port
|==============================================================================|
|========= OpenRAM v1.2.49 =========|
|========= =========|
|========= VLSI Design and Automation Lab =========|
|========= Computer Science and Engineering Department =========|
|========= University of California Santa Cruz =========|
|========= =========|
|========= Usage help: openram-user-group@ucsc.edu =========|
|========= Development help: openram-dev-group@ucsc.edu =========|
|========= See LICENSE for license info =========|
|==============================================================================|
** Start: 03/12/2026 08:54:33
Technology: sky130
Total size: 8192 bits
Word size: 64
Words: 128
Banks: 1
Write size: 8
RW ports: 1
R-only ports: 0
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only generating nominal corner timing.
Words per row: 2
Output files are:
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.lvs
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.sp
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.v
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.lib
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.py
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.html
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.log
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.lef
/var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.gds
[openram.sram_config/recompute_sizes]: Recomputing with words per row: 2
[openram.sram_config/recompute_sizes]: Rows: 64 Cols: 128
[openram.sram_config/recompute_sizes]: Row addr size: 7 Col addr size: 1 Bank addr size: 8
[openram.sram_config/compute_sizes]: Set SRAM Words Per Row=2
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_capped_replica_bitcell_array 65 x 129
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_capped_replica_bitcell_array 65 x 129
[openram.custom.sky130_capped_replica_bitcell_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_capped_replica_bitcell_array 65 x 129 rbls: [1, 0] left_rbl: [0] right_rbl: []
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_replica_bitcell_array 65 x 129
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_replica_bitcell_array 65 x 129
[openram.custom.replica_bitcell_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_replica_bitcell_array 65 x 129 rbls: [1, 0] left_rbl: [0] right_rbl: []
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_bitcell_array 65 x 129
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_bitcell_array 65 x 129
[openram.custom.sky130_bitcell_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_bitcell_array 65 x 129
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_replica_column 66 x 1
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_replica_column 66 x 1
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_dummy_array 1 x 129
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_dummy_array 1 x 129
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_col_cap_array 1 x 129
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_col_cap_array 1 x 129
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_col_cap_array_0 1 x 129
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_col_cap_array_0 1 x 129
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_row_cap_array 66 x 1
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_row_cap_array 66 x 1
[openram.modules.bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_row_cap_array_0 66 x 1
[openram.custom.sky130_bitcell_base_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sky130_row_cap_array_0 66 x 1
[openram.modules.and2_dec/init]: Creating and2_dec and2_dec
[openram.modules.and3_dec/init]: Creating and3_dec and3_dec
[openram.modules.and4_dec/init]: Creating and4_dec and4_dec
[openram.modules.wordline_driver_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_wordline_driver_array
[openram.modules.wordline_driver/init]: Creating wordline_driver wordline_driver
[openram.modules.and2_dec/init]: Creating and2_dec and2_dec_0
[openram.modules.precharge_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_precharge_array
[openram.modules.sense_amp_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_sense_amp_array
[openram.modules.column_mux_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_column_mux_array
[openram.modules.write_driver_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_write_driver_array
[openram.modules.write_mask_and_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_write_mask_and_array
[openram.modules.pand2/init]: Creating pand2 pand2
[openram.modules.pdriver/init]: creating pdriver pdriver
[openram.modules.pinvbuf/init]: creating pinvbuf pinvbuf
[openram.modules.dff_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_row_addr_dff rows=7 cols=1
[openram.modules.dff_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_col_addr_dff rows=1 cols=1
[openram.modules.dff_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_data_dff rows=1 cols=65
[openram.modules.dff_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_wmask_dff rows=1 cols=8
[openram.modules.control_logic_base/init]: Creating control_logic_rw
[openram.modules.dff_buf/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_dff_buf
[openram.modules.dff_buf_array/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_dff_buf_array
[openram.modules.dff_buf/init]: Creating sky130_sram_1kbytes_1rw_64x128_8_dff_buf_0
[openram.modules.pand2/init]: Creating pand2 pand2_0
[openram.modules.pdriver/init]: creating pdriver pdriver_0
[openram.modules.pbuf/init]: creating pbuf with size of 129
[openram.modules.pdriver/init]: creating pdriver pdriver_1
[openram.modules.pdriver/init]: creating pdriver pdriver_2
[openram.modules.pand3/init]: Creating pand3 pand3
[openram.modules.pdriver/init]: creating pdriver pdriver_3
[openram.modules.pand3/init]: Creating pand3 pand3_0
[openram.modules.pdriver/init]: creating pdriver pdriver_4
[openram.modules.pdriver/init]: creating pdriver pdriver_5
[openram.modules.delay_chain/init]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
** Submodules: 108.9 seconds
** Placement: 0.1 seconds
[openram.base.hierarchy_layout/get_bbox]: Size: 540.86 x 198.315 with perimeter margin 0
[openram.router.router_tech/init]: Minimum track width: 0.680
[openram.router.router_tech/init]: Minimum track space: 0.300
[openram.router.router_tech/init]: Minimum track wire width: 0.380
[openram.router.signal_escape_router/route]: Running signal escape router...
[openram.router.router_tech/init]: Minimum track width: 0.680
[openram.router.router_tech/init]: Minimum track space: 0.300
[openram.router.router_tech/init]: Minimum track wire width: 0.380
[openram.router.supply_router/route]: Running router for vdd and gnd...
** Routing: 484.5 seconds
** Verification: 0.0 seconds
** SRAM creation: 593.6 seconds
SP: Writing to /var/tmp/OpenRAM/macros/sky130_sram_1kbytes_1rw_64x128_8/sky130_sram_1kbytes_1rw_64x128_8.sp
[openram.characterizer.functional/init]: Random seed for functional simulation: 1773306266988984207
** Spice writing: 0.2 seconds
DELAY: Writing stimulus...
ERROR: file simulation.py: line 605: Could not find bl net in timing paths.
Traceback (most recent call last):
File "sram_compiler.py", line 76, in
s.save()
File "/var/tmp/OpenRAM/compiler/sram.py", line 130, in save
d.analysis_init(probe_address, probe_data)
File "/var/tmp/OpenRAM/compiler/characterizer/delay.py", line 1288, in analysis_init
self.set_internal_spice_names()
File "/var/tmp/OpenRAM/compiler/characterizer/simulation.py", line 520, in set_internal_spice_names
bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
File "/var/tmp/OpenRAM/compiler/characterizer/simulation.py", line 624, in get_bl_name
bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
File "/var/tmp/OpenRAM/compiler/characterizer/simulation.py", line 605, in get_alias_in_path
debug.error("Could not find {} net in timing paths.".format(internal_net), 1)
File "/var/tmp/OpenRAM/compiler/debug.py", line 48, in error
assert return_value == 0
AssertionError