IAR support

[praqma-thi]

Support for IAR compilers

Trello card from old roadmap with a few more details that can be useful.

[buep]

Roland Stahn mentionson the Trello card that he have added some example IAR Linker MAP files to this issue in the Jenkins JIRA: https://issues.jenkins-ci.org/browse/JENKINS-19840

[buep]

See also the relevant comments and supplied examples from Roland Stahn in JENKINS-19840 (which is now closed as we only use GHI going forward).

[kvdz]

HI, i would like to make this, actually is have started already. https://github.com/kvdz/memory-map-plugin
but what is adviced?

look for each for ".text", ".noinit", ".bss"and ".data"?
Or look for the summary of the compilation:

Module                  ro code  ro data  rw data  rw data
                                                    (abs)
---------                -------  -------  -------  -------

---

Grand Total:             22 857    2 487    3 469      230

specially the Grand Total: ..... line.
because of proprietary software the content has been excluded.

The numbers are an example how much flash is used for code and data, same counts for RAM use

[buep]

Hi @kvdz

Great, we're happy to take in contributions and supply you with some answers etc.

Regarding your question above we would prefer if find the different .text, .bss etc so they can be used for making graphs. You need to implement a new parser in src/main/java/net/praqma/jenkins/memorymap/parser/ like the one for TI and GCC.
I haven't programmed any of it, but it should mostly be copy past and then fixing the regular expressions that looks for the values and adjusting a few other things.

For testing you should supply as minimum some example output file you can use in testing, so maybe from a non proprietary example?

Please note that to get your changes release you should make the pull request on this repository, not the jenkins-ci your fork i based on. But that is simply a matter of some git gymnastics.

Let's keep in touch on this issue.

[kvdz]

The reason i am asking is because i am not confident that it will work for IAR map file.
why because the illustrations in here https://github.com/Praqma/memory-map-plugin/blob/master/docs/ResearchNotes.md are not always true for IAR.

you could have 2 programs (bootloader, main program) bootloader can ben in the upper space of in the lowest space of the flash. The main program and the bootloader can have the same vector table or have different onces.

also the output from the IAR compiler (map file) is set up that it is grouped by sections of flash. into absolute sections and relative sections and what this sections contains. i don't see any of this in the TI of gcc test map file. By TI and gcc they are grouped by memory type.

[kvdz]

example some parts are removed:

---

*** PLACEMENT SUMMARY

---

"A1": place at 0x10001fe0 { section .noinit };
"A2": place at start of [0x00000000-0x000002ff] { ro section .intvec };
"A3": place at start of [0x00000300-0x0000cfff] { ro section .cstartup };
"P1": place in [from 0x00000300 to 0x0000cfff] { ro };
"P2": place in [from 0x000002fc to 0x000002ff] { ro section .crp };
"P3": place in [from 0x10000000 to 0x10001edf] { rw, block CSTACK, block HEAP };

Section Kind Address Size Object

---

"A2": 0xc0
.intvec ro code 0x00000000 0xc0 LPC11xx_IAR.o [1]
- 0x000000c0 0xc0

"P2": 0x4
.crp const 0x000002fc 0x4 GeneralAPI.o [1]
- 0x00000300 0x4

"A3": 0x10
.cstartup ro code 0x00000300 0x10 LPC11xx_IAR.o [1]
- 0x00000310 0x10

"P1": 0x622c
.text ro code 0x00000310 0xdd8 xxxx.o [1]
.rodata const 0x00001f6a 0x2 xxxx.o [1]
.text ro code 0x00001fb8 0x3b0 main.o [1]
.rodata const 0x00005a84 0x468 xxxx.o [1]
.iar.init_table const 0x00006390 0x24 - Linker created -
.text ro code 0x000063f0 0x14 LPC11xx_IAR.o [1]
.text ro code 0x00006404 0xc cstartup_M.o [5]
.rodata const 0x00006410 0x0 zero_init3.o [5]
.rodata const 0x00006410 0x0 copy_init3.o [5]
Initializer bytes ro data 0x00006410 0x12c (used: 0x128)
- 0x0000653c 0x622c

Absolute sections, part 1 of 34: 0x4
.noinit uninit 0x10000000 0x4 Bootloader_LPC11xx.o [1]
- 0x10000004 0x4

"P3", part 1 of 3: 0x12c
P3 s0 0x10000008 0x128
.data inited 0x1000011c 0x4 Bootloader_LPC11xx.o [1]
.data inited 0x10000120 0x4 GeneralAPI.o [1]
- 0x10000130 0x12c

"P3", part 2 of 3: 0x450
.bss zero 0x10000130 0xfc main.o [1]
.bss zero 0x1000022c 0xac main.o [1]
.bss zero 0x100004b0 0x20 main.o [1]
.bss zero 0x100004d0 0x20 main.o [1]
.bss zero 0x100004f0 0x20 main.o [1]
.bss zero 0x10000524 0x10 GeneralAPI.o [1]
.bss zero 0x10000534 0x10 main.o [1]
__DLIB_PERTHREAD zero 0x10000564 0x4 errno.o [3]

                        - 0x1000057e   0x44e

"P3", part 3 of 3: 0x800
CSTACK 0x10000580 0x800
CSTACK uninit 0x10000580 0x800
- 0x10000d80 0x800

[rstahn]

Nice to read about progress on this feature! I am happy to provide even more map files to be tested: EWARM_MAP2.ZIP
This contains MAP output of IAR EWARM v7.60.1 and the quite new v8.20.1.

I also added the associated linker configuration file for each map file, since I just learned that the memory map plugin evaluates this as well. My examples include three different STM32 devices (STM32F0, STM32L1, STM32L1-X). Especially the STM32L1-X is interesting, as its memory layout contains two flash banks (192kB each) with a gap in between!

Is the new IAR parser already able to evaluate the linker config files?